1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "core_types.h" 28 #include "reg_helper.h" 29 #include "dcn30_dpp.h" 30 #include "basics/conversion.h" 31 #include "dcn30_cm_common.h" 32 33 #define REG(reg)\ 34 dpp->tf_regs->reg 35 36 #define CTX \ 37 dpp->base.ctx 38 39 #undef FN 40 #define FN(reg_name, field_name) \ 41 dpp->tf_shift->field_name, dpp->tf_mask->field_name 42 43 44 void dpp30_read_state(struct dpp *dpp_base, 45 struct dcn_dpp_state *s) 46 { 47 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); 48 49 REG_GET(DPP_CONTROL, 50 DPP_CLOCK_ENABLE, &s->is_enabled); 51 52 // TODO: Implement for DCN3 53 } 54 /*program post scaler scs block in dpp CM*/ 55 void dpp3_program_post_csc( 56 struct dpp *dpp_base, 57 enum dc_color_space color_space, 58 enum dcn10_input_csc_select input_select, 59 const struct out_csc_color_matrix *tbl_entry) 60 { 61 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 62 int i; 63 int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix); 64 const uint16_t *regval = NULL; 65 uint32_t cur_select = 0; 66 enum dcn10_input_csc_select select; 67 struct color_matrices_reg gam_regs; 68 69 if (input_select == INPUT_CSC_SELECT_BYPASS) { 70 REG_SET(CM_POST_CSC_CONTROL, 0, CM_POST_CSC_MODE, 0); 71 return; 72 } 73 74 if (tbl_entry == NULL) { 75 for (i = 0; i < arr_size; i++) 76 if (dpp_input_csc_matrix[i].color_space == color_space) { 77 regval = dpp_input_csc_matrix[i].regval; 78 break; 79 } 80 81 if (regval == NULL) { 82 BREAK_TO_DEBUGGER(); 83 return; 84 } 85 } else { 86 regval = tbl_entry->regval; 87 } 88 89 /* determine which CSC matrix (icsc or coma) we are using 90 * currently. select the alternate set to double buffer 91 * the CSC update so CSC is updated on frame boundary 92 */ 93 REG_GET(CM_POST_CSC_CONTROL, 94 CM_POST_CSC_MODE_CURRENT, &cur_select); 95 96 if (cur_select != INPUT_CSC_SELECT_ICSC) 97 select = INPUT_CSC_SELECT_ICSC; 98 else 99 select = INPUT_CSC_SELECT_COMA; 100 101 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11; 102 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11; 103 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12; 104 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12; 105 106 if (select == INPUT_CSC_SELECT_ICSC) { 107 108 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12); 109 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34); 110 111 } else { 112 113 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12); 114 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34); 115 116 } 117 118 cm_helper_program_color_matrices( 119 dpp->base.ctx, 120 regval, 121 &gam_regs); 122 123 REG_SET(CM_POST_CSC_CONTROL, 0, 124 CM_POST_CSC_MODE, select); 125 } 126 127 128 /*CNVC degam unit has read only LUTs*/ 129 void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr) 130 { 131 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 132 int pre_degam_en = 1; 133 int degamma_lut_selection = 0; 134 135 switch (tr) { 136 case TRANSFER_FUNCTION_LINEAR: 137 case TRANSFER_FUNCTION_UNITY: 138 pre_degam_en = 0; //bypass 139 break; 140 case TRANSFER_FUNCTION_SRGB: 141 degamma_lut_selection = 0; 142 break; 143 case TRANSFER_FUNCTION_BT709: 144 degamma_lut_selection = 4; 145 break; 146 case TRANSFER_FUNCTION_PQ: 147 degamma_lut_selection = 5; 148 break; 149 case TRANSFER_FUNCTION_HLG: 150 degamma_lut_selection = 6; 151 break; 152 case TRANSFER_FUNCTION_GAMMA22: 153 degamma_lut_selection = 1; 154 break; 155 case TRANSFER_FUNCTION_GAMMA24: 156 degamma_lut_selection = 2; 157 break; 158 case TRANSFER_FUNCTION_GAMMA26: 159 degamma_lut_selection = 3; 160 break; 161 default: 162 pre_degam_en = 0; 163 break; 164 } 165 166 REG_SET_2(PRE_DEGAM, 0, 167 PRE_DEGAM_MODE, pre_degam_en, 168 PRE_DEGAM_SELECT, degamma_lut_selection); 169 } 170 171 static void dpp3_cnv_setup ( 172 struct dpp *dpp_base, 173 enum surface_pixel_format format, 174 enum expansion_mode mode, 175 struct dc_csc_transform input_csc_color_matrix, 176 enum dc_color_space input_color_space, 177 struct cnv_alpha_2bit_lut *alpha_2bit_lut) 178 { 179 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 180 uint32_t pixel_format = 0; 181 uint32_t alpha_en = 1; 182 enum dc_color_space color_space = COLOR_SPACE_SRGB; 183 enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS; 184 bool force_disable_cursor = false; 185 uint32_t is_2bit = 0; 186 uint32_t alpha_plane_enable = 0; 187 uint32_t dealpha_en = 0, dealpha_ablnd_en = 0; 188 uint32_t realpha_en = 0, realpha_ablnd_en = 0; 189 uint32_t program_prealpha_dealpha = 0; 190 struct out_csc_color_matrix tbl_entry; 191 int i; 192 193 REG_SET_2(FORMAT_CONTROL, 0, 194 CNVC_BYPASS, 0, 195 FORMAT_EXPANSION_MODE, mode); 196 197 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); 198 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); 199 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); 200 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); 201 202 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0); 203 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1); 204 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2); 205 206 switch (format) { 207 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 208 pixel_format = 1; 209 break; 210 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 211 pixel_format = 3; 212 alpha_en = 0; 213 break; 214 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 215 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 216 pixel_format = 8; 217 break; 218 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 219 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 220 pixel_format = 10; 221 is_2bit = 1; 222 break; 223 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 224 force_disable_cursor = false; 225 pixel_format = 65; 226 color_space = COLOR_SPACE_YCBCR709; 227 select = INPUT_CSC_SELECT_ICSC; 228 break; 229 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 230 force_disable_cursor = true; 231 pixel_format = 64; 232 color_space = COLOR_SPACE_YCBCR709; 233 select = INPUT_CSC_SELECT_ICSC; 234 break; 235 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 236 force_disable_cursor = true; 237 pixel_format = 67; 238 color_space = COLOR_SPACE_YCBCR709; 239 select = INPUT_CSC_SELECT_ICSC; 240 break; 241 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 242 force_disable_cursor = true; 243 pixel_format = 66; 244 color_space = COLOR_SPACE_YCBCR709; 245 select = INPUT_CSC_SELECT_ICSC; 246 break; 247 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 248 pixel_format = 22; 249 break; 250 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 251 pixel_format = 24; 252 break; 253 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 254 pixel_format = 25; 255 break; 256 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 257 pixel_format = 12; 258 color_space = COLOR_SPACE_YCBCR709; 259 select = INPUT_CSC_SELECT_ICSC; 260 break; 261 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 262 pixel_format = 112; 263 break; 264 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 265 pixel_format = 113; 266 break; 267 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: 268 pixel_format = 114; 269 color_space = COLOR_SPACE_YCBCR709; 270 select = INPUT_CSC_SELECT_ICSC; 271 is_2bit = 1; 272 break; 273 case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: 274 pixel_format = 115; 275 color_space = COLOR_SPACE_YCBCR709; 276 select = INPUT_CSC_SELECT_ICSC; 277 is_2bit = 1; 278 break; 279 case SURFACE_PIXEL_FORMAT_GRPH_RGBE: 280 pixel_format = 116; 281 alpha_plane_enable = 0; 282 break; 283 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 284 pixel_format = 116; 285 alpha_plane_enable = 1; 286 break; 287 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 288 pixel_format = 118; 289 break; 290 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 291 pixel_format = 119; 292 break; 293 default: 294 break; 295 } 296 297 if (is_2bit == 1 && alpha_2bit_lut != NULL) { 298 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); 299 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); 300 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); 301 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3); 302 } 303 304 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0, 305 CNVC_SURFACE_PIXEL_FORMAT, pixel_format, 306 CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable); 307 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); 308 309 if (program_prealpha_dealpha) { 310 dealpha_en = 1; 311 realpha_en = 1; 312 } 313 REG_SET_2(PRE_DEALPHA, 0, 314 PRE_DEALPHA_EN, dealpha_en, 315 PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en); 316 REG_SET_2(PRE_REALPHA, 0, 317 PRE_REALPHA_EN, realpha_en, 318 PRE_REALPHA_ABLND_EN, realpha_ablnd_en); 319 320 /* If input adjustment exists, program the ICSC with those values. */ 321 if (input_csc_color_matrix.enable_adjustment == true) { 322 for (i = 0; i < 12; i++) 323 tbl_entry.regval[i] = input_csc_color_matrix.matrix[i]; 324 325 tbl_entry.color_space = input_color_space; 326 327 if (color_space >= COLOR_SPACE_YCBCR601) 328 select = INPUT_CSC_SELECT_ICSC; 329 else 330 select = INPUT_CSC_SELECT_BYPASS; 331 332 dpp3_program_post_csc(dpp_base, color_space, select, 333 &tbl_entry); 334 } else { 335 dpp3_program_post_csc(dpp_base, color_space, select, NULL); 336 } 337 338 if (force_disable_cursor) { 339 REG_UPDATE(CURSOR_CONTROL, 340 CURSOR_ENABLE, 0); 341 REG_UPDATE(CURSOR0_CONTROL, 342 CUR0_ENABLE, 0); 343 } 344 } 345 346 #define IDENTITY_RATIO(ratio) (dc_fixpt_u3d19(ratio) == (1 << 19)) 347 348 void dpp3_set_cursor_attributes( 349 struct dpp *dpp_base, 350 struct dc_cursor_attributes *cursor_attributes) 351 { 352 enum dc_cursor_color_format color_format = cursor_attributes->color_format; 353 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 354 int cur_rom_en = 0; 355 356 if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA || 357 color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) 358 cur_rom_en = 1; 359 360 REG_UPDATE_3(CURSOR0_CONTROL, 361 CUR0_MODE, color_format, 362 CUR0_EXPANSION_MODE, 0, 363 CUR0_ROM_EN, cur_rom_en); 364 365 if (color_format == CURSOR_MODE_MONO) { 366 /* todo: clarify what to program these to */ 367 REG_UPDATE(CURSOR0_COLOR0, 368 CUR0_COLOR0, 0x00000000); 369 REG_UPDATE(CURSOR0_COLOR1, 370 CUR0_COLOR1, 0xFFFFFFFF); 371 } 372 } 373 374 375 bool dpp3_get_optimal_number_of_taps( 376 struct dpp *dpp, 377 struct scaler_data *scl_data, 378 const struct scaling_taps *in_taps) 379 { 380 int num_part_y, num_part_c; 381 int max_taps_y, max_taps_c; 382 int min_taps_y, min_taps_c; 383 enum lb_memory_config lb_config; 384 385 /* Some ASICs does not support FP16 scaling, so we reject modes require this*/ 386 if (scl_data->viewport.width != scl_data->h_active && 387 scl_data->viewport.height != scl_data->v_active && 388 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT && 389 scl_data->format == PIXEL_FORMAT_FP16) 390 return false; 391 392 if (scl_data->viewport.width > scl_data->h_active && 393 dpp->ctx->dc->debug.max_downscale_src_width != 0 && 394 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) 395 return false; 396 397 /* 398 * Set default taps if none are provided 399 * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling 400 * taps = 4 for upscaling 401 */ 402 if (in_taps->h_taps == 0) { 403 if (dc_fixpt_ceil(scl_data->ratios.horz) > 1) 404 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8); 405 else 406 scl_data->taps.h_taps = 4; 407 } else 408 scl_data->taps.h_taps = in_taps->h_taps; 409 if (in_taps->v_taps == 0) { 410 if (dc_fixpt_ceil(scl_data->ratios.vert) > 1) 411 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8); 412 else 413 scl_data->taps.v_taps = 4; 414 } else 415 scl_data->taps.v_taps = in_taps->v_taps; 416 if (in_taps->v_taps_c == 0) { 417 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 1) 418 scl_data->taps.v_taps_c = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert_c, 2)), 8); 419 else 420 scl_data->taps.v_taps_c = 4; 421 } else 422 scl_data->taps.v_taps_c = in_taps->v_taps_c; 423 if (in_taps->h_taps_c == 0) { 424 if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 1) 425 scl_data->taps.h_taps_c = min(2 * dc_fixpt_ceil(scl_data->ratios.horz_c), 8); 426 else 427 scl_data->taps.h_taps_c = 4; 428 } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1) 429 /* Only 1 and even h_taps_c are supported by hw */ 430 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1; 431 else 432 scl_data->taps.h_taps_c = in_taps->h_taps_c; 433 434 /*Ensure we can support the requested number of vtaps*/ 435 min_taps_y = dc_fixpt_ceil(scl_data->ratios.vert); 436 min_taps_c = dc_fixpt_ceil(scl_data->ratios.vert_c); 437 438 /* Use LB_MEMORY_CONFIG_3 for 4:2:0 */ 439 if ((scl_data->format == PIXEL_FORMAT_420BPP8) || (scl_data->format == PIXEL_FORMAT_420BPP10)) 440 lb_config = LB_MEMORY_CONFIG_3; 441 else 442 lb_config = LB_MEMORY_CONFIG_0; 443 444 dpp->caps->dscl_calc_lb_num_partitions( 445 scl_data, lb_config, &num_part_y, &num_part_c); 446 447 /* MAX_V_TAPS = MIN (NUM_LINES - MAX(CEILING(V_RATIO,1)-2, 0), 8) */ 448 if (dc_fixpt_ceil(scl_data->ratios.vert) > 2) 449 max_taps_y = num_part_y - (dc_fixpt_ceil(scl_data->ratios.vert) - 2); 450 else 451 max_taps_y = num_part_y; 452 453 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 2) 454 max_taps_c = num_part_c - (dc_fixpt_ceil(scl_data->ratios.vert_c) - 2); 455 else 456 max_taps_c = num_part_c; 457 458 if (max_taps_y < min_taps_y) 459 return false; 460 else if (max_taps_c < min_taps_c) 461 return false; 462 463 if (scl_data->taps.v_taps > max_taps_y) 464 scl_data->taps.v_taps = max_taps_y; 465 466 if (scl_data->taps.v_taps_c > max_taps_c) 467 scl_data->taps.v_taps_c = max_taps_c; 468 469 if (!dpp->ctx->dc->debug.always_scale) { 470 if (IDENTITY_RATIO(scl_data->ratios.horz)) 471 scl_data->taps.h_taps = 1; 472 if (IDENTITY_RATIO(scl_data->ratios.vert)) 473 scl_data->taps.v_taps = 1; 474 if (IDENTITY_RATIO(scl_data->ratios.horz_c)) 475 scl_data->taps.h_taps_c = 1; 476 if (IDENTITY_RATIO(scl_data->ratios.vert_c)) 477 scl_data->taps.v_taps_c = 1; 478 } 479 480 return true; 481 } 482 483 void dpp3_cnv_set_bias_scale( 484 struct dpp *dpp_base, 485 struct dc_bias_and_scale *bias_and_scale) 486 { 487 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 488 489 REG_UPDATE(FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, bias_and_scale->bias_red); 490 REG_UPDATE(FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, bias_and_scale->bias_green); 491 REG_UPDATE(FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, bias_and_scale->bias_blue); 492 REG_UPDATE(FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, bias_and_scale->scale_red); 493 REG_UPDATE(FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, bias_and_scale->scale_green); 494 REG_UPDATE(FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, bias_and_scale->scale_blue); 495 } 496 497 static void dpp3_power_on_blnd_lut( 498 struct dpp *dpp_base, 499 bool power_on) 500 { 501 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 502 503 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) { 504 REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, power_on ? 0 : 3); 505 if (power_on) 506 REG_WAIT(CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, 0, 1, 5); 507 } else { 508 REG_SET(CM_MEM_PWR_CTRL, 0, 509 BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0 : 1); 510 } 511 } 512 513 static void dpp3_power_on_hdr3dlut( 514 struct dpp *dpp_base, 515 bool power_on) 516 { 517 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 518 519 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) { 520 REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, power_on ? 0 : 3); 521 if (power_on) 522 REG_WAIT(CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, 0, 1, 5); 523 } 524 } 525 526 static void dpp3_power_on_shaper( 527 struct dpp *dpp_base, 528 bool power_on) 529 { 530 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 531 532 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) { 533 REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, power_on ? 0 : 3); 534 if (power_on) 535 REG_WAIT(CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, 0, 1, 5); 536 } 537 } 538 539 static void dpp3_configure_blnd_lut( 540 struct dpp *dpp_base, 541 bool is_ram_a) 542 { 543 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 544 545 REG_UPDATE_2(CM_BLNDGAM_LUT_CONTROL, 546 CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 7, 547 CM_BLNDGAM_LUT_HOST_SEL, is_ram_a == true ? 0 : 1); 548 549 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0); 550 } 551 552 static void dpp3_program_blnd_pwl( 553 struct dpp *dpp_base, 554 const struct pwl_result_data *rgb, 555 uint32_t num) 556 { 557 uint32_t i; 558 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 559 uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg; 560 uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg; 561 uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg; 562 563 if (is_rgb_equal(rgb, num)) { 564 for (i = 0 ; i < num; i++) 565 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg); 566 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red); 567 } else { 568 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 4); 569 for (i = 0 ; i < num; i++) 570 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg); 571 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red); 572 573 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 2); 574 for (i = 0 ; i < num; i++) 575 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg); 576 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_green); 577 578 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 1); 579 for (i = 0 ; i < num; i++) 580 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg); 581 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_blue); 582 } 583 } 584 585 static void dcn3_dpp_cm_get_reg_field( 586 struct dcn3_dpp *dpp, 587 struct dcn3_xfer_func_reg *reg) 588 { 589 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; 590 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; 591 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; 592 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; 593 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; 594 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; 595 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; 596 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; 597 598 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; 599 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; 600 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; 601 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; 602 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; 603 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; 604 reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B; 605 reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B; 606 reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B; 607 reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B; 608 reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; 609 reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; 610 } 611 612 /*program blnd lut RAM A*/ 613 static void dpp3_program_blnd_luta_settings( 614 struct dpp *dpp_base, 615 const struct pwl_params *params) 616 { 617 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 618 struct dcn3_xfer_func_reg gam_regs; 619 620 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs); 621 622 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B); 623 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G); 624 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R); 625 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B); 626 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G); 627 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R); 628 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B); 629 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B); 630 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G); 631 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G); 632 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R); 633 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R); 634 gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1); 635 gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33); 636 637 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs); 638 } 639 640 /*program blnd lut RAM B*/ 641 static void dpp3_program_blnd_lutb_settings( 642 struct dpp *dpp_base, 643 const struct pwl_params *params) 644 { 645 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 646 struct dcn3_xfer_func_reg gam_regs; 647 648 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs); 649 650 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B); 651 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G); 652 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R); 653 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B); 654 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G); 655 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R); 656 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B); 657 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B); 658 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G); 659 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G); 660 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R); 661 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R); 662 gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1); 663 gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33); 664 665 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs); 666 } 667 668 static enum dc_lut_mode dpp3_get_blndgam_current(struct dpp *dpp_base) 669 { 670 enum dc_lut_mode mode; 671 uint32_t mode_current = 0; 672 uint32_t in_use = 0; 673 674 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 675 676 REG_GET(CM_BLNDGAM_CONTROL, 677 CM_BLNDGAM_MODE_CURRENT, &mode_current); 678 REG_GET(CM_BLNDGAM_CONTROL, 679 CM_BLNDGAM_SELECT_CURRENT, &in_use); 680 681 switch (mode_current) { 682 case 0: 683 case 1: 684 mode = LUT_BYPASS; 685 break; 686 687 case 2: 688 if (in_use == 0) 689 mode = LUT_RAM_A; 690 else 691 mode = LUT_RAM_B; 692 break; 693 default: 694 mode = LUT_BYPASS; 695 break; 696 } 697 return mode; 698 } 699 700 bool dpp3_program_blnd_lut( 701 struct dpp *dpp_base, const struct pwl_params *params) 702 { 703 enum dc_lut_mode current_mode; 704 enum dc_lut_mode next_mode; 705 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 706 707 if (params == NULL) { 708 REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_MODE, 0); 709 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) 710 dpp3_power_on_blnd_lut(dpp_base, false); 711 return false; 712 } 713 714 current_mode = dpp3_get_blndgam_current(dpp_base); 715 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_B) 716 next_mode = LUT_RAM_A; 717 else 718 next_mode = LUT_RAM_B; 719 720 dpp3_power_on_blnd_lut(dpp_base, true); 721 dpp3_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A ? true:false); 722 723 if (next_mode == LUT_RAM_A) 724 dpp3_program_blnd_luta_settings(dpp_base, params); 725 else 726 dpp3_program_blnd_lutb_settings(dpp_base, params); 727 728 dpp3_program_blnd_pwl( 729 dpp_base, params->rgb_resulted, params->hw_points_num); 730 731 REG_UPDATE_2(CM_BLNDGAM_CONTROL, 732 CM_BLNDGAM_MODE, 2, 733 CM_BLNDGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1); 734 735 return true; 736 } 737 738 739 static void dpp3_program_shaper_lut( 740 struct dpp *dpp_base, 741 const struct pwl_result_data *rgb, 742 uint32_t num) 743 { 744 uint32_t i, red, green, blue; 745 uint32_t red_delta, green_delta, blue_delta; 746 uint32_t red_value, green_value, blue_value; 747 748 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 749 750 for (i = 0 ; i < num; i++) { 751 752 red = rgb[i].red_reg; 753 green = rgb[i].green_reg; 754 blue = rgb[i].blue_reg; 755 756 red_delta = rgb[i].delta_red_reg; 757 green_delta = rgb[i].delta_green_reg; 758 blue_delta = rgb[i].delta_blue_reg; 759 760 red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff); 761 green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff); 762 blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff); 763 764 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, red_value); 765 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, green_value); 766 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, blue_value); 767 } 768 769 } 770 771 static enum dc_lut_mode dpp3_get_shaper_current(struct dpp *dpp_base) 772 { 773 enum dc_lut_mode mode; 774 uint32_t state_mode; 775 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 776 777 REG_GET(CM_SHAPER_CONTROL, 778 CM_SHAPER_MODE_CURRENT, &state_mode); 779 780 switch (state_mode) { 781 case 0: 782 mode = LUT_BYPASS; 783 break; 784 case 1: 785 mode = LUT_RAM_A; 786 break; 787 case 2: 788 mode = LUT_RAM_B; 789 break; 790 default: 791 mode = LUT_BYPASS; 792 break; 793 } 794 return mode; 795 } 796 797 static void dpp3_configure_shaper_lut( 798 struct dpp *dpp_base, 799 bool is_ram_a) 800 { 801 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 802 803 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK, 804 CM_SHAPER_LUT_WRITE_EN_MASK, 7); 805 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK, 806 CM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1); 807 REG_SET(CM_SHAPER_LUT_INDEX, 0, CM_SHAPER_LUT_INDEX, 0); 808 } 809 810 /*program shaper RAM A*/ 811 812 static void dpp3_program_shaper_luta_settings( 813 struct dpp *dpp_base, 814 const struct pwl_params *params) 815 { 816 const struct gamma_curve *curve; 817 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 818 819 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0, 820 CM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, 821 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); 822 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0, 823 CM_SHAPER_RAMA_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x, 824 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, 0); 825 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0, 826 CM_SHAPER_RAMA_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x, 827 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, 0); 828 829 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0, 830 CM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, 831 CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); 832 833 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0, 834 CM_SHAPER_RAMA_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x, 835 CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y); 836 837 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0, 838 CM_SHAPER_RAMA_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x, 839 CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y); 840 841 curve = params->arr_curve_points; 842 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0, 843 CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 844 CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 845 CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 846 CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 847 848 curve += 2; 849 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0, 850 CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset, 851 CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, 852 CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset, 853 CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); 854 855 curve += 2; 856 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0, 857 CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset, 858 CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, 859 CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset, 860 CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); 861 862 curve += 2; 863 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0, 864 CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset, 865 CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, 866 CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset, 867 CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); 868 869 curve += 2; 870 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0, 871 CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset, 872 CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, 873 CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset, 874 CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); 875 876 curve += 2; 877 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0, 878 CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset, 879 CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, 880 CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset, 881 CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); 882 883 curve += 2; 884 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0, 885 CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset, 886 CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, 887 CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset, 888 CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); 889 890 curve += 2; 891 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0, 892 CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset, 893 CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, 894 CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset, 895 CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); 896 897 curve += 2; 898 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0, 899 CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset, 900 CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num, 901 CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset, 902 CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num); 903 904 curve += 2; 905 REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0, 906 CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset, 907 CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num, 908 CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset, 909 CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num); 910 911 curve += 2; 912 REG_SET_4(CM_SHAPER_RAMA_REGION_20_21, 0, 913 CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset, 914 CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num, 915 CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset, 916 CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num); 917 918 curve += 2; 919 REG_SET_4(CM_SHAPER_RAMA_REGION_22_23, 0, 920 CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset, 921 CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num, 922 CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset, 923 CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num); 924 925 curve += 2; 926 REG_SET_4(CM_SHAPER_RAMA_REGION_24_25, 0, 927 CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset, 928 CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num, 929 CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset, 930 CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num); 931 932 curve += 2; 933 REG_SET_4(CM_SHAPER_RAMA_REGION_26_27, 0, 934 CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset, 935 CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num, 936 CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset, 937 CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num); 938 939 curve += 2; 940 REG_SET_4(CM_SHAPER_RAMA_REGION_28_29, 0, 941 CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset, 942 CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num, 943 CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset, 944 CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num); 945 946 curve += 2; 947 REG_SET_4(CM_SHAPER_RAMA_REGION_30_31, 0, 948 CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset, 949 CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num, 950 CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset, 951 CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num); 952 953 curve += 2; 954 REG_SET_4(CM_SHAPER_RAMA_REGION_32_33, 0, 955 CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset, 956 CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num, 957 CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset, 958 CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num); 959 } 960 961 /*program shaper RAM B*/ 962 static void dpp3_program_shaper_lutb_settings( 963 struct dpp *dpp_base, 964 const struct pwl_params *params) 965 { 966 const struct gamma_curve *curve; 967 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 968 969 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0, 970 CM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, 971 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0); 972 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0, 973 CM_SHAPER_RAMB_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x, 974 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, 0); 975 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0, 976 CM_SHAPER_RAMB_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x, 977 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, 0); 978 979 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0, 980 CM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, 981 CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); 982 983 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_G, 0, 984 CM_SHAPER_RAMB_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x, 985 CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y); 986 987 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_R, 0, 988 CM_SHAPER_RAMB_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x, 989 CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y); 990 991 curve = params->arr_curve_points; 992 REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0, 993 CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 994 CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 995 CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 996 CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 997 998 curve += 2; 999 REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0, 1000 CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset, 1001 CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, 1002 CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset, 1003 CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); 1004 1005 curve += 2; 1006 REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0, 1007 CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset, 1008 CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, 1009 CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset, 1010 CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); 1011 1012 curve += 2; 1013 REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0, 1014 CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset, 1015 CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, 1016 CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset, 1017 CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); 1018 1019 curve += 2; 1020 REG_SET_4(CM_SHAPER_RAMB_REGION_8_9, 0, 1021 CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset, 1022 CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, 1023 CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset, 1024 CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); 1025 1026 curve += 2; 1027 REG_SET_4(CM_SHAPER_RAMB_REGION_10_11, 0, 1028 CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset, 1029 CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, 1030 CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset, 1031 CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); 1032 1033 curve += 2; 1034 REG_SET_4(CM_SHAPER_RAMB_REGION_12_13, 0, 1035 CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset, 1036 CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, 1037 CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset, 1038 CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); 1039 1040 curve += 2; 1041 REG_SET_4(CM_SHAPER_RAMB_REGION_14_15, 0, 1042 CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset, 1043 CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, 1044 CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset, 1045 CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); 1046 1047 curve += 2; 1048 REG_SET_4(CM_SHAPER_RAMB_REGION_16_17, 0, 1049 CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset, 1050 CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num, 1051 CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset, 1052 CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num); 1053 1054 curve += 2; 1055 REG_SET_4(CM_SHAPER_RAMB_REGION_18_19, 0, 1056 CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset, 1057 CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num, 1058 CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset, 1059 CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num); 1060 1061 curve += 2; 1062 REG_SET_4(CM_SHAPER_RAMB_REGION_20_21, 0, 1063 CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset, 1064 CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num, 1065 CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset, 1066 CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num); 1067 1068 curve += 2; 1069 REG_SET_4(CM_SHAPER_RAMB_REGION_22_23, 0, 1070 CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset, 1071 CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num, 1072 CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset, 1073 CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num); 1074 1075 curve += 2; 1076 REG_SET_4(CM_SHAPER_RAMB_REGION_24_25, 0, 1077 CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset, 1078 CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num, 1079 CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset, 1080 CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num); 1081 1082 curve += 2; 1083 REG_SET_4(CM_SHAPER_RAMB_REGION_26_27, 0, 1084 CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset, 1085 CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num, 1086 CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset, 1087 CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num); 1088 1089 curve += 2; 1090 REG_SET_4(CM_SHAPER_RAMB_REGION_28_29, 0, 1091 CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset, 1092 CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num, 1093 CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset, 1094 CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num); 1095 1096 curve += 2; 1097 REG_SET_4(CM_SHAPER_RAMB_REGION_30_31, 0, 1098 CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset, 1099 CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num, 1100 CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset, 1101 CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num); 1102 1103 curve += 2; 1104 REG_SET_4(CM_SHAPER_RAMB_REGION_32_33, 0, 1105 CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset, 1106 CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num, 1107 CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset, 1108 CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num); 1109 1110 } 1111 1112 1113 bool dpp3_program_shaper( 1114 struct dpp *dpp_base, 1115 const struct pwl_params *params) 1116 { 1117 enum dc_lut_mode current_mode; 1118 enum dc_lut_mode next_mode; 1119 1120 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1121 1122 if (params == NULL) { 1123 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0); 1124 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) 1125 dpp3_power_on_shaper(dpp_base, false); 1126 return false; 1127 } 1128 1129 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) 1130 dpp3_power_on_shaper(dpp_base, true); 1131 1132 current_mode = dpp3_get_shaper_current(dpp_base); 1133 1134 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A) 1135 next_mode = LUT_RAM_B; 1136 else 1137 next_mode = LUT_RAM_A; 1138 1139 dpp3_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A ? true:false); 1140 1141 if (next_mode == LUT_RAM_A) 1142 dpp3_program_shaper_luta_settings(dpp_base, params); 1143 else 1144 dpp3_program_shaper_lutb_settings(dpp_base, params); 1145 1146 dpp3_program_shaper_lut( 1147 dpp_base, params->rgb_resulted, params->hw_points_num); 1148 1149 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2); 1150 1151 return true; 1152 1153 } 1154 1155 static enum dc_lut_mode get3dlut_config( 1156 struct dpp *dpp_base, 1157 bool *is_17x17x17, 1158 bool *is_12bits_color_channel) 1159 { 1160 uint32_t i_mode, i_enable_10bits, lut_size; 1161 enum dc_lut_mode mode; 1162 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1163 1164 REG_GET(CM_3DLUT_READ_WRITE_CONTROL, 1165 CM_3DLUT_30BIT_EN, &i_enable_10bits); 1166 REG_GET(CM_3DLUT_MODE, 1167 CM_3DLUT_MODE_CURRENT, &i_mode); 1168 1169 switch (i_mode) { 1170 case 0: 1171 mode = LUT_BYPASS; 1172 break; 1173 case 1: 1174 mode = LUT_RAM_A; 1175 break; 1176 case 2: 1177 mode = LUT_RAM_B; 1178 break; 1179 default: 1180 mode = LUT_BYPASS; 1181 break; 1182 } 1183 if (i_enable_10bits > 0) 1184 *is_12bits_color_channel = false; 1185 else 1186 *is_12bits_color_channel = true; 1187 1188 REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &lut_size); 1189 1190 if (lut_size == 0) 1191 *is_17x17x17 = true; 1192 else 1193 *is_17x17x17 = false; 1194 1195 return mode; 1196 } 1197 /* 1198 * select ramA or ramB, or bypass 1199 * select color channel size 10 or 12 bits 1200 * select 3dlut size 17x17x17 or 9x9x9 1201 */ 1202 static void dpp3_set_3dlut_mode( 1203 struct dpp *dpp_base, 1204 enum dc_lut_mode mode, 1205 bool is_color_channel_12bits, 1206 bool is_lut_size17x17x17) 1207 { 1208 uint32_t lut_mode; 1209 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1210 1211 if (mode == LUT_BYPASS) 1212 lut_mode = 0; 1213 else if (mode == LUT_RAM_A) 1214 lut_mode = 1; 1215 else 1216 lut_mode = 2; 1217 1218 REG_UPDATE_2(CM_3DLUT_MODE, 1219 CM_3DLUT_MODE, lut_mode, 1220 CM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1); 1221 } 1222 1223 static void dpp3_select_3dlut_ram( 1224 struct dpp *dpp_base, 1225 enum dc_lut_mode mode, 1226 bool is_color_channel_12bits) 1227 { 1228 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1229 1230 REG_UPDATE_2(CM_3DLUT_READ_WRITE_CONTROL, 1231 CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1, 1232 CM_3DLUT_30BIT_EN, 1233 is_color_channel_12bits == true ? 0:1); 1234 } 1235 1236 1237 1238 static void dpp3_set3dlut_ram12( 1239 struct dpp *dpp_base, 1240 const struct dc_rgb *lut, 1241 uint32_t entries) 1242 { 1243 uint32_t i, red, green, blue, red1, green1, blue1; 1244 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1245 1246 for (i = 0 ; i < entries; i += 2) { 1247 red = lut[i].red<<4; 1248 green = lut[i].green<<4; 1249 blue = lut[i].blue<<4; 1250 red1 = lut[i+1].red<<4; 1251 green1 = lut[i+1].green<<4; 1252 blue1 = lut[i+1].blue<<4; 1253 1254 REG_SET_2(CM_3DLUT_DATA, 0, 1255 CM_3DLUT_DATA0, red, 1256 CM_3DLUT_DATA1, red1); 1257 1258 REG_SET_2(CM_3DLUT_DATA, 0, 1259 CM_3DLUT_DATA0, green, 1260 CM_3DLUT_DATA1, green1); 1261 1262 REG_SET_2(CM_3DLUT_DATA, 0, 1263 CM_3DLUT_DATA0, blue, 1264 CM_3DLUT_DATA1, blue1); 1265 1266 } 1267 } 1268 1269 /* 1270 * load selected lut with 10 bits color channels 1271 */ 1272 static void dpp3_set3dlut_ram10( 1273 struct dpp *dpp_base, 1274 const struct dc_rgb *lut, 1275 uint32_t entries) 1276 { 1277 uint32_t i, red, green, blue, value; 1278 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1279 1280 for (i = 0; i < entries; i++) { 1281 red = lut[i].red; 1282 green = lut[i].green; 1283 blue = lut[i].blue; 1284 1285 value = (red<<20) | (green<<10) | blue; 1286 1287 REG_SET(CM_3DLUT_DATA_30BIT, 0, CM_3DLUT_DATA_30BIT, value); 1288 } 1289 1290 } 1291 1292 1293 static void dpp3_select_3dlut_ram_mask( 1294 struct dpp *dpp_base, 1295 uint32_t ram_selection_mask) 1296 { 1297 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1298 1299 REG_UPDATE(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK, 1300 ram_selection_mask); 1301 REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0); 1302 } 1303 1304 bool dpp3_program_3dlut( 1305 struct dpp *dpp_base, 1306 struct tetrahedral_params *params) 1307 { 1308 enum dc_lut_mode mode; 1309 bool is_17x17x17; 1310 bool is_12bits_color_channel; 1311 struct dc_rgb *lut0; 1312 struct dc_rgb *lut1; 1313 struct dc_rgb *lut2; 1314 struct dc_rgb *lut3; 1315 int lut_size0; 1316 int lut_size; 1317 1318 if (params == NULL) { 1319 dpp3_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false); 1320 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) 1321 dpp3_power_on_hdr3dlut(dpp_base, false); 1322 return false; 1323 } 1324 1325 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) 1326 dpp3_power_on_hdr3dlut(dpp_base, true); 1327 1328 mode = get3dlut_config(dpp_base, &is_17x17x17, &is_12bits_color_channel); 1329 1330 if (mode == LUT_BYPASS || mode == LUT_RAM_B) 1331 mode = LUT_RAM_A; 1332 else 1333 mode = LUT_RAM_B; 1334 1335 is_17x17x17 = !params->use_tetrahedral_9; 1336 is_12bits_color_channel = params->use_12bits; 1337 if (is_17x17x17) { 1338 lut0 = params->tetrahedral_17.lut0; 1339 lut1 = params->tetrahedral_17.lut1; 1340 lut2 = params->tetrahedral_17.lut2; 1341 lut3 = params->tetrahedral_17.lut3; 1342 lut_size0 = sizeof(params->tetrahedral_17.lut0)/ 1343 sizeof(params->tetrahedral_17.lut0[0]); 1344 lut_size = sizeof(params->tetrahedral_17.lut1)/ 1345 sizeof(params->tetrahedral_17.lut1[0]); 1346 } else { 1347 lut0 = params->tetrahedral_9.lut0; 1348 lut1 = params->tetrahedral_9.lut1; 1349 lut2 = params->tetrahedral_9.lut2; 1350 lut3 = params->tetrahedral_9.lut3; 1351 lut_size0 = sizeof(params->tetrahedral_9.lut0)/ 1352 sizeof(params->tetrahedral_9.lut0[0]); 1353 lut_size = sizeof(params->tetrahedral_9.lut1)/ 1354 sizeof(params->tetrahedral_9.lut1[0]); 1355 } 1356 1357 dpp3_select_3dlut_ram(dpp_base, mode, 1358 is_12bits_color_channel); 1359 dpp3_select_3dlut_ram_mask(dpp_base, 0x1); 1360 if (is_12bits_color_channel) 1361 dpp3_set3dlut_ram12(dpp_base, lut0, lut_size0); 1362 else 1363 dpp3_set3dlut_ram10(dpp_base, lut0, lut_size0); 1364 1365 dpp3_select_3dlut_ram_mask(dpp_base, 0x2); 1366 if (is_12bits_color_channel) 1367 dpp3_set3dlut_ram12(dpp_base, lut1, lut_size); 1368 else 1369 dpp3_set3dlut_ram10(dpp_base, lut1, lut_size); 1370 1371 dpp3_select_3dlut_ram_mask(dpp_base, 0x4); 1372 if (is_12bits_color_channel) 1373 dpp3_set3dlut_ram12(dpp_base, lut2, lut_size); 1374 else 1375 dpp3_set3dlut_ram10(dpp_base, lut2, lut_size); 1376 1377 dpp3_select_3dlut_ram_mask(dpp_base, 0x8); 1378 if (is_12bits_color_channel) 1379 dpp3_set3dlut_ram12(dpp_base, lut3, lut_size); 1380 else 1381 dpp3_set3dlut_ram10(dpp_base, lut3, lut_size); 1382 1383 1384 dpp3_set_3dlut_mode(dpp_base, mode, is_12bits_color_channel, 1385 is_17x17x17); 1386 1387 return true; 1388 } 1389 static struct dpp_funcs dcn30_dpp_funcs = { 1390 .dpp_program_gamcor_lut = dpp3_program_gamcor_lut, 1391 .dpp_read_state = dpp30_read_state, 1392 .dpp_reset = dpp_reset, 1393 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale, 1394 .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps, 1395 .dpp_set_gamut_remap = dpp3_cm_set_gamut_remap, 1396 .dpp_set_csc_adjustment = NULL, 1397 .dpp_set_csc_default = NULL, 1398 .dpp_program_regamma_pwl = NULL, 1399 .dpp_set_pre_degam = dpp3_set_pre_degam, 1400 .dpp_program_input_lut = NULL, 1401 .dpp_full_bypass = dpp1_full_bypass, 1402 .dpp_setup = dpp3_cnv_setup, 1403 .dpp_program_degamma_pwl = NULL, 1404 .dpp_program_cm_dealpha = dpp3_program_cm_dealpha, 1405 .dpp_program_cm_bias = dpp3_program_cm_bias, 1406 .dpp_program_blnd_lut = dpp3_program_blnd_lut, 1407 .dpp_program_shaper_lut = dpp3_program_shaper, 1408 .dpp_program_3dlut = dpp3_program_3dlut, 1409 .dpp_program_bias_and_scale = NULL, 1410 .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer, 1411 .set_cursor_attributes = dpp3_set_cursor_attributes, 1412 .set_cursor_position = dpp1_set_cursor_position, 1413 .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes, 1414 .dpp_dppclk_control = dpp1_dppclk_control, 1415 .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier, 1416 }; 1417 1418 1419 static struct dpp_caps dcn30_dpp_cap = { 1420 .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT, 1421 .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions, 1422 }; 1423 1424 bool dpp3_construct( 1425 struct dcn3_dpp *dpp, 1426 struct dc_context *ctx, 1427 uint32_t inst, 1428 const struct dcn3_dpp_registers *tf_regs, 1429 const struct dcn3_dpp_shift *tf_shift, 1430 const struct dcn3_dpp_mask *tf_mask) 1431 { 1432 dpp->base.ctx = ctx; 1433 1434 dpp->base.inst = inst; 1435 dpp->base.funcs = &dcn30_dpp_funcs; 1436 dpp->base.caps = &dcn30_dpp_cap; 1437 1438 dpp->tf_regs = tf_regs; 1439 dpp->tf_shift = tf_shift; 1440 dpp->tf_mask = tf_mask; 1441 1442 dpp->lb_pixel_depth_supported = 1443 LB_PIXEL_DEPTH_18BPP | 1444 LB_PIXEL_DEPTH_24BPP | 1445 LB_PIXEL_DEPTH_30BPP; 1446 1447 dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY; 1448 dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/ 1449 1450 return true; 1451 } 1452 1453