1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "core_types.h" 28 #include "reg_helper.h" 29 #include "dcn30_dpp.h" 30 #include "basics/conversion.h" 31 #include "dcn30_cm_common.h" 32 33 #define REG(reg)\ 34 dpp->tf_regs->reg 35 36 #define CTX \ 37 dpp->base.ctx 38 39 #undef FN 40 #define FN(reg_name, field_name) \ 41 dpp->tf_shift->field_name, dpp->tf_mask->field_name 42 43 44 void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s) 45 { 46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 47 48 REG_GET(DPP_CONTROL, 49 DPP_CLOCK_ENABLE, &s->is_enabled); 50 51 // TODO: Implement for DCN3 52 } 53 /*program post scaler scs block in dpp CM*/ 54 void dpp3_program_post_csc( 55 struct dpp *dpp_base, 56 enum dc_color_space color_space, 57 enum dcn10_input_csc_select input_select, 58 const struct out_csc_color_matrix *tbl_entry) 59 { 60 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 61 int i; 62 int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix); 63 const uint16_t *regval = NULL; 64 uint32_t cur_select = 0; 65 enum dcn10_input_csc_select select; 66 struct color_matrices_reg gam_regs; 67 68 if (input_select == INPUT_CSC_SELECT_BYPASS) { 69 REG_SET(CM_POST_CSC_CONTROL, 0, CM_POST_CSC_MODE, 0); 70 return; 71 } 72 73 if (tbl_entry == NULL) { 74 for (i = 0; i < arr_size; i++) 75 if (dpp_input_csc_matrix[i].color_space == color_space) { 76 regval = dpp_input_csc_matrix[i].regval; 77 break; 78 } 79 80 if (regval == NULL) { 81 BREAK_TO_DEBUGGER(); 82 return; 83 } 84 } else { 85 regval = tbl_entry->regval; 86 } 87 88 /* determine which CSC matrix (icsc or coma) we are using 89 * currently. select the alternate set to double buffer 90 * the CSC update so CSC is updated on frame boundary 91 */ 92 REG_GET(CM_POST_CSC_CONTROL, 93 CM_POST_CSC_MODE_CURRENT, &cur_select); 94 95 if (cur_select != INPUT_CSC_SELECT_ICSC) 96 select = INPUT_CSC_SELECT_ICSC; 97 else 98 select = INPUT_CSC_SELECT_COMA; 99 100 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11; 101 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11; 102 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12; 103 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12; 104 105 if (select == INPUT_CSC_SELECT_ICSC) { 106 107 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12); 108 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34); 109 110 } else { 111 112 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12); 113 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34); 114 115 } 116 117 cm_helper_program_color_matrices( 118 dpp->base.ctx, 119 regval, 120 &gam_regs); 121 122 REG_SET(CM_POST_CSC_CONTROL, 0, 123 CM_POST_CSC_MODE, select); 124 } 125 126 127 /*CNVC degam unit has read only LUTs*/ 128 void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr) 129 { 130 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 131 int pre_degam_en = 1; 132 int degamma_lut_selection = 0; 133 134 switch (tr) { 135 case TRANSFER_FUNCTION_LINEAR: 136 case TRANSFER_FUNCTION_UNITY: 137 pre_degam_en = 0; //bypass 138 break; 139 case TRANSFER_FUNCTION_SRGB: 140 degamma_lut_selection = 0; 141 break; 142 case TRANSFER_FUNCTION_BT709: 143 degamma_lut_selection = 4; 144 break; 145 case TRANSFER_FUNCTION_PQ: 146 degamma_lut_selection = 5; 147 break; 148 case TRANSFER_FUNCTION_HLG: 149 degamma_lut_selection = 6; 150 break; 151 case TRANSFER_FUNCTION_GAMMA22: 152 degamma_lut_selection = 1; 153 break; 154 case TRANSFER_FUNCTION_GAMMA24: 155 degamma_lut_selection = 2; 156 break; 157 case TRANSFER_FUNCTION_GAMMA26: 158 degamma_lut_selection = 3; 159 break; 160 default: 161 pre_degam_en = 0; 162 break; 163 } 164 165 REG_SET_2(PRE_DEGAM, 0, 166 PRE_DEGAM_MODE, pre_degam_en, 167 PRE_DEGAM_SELECT, degamma_lut_selection); 168 } 169 170 void dpp3_cnv_setup ( 171 struct dpp *dpp_base, 172 enum surface_pixel_format format, 173 enum expansion_mode mode, 174 struct dc_csc_transform input_csc_color_matrix, 175 enum dc_color_space input_color_space, 176 struct cnv_alpha_2bit_lut *alpha_2bit_lut) 177 { 178 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 179 uint32_t pixel_format = 0; 180 uint32_t alpha_en = 1; 181 enum dc_color_space color_space = COLOR_SPACE_SRGB; 182 enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS; 183 bool force_disable_cursor = false; 184 uint32_t is_2bit = 0; 185 uint32_t alpha_plane_enable = 0; 186 uint32_t dealpha_en = 0, dealpha_ablnd_en = 0; 187 uint32_t realpha_en = 0, realpha_ablnd_en = 0; 188 uint32_t program_prealpha_dealpha = 0; 189 struct out_csc_color_matrix tbl_entry; 190 int i; 191 192 REG_SET_2(FORMAT_CONTROL, 0, 193 CNVC_BYPASS, 0, 194 FORMAT_EXPANSION_MODE, mode); 195 196 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); 197 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); 198 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); 199 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); 200 201 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0); 202 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1); 203 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2); 204 205 switch (format) { 206 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 207 pixel_format = 1; 208 break; 209 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 210 pixel_format = 3; 211 alpha_en = 0; 212 break; 213 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 214 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 215 pixel_format = 8; 216 break; 217 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 218 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 219 pixel_format = 10; 220 is_2bit = 1; 221 break; 222 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 223 force_disable_cursor = false; 224 pixel_format = 65; 225 color_space = COLOR_SPACE_YCBCR709; 226 select = INPUT_CSC_SELECT_ICSC; 227 break; 228 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 229 force_disable_cursor = true; 230 pixel_format = 64; 231 color_space = COLOR_SPACE_YCBCR709; 232 select = INPUT_CSC_SELECT_ICSC; 233 break; 234 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 235 force_disable_cursor = true; 236 pixel_format = 67; 237 color_space = COLOR_SPACE_YCBCR709; 238 select = INPUT_CSC_SELECT_ICSC; 239 break; 240 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 241 force_disable_cursor = true; 242 pixel_format = 66; 243 color_space = COLOR_SPACE_YCBCR709; 244 select = INPUT_CSC_SELECT_ICSC; 245 break; 246 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 247 pixel_format = 22; 248 break; 249 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 250 pixel_format = 26; /* ARGB16161616_UNORM */ 251 break; 252 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 253 pixel_format = 24; 254 break; 255 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 256 pixel_format = 25; 257 break; 258 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 259 pixel_format = 12; 260 color_space = COLOR_SPACE_YCBCR709; 261 select = INPUT_CSC_SELECT_ICSC; 262 break; 263 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 264 pixel_format = 112; 265 break; 266 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 267 pixel_format = 113; 268 break; 269 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: 270 pixel_format = 114; 271 color_space = COLOR_SPACE_YCBCR709; 272 select = INPUT_CSC_SELECT_ICSC; 273 is_2bit = 1; 274 break; 275 case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: 276 pixel_format = 115; 277 color_space = COLOR_SPACE_YCBCR709; 278 select = INPUT_CSC_SELECT_ICSC; 279 is_2bit = 1; 280 break; 281 case SURFACE_PIXEL_FORMAT_GRPH_RGBE: 282 pixel_format = 116; 283 alpha_plane_enable = 0; 284 break; 285 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 286 pixel_format = 116; 287 alpha_plane_enable = 1; 288 break; 289 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 290 pixel_format = 118; 291 break; 292 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 293 pixel_format = 119; 294 break; 295 default: 296 break; 297 } 298 299 /* Set default color space based on format if none is given. */ 300 color_space = input_color_space ? input_color_space : color_space; 301 302 if (is_2bit == 1 && alpha_2bit_lut != NULL) { 303 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); 304 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); 305 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); 306 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3); 307 } 308 309 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0, 310 CNVC_SURFACE_PIXEL_FORMAT, pixel_format, 311 CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable); 312 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); 313 314 if (program_prealpha_dealpha) { 315 dealpha_en = 1; 316 realpha_en = 1; 317 } 318 REG_SET_2(PRE_DEALPHA, 0, 319 PRE_DEALPHA_EN, dealpha_en, 320 PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en); 321 REG_SET_2(PRE_REALPHA, 0, 322 PRE_REALPHA_EN, realpha_en, 323 PRE_REALPHA_ABLND_EN, realpha_ablnd_en); 324 325 /* If input adjustment exists, program the ICSC with those values. */ 326 if (input_csc_color_matrix.enable_adjustment == true) { 327 for (i = 0; i < 12; i++) 328 tbl_entry.regval[i] = input_csc_color_matrix.matrix[i]; 329 330 tbl_entry.color_space = input_color_space; 331 332 if (color_space >= COLOR_SPACE_YCBCR601) 333 select = INPUT_CSC_SELECT_ICSC; 334 else 335 select = INPUT_CSC_SELECT_BYPASS; 336 337 dpp3_program_post_csc(dpp_base, color_space, select, 338 &tbl_entry); 339 } else { 340 dpp3_program_post_csc(dpp_base, color_space, select, NULL); 341 } 342 343 if (force_disable_cursor) { 344 REG_UPDATE(CURSOR_CONTROL, 345 CURSOR_ENABLE, 0); 346 REG_UPDATE(CURSOR0_CONTROL, 347 CUR0_ENABLE, 0); 348 } 349 } 350 351 #define IDENTITY_RATIO(ratio) (dc_fixpt_u3d19(ratio) == (1 << 19)) 352 353 void dpp3_set_cursor_attributes( 354 struct dpp *dpp_base, 355 struct dc_cursor_attributes *cursor_attributes) 356 { 357 enum dc_cursor_color_format color_format = cursor_attributes->color_format; 358 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 359 int cur_rom_en = 0; 360 361 if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA || 362 color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) 363 cur_rom_en = 1; 364 365 REG_UPDATE_3(CURSOR0_CONTROL, 366 CUR0_MODE, color_format, 367 CUR0_EXPANSION_MODE, 0, 368 CUR0_ROM_EN, cur_rom_en); 369 370 if (color_format == CURSOR_MODE_MONO) { 371 /* todo: clarify what to program these to */ 372 REG_UPDATE(CURSOR0_COLOR0, 373 CUR0_COLOR0, 0x00000000); 374 REG_UPDATE(CURSOR0_COLOR1, 375 CUR0_COLOR1, 0xFFFFFFFF); 376 } 377 } 378 379 380 bool dpp3_get_optimal_number_of_taps( 381 struct dpp *dpp, 382 struct scaler_data *scl_data, 383 const struct scaling_taps *in_taps) 384 { 385 int num_part_y, num_part_c; 386 int max_taps_y, max_taps_c; 387 int min_taps_y, min_taps_c; 388 enum lb_memory_config lb_config; 389 390 if (scl_data->viewport.width > scl_data->h_active && 391 dpp->ctx->dc->debug.max_downscale_src_width != 0 && 392 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) 393 return false; 394 395 /* 396 * Set default taps if none are provided 397 * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling 398 * taps = 4 for upscaling 399 */ 400 if (in_taps->h_taps == 0) { 401 if (dc_fixpt_ceil(scl_data->ratios.horz) > 1) 402 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8); 403 else 404 scl_data->taps.h_taps = 4; 405 } else 406 scl_data->taps.h_taps = in_taps->h_taps; 407 if (in_taps->v_taps == 0) { 408 if (dc_fixpt_ceil(scl_data->ratios.vert) > 1) 409 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8); 410 else 411 scl_data->taps.v_taps = 4; 412 } else 413 scl_data->taps.v_taps = in_taps->v_taps; 414 if (in_taps->v_taps_c == 0) { 415 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 1) 416 scl_data->taps.v_taps_c = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert_c, 2)), 8); 417 else 418 scl_data->taps.v_taps_c = 4; 419 } else 420 scl_data->taps.v_taps_c = in_taps->v_taps_c; 421 if (in_taps->h_taps_c == 0) { 422 if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 1) 423 scl_data->taps.h_taps_c = min(2 * dc_fixpt_ceil(scl_data->ratios.horz_c), 8); 424 else 425 scl_data->taps.h_taps_c = 4; 426 } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1) 427 /* Only 1 and even h_taps_c are supported by hw */ 428 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1; 429 else 430 scl_data->taps.h_taps_c = in_taps->h_taps_c; 431 432 /*Ensure we can support the requested number of vtaps*/ 433 min_taps_y = dc_fixpt_ceil(scl_data->ratios.vert); 434 min_taps_c = dc_fixpt_ceil(scl_data->ratios.vert_c); 435 436 /* Use LB_MEMORY_CONFIG_3 for 4:2:0 */ 437 if ((scl_data->format == PIXEL_FORMAT_420BPP8) || (scl_data->format == PIXEL_FORMAT_420BPP10)) 438 lb_config = LB_MEMORY_CONFIG_3; 439 else 440 lb_config = LB_MEMORY_CONFIG_0; 441 442 dpp->caps->dscl_calc_lb_num_partitions( 443 scl_data, lb_config, &num_part_y, &num_part_c); 444 445 /* MAX_V_TAPS = MIN (NUM_LINES - MAX(CEILING(V_RATIO,1)-2, 0), 8) */ 446 if (dc_fixpt_ceil(scl_data->ratios.vert) > 2) 447 max_taps_y = num_part_y - (dc_fixpt_ceil(scl_data->ratios.vert) - 2); 448 else 449 max_taps_y = num_part_y; 450 451 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 2) 452 max_taps_c = num_part_c - (dc_fixpt_ceil(scl_data->ratios.vert_c) - 2); 453 else 454 max_taps_c = num_part_c; 455 456 if (max_taps_y < min_taps_y) 457 return false; 458 else if (max_taps_c < min_taps_c) 459 return false; 460 461 if (scl_data->taps.v_taps > max_taps_y) 462 scl_data->taps.v_taps = max_taps_y; 463 464 if (scl_data->taps.v_taps_c > max_taps_c) 465 scl_data->taps.v_taps_c = max_taps_c; 466 467 if (!dpp->ctx->dc->debug.always_scale) { 468 if (IDENTITY_RATIO(scl_data->ratios.horz)) 469 scl_data->taps.h_taps = 1; 470 if (IDENTITY_RATIO(scl_data->ratios.vert)) 471 scl_data->taps.v_taps = 1; 472 if (IDENTITY_RATIO(scl_data->ratios.horz_c)) 473 scl_data->taps.h_taps_c = 1; 474 if (IDENTITY_RATIO(scl_data->ratios.vert_c)) 475 scl_data->taps.v_taps_c = 1; 476 } 477 478 return true; 479 } 480 481 static void dpp3_deferred_update(struct dpp *dpp_base) 482 { 483 int bypass_state; 484 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 485 486 if (dpp_base->deferred_reg_writes.bits.disable_dscl) { 487 REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 3); 488 dpp_base->deferred_reg_writes.bits.disable_dscl = false; 489 } 490 491 if (dpp_base->deferred_reg_writes.bits.disable_gamcor) { 492 REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, &bypass_state); 493 if (bypass_state == 0) { // only program if bypass was latched 494 REG_UPDATE(CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, 3); 495 } else 496 ASSERT(0); // LUT select was updated again before vupdate 497 dpp_base->deferred_reg_writes.bits.disable_gamcor = false; 498 } 499 500 if (dpp_base->deferred_reg_writes.bits.disable_blnd_lut) { 501 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &bypass_state); 502 if (bypass_state == 0) { // only program if bypass was latched 503 REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 3); 504 } else 505 ASSERT(0); // LUT select was updated again before vupdate 506 dpp_base->deferred_reg_writes.bits.disable_blnd_lut = false; 507 } 508 509 if (dpp_base->deferred_reg_writes.bits.disable_3dlut) { 510 REG_GET(CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, &bypass_state); 511 if (bypass_state == 0) { // only program if bypass was latched 512 REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 3); 513 } else 514 ASSERT(0); // LUT select was updated again before vupdate 515 dpp_base->deferred_reg_writes.bits.disable_3dlut = false; 516 } 517 518 if (dpp_base->deferred_reg_writes.bits.disable_shaper) { 519 REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &bypass_state); 520 if (bypass_state == 0) { // only program if bypass was latched 521 REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 3); 522 } else 523 ASSERT(0); // LUT select was updated again before vupdate 524 dpp_base->deferred_reg_writes.bits.disable_shaper = false; 525 } 526 } 527 528 static void dpp3_power_on_blnd_lut( 529 struct dpp *dpp_base, 530 bool power_on) 531 { 532 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 533 534 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) { 535 if (power_on) { 536 REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 0); 537 REG_WAIT(CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, 0, 1, 5); 538 } else { 539 dpp_base->ctx->dc->optimized_required = true; 540 dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true; 541 } 542 } else { 543 REG_SET(CM_MEM_PWR_CTRL, 0, 544 BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0 : 1); 545 } 546 } 547 548 static void dpp3_power_on_hdr3dlut( 549 struct dpp *dpp_base, 550 bool power_on) 551 { 552 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 553 554 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) { 555 if (power_on) { 556 REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 0); 557 REG_WAIT(CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, 0, 1, 5); 558 } else { 559 dpp_base->ctx->dc->optimized_required = true; 560 dpp_base->deferred_reg_writes.bits.disable_3dlut = true; 561 } 562 } 563 } 564 565 static void dpp3_power_on_shaper( 566 struct dpp *dpp_base, 567 bool power_on) 568 { 569 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 570 571 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) { 572 if (power_on) { 573 REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 0); 574 REG_WAIT(CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, 0, 1, 5); 575 } else { 576 dpp_base->ctx->dc->optimized_required = true; 577 dpp_base->deferred_reg_writes.bits.disable_shaper = true; 578 } 579 } 580 } 581 582 static void dpp3_configure_blnd_lut( 583 struct dpp *dpp_base, 584 bool is_ram_a) 585 { 586 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 587 588 REG_UPDATE_2(CM_BLNDGAM_LUT_CONTROL, 589 CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 7, 590 CM_BLNDGAM_LUT_HOST_SEL, is_ram_a == true ? 0 : 1); 591 592 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0); 593 } 594 595 static void dpp3_program_blnd_pwl( 596 struct dpp *dpp_base, 597 const struct pwl_result_data *rgb, 598 uint32_t num) 599 { 600 uint32_t i; 601 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 602 uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg; 603 uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg; 604 uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg; 605 606 if (is_rgb_equal(rgb, num)) { 607 for (i = 0 ; i < num; i++) 608 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg); 609 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red); 610 } else { 611 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 4); 612 for (i = 0 ; i < num; i++) 613 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg); 614 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red); 615 616 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 2); 617 for (i = 0 ; i < num; i++) 618 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg); 619 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_green); 620 621 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 1); 622 for (i = 0 ; i < num; i++) 623 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg); 624 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_blue); 625 } 626 } 627 628 static void dcn3_dpp_cm_get_reg_field( 629 struct dcn3_dpp *dpp, 630 struct dcn3_xfer_func_reg *reg) 631 { 632 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; 633 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; 634 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; 635 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; 636 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; 637 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; 638 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; 639 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; 640 641 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; 642 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; 643 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; 644 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; 645 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; 646 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; 647 reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B; 648 reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B; 649 reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B; 650 reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B; 651 reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; 652 reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; 653 } 654 655 /*program blnd lut RAM A*/ 656 static void dpp3_program_blnd_luta_settings( 657 struct dpp *dpp_base, 658 const struct pwl_params *params) 659 { 660 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 661 struct dcn3_xfer_func_reg gam_regs; 662 663 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs); 664 665 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B); 666 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G); 667 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R); 668 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B); 669 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G); 670 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R); 671 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B); 672 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B); 673 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G); 674 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G); 675 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R); 676 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R); 677 gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1); 678 gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33); 679 680 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs); 681 } 682 683 /*program blnd lut RAM B*/ 684 static void dpp3_program_blnd_lutb_settings( 685 struct dpp *dpp_base, 686 const struct pwl_params *params) 687 { 688 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 689 struct dcn3_xfer_func_reg gam_regs; 690 691 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs); 692 693 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B); 694 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G); 695 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R); 696 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B); 697 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G); 698 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R); 699 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B); 700 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B); 701 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G); 702 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G); 703 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R); 704 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R); 705 gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1); 706 gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33); 707 708 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs); 709 } 710 711 static enum dc_lut_mode dpp3_get_blndgam_current(struct dpp *dpp_base) 712 { 713 enum dc_lut_mode mode; 714 uint32_t mode_current = 0; 715 uint32_t in_use = 0; 716 717 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 718 719 REG_GET(CM_BLNDGAM_CONTROL, 720 CM_BLNDGAM_MODE_CURRENT, &mode_current); 721 REG_GET(CM_BLNDGAM_CONTROL, 722 CM_BLNDGAM_SELECT_CURRENT, &in_use); 723 724 switch (mode_current) { 725 case 0: 726 case 1: 727 mode = LUT_BYPASS; 728 break; 729 730 case 2: 731 if (in_use == 0) 732 mode = LUT_RAM_A; 733 else 734 mode = LUT_RAM_B; 735 break; 736 default: 737 mode = LUT_BYPASS; 738 break; 739 } 740 return mode; 741 } 742 743 static bool dpp3_program_blnd_lut(struct dpp *dpp_base, 744 const struct pwl_params *params) 745 { 746 enum dc_lut_mode current_mode; 747 enum dc_lut_mode next_mode; 748 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 749 750 if (params == NULL) { 751 REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_MODE, 0); 752 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) 753 dpp3_power_on_blnd_lut(dpp_base, false); 754 return false; 755 } 756 757 current_mode = dpp3_get_blndgam_current(dpp_base); 758 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_B) 759 next_mode = LUT_RAM_A; 760 else 761 next_mode = LUT_RAM_B; 762 763 dpp3_power_on_blnd_lut(dpp_base, true); 764 dpp3_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A); 765 766 if (next_mode == LUT_RAM_A) 767 dpp3_program_blnd_luta_settings(dpp_base, params); 768 else 769 dpp3_program_blnd_lutb_settings(dpp_base, params); 770 771 dpp3_program_blnd_pwl( 772 dpp_base, params->rgb_resulted, params->hw_points_num); 773 774 REG_UPDATE_2(CM_BLNDGAM_CONTROL, 775 CM_BLNDGAM_MODE, 2, 776 CM_BLNDGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1); 777 778 return true; 779 } 780 781 782 static void dpp3_program_shaper_lut( 783 struct dpp *dpp_base, 784 const struct pwl_result_data *rgb, 785 uint32_t num) 786 { 787 uint32_t i, red, green, blue; 788 uint32_t red_delta, green_delta, blue_delta; 789 uint32_t red_value, green_value, blue_value; 790 791 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 792 793 for (i = 0 ; i < num; i++) { 794 795 red = rgb[i].red_reg; 796 green = rgb[i].green_reg; 797 blue = rgb[i].blue_reg; 798 799 red_delta = rgb[i].delta_red_reg; 800 green_delta = rgb[i].delta_green_reg; 801 blue_delta = rgb[i].delta_blue_reg; 802 803 red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff); 804 green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff); 805 blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff); 806 807 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, red_value); 808 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, green_value); 809 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, blue_value); 810 } 811 812 } 813 814 static enum dc_lut_mode dpp3_get_shaper_current(struct dpp *dpp_base) 815 { 816 enum dc_lut_mode mode; 817 uint32_t state_mode; 818 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 819 820 REG_GET(CM_SHAPER_CONTROL, 821 CM_SHAPER_MODE_CURRENT, &state_mode); 822 823 switch (state_mode) { 824 case 0: 825 mode = LUT_BYPASS; 826 break; 827 case 1: 828 mode = LUT_RAM_A; 829 break; 830 case 2: 831 mode = LUT_RAM_B; 832 break; 833 default: 834 mode = LUT_BYPASS; 835 break; 836 } 837 return mode; 838 } 839 840 static void dpp3_configure_shaper_lut( 841 struct dpp *dpp_base, 842 bool is_ram_a) 843 { 844 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 845 846 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK, 847 CM_SHAPER_LUT_WRITE_EN_MASK, 7); 848 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK, 849 CM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1); 850 REG_SET(CM_SHAPER_LUT_INDEX, 0, CM_SHAPER_LUT_INDEX, 0); 851 } 852 853 /*program shaper RAM A*/ 854 855 static void dpp3_program_shaper_luta_settings( 856 struct dpp *dpp_base, 857 const struct pwl_params *params) 858 { 859 const struct gamma_curve *curve; 860 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 861 862 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0, 863 CM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, 864 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); 865 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0, 866 CM_SHAPER_RAMA_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x, 867 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, 0); 868 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0, 869 CM_SHAPER_RAMA_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x, 870 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, 0); 871 872 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0, 873 CM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, 874 CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); 875 876 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0, 877 CM_SHAPER_RAMA_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x, 878 CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y); 879 880 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0, 881 CM_SHAPER_RAMA_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x, 882 CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y); 883 884 curve = params->arr_curve_points; 885 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0, 886 CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 887 CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 888 CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 889 CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 890 891 curve += 2; 892 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0, 893 CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset, 894 CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, 895 CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset, 896 CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); 897 898 curve += 2; 899 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0, 900 CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset, 901 CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, 902 CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset, 903 CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); 904 905 curve += 2; 906 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0, 907 CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset, 908 CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, 909 CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset, 910 CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); 911 912 curve += 2; 913 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0, 914 CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset, 915 CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, 916 CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset, 917 CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); 918 919 curve += 2; 920 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0, 921 CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset, 922 CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, 923 CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset, 924 CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); 925 926 curve += 2; 927 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0, 928 CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset, 929 CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, 930 CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset, 931 CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); 932 933 curve += 2; 934 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0, 935 CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset, 936 CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, 937 CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset, 938 CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); 939 940 curve += 2; 941 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0, 942 CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset, 943 CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num, 944 CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset, 945 CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num); 946 947 curve += 2; 948 REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0, 949 CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset, 950 CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num, 951 CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset, 952 CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num); 953 954 curve += 2; 955 REG_SET_4(CM_SHAPER_RAMA_REGION_20_21, 0, 956 CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset, 957 CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num, 958 CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset, 959 CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num); 960 961 curve += 2; 962 REG_SET_4(CM_SHAPER_RAMA_REGION_22_23, 0, 963 CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset, 964 CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num, 965 CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset, 966 CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num); 967 968 curve += 2; 969 REG_SET_4(CM_SHAPER_RAMA_REGION_24_25, 0, 970 CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset, 971 CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num, 972 CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset, 973 CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num); 974 975 curve += 2; 976 REG_SET_4(CM_SHAPER_RAMA_REGION_26_27, 0, 977 CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset, 978 CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num, 979 CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset, 980 CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num); 981 982 curve += 2; 983 REG_SET_4(CM_SHAPER_RAMA_REGION_28_29, 0, 984 CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset, 985 CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num, 986 CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset, 987 CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num); 988 989 curve += 2; 990 REG_SET_4(CM_SHAPER_RAMA_REGION_30_31, 0, 991 CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset, 992 CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num, 993 CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset, 994 CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num); 995 996 curve += 2; 997 REG_SET_4(CM_SHAPER_RAMA_REGION_32_33, 0, 998 CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset, 999 CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num, 1000 CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset, 1001 CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num); 1002 } 1003 1004 /*program shaper RAM B*/ 1005 static void dpp3_program_shaper_lutb_settings( 1006 struct dpp *dpp_base, 1007 const struct pwl_params *params) 1008 { 1009 const struct gamma_curve *curve; 1010 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1011 1012 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0, 1013 CM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, 1014 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0); 1015 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0, 1016 CM_SHAPER_RAMB_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x, 1017 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, 0); 1018 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0, 1019 CM_SHAPER_RAMB_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x, 1020 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, 0); 1021 1022 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0, 1023 CM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, 1024 CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); 1025 1026 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_G, 0, 1027 CM_SHAPER_RAMB_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x, 1028 CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y); 1029 1030 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_R, 0, 1031 CM_SHAPER_RAMB_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x, 1032 CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y); 1033 1034 curve = params->arr_curve_points; 1035 REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0, 1036 CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 1037 CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 1038 CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 1039 CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 1040 1041 curve += 2; 1042 REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0, 1043 CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset, 1044 CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, 1045 CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset, 1046 CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); 1047 1048 curve += 2; 1049 REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0, 1050 CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset, 1051 CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, 1052 CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset, 1053 CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); 1054 1055 curve += 2; 1056 REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0, 1057 CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset, 1058 CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, 1059 CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset, 1060 CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); 1061 1062 curve += 2; 1063 REG_SET_4(CM_SHAPER_RAMB_REGION_8_9, 0, 1064 CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset, 1065 CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, 1066 CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset, 1067 CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); 1068 1069 curve += 2; 1070 REG_SET_4(CM_SHAPER_RAMB_REGION_10_11, 0, 1071 CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset, 1072 CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, 1073 CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset, 1074 CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); 1075 1076 curve += 2; 1077 REG_SET_4(CM_SHAPER_RAMB_REGION_12_13, 0, 1078 CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset, 1079 CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, 1080 CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset, 1081 CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); 1082 1083 curve += 2; 1084 REG_SET_4(CM_SHAPER_RAMB_REGION_14_15, 0, 1085 CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset, 1086 CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, 1087 CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset, 1088 CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); 1089 1090 curve += 2; 1091 REG_SET_4(CM_SHAPER_RAMB_REGION_16_17, 0, 1092 CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset, 1093 CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num, 1094 CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset, 1095 CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num); 1096 1097 curve += 2; 1098 REG_SET_4(CM_SHAPER_RAMB_REGION_18_19, 0, 1099 CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset, 1100 CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num, 1101 CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset, 1102 CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num); 1103 1104 curve += 2; 1105 REG_SET_4(CM_SHAPER_RAMB_REGION_20_21, 0, 1106 CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset, 1107 CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num, 1108 CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset, 1109 CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num); 1110 1111 curve += 2; 1112 REG_SET_4(CM_SHAPER_RAMB_REGION_22_23, 0, 1113 CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset, 1114 CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num, 1115 CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset, 1116 CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num); 1117 1118 curve += 2; 1119 REG_SET_4(CM_SHAPER_RAMB_REGION_24_25, 0, 1120 CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset, 1121 CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num, 1122 CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset, 1123 CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num); 1124 1125 curve += 2; 1126 REG_SET_4(CM_SHAPER_RAMB_REGION_26_27, 0, 1127 CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset, 1128 CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num, 1129 CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset, 1130 CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num); 1131 1132 curve += 2; 1133 REG_SET_4(CM_SHAPER_RAMB_REGION_28_29, 0, 1134 CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset, 1135 CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num, 1136 CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset, 1137 CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num); 1138 1139 curve += 2; 1140 REG_SET_4(CM_SHAPER_RAMB_REGION_30_31, 0, 1141 CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset, 1142 CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num, 1143 CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset, 1144 CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num); 1145 1146 curve += 2; 1147 REG_SET_4(CM_SHAPER_RAMB_REGION_32_33, 0, 1148 CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset, 1149 CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num, 1150 CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset, 1151 CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num); 1152 1153 } 1154 1155 1156 static bool dpp3_program_shaper(struct dpp *dpp_base, 1157 const struct pwl_params *params) 1158 { 1159 enum dc_lut_mode current_mode; 1160 enum dc_lut_mode next_mode; 1161 1162 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1163 1164 if (params == NULL) { 1165 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0); 1166 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) 1167 dpp3_power_on_shaper(dpp_base, false); 1168 return false; 1169 } 1170 1171 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) 1172 dpp3_power_on_shaper(dpp_base, true); 1173 1174 current_mode = dpp3_get_shaper_current(dpp_base); 1175 1176 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A) 1177 next_mode = LUT_RAM_B; 1178 else 1179 next_mode = LUT_RAM_A; 1180 1181 dpp3_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A); 1182 1183 if (next_mode == LUT_RAM_A) 1184 dpp3_program_shaper_luta_settings(dpp_base, params); 1185 else 1186 dpp3_program_shaper_lutb_settings(dpp_base, params); 1187 1188 dpp3_program_shaper_lut( 1189 dpp_base, params->rgb_resulted, params->hw_points_num); 1190 1191 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2); 1192 1193 return true; 1194 1195 } 1196 1197 static enum dc_lut_mode get3dlut_config( 1198 struct dpp *dpp_base, 1199 bool *is_17x17x17, 1200 bool *is_12bits_color_channel) 1201 { 1202 uint32_t i_mode, i_enable_10bits, lut_size; 1203 enum dc_lut_mode mode; 1204 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1205 1206 REG_GET(CM_3DLUT_READ_WRITE_CONTROL, 1207 CM_3DLUT_30BIT_EN, &i_enable_10bits); 1208 REG_GET(CM_3DLUT_MODE, 1209 CM_3DLUT_MODE_CURRENT, &i_mode); 1210 1211 switch (i_mode) { 1212 case 0: 1213 mode = LUT_BYPASS; 1214 break; 1215 case 1: 1216 mode = LUT_RAM_A; 1217 break; 1218 case 2: 1219 mode = LUT_RAM_B; 1220 break; 1221 default: 1222 mode = LUT_BYPASS; 1223 break; 1224 } 1225 if (i_enable_10bits > 0) 1226 *is_12bits_color_channel = false; 1227 else 1228 *is_12bits_color_channel = true; 1229 1230 REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &lut_size); 1231 1232 if (lut_size == 0) 1233 *is_17x17x17 = true; 1234 else 1235 *is_17x17x17 = false; 1236 1237 return mode; 1238 } 1239 /* 1240 * select ramA or ramB, or bypass 1241 * select color channel size 10 or 12 bits 1242 * select 3dlut size 17x17x17 or 9x9x9 1243 */ 1244 static void dpp3_set_3dlut_mode( 1245 struct dpp *dpp_base, 1246 enum dc_lut_mode mode, 1247 bool is_color_channel_12bits, 1248 bool is_lut_size17x17x17) 1249 { 1250 uint32_t lut_mode; 1251 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1252 1253 if (mode == LUT_BYPASS) 1254 lut_mode = 0; 1255 else if (mode == LUT_RAM_A) 1256 lut_mode = 1; 1257 else 1258 lut_mode = 2; 1259 1260 REG_UPDATE_2(CM_3DLUT_MODE, 1261 CM_3DLUT_MODE, lut_mode, 1262 CM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1); 1263 } 1264 1265 static void dpp3_select_3dlut_ram( 1266 struct dpp *dpp_base, 1267 enum dc_lut_mode mode, 1268 bool is_color_channel_12bits) 1269 { 1270 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1271 1272 REG_UPDATE_2(CM_3DLUT_READ_WRITE_CONTROL, 1273 CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1, 1274 CM_3DLUT_30BIT_EN, 1275 is_color_channel_12bits == true ? 0:1); 1276 } 1277 1278 1279 1280 static void dpp3_set3dlut_ram12( 1281 struct dpp *dpp_base, 1282 const struct dc_rgb *lut, 1283 uint32_t entries) 1284 { 1285 uint32_t i, red, green, blue, red1, green1, blue1; 1286 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1287 1288 for (i = 0 ; i < entries; i += 2) { 1289 red = lut[i].red<<4; 1290 green = lut[i].green<<4; 1291 blue = lut[i].blue<<4; 1292 red1 = lut[i+1].red<<4; 1293 green1 = lut[i+1].green<<4; 1294 blue1 = lut[i+1].blue<<4; 1295 1296 REG_SET_2(CM_3DLUT_DATA, 0, 1297 CM_3DLUT_DATA0, red, 1298 CM_3DLUT_DATA1, red1); 1299 1300 REG_SET_2(CM_3DLUT_DATA, 0, 1301 CM_3DLUT_DATA0, green, 1302 CM_3DLUT_DATA1, green1); 1303 1304 REG_SET_2(CM_3DLUT_DATA, 0, 1305 CM_3DLUT_DATA0, blue, 1306 CM_3DLUT_DATA1, blue1); 1307 1308 } 1309 } 1310 1311 /* 1312 * load selected lut with 10 bits color channels 1313 */ 1314 static void dpp3_set3dlut_ram10( 1315 struct dpp *dpp_base, 1316 const struct dc_rgb *lut, 1317 uint32_t entries) 1318 { 1319 uint32_t i, red, green, blue, value; 1320 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1321 1322 for (i = 0; i < entries; i++) { 1323 red = lut[i].red; 1324 green = lut[i].green; 1325 blue = lut[i].blue; 1326 1327 value = (red<<20) | (green<<10) | blue; 1328 1329 REG_SET(CM_3DLUT_DATA_30BIT, 0, CM_3DLUT_DATA_30BIT, value); 1330 } 1331 1332 } 1333 1334 1335 static void dpp3_select_3dlut_ram_mask( 1336 struct dpp *dpp_base, 1337 uint32_t ram_selection_mask) 1338 { 1339 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1340 1341 REG_UPDATE(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK, 1342 ram_selection_mask); 1343 REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0); 1344 } 1345 1346 static bool dpp3_program_3dlut(struct dpp *dpp_base, 1347 struct tetrahedral_params *params) 1348 { 1349 enum dc_lut_mode mode; 1350 bool is_17x17x17; 1351 bool is_12bits_color_channel; 1352 struct dc_rgb *lut0; 1353 struct dc_rgb *lut1; 1354 struct dc_rgb *lut2; 1355 struct dc_rgb *lut3; 1356 int lut_size0; 1357 int lut_size; 1358 1359 if (params == NULL) { 1360 dpp3_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false); 1361 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) 1362 dpp3_power_on_hdr3dlut(dpp_base, false); 1363 return false; 1364 } 1365 1366 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) 1367 dpp3_power_on_hdr3dlut(dpp_base, true); 1368 1369 mode = get3dlut_config(dpp_base, &is_17x17x17, &is_12bits_color_channel); 1370 1371 if (mode == LUT_BYPASS || mode == LUT_RAM_B) 1372 mode = LUT_RAM_A; 1373 else 1374 mode = LUT_RAM_B; 1375 1376 is_17x17x17 = !params->use_tetrahedral_9; 1377 is_12bits_color_channel = params->use_12bits; 1378 if (is_17x17x17) { 1379 lut0 = params->tetrahedral_17.lut0; 1380 lut1 = params->tetrahedral_17.lut1; 1381 lut2 = params->tetrahedral_17.lut2; 1382 lut3 = params->tetrahedral_17.lut3; 1383 lut_size0 = sizeof(params->tetrahedral_17.lut0)/ 1384 sizeof(params->tetrahedral_17.lut0[0]); 1385 lut_size = sizeof(params->tetrahedral_17.lut1)/ 1386 sizeof(params->tetrahedral_17.lut1[0]); 1387 } else { 1388 lut0 = params->tetrahedral_9.lut0; 1389 lut1 = params->tetrahedral_9.lut1; 1390 lut2 = params->tetrahedral_9.lut2; 1391 lut3 = params->tetrahedral_9.lut3; 1392 lut_size0 = sizeof(params->tetrahedral_9.lut0)/ 1393 sizeof(params->tetrahedral_9.lut0[0]); 1394 lut_size = sizeof(params->tetrahedral_9.lut1)/ 1395 sizeof(params->tetrahedral_9.lut1[0]); 1396 } 1397 1398 dpp3_select_3dlut_ram(dpp_base, mode, 1399 is_12bits_color_channel); 1400 dpp3_select_3dlut_ram_mask(dpp_base, 0x1); 1401 if (is_12bits_color_channel) 1402 dpp3_set3dlut_ram12(dpp_base, lut0, lut_size0); 1403 else 1404 dpp3_set3dlut_ram10(dpp_base, lut0, lut_size0); 1405 1406 dpp3_select_3dlut_ram_mask(dpp_base, 0x2); 1407 if (is_12bits_color_channel) 1408 dpp3_set3dlut_ram12(dpp_base, lut1, lut_size); 1409 else 1410 dpp3_set3dlut_ram10(dpp_base, lut1, lut_size); 1411 1412 dpp3_select_3dlut_ram_mask(dpp_base, 0x4); 1413 if (is_12bits_color_channel) 1414 dpp3_set3dlut_ram12(dpp_base, lut2, lut_size); 1415 else 1416 dpp3_set3dlut_ram10(dpp_base, lut2, lut_size); 1417 1418 dpp3_select_3dlut_ram_mask(dpp_base, 0x8); 1419 if (is_12bits_color_channel) 1420 dpp3_set3dlut_ram12(dpp_base, lut3, lut_size); 1421 else 1422 dpp3_set3dlut_ram10(dpp_base, lut3, lut_size); 1423 1424 1425 dpp3_set_3dlut_mode(dpp_base, mode, is_12bits_color_channel, 1426 is_17x17x17); 1427 1428 return true; 1429 } 1430 static struct dpp_funcs dcn30_dpp_funcs = { 1431 .dpp_program_gamcor_lut = dpp3_program_gamcor_lut, 1432 .dpp_read_state = dpp30_read_state, 1433 .dpp_reset = dpp_reset, 1434 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale, 1435 .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps, 1436 .dpp_set_gamut_remap = dpp3_cm_set_gamut_remap, 1437 .dpp_set_csc_adjustment = NULL, 1438 .dpp_set_csc_default = NULL, 1439 .dpp_program_regamma_pwl = NULL, 1440 .dpp_set_pre_degam = dpp3_set_pre_degam, 1441 .dpp_program_input_lut = NULL, 1442 .dpp_full_bypass = dpp1_full_bypass, 1443 .dpp_setup = dpp3_cnv_setup, 1444 .dpp_program_degamma_pwl = NULL, 1445 .dpp_program_cm_dealpha = dpp3_program_cm_dealpha, 1446 .dpp_program_cm_bias = dpp3_program_cm_bias, 1447 .dpp_program_blnd_lut = dpp3_program_blnd_lut, 1448 .dpp_program_shaper_lut = dpp3_program_shaper, 1449 .dpp_program_3dlut = dpp3_program_3dlut, 1450 .dpp_deferred_update = dpp3_deferred_update, 1451 .dpp_program_bias_and_scale = NULL, 1452 .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer, 1453 .set_cursor_attributes = dpp3_set_cursor_attributes, 1454 .set_cursor_position = dpp1_set_cursor_position, 1455 .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes, 1456 .dpp_dppclk_control = dpp1_dppclk_control, 1457 .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier, 1458 }; 1459 1460 1461 static struct dpp_caps dcn30_dpp_cap = { 1462 .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT, 1463 .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions, 1464 }; 1465 1466 bool dpp3_construct( 1467 struct dcn3_dpp *dpp, 1468 struct dc_context *ctx, 1469 uint32_t inst, 1470 const struct dcn3_dpp_registers *tf_regs, 1471 const struct dcn3_dpp_shift *tf_shift, 1472 const struct dcn3_dpp_mask *tf_mask) 1473 { 1474 dpp->base.ctx = ctx; 1475 1476 dpp->base.inst = inst; 1477 dpp->base.funcs = &dcn30_dpp_funcs; 1478 dpp->base.caps = &dcn30_dpp_cap; 1479 1480 dpp->tf_regs = tf_regs; 1481 dpp->tf_shift = tf_shift; 1482 dpp->tf_mask = tf_mask; 1483 1484 return true; 1485 } 1486 1487