1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "core_types.h" 28 #include "reg_helper.h" 29 #include "dcn30_dpp.h" 30 #include "basics/conversion.h" 31 #include "dcn30_cm_common.h" 32 33 #define REG(reg)\ 34 dpp->tf_regs->reg 35 36 #define CTX \ 37 dpp->base.ctx 38 39 #undef FN 40 #define FN(reg_name, field_name) \ 41 dpp->tf_shift->field_name, dpp->tf_mask->field_name 42 43 44 void dpp30_read_state(struct dpp *dpp_base, 45 struct dcn_dpp_state *s) 46 { 47 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); 48 49 REG_GET(DPP_CONTROL, 50 DPP_CLOCK_ENABLE, &s->is_enabled); 51 52 // TODO: Implement for DCN3 53 } 54 /*program post scaler scs block in dpp CM*/ 55 void dpp3_program_post_csc( 56 struct dpp *dpp_base, 57 enum dc_color_space color_space, 58 enum dcn10_input_csc_select input_select, 59 const struct out_csc_color_matrix *tbl_entry) 60 { 61 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 62 int i; 63 int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix); 64 const uint16_t *regval = NULL; 65 uint32_t cur_select = 0; 66 enum dcn10_input_csc_select select; 67 struct color_matrices_reg gam_regs; 68 69 if (input_select == INPUT_CSC_SELECT_BYPASS) { 70 REG_SET(CM_POST_CSC_CONTROL, 0, CM_POST_CSC_MODE, 0); 71 return; 72 } 73 74 if (tbl_entry == NULL) { 75 for (i = 0; i < arr_size; i++) 76 if (dpp_input_csc_matrix[i].color_space == color_space) { 77 regval = dpp_input_csc_matrix[i].regval; 78 break; 79 } 80 81 if (regval == NULL) { 82 BREAK_TO_DEBUGGER(); 83 return; 84 } 85 } else { 86 regval = tbl_entry->regval; 87 } 88 89 /* determine which CSC matrix (icsc or coma) we are using 90 * currently. select the alternate set to double buffer 91 * the CSC update so CSC is updated on frame boundary 92 */ 93 REG_GET(CM_POST_CSC_CONTROL, 94 CM_POST_CSC_MODE_CURRENT, &cur_select); 95 96 if (cur_select != INPUT_CSC_SELECT_ICSC) 97 select = INPUT_CSC_SELECT_ICSC; 98 else 99 select = INPUT_CSC_SELECT_COMA; 100 101 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11; 102 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11; 103 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12; 104 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12; 105 106 if (select == INPUT_CSC_SELECT_ICSC) { 107 108 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12); 109 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34); 110 111 } else { 112 113 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12); 114 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34); 115 116 } 117 118 cm_helper_program_color_matrices( 119 dpp->base.ctx, 120 regval, 121 &gam_regs); 122 123 REG_SET(CM_POST_CSC_CONTROL, 0, 124 CM_POST_CSC_MODE, select); 125 } 126 127 128 /*CNVC degam unit has read only LUTs*/ 129 void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr) 130 { 131 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 132 int pre_degam_en = 1; 133 int degamma_lut_selection = 0; 134 135 switch (tr) { 136 case TRANSFER_FUNCTION_LINEAR: 137 case TRANSFER_FUNCTION_UNITY: 138 pre_degam_en = 0; //bypass 139 break; 140 case TRANSFER_FUNCTION_SRGB: 141 degamma_lut_selection = 0; 142 break; 143 case TRANSFER_FUNCTION_BT709: 144 degamma_lut_selection = 4; 145 break; 146 case TRANSFER_FUNCTION_PQ: 147 degamma_lut_selection = 5; 148 break; 149 case TRANSFER_FUNCTION_HLG: 150 degamma_lut_selection = 6; 151 break; 152 case TRANSFER_FUNCTION_GAMMA22: 153 degamma_lut_selection = 1; 154 break; 155 case TRANSFER_FUNCTION_GAMMA24: 156 degamma_lut_selection = 2; 157 break; 158 case TRANSFER_FUNCTION_GAMMA26: 159 degamma_lut_selection = 3; 160 break; 161 default: 162 pre_degam_en = 0; 163 break; 164 } 165 166 REG_SET_2(PRE_DEGAM, 0, 167 PRE_DEGAM_MODE, pre_degam_en, 168 PRE_DEGAM_SELECT, degamma_lut_selection); 169 } 170 171 static void dpp3_cnv_setup ( 172 struct dpp *dpp_base, 173 enum surface_pixel_format format, 174 enum expansion_mode mode, 175 struct dc_csc_transform input_csc_color_matrix, 176 enum dc_color_space input_color_space, 177 struct cnv_alpha_2bit_lut *alpha_2bit_lut) 178 { 179 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 180 uint32_t pixel_format = 0; 181 uint32_t alpha_en = 1; 182 enum dc_color_space color_space = COLOR_SPACE_SRGB; 183 enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS; 184 bool force_disable_cursor = false; 185 uint32_t is_2bit = 0; 186 uint32_t alpha_plane_enable = 0; 187 uint32_t dealpha_en = 0, dealpha_ablnd_en = 0; 188 uint32_t realpha_en = 0, realpha_ablnd_en = 0; 189 uint32_t program_prealpha_dealpha = 0; 190 struct out_csc_color_matrix tbl_entry; 191 int i; 192 193 REG_SET_2(FORMAT_CONTROL, 0, 194 CNVC_BYPASS, 0, 195 FORMAT_EXPANSION_MODE, mode); 196 197 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); 198 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); 199 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); 200 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); 201 202 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0); 203 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1); 204 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2); 205 206 switch (format) { 207 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 208 pixel_format = 1; 209 break; 210 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 211 pixel_format = 3; 212 alpha_en = 0; 213 break; 214 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 215 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 216 pixel_format = 8; 217 break; 218 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 219 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 220 pixel_format = 10; 221 is_2bit = 1; 222 break; 223 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 224 force_disable_cursor = false; 225 pixel_format = 65; 226 color_space = COLOR_SPACE_YCBCR709; 227 select = INPUT_CSC_SELECT_ICSC; 228 break; 229 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 230 force_disable_cursor = true; 231 pixel_format = 64; 232 color_space = COLOR_SPACE_YCBCR709; 233 select = INPUT_CSC_SELECT_ICSC; 234 break; 235 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 236 force_disable_cursor = true; 237 pixel_format = 67; 238 color_space = COLOR_SPACE_YCBCR709; 239 select = INPUT_CSC_SELECT_ICSC; 240 break; 241 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 242 force_disable_cursor = true; 243 pixel_format = 66; 244 color_space = COLOR_SPACE_YCBCR709; 245 select = INPUT_CSC_SELECT_ICSC; 246 break; 247 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 248 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 249 pixel_format = 26; /* ARGB16161616_UNORM */ 250 break; 251 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 252 pixel_format = 24; 253 break; 254 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 255 pixel_format = 25; 256 break; 257 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 258 pixel_format = 12; 259 color_space = COLOR_SPACE_YCBCR709; 260 select = INPUT_CSC_SELECT_ICSC; 261 break; 262 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 263 pixel_format = 112; 264 break; 265 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 266 pixel_format = 113; 267 break; 268 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: 269 pixel_format = 114; 270 color_space = COLOR_SPACE_YCBCR709; 271 select = INPUT_CSC_SELECT_ICSC; 272 is_2bit = 1; 273 break; 274 case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: 275 pixel_format = 115; 276 color_space = COLOR_SPACE_YCBCR709; 277 select = INPUT_CSC_SELECT_ICSC; 278 is_2bit = 1; 279 break; 280 case SURFACE_PIXEL_FORMAT_GRPH_RGBE: 281 pixel_format = 116; 282 alpha_plane_enable = 0; 283 break; 284 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 285 pixel_format = 116; 286 alpha_plane_enable = 1; 287 break; 288 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 289 pixel_format = 118; 290 break; 291 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 292 pixel_format = 119; 293 break; 294 default: 295 break; 296 } 297 298 if (is_2bit == 1 && alpha_2bit_lut != NULL) { 299 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); 300 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); 301 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); 302 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3); 303 } 304 305 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0, 306 CNVC_SURFACE_PIXEL_FORMAT, pixel_format, 307 CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable); 308 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); 309 310 if (program_prealpha_dealpha) { 311 dealpha_en = 1; 312 realpha_en = 1; 313 } 314 REG_SET_2(PRE_DEALPHA, 0, 315 PRE_DEALPHA_EN, dealpha_en, 316 PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en); 317 REG_SET_2(PRE_REALPHA, 0, 318 PRE_REALPHA_EN, realpha_en, 319 PRE_REALPHA_ABLND_EN, realpha_ablnd_en); 320 321 /* If input adjustment exists, program the ICSC with those values. */ 322 if (input_csc_color_matrix.enable_adjustment == true) { 323 for (i = 0; i < 12; i++) 324 tbl_entry.regval[i] = input_csc_color_matrix.matrix[i]; 325 326 tbl_entry.color_space = input_color_space; 327 328 if (color_space >= COLOR_SPACE_YCBCR601) 329 select = INPUT_CSC_SELECT_ICSC; 330 else 331 select = INPUT_CSC_SELECT_BYPASS; 332 333 dpp3_program_post_csc(dpp_base, color_space, select, 334 &tbl_entry); 335 } else { 336 dpp3_program_post_csc(dpp_base, color_space, select, NULL); 337 } 338 339 if (force_disable_cursor) { 340 REG_UPDATE(CURSOR_CONTROL, 341 CURSOR_ENABLE, 0); 342 REG_UPDATE(CURSOR0_CONTROL, 343 CUR0_ENABLE, 0); 344 } 345 } 346 347 #define IDENTITY_RATIO(ratio) (dc_fixpt_u3d19(ratio) == (1 << 19)) 348 349 void dpp3_set_cursor_attributes( 350 struct dpp *dpp_base, 351 struct dc_cursor_attributes *cursor_attributes) 352 { 353 enum dc_cursor_color_format color_format = cursor_attributes->color_format; 354 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 355 int cur_rom_en = 0; 356 357 if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA || 358 color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) 359 cur_rom_en = 1; 360 361 REG_UPDATE_3(CURSOR0_CONTROL, 362 CUR0_MODE, color_format, 363 CUR0_EXPANSION_MODE, 0, 364 CUR0_ROM_EN, cur_rom_en); 365 366 if (color_format == CURSOR_MODE_MONO) { 367 /* todo: clarify what to program these to */ 368 REG_UPDATE(CURSOR0_COLOR0, 369 CUR0_COLOR0, 0x00000000); 370 REG_UPDATE(CURSOR0_COLOR1, 371 CUR0_COLOR1, 0xFFFFFFFF); 372 } 373 } 374 375 376 bool dpp3_get_optimal_number_of_taps( 377 struct dpp *dpp, 378 struct scaler_data *scl_data, 379 const struct scaling_taps *in_taps) 380 { 381 int num_part_y, num_part_c; 382 int max_taps_y, max_taps_c; 383 int min_taps_y, min_taps_c; 384 enum lb_memory_config lb_config; 385 386 if (scl_data->viewport.width > scl_data->h_active && 387 dpp->ctx->dc->debug.max_downscale_src_width != 0 && 388 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) 389 return false; 390 391 /* 392 * Set default taps if none are provided 393 * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling 394 * taps = 4 for upscaling 395 */ 396 if (in_taps->h_taps == 0) { 397 if (dc_fixpt_ceil(scl_data->ratios.horz) > 1) 398 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8); 399 else 400 scl_data->taps.h_taps = 4; 401 } else 402 scl_data->taps.h_taps = in_taps->h_taps; 403 if (in_taps->v_taps == 0) { 404 if (dc_fixpt_ceil(scl_data->ratios.vert) > 1) 405 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8); 406 else 407 scl_data->taps.v_taps = 4; 408 } else 409 scl_data->taps.v_taps = in_taps->v_taps; 410 if (in_taps->v_taps_c == 0) { 411 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 1) 412 scl_data->taps.v_taps_c = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert_c, 2)), 8); 413 else 414 scl_data->taps.v_taps_c = 4; 415 } else 416 scl_data->taps.v_taps_c = in_taps->v_taps_c; 417 if (in_taps->h_taps_c == 0) { 418 if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 1) 419 scl_data->taps.h_taps_c = min(2 * dc_fixpt_ceil(scl_data->ratios.horz_c), 8); 420 else 421 scl_data->taps.h_taps_c = 4; 422 } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1) 423 /* Only 1 and even h_taps_c are supported by hw */ 424 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1; 425 else 426 scl_data->taps.h_taps_c = in_taps->h_taps_c; 427 428 /*Ensure we can support the requested number of vtaps*/ 429 min_taps_y = dc_fixpt_ceil(scl_data->ratios.vert); 430 min_taps_c = dc_fixpt_ceil(scl_data->ratios.vert_c); 431 432 /* Use LB_MEMORY_CONFIG_3 for 4:2:0 */ 433 if ((scl_data->format == PIXEL_FORMAT_420BPP8) || (scl_data->format == PIXEL_FORMAT_420BPP10)) 434 lb_config = LB_MEMORY_CONFIG_3; 435 else 436 lb_config = LB_MEMORY_CONFIG_0; 437 438 dpp->caps->dscl_calc_lb_num_partitions( 439 scl_data, lb_config, &num_part_y, &num_part_c); 440 441 /* MAX_V_TAPS = MIN (NUM_LINES - MAX(CEILING(V_RATIO,1)-2, 0), 8) */ 442 if (dc_fixpt_ceil(scl_data->ratios.vert) > 2) 443 max_taps_y = num_part_y - (dc_fixpt_ceil(scl_data->ratios.vert) - 2); 444 else 445 max_taps_y = num_part_y; 446 447 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 2) 448 max_taps_c = num_part_c - (dc_fixpt_ceil(scl_data->ratios.vert_c) - 2); 449 else 450 max_taps_c = num_part_c; 451 452 if (max_taps_y < min_taps_y) 453 return false; 454 else if (max_taps_c < min_taps_c) 455 return false; 456 457 if (scl_data->taps.v_taps > max_taps_y) 458 scl_data->taps.v_taps = max_taps_y; 459 460 if (scl_data->taps.v_taps_c > max_taps_c) 461 scl_data->taps.v_taps_c = max_taps_c; 462 463 if (!dpp->ctx->dc->debug.always_scale) { 464 if (IDENTITY_RATIO(scl_data->ratios.horz)) 465 scl_data->taps.h_taps = 1; 466 if (IDENTITY_RATIO(scl_data->ratios.vert)) 467 scl_data->taps.v_taps = 1; 468 if (IDENTITY_RATIO(scl_data->ratios.horz_c)) 469 scl_data->taps.h_taps_c = 1; 470 if (IDENTITY_RATIO(scl_data->ratios.vert_c)) 471 scl_data->taps.v_taps_c = 1; 472 } 473 474 return true; 475 } 476 477 void dpp3_cnv_set_bias_scale( 478 struct dpp *dpp_base, 479 struct dc_bias_and_scale *bias_and_scale) 480 { 481 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 482 483 REG_UPDATE(FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, bias_and_scale->bias_red); 484 REG_UPDATE(FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, bias_and_scale->bias_green); 485 REG_UPDATE(FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, bias_and_scale->bias_blue); 486 REG_UPDATE(FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, bias_and_scale->scale_red); 487 REG_UPDATE(FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, bias_and_scale->scale_green); 488 REG_UPDATE(FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, bias_and_scale->scale_blue); 489 } 490 491 void dpp3_deferred_update( 492 struct dpp *dpp_base) 493 { 494 int bypass_state; 495 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 496 497 if (dpp_base->deferred_reg_writes.bits.disable_blnd_lut) { 498 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &bypass_state); 499 if (bypass_state == 0) { // only program if bypass was latched 500 REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 3); 501 } else 502 ASSERT(0); // LUT select was updated again before vupdate 503 dpp_base->deferred_reg_writes.bits.disable_blnd_lut = false; 504 } 505 506 if (dpp_base->deferred_reg_writes.bits.disable_3dlut) { 507 REG_GET(CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, &bypass_state); 508 if (bypass_state == 0) { // only program if bypass was latched 509 REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 3); 510 } else 511 ASSERT(0); // LUT select was updated again before vupdate 512 dpp_base->deferred_reg_writes.bits.disable_3dlut = false; 513 } 514 515 if (dpp_base->deferred_reg_writes.bits.disable_shaper) { 516 REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &bypass_state); 517 if (bypass_state == 0) { // only program if bypass was latched 518 REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 3); 519 } else 520 ASSERT(0); // LUT select was updated again before vupdate 521 dpp_base->deferred_reg_writes.bits.disable_shaper = false; 522 } 523 } 524 525 static void dpp3_power_on_blnd_lut( 526 struct dpp *dpp_base, 527 bool power_on) 528 { 529 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 530 531 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) { 532 if (power_on) { 533 REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 0); 534 REG_WAIT(CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, 0, 1, 5); 535 } else { 536 dpp_base->ctx->dc->optimized_required = true; 537 dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true; 538 } 539 } else { 540 REG_SET(CM_MEM_PWR_CTRL, 0, 541 BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0 : 1); 542 } 543 } 544 545 static void dpp3_power_on_hdr3dlut( 546 struct dpp *dpp_base, 547 bool power_on) 548 { 549 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 550 551 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) { 552 if (power_on) { 553 REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 0); 554 REG_WAIT(CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, 0, 1, 5); 555 } else { 556 dpp_base->ctx->dc->optimized_required = true; 557 dpp_base->deferred_reg_writes.bits.disable_3dlut = true; 558 } 559 } 560 } 561 562 static void dpp3_power_on_shaper( 563 struct dpp *dpp_base, 564 bool power_on) 565 { 566 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 567 568 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) { 569 if (power_on) { 570 REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 0); 571 REG_WAIT(CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, 0, 1, 5); 572 } else { 573 dpp_base->ctx->dc->optimized_required = true; 574 dpp_base->deferred_reg_writes.bits.disable_shaper = true; 575 } 576 } 577 } 578 579 static void dpp3_configure_blnd_lut( 580 struct dpp *dpp_base, 581 bool is_ram_a) 582 { 583 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 584 585 REG_UPDATE_2(CM_BLNDGAM_LUT_CONTROL, 586 CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 7, 587 CM_BLNDGAM_LUT_HOST_SEL, is_ram_a == true ? 0 : 1); 588 589 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0); 590 } 591 592 static void dpp3_program_blnd_pwl( 593 struct dpp *dpp_base, 594 const struct pwl_result_data *rgb, 595 uint32_t num) 596 { 597 uint32_t i; 598 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 599 uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg; 600 uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg; 601 uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg; 602 603 if (is_rgb_equal(rgb, num)) { 604 for (i = 0 ; i < num; i++) 605 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg); 606 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red); 607 } else { 608 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 4); 609 for (i = 0 ; i < num; i++) 610 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg); 611 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red); 612 613 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 2); 614 for (i = 0 ; i < num; i++) 615 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg); 616 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_green); 617 618 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 1); 619 for (i = 0 ; i < num; i++) 620 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg); 621 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_blue); 622 } 623 } 624 625 static void dcn3_dpp_cm_get_reg_field( 626 struct dcn3_dpp *dpp, 627 struct dcn3_xfer_func_reg *reg) 628 { 629 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; 630 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; 631 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; 632 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; 633 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; 634 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; 635 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; 636 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; 637 638 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; 639 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; 640 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; 641 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; 642 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; 643 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; 644 reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B; 645 reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B; 646 reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B; 647 reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B; 648 reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; 649 reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; 650 } 651 652 /*program blnd lut RAM A*/ 653 static void dpp3_program_blnd_luta_settings( 654 struct dpp *dpp_base, 655 const struct pwl_params *params) 656 { 657 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 658 struct dcn3_xfer_func_reg gam_regs; 659 660 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs); 661 662 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B); 663 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G); 664 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R); 665 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B); 666 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G); 667 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R); 668 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B); 669 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B); 670 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G); 671 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G); 672 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R); 673 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R); 674 gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1); 675 gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33); 676 677 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs); 678 } 679 680 /*program blnd lut RAM B*/ 681 static void dpp3_program_blnd_lutb_settings( 682 struct dpp *dpp_base, 683 const struct pwl_params *params) 684 { 685 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 686 struct dcn3_xfer_func_reg gam_regs; 687 688 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs); 689 690 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B); 691 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G); 692 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R); 693 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B); 694 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G); 695 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R); 696 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B); 697 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B); 698 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G); 699 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G); 700 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R); 701 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R); 702 gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1); 703 gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33); 704 705 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs); 706 } 707 708 static enum dc_lut_mode dpp3_get_blndgam_current(struct dpp *dpp_base) 709 { 710 enum dc_lut_mode mode; 711 uint32_t mode_current = 0; 712 uint32_t in_use = 0; 713 714 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 715 716 REG_GET(CM_BLNDGAM_CONTROL, 717 CM_BLNDGAM_MODE_CURRENT, &mode_current); 718 REG_GET(CM_BLNDGAM_CONTROL, 719 CM_BLNDGAM_SELECT_CURRENT, &in_use); 720 721 switch (mode_current) { 722 case 0: 723 case 1: 724 mode = LUT_BYPASS; 725 break; 726 727 case 2: 728 if (in_use == 0) 729 mode = LUT_RAM_A; 730 else 731 mode = LUT_RAM_B; 732 break; 733 default: 734 mode = LUT_BYPASS; 735 break; 736 } 737 return mode; 738 } 739 740 bool dpp3_program_blnd_lut( 741 struct dpp *dpp_base, const struct pwl_params *params) 742 { 743 enum dc_lut_mode current_mode; 744 enum dc_lut_mode next_mode; 745 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 746 747 if (params == NULL) { 748 REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_MODE, 0); 749 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) 750 dpp3_power_on_blnd_lut(dpp_base, false); 751 return false; 752 } 753 754 current_mode = dpp3_get_blndgam_current(dpp_base); 755 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_B) 756 next_mode = LUT_RAM_A; 757 else 758 next_mode = LUT_RAM_B; 759 760 dpp3_power_on_blnd_lut(dpp_base, true); 761 dpp3_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A); 762 763 if (next_mode == LUT_RAM_A) 764 dpp3_program_blnd_luta_settings(dpp_base, params); 765 else 766 dpp3_program_blnd_lutb_settings(dpp_base, params); 767 768 dpp3_program_blnd_pwl( 769 dpp_base, params->rgb_resulted, params->hw_points_num); 770 771 REG_UPDATE_2(CM_BLNDGAM_CONTROL, 772 CM_BLNDGAM_MODE, 2, 773 CM_BLNDGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1); 774 775 return true; 776 } 777 778 779 static void dpp3_program_shaper_lut( 780 struct dpp *dpp_base, 781 const struct pwl_result_data *rgb, 782 uint32_t num) 783 { 784 uint32_t i, red, green, blue; 785 uint32_t red_delta, green_delta, blue_delta; 786 uint32_t red_value, green_value, blue_value; 787 788 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 789 790 for (i = 0 ; i < num; i++) { 791 792 red = rgb[i].red_reg; 793 green = rgb[i].green_reg; 794 blue = rgb[i].blue_reg; 795 796 red_delta = rgb[i].delta_red_reg; 797 green_delta = rgb[i].delta_green_reg; 798 blue_delta = rgb[i].delta_blue_reg; 799 800 red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff); 801 green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff); 802 blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff); 803 804 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, red_value); 805 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, green_value); 806 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, blue_value); 807 } 808 809 } 810 811 static enum dc_lut_mode dpp3_get_shaper_current(struct dpp *dpp_base) 812 { 813 enum dc_lut_mode mode; 814 uint32_t state_mode; 815 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 816 817 REG_GET(CM_SHAPER_CONTROL, 818 CM_SHAPER_MODE_CURRENT, &state_mode); 819 820 switch (state_mode) { 821 case 0: 822 mode = LUT_BYPASS; 823 break; 824 case 1: 825 mode = LUT_RAM_A; 826 break; 827 case 2: 828 mode = LUT_RAM_B; 829 break; 830 default: 831 mode = LUT_BYPASS; 832 break; 833 } 834 return mode; 835 } 836 837 static void dpp3_configure_shaper_lut( 838 struct dpp *dpp_base, 839 bool is_ram_a) 840 { 841 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 842 843 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK, 844 CM_SHAPER_LUT_WRITE_EN_MASK, 7); 845 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK, 846 CM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1); 847 REG_SET(CM_SHAPER_LUT_INDEX, 0, CM_SHAPER_LUT_INDEX, 0); 848 } 849 850 /*program shaper RAM A*/ 851 852 static void dpp3_program_shaper_luta_settings( 853 struct dpp *dpp_base, 854 const struct pwl_params *params) 855 { 856 const struct gamma_curve *curve; 857 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 858 859 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0, 860 CM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, 861 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); 862 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0, 863 CM_SHAPER_RAMA_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x, 864 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, 0); 865 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0, 866 CM_SHAPER_RAMA_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x, 867 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, 0); 868 869 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0, 870 CM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, 871 CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); 872 873 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0, 874 CM_SHAPER_RAMA_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x, 875 CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y); 876 877 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0, 878 CM_SHAPER_RAMA_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x, 879 CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y); 880 881 curve = params->arr_curve_points; 882 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0, 883 CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 884 CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 885 CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 886 CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 887 888 curve += 2; 889 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0, 890 CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset, 891 CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, 892 CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset, 893 CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); 894 895 curve += 2; 896 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0, 897 CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset, 898 CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, 899 CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset, 900 CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); 901 902 curve += 2; 903 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0, 904 CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset, 905 CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, 906 CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset, 907 CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); 908 909 curve += 2; 910 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0, 911 CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset, 912 CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, 913 CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset, 914 CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); 915 916 curve += 2; 917 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0, 918 CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset, 919 CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, 920 CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset, 921 CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); 922 923 curve += 2; 924 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0, 925 CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset, 926 CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, 927 CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset, 928 CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); 929 930 curve += 2; 931 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0, 932 CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset, 933 CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, 934 CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset, 935 CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); 936 937 curve += 2; 938 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0, 939 CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset, 940 CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num, 941 CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset, 942 CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num); 943 944 curve += 2; 945 REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0, 946 CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset, 947 CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num, 948 CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset, 949 CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num); 950 951 curve += 2; 952 REG_SET_4(CM_SHAPER_RAMA_REGION_20_21, 0, 953 CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset, 954 CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num, 955 CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset, 956 CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num); 957 958 curve += 2; 959 REG_SET_4(CM_SHAPER_RAMA_REGION_22_23, 0, 960 CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset, 961 CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num, 962 CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset, 963 CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num); 964 965 curve += 2; 966 REG_SET_4(CM_SHAPER_RAMA_REGION_24_25, 0, 967 CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset, 968 CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num, 969 CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset, 970 CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num); 971 972 curve += 2; 973 REG_SET_4(CM_SHAPER_RAMA_REGION_26_27, 0, 974 CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset, 975 CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num, 976 CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset, 977 CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num); 978 979 curve += 2; 980 REG_SET_4(CM_SHAPER_RAMA_REGION_28_29, 0, 981 CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset, 982 CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num, 983 CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset, 984 CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num); 985 986 curve += 2; 987 REG_SET_4(CM_SHAPER_RAMA_REGION_30_31, 0, 988 CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset, 989 CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num, 990 CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset, 991 CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num); 992 993 curve += 2; 994 REG_SET_4(CM_SHAPER_RAMA_REGION_32_33, 0, 995 CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset, 996 CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num, 997 CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset, 998 CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num); 999 } 1000 1001 /*program shaper RAM B*/ 1002 static void dpp3_program_shaper_lutb_settings( 1003 struct dpp *dpp_base, 1004 const struct pwl_params *params) 1005 { 1006 const struct gamma_curve *curve; 1007 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1008 1009 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0, 1010 CM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, 1011 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0); 1012 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0, 1013 CM_SHAPER_RAMB_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x, 1014 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, 0); 1015 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0, 1016 CM_SHAPER_RAMB_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x, 1017 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, 0); 1018 1019 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0, 1020 CM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, 1021 CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); 1022 1023 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_G, 0, 1024 CM_SHAPER_RAMB_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x, 1025 CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y); 1026 1027 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_R, 0, 1028 CM_SHAPER_RAMB_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x, 1029 CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y); 1030 1031 curve = params->arr_curve_points; 1032 REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0, 1033 CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 1034 CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 1035 CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 1036 CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 1037 1038 curve += 2; 1039 REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0, 1040 CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset, 1041 CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, 1042 CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset, 1043 CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); 1044 1045 curve += 2; 1046 REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0, 1047 CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset, 1048 CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, 1049 CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset, 1050 CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); 1051 1052 curve += 2; 1053 REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0, 1054 CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset, 1055 CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, 1056 CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset, 1057 CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); 1058 1059 curve += 2; 1060 REG_SET_4(CM_SHAPER_RAMB_REGION_8_9, 0, 1061 CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset, 1062 CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, 1063 CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset, 1064 CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); 1065 1066 curve += 2; 1067 REG_SET_4(CM_SHAPER_RAMB_REGION_10_11, 0, 1068 CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset, 1069 CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, 1070 CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset, 1071 CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); 1072 1073 curve += 2; 1074 REG_SET_4(CM_SHAPER_RAMB_REGION_12_13, 0, 1075 CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset, 1076 CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, 1077 CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset, 1078 CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); 1079 1080 curve += 2; 1081 REG_SET_4(CM_SHAPER_RAMB_REGION_14_15, 0, 1082 CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset, 1083 CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, 1084 CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset, 1085 CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); 1086 1087 curve += 2; 1088 REG_SET_4(CM_SHAPER_RAMB_REGION_16_17, 0, 1089 CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset, 1090 CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num, 1091 CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset, 1092 CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num); 1093 1094 curve += 2; 1095 REG_SET_4(CM_SHAPER_RAMB_REGION_18_19, 0, 1096 CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset, 1097 CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num, 1098 CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset, 1099 CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num); 1100 1101 curve += 2; 1102 REG_SET_4(CM_SHAPER_RAMB_REGION_20_21, 0, 1103 CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset, 1104 CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num, 1105 CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset, 1106 CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num); 1107 1108 curve += 2; 1109 REG_SET_4(CM_SHAPER_RAMB_REGION_22_23, 0, 1110 CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset, 1111 CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num, 1112 CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset, 1113 CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num); 1114 1115 curve += 2; 1116 REG_SET_4(CM_SHAPER_RAMB_REGION_24_25, 0, 1117 CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset, 1118 CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num, 1119 CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset, 1120 CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num); 1121 1122 curve += 2; 1123 REG_SET_4(CM_SHAPER_RAMB_REGION_26_27, 0, 1124 CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset, 1125 CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num, 1126 CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset, 1127 CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num); 1128 1129 curve += 2; 1130 REG_SET_4(CM_SHAPER_RAMB_REGION_28_29, 0, 1131 CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset, 1132 CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num, 1133 CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset, 1134 CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num); 1135 1136 curve += 2; 1137 REG_SET_4(CM_SHAPER_RAMB_REGION_30_31, 0, 1138 CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset, 1139 CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num, 1140 CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset, 1141 CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num); 1142 1143 curve += 2; 1144 REG_SET_4(CM_SHAPER_RAMB_REGION_32_33, 0, 1145 CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset, 1146 CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num, 1147 CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset, 1148 CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num); 1149 1150 } 1151 1152 1153 bool dpp3_program_shaper( 1154 struct dpp *dpp_base, 1155 const struct pwl_params *params) 1156 { 1157 enum dc_lut_mode current_mode; 1158 enum dc_lut_mode next_mode; 1159 1160 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1161 1162 if (params == NULL) { 1163 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0); 1164 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) 1165 dpp3_power_on_shaper(dpp_base, false); 1166 return false; 1167 } 1168 1169 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) 1170 dpp3_power_on_shaper(dpp_base, true); 1171 1172 current_mode = dpp3_get_shaper_current(dpp_base); 1173 1174 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A) 1175 next_mode = LUT_RAM_B; 1176 else 1177 next_mode = LUT_RAM_A; 1178 1179 dpp3_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A); 1180 1181 if (next_mode == LUT_RAM_A) 1182 dpp3_program_shaper_luta_settings(dpp_base, params); 1183 else 1184 dpp3_program_shaper_lutb_settings(dpp_base, params); 1185 1186 dpp3_program_shaper_lut( 1187 dpp_base, params->rgb_resulted, params->hw_points_num); 1188 1189 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2); 1190 1191 return true; 1192 1193 } 1194 1195 static enum dc_lut_mode get3dlut_config( 1196 struct dpp *dpp_base, 1197 bool *is_17x17x17, 1198 bool *is_12bits_color_channel) 1199 { 1200 uint32_t i_mode, i_enable_10bits, lut_size; 1201 enum dc_lut_mode mode; 1202 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1203 1204 REG_GET(CM_3DLUT_READ_WRITE_CONTROL, 1205 CM_3DLUT_30BIT_EN, &i_enable_10bits); 1206 REG_GET(CM_3DLUT_MODE, 1207 CM_3DLUT_MODE_CURRENT, &i_mode); 1208 1209 switch (i_mode) { 1210 case 0: 1211 mode = LUT_BYPASS; 1212 break; 1213 case 1: 1214 mode = LUT_RAM_A; 1215 break; 1216 case 2: 1217 mode = LUT_RAM_B; 1218 break; 1219 default: 1220 mode = LUT_BYPASS; 1221 break; 1222 } 1223 if (i_enable_10bits > 0) 1224 *is_12bits_color_channel = false; 1225 else 1226 *is_12bits_color_channel = true; 1227 1228 REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &lut_size); 1229 1230 if (lut_size == 0) 1231 *is_17x17x17 = true; 1232 else 1233 *is_17x17x17 = false; 1234 1235 return mode; 1236 } 1237 /* 1238 * select ramA or ramB, or bypass 1239 * select color channel size 10 or 12 bits 1240 * select 3dlut size 17x17x17 or 9x9x9 1241 */ 1242 static void dpp3_set_3dlut_mode( 1243 struct dpp *dpp_base, 1244 enum dc_lut_mode mode, 1245 bool is_color_channel_12bits, 1246 bool is_lut_size17x17x17) 1247 { 1248 uint32_t lut_mode; 1249 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1250 1251 if (mode == LUT_BYPASS) 1252 lut_mode = 0; 1253 else if (mode == LUT_RAM_A) 1254 lut_mode = 1; 1255 else 1256 lut_mode = 2; 1257 1258 REG_UPDATE_2(CM_3DLUT_MODE, 1259 CM_3DLUT_MODE, lut_mode, 1260 CM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1); 1261 } 1262 1263 static void dpp3_select_3dlut_ram( 1264 struct dpp *dpp_base, 1265 enum dc_lut_mode mode, 1266 bool is_color_channel_12bits) 1267 { 1268 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1269 1270 REG_UPDATE_2(CM_3DLUT_READ_WRITE_CONTROL, 1271 CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1, 1272 CM_3DLUT_30BIT_EN, 1273 is_color_channel_12bits == true ? 0:1); 1274 } 1275 1276 1277 1278 static void dpp3_set3dlut_ram12( 1279 struct dpp *dpp_base, 1280 const struct dc_rgb *lut, 1281 uint32_t entries) 1282 { 1283 uint32_t i, red, green, blue, red1, green1, blue1; 1284 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1285 1286 for (i = 0 ; i < entries; i += 2) { 1287 red = lut[i].red<<4; 1288 green = lut[i].green<<4; 1289 blue = lut[i].blue<<4; 1290 red1 = lut[i+1].red<<4; 1291 green1 = lut[i+1].green<<4; 1292 blue1 = lut[i+1].blue<<4; 1293 1294 REG_SET_2(CM_3DLUT_DATA, 0, 1295 CM_3DLUT_DATA0, red, 1296 CM_3DLUT_DATA1, red1); 1297 1298 REG_SET_2(CM_3DLUT_DATA, 0, 1299 CM_3DLUT_DATA0, green, 1300 CM_3DLUT_DATA1, green1); 1301 1302 REG_SET_2(CM_3DLUT_DATA, 0, 1303 CM_3DLUT_DATA0, blue, 1304 CM_3DLUT_DATA1, blue1); 1305 1306 } 1307 } 1308 1309 /* 1310 * load selected lut with 10 bits color channels 1311 */ 1312 static void dpp3_set3dlut_ram10( 1313 struct dpp *dpp_base, 1314 const struct dc_rgb *lut, 1315 uint32_t entries) 1316 { 1317 uint32_t i, red, green, blue, value; 1318 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1319 1320 for (i = 0; i < entries; i++) { 1321 red = lut[i].red; 1322 green = lut[i].green; 1323 blue = lut[i].blue; 1324 1325 value = (red<<20) | (green<<10) | blue; 1326 1327 REG_SET(CM_3DLUT_DATA_30BIT, 0, CM_3DLUT_DATA_30BIT, value); 1328 } 1329 1330 } 1331 1332 1333 static void dpp3_select_3dlut_ram_mask( 1334 struct dpp *dpp_base, 1335 uint32_t ram_selection_mask) 1336 { 1337 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); 1338 1339 REG_UPDATE(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK, 1340 ram_selection_mask); 1341 REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0); 1342 } 1343 1344 bool dpp3_program_3dlut( 1345 struct dpp *dpp_base, 1346 struct tetrahedral_params *params) 1347 { 1348 enum dc_lut_mode mode; 1349 bool is_17x17x17; 1350 bool is_12bits_color_channel; 1351 struct dc_rgb *lut0; 1352 struct dc_rgb *lut1; 1353 struct dc_rgb *lut2; 1354 struct dc_rgb *lut3; 1355 int lut_size0; 1356 int lut_size; 1357 1358 if (params == NULL) { 1359 dpp3_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false); 1360 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) 1361 dpp3_power_on_hdr3dlut(dpp_base, false); 1362 return false; 1363 } 1364 1365 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) 1366 dpp3_power_on_hdr3dlut(dpp_base, true); 1367 1368 mode = get3dlut_config(dpp_base, &is_17x17x17, &is_12bits_color_channel); 1369 1370 if (mode == LUT_BYPASS || mode == LUT_RAM_B) 1371 mode = LUT_RAM_A; 1372 else 1373 mode = LUT_RAM_B; 1374 1375 is_17x17x17 = !params->use_tetrahedral_9; 1376 is_12bits_color_channel = params->use_12bits; 1377 if (is_17x17x17) { 1378 lut0 = params->tetrahedral_17.lut0; 1379 lut1 = params->tetrahedral_17.lut1; 1380 lut2 = params->tetrahedral_17.lut2; 1381 lut3 = params->tetrahedral_17.lut3; 1382 lut_size0 = sizeof(params->tetrahedral_17.lut0)/ 1383 sizeof(params->tetrahedral_17.lut0[0]); 1384 lut_size = sizeof(params->tetrahedral_17.lut1)/ 1385 sizeof(params->tetrahedral_17.lut1[0]); 1386 } else { 1387 lut0 = params->tetrahedral_9.lut0; 1388 lut1 = params->tetrahedral_9.lut1; 1389 lut2 = params->tetrahedral_9.lut2; 1390 lut3 = params->tetrahedral_9.lut3; 1391 lut_size0 = sizeof(params->tetrahedral_9.lut0)/ 1392 sizeof(params->tetrahedral_9.lut0[0]); 1393 lut_size = sizeof(params->tetrahedral_9.lut1)/ 1394 sizeof(params->tetrahedral_9.lut1[0]); 1395 } 1396 1397 dpp3_select_3dlut_ram(dpp_base, mode, 1398 is_12bits_color_channel); 1399 dpp3_select_3dlut_ram_mask(dpp_base, 0x1); 1400 if (is_12bits_color_channel) 1401 dpp3_set3dlut_ram12(dpp_base, lut0, lut_size0); 1402 else 1403 dpp3_set3dlut_ram10(dpp_base, lut0, lut_size0); 1404 1405 dpp3_select_3dlut_ram_mask(dpp_base, 0x2); 1406 if (is_12bits_color_channel) 1407 dpp3_set3dlut_ram12(dpp_base, lut1, lut_size); 1408 else 1409 dpp3_set3dlut_ram10(dpp_base, lut1, lut_size); 1410 1411 dpp3_select_3dlut_ram_mask(dpp_base, 0x4); 1412 if (is_12bits_color_channel) 1413 dpp3_set3dlut_ram12(dpp_base, lut2, lut_size); 1414 else 1415 dpp3_set3dlut_ram10(dpp_base, lut2, lut_size); 1416 1417 dpp3_select_3dlut_ram_mask(dpp_base, 0x8); 1418 if (is_12bits_color_channel) 1419 dpp3_set3dlut_ram12(dpp_base, lut3, lut_size); 1420 else 1421 dpp3_set3dlut_ram10(dpp_base, lut3, lut_size); 1422 1423 1424 dpp3_set_3dlut_mode(dpp_base, mode, is_12bits_color_channel, 1425 is_17x17x17); 1426 1427 return true; 1428 } 1429 static struct dpp_funcs dcn30_dpp_funcs = { 1430 .dpp_program_gamcor_lut = dpp3_program_gamcor_lut, 1431 .dpp_read_state = dpp30_read_state, 1432 .dpp_reset = dpp_reset, 1433 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale, 1434 .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps, 1435 .dpp_set_gamut_remap = dpp3_cm_set_gamut_remap, 1436 .dpp_set_csc_adjustment = NULL, 1437 .dpp_set_csc_default = NULL, 1438 .dpp_program_regamma_pwl = NULL, 1439 .dpp_set_pre_degam = dpp3_set_pre_degam, 1440 .dpp_program_input_lut = NULL, 1441 .dpp_full_bypass = dpp1_full_bypass, 1442 .dpp_setup = dpp3_cnv_setup, 1443 .dpp_program_degamma_pwl = NULL, 1444 .dpp_program_cm_dealpha = dpp3_program_cm_dealpha, 1445 .dpp_program_cm_bias = dpp3_program_cm_bias, 1446 .dpp_program_blnd_lut = dpp3_program_blnd_lut, 1447 .dpp_program_shaper_lut = dpp3_program_shaper, 1448 .dpp_program_3dlut = dpp3_program_3dlut, 1449 .dpp_deferred_update = dpp3_deferred_update, 1450 .dpp_program_bias_and_scale = NULL, 1451 .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer, 1452 .set_cursor_attributes = dpp3_set_cursor_attributes, 1453 .set_cursor_position = dpp1_set_cursor_position, 1454 .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes, 1455 .dpp_dppclk_control = dpp1_dppclk_control, 1456 .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier, 1457 }; 1458 1459 1460 static struct dpp_caps dcn30_dpp_cap = { 1461 .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT, 1462 .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions, 1463 }; 1464 1465 bool dpp3_construct( 1466 struct dcn3_dpp *dpp, 1467 struct dc_context *ctx, 1468 uint32_t inst, 1469 const struct dcn3_dpp_registers *tf_regs, 1470 const struct dcn3_dpp_shift *tf_shift, 1471 const struct dcn3_dpp_mask *tf_mask) 1472 { 1473 dpp->base.ctx = ctx; 1474 1475 dpp->base.inst = inst; 1476 dpp->base.funcs = &dcn30_dpp_funcs; 1477 dpp->base.caps = &dcn30_dpp_cap; 1478 1479 dpp->tf_regs = tf_regs; 1480 dpp->tf_shift = tf_shift; 1481 dpp->tf_mask = tf_mask; 1482 1483 return true; 1484 } 1485 1486