1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dc_bios_types.h" 28 #include "dcn30_dio_stream_encoder.h" 29 #include "reg_helper.h" 30 #include "hw_shared.h" 31 #include "core_types.h" 32 #include <linux/delay.h> 33 34 35 #define DC_LOGGER \ 36 enc1->base.ctx->logger 37 38 39 #define REG(reg)\ 40 (enc1->regs->reg) 41 42 #undef FN 43 #define FN(reg_name, field_name) \ 44 enc1->se_shift->field_name, enc1->se_mask->field_name 45 46 #define VBI_LINE_0 0 47 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 48 49 #define CTX \ 50 enc1->base.ctx 51 52 53 void convert_dc_info_packet_to_128( 54 const struct dc_info_packet *info_packet, 55 struct dc_info_packet_128 *info_packet_128) 56 { 57 unsigned int i; 58 59 info_packet_128->hb0 = info_packet->hb0; 60 info_packet_128->hb1 = info_packet->hb1; 61 info_packet_128->hb2 = info_packet->hb2; 62 info_packet_128->hb3 = info_packet->hb3; 63 64 for (i = 0; i < 32; i++) { 65 info_packet_128->sb[i] = info_packet->sb[i]; 66 } 67 68 } 69 static void enc3_update_hdmi_info_packet( 70 struct dcn10_stream_encoder *enc1, 71 uint32_t packet_index, 72 const struct dc_info_packet *info_packet) 73 { 74 uint32_t cont, send, line; 75 76 if (info_packet->valid) { 77 enc1->base.vpg->funcs->update_generic_info_packet( 78 enc1->base.vpg, 79 packet_index, 80 info_packet); 81 82 /* enable transmission of packet(s) - 83 * packet transmission begins on the next frame */ 84 cont = 1; 85 /* send packet(s) every frame */ 86 send = 1; 87 /* select line number to send packets on */ 88 line = 2; 89 } else { 90 cont = 0; 91 send = 0; 92 line = 0; 93 } 94 95 /* DP_SEC_GSP[x]_LINE_REFERENCE - keep default value REFER_TO_DP_SOF */ 96 97 /* choose which generic packet control to use */ 98 switch (packet_index) { 99 case 0: 100 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, 101 HDMI_GENERIC0_CONT, cont, 102 HDMI_GENERIC0_SEND, send); 103 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, 104 HDMI_GENERIC0_LINE, line); 105 break; 106 case 1: 107 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, 108 HDMI_GENERIC1_CONT, cont, 109 HDMI_GENERIC1_SEND, send); 110 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, 111 HDMI_GENERIC1_LINE, line); 112 break; 113 case 2: 114 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, 115 HDMI_GENERIC2_CONT, cont, 116 HDMI_GENERIC2_SEND, send); 117 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, 118 HDMI_GENERIC2_LINE, line); 119 break; 120 case 3: 121 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, 122 HDMI_GENERIC3_CONT, cont, 123 HDMI_GENERIC3_SEND, send); 124 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, 125 HDMI_GENERIC3_LINE, line); 126 break; 127 case 4: 128 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, 129 HDMI_GENERIC4_CONT, cont, 130 HDMI_GENERIC4_SEND, send); 131 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, 132 HDMI_GENERIC4_LINE, line); 133 break; 134 case 5: 135 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, 136 HDMI_GENERIC5_CONT, cont, 137 HDMI_GENERIC5_SEND, send); 138 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, 139 HDMI_GENERIC5_LINE, line); 140 break; 141 case 6: 142 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, 143 HDMI_GENERIC6_CONT, cont, 144 HDMI_GENERIC6_SEND, send); 145 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4, 146 HDMI_GENERIC6_LINE, line); 147 break; 148 case 7: 149 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, 150 HDMI_GENERIC7_CONT, cont, 151 HDMI_GENERIC7_SEND, send); 152 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4, 153 HDMI_GENERIC7_LINE, line); 154 break; 155 case 8: 156 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6, 157 HDMI_GENERIC8_CONT, cont, 158 HDMI_GENERIC8_SEND, send); 159 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7, 160 HDMI_GENERIC8_LINE, line); 161 break; 162 case 9: 163 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6, 164 HDMI_GENERIC9_CONT, cont, 165 HDMI_GENERIC9_SEND, send); 166 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7, 167 HDMI_GENERIC9_LINE, line); 168 break; 169 case 10: 170 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6, 171 HDMI_GENERIC10_CONT, cont, 172 HDMI_GENERIC10_SEND, send); 173 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL8, 174 HDMI_GENERIC10_LINE, line); 175 break; 176 case 11: 177 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6, 178 HDMI_GENERIC11_CONT, cont, 179 HDMI_GENERIC11_SEND, send); 180 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL8, 181 HDMI_GENERIC11_LINE, line); 182 break; 183 case 12: 184 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6, 185 HDMI_GENERIC12_CONT, cont, 186 HDMI_GENERIC12_SEND, send); 187 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL9, 188 HDMI_GENERIC12_LINE, line); 189 break; 190 case 13: 191 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6, 192 HDMI_GENERIC13_CONT, cont, 193 HDMI_GENERIC13_SEND, send); 194 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL9, 195 HDMI_GENERIC13_LINE, line); 196 break; 197 case 14: 198 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6, 199 HDMI_GENERIC14_CONT, cont, 200 HDMI_GENERIC14_SEND, send); 201 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL10, 202 HDMI_GENERIC14_LINE, line); 203 break; 204 default: 205 /* invalid HW packet index */ 206 DC_LOG_WARNING( 207 "Invalid HW packet index: %s()\n", 208 __func__); 209 return; 210 } 211 } 212 213 static void enc3_stream_encoder_update_hdmi_info_packets( 214 struct stream_encoder *enc, 215 const struct encoder_info_frame *info_frame) 216 { 217 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 218 219 /* for bring up, disable dp double TODO */ 220 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); 221 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 222 223 /*Always add mandatory packets first followed by optional ones*/ 224 enc3_update_hdmi_info_packet(enc1, 0, &info_frame->avi); 225 enc3_update_hdmi_info_packet(enc1, 5, &info_frame->hfvsif); 226 enc3_update_hdmi_info_packet(enc1, 2, &info_frame->gamut); 227 enc3_update_hdmi_info_packet(enc1, 1, &info_frame->vendor); 228 enc3_update_hdmi_info_packet(enc1, 3, &info_frame->spd); 229 enc3_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd); 230 } 231 232 static void enc3_stream_encoder_stop_hdmi_info_packets( 233 struct stream_encoder *enc) 234 { 235 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 236 237 /* stop generic packets 0,1 on HDMI */ 238 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, 239 HDMI_GENERIC0_CONT, 0, 240 HDMI_GENERIC0_SEND, 0, 241 HDMI_GENERIC1_CONT, 0, 242 HDMI_GENERIC1_SEND, 0); 243 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0, 244 HDMI_GENERIC0_LINE, 0, 245 HDMI_GENERIC1_LINE, 0); 246 247 /* stop generic packets 2,3 on HDMI */ 248 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, 249 HDMI_GENERIC2_CONT, 0, 250 HDMI_GENERIC2_SEND, 0, 251 HDMI_GENERIC3_CONT, 0, 252 HDMI_GENERIC3_SEND, 0); 253 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0, 254 HDMI_GENERIC2_LINE, 0, 255 HDMI_GENERIC3_LINE, 0); 256 257 /* stop generic packets 4,5 on HDMI */ 258 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, 259 HDMI_GENERIC4_CONT, 0, 260 HDMI_GENERIC4_SEND, 0, 261 HDMI_GENERIC5_CONT, 0, 262 HDMI_GENERIC5_SEND, 0); 263 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0, 264 HDMI_GENERIC4_LINE, 0, 265 HDMI_GENERIC5_LINE, 0); 266 267 /* stop generic packets 6,7 on HDMI */ 268 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, 269 HDMI_GENERIC6_CONT, 0, 270 HDMI_GENERIC6_SEND, 0, 271 HDMI_GENERIC7_CONT, 0, 272 HDMI_GENERIC7_SEND, 0); 273 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0, 274 HDMI_GENERIC6_LINE, 0, 275 HDMI_GENERIC7_LINE, 0); 276 277 /* stop generic packets 8,9 on HDMI */ 278 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0, 279 HDMI_GENERIC8_CONT, 0, 280 HDMI_GENERIC8_SEND, 0, 281 HDMI_GENERIC9_CONT, 0, 282 HDMI_GENERIC9_SEND, 0); 283 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL7, 0, 284 HDMI_GENERIC8_LINE, 0, 285 HDMI_GENERIC9_LINE, 0); 286 287 /* stop generic packets 10,11 on HDMI */ 288 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0, 289 HDMI_GENERIC10_CONT, 0, 290 HDMI_GENERIC10_SEND, 0, 291 HDMI_GENERIC11_CONT, 0, 292 HDMI_GENERIC11_SEND, 0); 293 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL8, 0, 294 HDMI_GENERIC10_LINE, 0, 295 HDMI_GENERIC11_LINE, 0); 296 297 /* stop generic packets 12,13 on HDMI */ 298 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0, 299 HDMI_GENERIC12_CONT, 0, 300 HDMI_GENERIC12_SEND, 0, 301 HDMI_GENERIC13_CONT, 0, 302 HDMI_GENERIC13_SEND, 0); 303 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL9, 0, 304 HDMI_GENERIC12_LINE, 0, 305 HDMI_GENERIC13_LINE, 0); 306 307 /* stop generic packet 14 on HDMI */ 308 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL6, 0, 309 HDMI_GENERIC14_CONT, 0, 310 HDMI_GENERIC14_SEND, 0); 311 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL10, 312 HDMI_GENERIC14_LINE, 0); 313 } 314 315 /* Set DSC-related configuration. 316 * dsc_mode: 0 disables DSC, other values enable DSC in specified format 317 * sc_bytes_per_pixel: Bytes per pixel in u3.28 format 318 * dsc_slice_width: Slice width in pixels 319 */ 320 static void enc3_dp_set_dsc_config(struct stream_encoder *enc, 321 enum optc_dsc_mode dsc_mode, 322 uint32_t dsc_bytes_per_pixel, 323 uint32_t dsc_slice_width) 324 { 325 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 326 327 REG_UPDATE_2(DP_DSC_CNTL, 328 DP_DSC_MODE, dsc_mode, 329 DP_DSC_SLICE_WIDTH, dsc_slice_width); 330 331 REG_SET(DP_DSC_BYTES_PER_PIXEL, 0, 332 DP_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel); 333 } 334 335 336 static void enc3_dp_set_dsc_pps_info_packet(struct stream_encoder *enc, 337 bool enable, 338 uint8_t *dsc_packed_pps) 339 { 340 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 341 342 if (enable) { 343 struct dc_info_packet pps_sdp; 344 int i; 345 346 /* Configure for PPS packet size (128 bytes) */ 347 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 1); 348 349 /* We need turn on clock before programming AFMT block 350 * 351 * TODO: We may not need this here anymore since update_generic_info_packet 352 * no longer touches AFMT 353 */ 354 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 355 356 /* Load PPS into infoframe (SDP) registers */ 357 pps_sdp.valid = true; 358 pps_sdp.hb0 = 0; 359 pps_sdp.hb1 = DC_DP_INFOFRAME_TYPE_PPS; 360 pps_sdp.hb2 = 127; 361 pps_sdp.hb3 = 0; 362 363 for (i = 0; i < 4; i++) { 364 memcpy(pps_sdp.sb, &dsc_packed_pps[i * 32], 32); 365 enc1->base.vpg->funcs->update_generic_info_packet( 366 enc1->base.vpg, 367 11 + i, 368 &pps_sdp); 369 } 370 371 /* SW should make sure VBID[6] update line number is bigger 372 * than PPS transmit line number 373 */ 374 REG_UPDATE(DP_GSP11_CNTL, 375 DP_SEC_GSP11_LINE_NUM, 2); 376 REG_UPDATE_2(DP_MSA_VBID_MISC, 377 DP_VBID6_LINE_REFERENCE, 0, 378 DP_VBID6_LINE_NUM, 3); 379 380 /* Send PPS data at the line number specified above. 381 * DP spec requires PPS to be sent only when it changes, however since 382 * decoder has to be able to handle its change on every frame, we're 383 * sending it always (i.e. on every frame) to reduce the chance it'd be 384 * missed by decoder. If it turns out required to send PPS only when it 385 * changes, we can use DP_SEC_GSP11_SEND register. 386 */ 387 REG_UPDATE(DP_GSP11_CNTL, 388 DP_SEC_GSP11_ENABLE, 1); 389 REG_UPDATE(DP_SEC_CNTL, 390 DP_SEC_STREAM_ENABLE, 1); 391 } else { 392 /* Disable Generic Stream Packet 11 (GSP) transmission */ 393 REG_UPDATE(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, 0); 394 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 0); 395 } 396 } 397 398 399 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state 400 * into a dcn_dsc_state struct. 401 */ 402 static void enc3_read_state(struct stream_encoder *enc, struct enc_state *s) 403 { 404 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 405 406 //if dsc is enabled, continue to read 407 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); 408 if (s->dsc_mode) { 409 REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width); 410 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num); 411 412 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference); 413 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num); 414 415 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable); 416 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); 417 } 418 } 419 420 static void enc3_stream_encoder_update_dp_info_packets( 421 struct stream_encoder *enc, 422 const struct encoder_info_frame *info_frame) 423 { 424 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 425 uint32_t value = 0; 426 uint32_t dmdata_packet_enabled = 0; 427 428 if (info_frame->vsc.valid) { 429 enc->vpg->funcs->update_generic_info_packet( 430 enc->vpg, 431 0, /* packetIndex */ 432 &info_frame->vsc); 433 } 434 if (info_frame->spd.valid) { 435 enc->vpg->funcs->update_generic_info_packet( 436 enc->vpg, 437 2, /* packetIndex */ 438 &info_frame->spd); 439 } 440 if (info_frame->hdrsmd.valid) { 441 enc->vpg->funcs->update_generic_info_packet( 442 enc->vpg, 443 3, /* packetIndex */ 444 &info_frame->hdrsmd); 445 } 446 /* packetIndex 4 is used for send immediate sdp message, and please 447 * use other packetIndex (such as 5,6) for other info packet 448 */ 449 450 /* enable/disable transmission of packet(s). 451 * If enabled, packet transmission begins on the next frame 452 */ 453 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); 454 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); 455 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); 456 457 /* This bit is the master enable bit. 458 * When enabling secondary stream engine, 459 * this master bit must also be set. 460 * This register shared with audio info frame. 461 * Therefore we need to enable master bit 462 * if at least on of the fields is not 0 463 */ 464 value = REG_READ(DP_SEC_CNTL); 465 if (value) 466 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 467 468 /* check if dynamic metadata packet transmission is enabled */ 469 REG_GET(DP_SEC_METADATA_TRANSMISSION, 470 DP_SEC_METADATA_PACKET_ENABLE, &dmdata_packet_enabled); 471 472 if (dmdata_packet_enabled) 473 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 474 } 475 476 static void enc3_dp_set_odm_combine( 477 struct stream_encoder *enc, 478 bool odm_combine) 479 { 480 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 481 482 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine); 483 } 484 485 /* setup stream encoder in dvi mode */ 486 void enc3_stream_encoder_dvi_set_stream_attribute( 487 struct stream_encoder *enc, 488 struct dc_crtc_timing *crtc_timing, 489 bool is_dual_link) 490 { 491 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 492 493 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { 494 struct bp_encoder_control cntl = {0}; 495 496 cntl.action = ENCODER_CONTROL_SETUP; 497 cntl.engine_id = enc1->base.id; 498 cntl.signal = is_dual_link ? 499 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; 500 cntl.enable_dp_audio = false; 501 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; 502 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; 503 504 if (enc1->base.bp->funcs->encoder_control( 505 enc1->base.bp, &cntl) != BP_RESULT_OK) 506 return; 507 508 } else { 509 510 //Set pattern for clock channel, default vlue 0x63 does not work 511 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); 512 513 //DIG_BE_TMDS_DVI_MODE : TMDS-DVI mode is already set in link_encoder_setup 514 515 //DIG_SOURCE_SELECT is already set in dig_connect_to_otg 516 517 /* set DIG_START to 0x1 to reset FIFO */ 518 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); 519 udelay(1); 520 521 /* write 0 to take the FIFO out of reset */ 522 REG_UPDATE(DIG_FE_CNTL, DIG_START, 0); 523 udelay(1); 524 } 525 526 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 527 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); 528 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); 529 } 530 531 /* setup stream encoder in hdmi mode */ 532 static void enc3_stream_encoder_hdmi_set_stream_attribute( 533 struct stream_encoder *enc, 534 struct dc_crtc_timing *crtc_timing, 535 int actual_pix_clk_khz, 536 bool enable_audio) 537 { 538 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 539 540 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { 541 struct bp_encoder_control cntl = {0}; 542 543 cntl.action = ENCODER_CONTROL_SETUP; 544 cntl.engine_id = enc1->base.id; 545 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; 546 cntl.enable_dp_audio = enable_audio; 547 cntl.pixel_clock = actual_pix_clk_khz; 548 cntl.lanes_number = LANE_COUNT_FOUR; 549 550 if (enc1->base.bp->funcs->encoder_control( 551 enc1->base.bp, &cntl) != BP_RESULT_OK) 552 return; 553 554 } else { 555 556 //Set pattern for clock channel, default vlue 0x63 does not work 557 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); 558 559 //DIG_BE_TMDS_HDMI_MODE : TMDS-HDMI mode is already set in link_encoder_setup 560 561 //DIG_SOURCE_SELECT is already set in dig_connect_to_otg 562 563 /* set DIG_START to 0x1 to reset FIFO */ 564 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); 565 udelay(1); 566 567 /* write 0 to take the FIFO out of reset */ 568 REG_UPDATE(DIG_FE_CNTL, DIG_START, 0); 569 udelay(1); 570 } 571 572 /* Configure pixel encoding */ 573 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); 574 575 /* setup HDMI engine */ 576 REG_UPDATE_6(HDMI_CONTROL, 577 HDMI_PACKET_GEN_VERSION, 1, 578 HDMI_KEEPOUT_MODE, 1, 579 HDMI_DEEP_COLOR_ENABLE, 0, 580 HDMI_DATA_SCRAMBLE_EN, 0, 581 HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1, 582 HDMI_CLOCK_CHANNEL_RATE, 0); 583 584 /* Configure color depth */ 585 switch (crtc_timing->display_color_depth) { 586 case COLOR_DEPTH_888: 587 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 588 break; 589 case COLOR_DEPTH_101010: 590 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 591 REG_UPDATE_2(HDMI_CONTROL, 592 HDMI_DEEP_COLOR_DEPTH, 1, 593 HDMI_DEEP_COLOR_ENABLE, 0); 594 } else { 595 REG_UPDATE_2(HDMI_CONTROL, 596 HDMI_DEEP_COLOR_DEPTH, 1, 597 HDMI_DEEP_COLOR_ENABLE, 1); 598 } 599 break; 600 case COLOR_DEPTH_121212: 601 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 602 REG_UPDATE_2(HDMI_CONTROL, 603 HDMI_DEEP_COLOR_DEPTH, 2, 604 HDMI_DEEP_COLOR_ENABLE, 0); 605 } else { 606 REG_UPDATE_2(HDMI_CONTROL, 607 HDMI_DEEP_COLOR_DEPTH, 2, 608 HDMI_DEEP_COLOR_ENABLE, 1); 609 } 610 break; 611 case COLOR_DEPTH_161616: 612 REG_UPDATE_2(HDMI_CONTROL, 613 HDMI_DEEP_COLOR_DEPTH, 3, 614 HDMI_DEEP_COLOR_ENABLE, 1); 615 break; 616 default: 617 break; 618 } 619 620 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { 621 /* enable HDMI data scrambler 622 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M 623 * Clock channel frequency is 1/4 of character rate. 624 */ 625 REG_UPDATE_2(HDMI_CONTROL, 626 HDMI_DATA_SCRAMBLE_EN, 1, 627 HDMI_CLOCK_CHANNEL_RATE, 1); 628 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { 629 630 /* TODO: New feature for DCE11, still need to implement */ 631 632 /* enable HDMI data scrambler 633 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE 634 * Clock channel frequency is the same 635 * as character rate 636 */ 637 REG_UPDATE_2(HDMI_CONTROL, 638 HDMI_DATA_SCRAMBLE_EN, 1, 639 HDMI_CLOCK_CHANNEL_RATE, 0); 640 } 641 642 643 /* Enable transmission of General Control packet on every frame */ 644 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, 645 HDMI_GC_CONT, 1, 646 HDMI_GC_SEND, 1, 647 HDMI_NULL_SEND, 1); 648 649 /* following belongs to audio */ 650 /* Enable Audio InfoFrame packet transmission. */ 651 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 652 653 /* update double-buffered AUDIO_INFO registers immediately */ 654 ASSERT (enc->afmt); 655 enc->afmt->funcs->audio_info_immediate_update(enc->afmt); 656 657 /* Select line number on which to send Audio InfoFrame packets */ 658 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 659 VBI_LINE_0 + 2); 660 661 /* set HDMI GC AVMUTE */ 662 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); 663 } 664 665 static void enc3_audio_mute_control( 666 struct stream_encoder *enc, 667 bool mute) 668 { 669 ASSERT (enc->afmt); 670 enc->afmt->funcs->audio_mute_control(enc->afmt, mute); 671 } 672 673 static void enc3_se_dp_audio_setup( 674 struct stream_encoder *enc, 675 unsigned int az_inst, 676 struct audio_info *info) 677 { 678 ASSERT (enc->afmt); 679 enc->afmt->funcs->se_audio_setup(enc->afmt, az_inst, info); 680 } 681 682 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 683 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 684 685 static void enc3_se_setup_dp_audio( 686 struct stream_encoder *enc) 687 { 688 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 689 690 /* --- DP Audio packet configurations --- */ 691 692 /* ATP Configuration */ 693 REG_SET(DP_SEC_AUD_N, 0, 694 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT); 695 696 /* Async/auto-calc timestamp mode */ 697 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, 698 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC); 699 700 ASSERT (enc->afmt); 701 enc->afmt->funcs->setup_dp_audio(enc->afmt); 702 } 703 704 static void enc3_se_dp_audio_enable( 705 struct stream_encoder *enc) 706 { 707 enc1_se_enable_audio_clock(enc, true); 708 enc3_se_setup_dp_audio(enc); 709 enc1_se_enable_dp_audio(enc); 710 } 711 712 static void enc3_se_setup_hdmi_audio( 713 struct stream_encoder *enc, 714 const struct audio_crtc_info *crtc_info) 715 { 716 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 717 718 struct audio_clock_info audio_clock_info = {0}; 719 720 /* Setup audio in AFMT - program AFMT block associated with DIO */ 721 ASSERT (enc->afmt); 722 enc->afmt->funcs->setup_hdmi_audio(enc->afmt); 723 724 /* HDMI_AUDIO_PACKET_CONTROL */ 725 REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL, 726 HDMI_AUDIO_DELAY_EN, 1); 727 728 /* HDMI_ACR_PACKET_CONTROL */ 729 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, 730 HDMI_ACR_AUTO_SEND, 1, 731 HDMI_ACR_SOURCE, 0, 732 HDMI_ACR_AUDIO_PRIORITY, 0); 733 734 /* Program audio clock sample/regeneration parameters */ 735 get_audio_clock_info(crtc_info->color_depth, 736 crtc_info->requested_pixel_clock_100Hz, 737 crtc_info->calculated_pixel_clock_100Hz, 738 &audio_clock_info); 739 DC_LOG_HW_AUDIO( 740 "\n%s:Input::requested_pixel_clock_100Hz = %d" \ 741 "calculated_pixel_clock_100Hz = %d \n", __func__, \ 742 crtc_info->requested_pixel_clock_100Hz, \ 743 crtc_info->calculated_pixel_clock_100Hz); 744 745 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ 746 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); 747 748 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ 749 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); 750 751 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ 752 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); 753 754 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ 755 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); 756 757 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ 758 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); 759 760 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ 761 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); 762 763 /* Video driver cannot know in advance which sample rate will 764 * be used by HD Audio driver 765 * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is 766 * programmed below in interruppt callback 767 */ 768 } 769 770 static void enc3_se_hdmi_audio_setup( 771 struct stream_encoder *enc, 772 unsigned int az_inst, 773 struct audio_info *info, 774 struct audio_crtc_info *audio_crtc_info) 775 { 776 enc1_se_enable_audio_clock(enc, true); 777 enc3_se_setup_hdmi_audio(enc, audio_crtc_info); 778 ASSERT (enc->afmt); 779 enc->afmt->funcs->se_audio_setup(enc->afmt, az_inst, info); 780 } 781 782 783 static const struct stream_encoder_funcs dcn30_str_enc_funcs = { 784 .dp_set_odm_combine = 785 enc3_dp_set_odm_combine, 786 .dp_set_stream_attribute = 787 enc2_stream_encoder_dp_set_stream_attribute, 788 .hdmi_set_stream_attribute = 789 enc3_stream_encoder_hdmi_set_stream_attribute, 790 .dvi_set_stream_attribute = 791 enc3_stream_encoder_dvi_set_stream_attribute, 792 .set_throttled_vcp_size = 793 enc1_stream_encoder_set_throttled_vcp_size, 794 .update_hdmi_info_packets = 795 enc3_stream_encoder_update_hdmi_info_packets, 796 .stop_hdmi_info_packets = 797 enc3_stream_encoder_stop_hdmi_info_packets, 798 .update_dp_info_packets = 799 enc3_stream_encoder_update_dp_info_packets, 800 .stop_dp_info_packets = 801 enc1_stream_encoder_stop_dp_info_packets, 802 .dp_blank = 803 enc1_stream_encoder_dp_blank, 804 .dp_unblank = 805 enc2_stream_encoder_dp_unblank, 806 .audio_mute_control = enc3_audio_mute_control, 807 808 .dp_audio_setup = enc3_se_dp_audio_setup, 809 .dp_audio_enable = enc3_se_dp_audio_enable, 810 .dp_audio_disable = enc1_se_dp_audio_disable, 811 812 .hdmi_audio_setup = enc3_se_hdmi_audio_setup, 813 .hdmi_audio_disable = enc1_se_hdmi_audio_disable, 814 .setup_stereo_sync = enc1_setup_stereo_sync, 815 .set_avmute = enc1_stream_encoder_set_avmute, 816 .dig_connect_to_otg = enc1_dig_connect_to_otg, 817 .dig_source_otg = enc1_dig_source_otg, 818 819 .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, 820 821 .enc_read_state = enc3_read_state, 822 .dp_set_dsc_config = enc3_dp_set_dsc_config, 823 .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, 824 .set_dynamic_metadata = enc2_set_dynamic_metadata, 825 .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, 826 827 .get_fifo_cal_average_level = enc2_get_fifo_cal_average_level, 828 }; 829 830 void dcn30_dio_stream_encoder_construct( 831 struct dcn10_stream_encoder *enc1, 832 struct dc_context *ctx, 833 struct dc_bios *bp, 834 enum engine_id eng_id, 835 struct vpg *vpg, 836 struct afmt *afmt, 837 const struct dcn10_stream_enc_registers *regs, 838 const struct dcn10_stream_encoder_shift *se_shift, 839 const struct dcn10_stream_encoder_mask *se_mask) 840 { 841 enc1->base.funcs = &dcn30_str_enc_funcs; 842 enc1->base.ctx = ctx; 843 enc1->base.id = eng_id; 844 enc1->base.bp = bp; 845 enc1->base.vpg = vpg; 846 enc1->base.afmt = afmt; 847 enc1->regs = regs; 848 enc1->se_shift = se_shift; 849 enc1->se_mask = se_mask; 850 enc1->base.stream_enc_inst = vpg->inst; 851 } 852 853