1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dc_bios_types.h" 28 #include "dcn30_dio_stream_encoder.h" 29 #include "reg_helper.h" 30 #include "hw_shared.h" 31 #include "core_types.h" 32 #include <linux/delay.h> 33 34 35 #define DC_LOGGER \ 36 enc1->base.ctx->logger 37 38 39 #define REG(reg)\ 40 (enc1->regs->reg) 41 42 #undef FN 43 #define FN(reg_name, field_name) \ 44 enc1->se_shift->field_name, enc1->se_mask->field_name 45 46 #define VBI_LINE_0 0 47 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 48 49 #define CTX \ 50 enc1->base.ctx 51 52 53 void convert_dc_info_packet_to_128( 54 const struct dc_info_packet *info_packet, 55 struct dc_info_packet_128 *info_packet_128) 56 { 57 unsigned int i; 58 59 info_packet_128->hb0 = info_packet->hb0; 60 info_packet_128->hb1 = info_packet->hb1; 61 info_packet_128->hb2 = info_packet->hb2; 62 info_packet_128->hb3 = info_packet->hb3; 63 64 for (i = 0; i < 32; i++) { 65 info_packet_128->sb[i] = info_packet->sb[i]; 66 } 67 68 } 69 static void enc3_update_hdmi_info_packet( 70 struct dcn10_stream_encoder *enc1, 71 uint32_t packet_index, 72 const struct dc_info_packet *info_packet) 73 { 74 uint32_t cont, send, line; 75 76 if (info_packet->valid) { 77 enc1->base.vpg->funcs->update_generic_info_packet( 78 enc1->base.vpg, 79 packet_index, 80 info_packet, 81 true); 82 83 /* enable transmission of packet(s) - 84 * packet transmission begins on the next frame */ 85 cont = 1; 86 /* send packet(s) every frame */ 87 send = 1; 88 /* select line number to send packets on */ 89 line = 2; 90 } else { 91 cont = 0; 92 send = 0; 93 line = 0; 94 } 95 96 /* DP_SEC_GSP[x]_LINE_REFERENCE - keep default value REFER_TO_DP_SOF */ 97 98 /* choose which generic packet control to use */ 99 switch (packet_index) { 100 case 0: 101 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, 102 HDMI_GENERIC0_CONT, cont, 103 HDMI_GENERIC0_SEND, send); 104 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, 105 HDMI_GENERIC0_LINE, line); 106 break; 107 case 1: 108 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, 109 HDMI_GENERIC1_CONT, cont, 110 HDMI_GENERIC1_SEND, send); 111 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, 112 HDMI_GENERIC1_LINE, line); 113 break; 114 case 2: 115 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, 116 HDMI_GENERIC2_CONT, cont, 117 HDMI_GENERIC2_SEND, send); 118 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, 119 HDMI_GENERIC2_LINE, line); 120 break; 121 case 3: 122 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, 123 HDMI_GENERIC3_CONT, cont, 124 HDMI_GENERIC3_SEND, send); 125 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, 126 HDMI_GENERIC3_LINE, line); 127 break; 128 case 4: 129 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, 130 HDMI_GENERIC4_CONT, cont, 131 HDMI_GENERIC4_SEND, send); 132 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, 133 HDMI_GENERIC4_LINE, line); 134 break; 135 case 5: 136 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, 137 HDMI_GENERIC5_CONT, cont, 138 HDMI_GENERIC5_SEND, send); 139 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, 140 HDMI_GENERIC5_LINE, line); 141 break; 142 case 6: 143 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, 144 HDMI_GENERIC6_CONT, cont, 145 HDMI_GENERIC6_SEND, send); 146 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4, 147 HDMI_GENERIC6_LINE, line); 148 break; 149 case 7: 150 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, 151 HDMI_GENERIC7_CONT, cont, 152 HDMI_GENERIC7_SEND, send); 153 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4, 154 HDMI_GENERIC7_LINE, line); 155 break; 156 case 8: 157 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6, 158 HDMI_GENERIC8_CONT, cont, 159 HDMI_GENERIC8_SEND, send); 160 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7, 161 HDMI_GENERIC8_LINE, line); 162 break; 163 case 9: 164 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6, 165 HDMI_GENERIC9_CONT, cont, 166 HDMI_GENERIC9_SEND, send); 167 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7, 168 HDMI_GENERIC9_LINE, line); 169 break; 170 case 10: 171 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6, 172 HDMI_GENERIC10_CONT, cont, 173 HDMI_GENERIC10_SEND, send); 174 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL8, 175 HDMI_GENERIC10_LINE, line); 176 break; 177 case 11: 178 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6, 179 HDMI_GENERIC11_CONT, cont, 180 HDMI_GENERIC11_SEND, send); 181 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL8, 182 HDMI_GENERIC11_LINE, line); 183 break; 184 case 12: 185 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6, 186 HDMI_GENERIC12_CONT, cont, 187 HDMI_GENERIC12_SEND, send); 188 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL9, 189 HDMI_GENERIC12_LINE, line); 190 break; 191 case 13: 192 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6, 193 HDMI_GENERIC13_CONT, cont, 194 HDMI_GENERIC13_SEND, send); 195 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL9, 196 HDMI_GENERIC13_LINE, line); 197 break; 198 case 14: 199 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6, 200 HDMI_GENERIC14_CONT, cont, 201 HDMI_GENERIC14_SEND, send); 202 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL10, 203 HDMI_GENERIC14_LINE, line); 204 break; 205 default: 206 /* invalid HW packet index */ 207 DC_LOG_WARNING( 208 "Invalid HW packet index: %s()\n", 209 __func__); 210 return; 211 } 212 } 213 214 static void enc3_stream_encoder_update_hdmi_info_packets( 215 struct stream_encoder *enc, 216 const struct encoder_info_frame *info_frame) 217 { 218 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 219 220 /* for bring up, disable dp double TODO */ 221 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); 222 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 223 224 /*Always add mandatory packets first followed by optional ones*/ 225 enc3_update_hdmi_info_packet(enc1, 0, &info_frame->avi); 226 enc3_update_hdmi_info_packet(enc1, 5, &info_frame->hfvsif); 227 enc3_update_hdmi_info_packet(enc1, 2, &info_frame->gamut); 228 enc3_update_hdmi_info_packet(enc1, 1, &info_frame->vendor); 229 enc3_update_hdmi_info_packet(enc1, 3, &info_frame->spd); 230 enc3_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd); 231 } 232 233 static void enc3_stream_encoder_stop_hdmi_info_packets( 234 struct stream_encoder *enc) 235 { 236 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 237 238 /* stop generic packets 0,1 on HDMI */ 239 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, 240 HDMI_GENERIC0_CONT, 0, 241 HDMI_GENERIC0_SEND, 0, 242 HDMI_GENERIC1_CONT, 0, 243 HDMI_GENERIC1_SEND, 0); 244 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0, 245 HDMI_GENERIC0_LINE, 0, 246 HDMI_GENERIC1_LINE, 0); 247 248 /* stop generic packets 2,3 on HDMI */ 249 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, 250 HDMI_GENERIC2_CONT, 0, 251 HDMI_GENERIC2_SEND, 0, 252 HDMI_GENERIC3_CONT, 0, 253 HDMI_GENERIC3_SEND, 0); 254 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0, 255 HDMI_GENERIC2_LINE, 0, 256 HDMI_GENERIC3_LINE, 0); 257 258 /* stop generic packets 4,5 on HDMI */ 259 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, 260 HDMI_GENERIC4_CONT, 0, 261 HDMI_GENERIC4_SEND, 0, 262 HDMI_GENERIC5_CONT, 0, 263 HDMI_GENERIC5_SEND, 0); 264 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0, 265 HDMI_GENERIC4_LINE, 0, 266 HDMI_GENERIC5_LINE, 0); 267 268 /* stop generic packets 6,7 on HDMI */ 269 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, 270 HDMI_GENERIC6_CONT, 0, 271 HDMI_GENERIC6_SEND, 0, 272 HDMI_GENERIC7_CONT, 0, 273 HDMI_GENERIC7_SEND, 0); 274 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0, 275 HDMI_GENERIC6_LINE, 0, 276 HDMI_GENERIC7_LINE, 0); 277 278 /* stop generic packets 8,9 on HDMI */ 279 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0, 280 HDMI_GENERIC8_CONT, 0, 281 HDMI_GENERIC8_SEND, 0, 282 HDMI_GENERIC9_CONT, 0, 283 HDMI_GENERIC9_SEND, 0); 284 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL7, 0, 285 HDMI_GENERIC8_LINE, 0, 286 HDMI_GENERIC9_LINE, 0); 287 288 /* stop generic packets 10,11 on HDMI */ 289 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0, 290 HDMI_GENERIC10_CONT, 0, 291 HDMI_GENERIC10_SEND, 0, 292 HDMI_GENERIC11_CONT, 0, 293 HDMI_GENERIC11_SEND, 0); 294 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL8, 0, 295 HDMI_GENERIC10_LINE, 0, 296 HDMI_GENERIC11_LINE, 0); 297 298 /* stop generic packets 12,13 on HDMI */ 299 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0, 300 HDMI_GENERIC12_CONT, 0, 301 HDMI_GENERIC12_SEND, 0, 302 HDMI_GENERIC13_CONT, 0, 303 HDMI_GENERIC13_SEND, 0); 304 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL9, 0, 305 HDMI_GENERIC12_LINE, 0, 306 HDMI_GENERIC13_LINE, 0); 307 308 /* stop generic packet 14 on HDMI */ 309 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL6, 0, 310 HDMI_GENERIC14_CONT, 0, 311 HDMI_GENERIC14_SEND, 0); 312 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL10, 313 HDMI_GENERIC14_LINE, 0); 314 } 315 316 /* Set DSC-related configuration. 317 * dsc_mode: 0 disables DSC, other values enable DSC in specified format 318 * sc_bytes_per_pixel: Bytes per pixel in u3.28 format 319 * dsc_slice_width: Slice width in pixels 320 */ 321 static void enc3_dp_set_dsc_config(struct stream_encoder *enc, 322 enum optc_dsc_mode dsc_mode, 323 uint32_t dsc_bytes_per_pixel, 324 uint32_t dsc_slice_width) 325 { 326 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 327 328 REG_UPDATE_2(DP_DSC_CNTL, 329 DP_DSC_MODE, dsc_mode, 330 DP_DSC_SLICE_WIDTH, dsc_slice_width); 331 332 REG_SET(DP_DSC_BYTES_PER_PIXEL, 0, 333 DP_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel); 334 } 335 336 337 static void enc3_dp_set_dsc_pps_info_packet(struct stream_encoder *enc, 338 bool enable, 339 uint8_t *dsc_packed_pps, 340 bool immediate_update) 341 { 342 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 343 344 if (enable) { 345 struct dc_info_packet pps_sdp; 346 int i; 347 348 /* Configure for PPS packet size (128 bytes) */ 349 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 1); 350 351 /* We need turn on clock before programming AFMT block 352 * 353 * TODO: We may not need this here anymore since update_generic_info_packet 354 * no longer touches AFMT 355 */ 356 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 357 358 /* Load PPS into infoframe (SDP) registers */ 359 pps_sdp.valid = true; 360 pps_sdp.hb0 = 0; 361 pps_sdp.hb1 = DC_DP_INFOFRAME_TYPE_PPS; 362 pps_sdp.hb2 = 127; 363 pps_sdp.hb3 = 0; 364 365 for (i = 0; i < 4; i++) { 366 memcpy(pps_sdp.sb, &dsc_packed_pps[i * 32], 32); 367 enc1->base.vpg->funcs->update_generic_info_packet( 368 enc1->base.vpg, 369 11 + i, 370 &pps_sdp, 371 immediate_update); 372 } 373 374 /* SW should make sure VBID[6] update line number is bigger 375 * than PPS transmit line number 376 */ 377 REG_UPDATE(DP_GSP11_CNTL, 378 DP_SEC_GSP11_LINE_NUM, 2); 379 REG_UPDATE_2(DP_MSA_VBID_MISC, 380 DP_VBID6_LINE_REFERENCE, 0, 381 DP_VBID6_LINE_NUM, 3); 382 383 /* Send PPS data at the line number specified above. 384 * DP spec requires PPS to be sent only when it changes, however since 385 * decoder has to be able to handle its change on every frame, we're 386 * sending it always (i.e. on every frame) to reduce the chance it'd be 387 * missed by decoder. If it turns out required to send PPS only when it 388 * changes, we can use DP_SEC_GSP11_SEND register. 389 */ 390 REG_UPDATE(DP_GSP11_CNTL, 391 DP_SEC_GSP11_ENABLE, 1); 392 REG_UPDATE(DP_SEC_CNTL, 393 DP_SEC_STREAM_ENABLE, 1); 394 } else { 395 /* Disable Generic Stream Packet 11 (GSP) transmission */ 396 REG_UPDATE(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, 0); 397 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 0); 398 } 399 } 400 401 402 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state 403 * into a dcn_dsc_state struct. 404 */ 405 static void enc3_read_state(struct stream_encoder *enc, struct enc_state *s) 406 { 407 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 408 409 //if dsc is enabled, continue to read 410 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); 411 if (s->dsc_mode) { 412 REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width); 413 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num); 414 415 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference); 416 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num); 417 418 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable); 419 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); 420 } 421 } 422 423 static void enc3_stream_encoder_update_dp_info_packets( 424 struct stream_encoder *enc, 425 const struct encoder_info_frame *info_frame) 426 { 427 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 428 uint32_t value = 0; 429 uint32_t dmdata_packet_enabled = 0; 430 431 if (info_frame->vsc.valid) { 432 enc->vpg->funcs->update_generic_info_packet( 433 enc->vpg, 434 0, /* packetIndex */ 435 &info_frame->vsc, 436 true); 437 } 438 if (info_frame->spd.valid) { 439 enc->vpg->funcs->update_generic_info_packet( 440 enc->vpg, 441 2, /* packetIndex */ 442 &info_frame->spd, 443 true); 444 } 445 if (info_frame->hdrsmd.valid) { 446 enc->vpg->funcs->update_generic_info_packet( 447 enc->vpg, 448 3, /* packetIndex */ 449 &info_frame->hdrsmd, 450 true); 451 } 452 /* packetIndex 4 is used for send immediate sdp message, and please 453 * use other packetIndex (such as 5,6) for other info packet 454 */ 455 456 /* enable/disable transmission of packet(s). 457 * If enabled, packet transmission begins on the next frame 458 */ 459 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); 460 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); 461 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); 462 463 /* This bit is the master enable bit. 464 * When enabling secondary stream engine, 465 * this master bit must also be set. 466 * This register shared with audio info frame. 467 * Therefore we need to enable master bit 468 * if at least on of the fields is not 0 469 */ 470 value = REG_READ(DP_SEC_CNTL); 471 if (value) 472 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 473 474 /* check if dynamic metadata packet transmission is enabled */ 475 REG_GET(DP_SEC_METADATA_TRANSMISSION, 476 DP_SEC_METADATA_PACKET_ENABLE, &dmdata_packet_enabled); 477 478 if (dmdata_packet_enabled) 479 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 480 } 481 482 static void enc3_dp_set_odm_combine( 483 struct stream_encoder *enc, 484 bool odm_combine) 485 { 486 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 487 488 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine); 489 } 490 491 /* setup stream encoder in dvi mode */ 492 void enc3_stream_encoder_dvi_set_stream_attribute( 493 struct stream_encoder *enc, 494 struct dc_crtc_timing *crtc_timing, 495 bool is_dual_link) 496 { 497 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 498 499 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { 500 struct bp_encoder_control cntl = {0}; 501 502 cntl.action = ENCODER_CONTROL_SETUP; 503 cntl.engine_id = enc1->base.id; 504 cntl.signal = is_dual_link ? 505 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; 506 cntl.enable_dp_audio = false; 507 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; 508 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; 509 510 if (enc1->base.bp->funcs->encoder_control( 511 enc1->base.bp, &cntl) != BP_RESULT_OK) 512 return; 513 514 } else { 515 516 //Set pattern for clock channel, default vlue 0x63 does not work 517 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); 518 519 //DIG_BE_TMDS_DVI_MODE : TMDS-DVI mode is already set in link_encoder_setup 520 521 //DIG_SOURCE_SELECT is already set in dig_connect_to_otg 522 523 /* set DIG_START to 0x1 to reset FIFO */ 524 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); 525 udelay(1); 526 527 /* write 0 to take the FIFO out of reset */ 528 REG_UPDATE(DIG_FE_CNTL, DIG_START, 0); 529 udelay(1); 530 } 531 532 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 533 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); 534 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); 535 } 536 537 /* setup stream encoder in hdmi mode */ 538 static void enc3_stream_encoder_hdmi_set_stream_attribute( 539 struct stream_encoder *enc, 540 struct dc_crtc_timing *crtc_timing, 541 int actual_pix_clk_khz, 542 bool enable_audio) 543 { 544 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 545 546 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { 547 struct bp_encoder_control cntl = {0}; 548 549 cntl.action = ENCODER_CONTROL_SETUP; 550 cntl.engine_id = enc1->base.id; 551 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; 552 cntl.enable_dp_audio = enable_audio; 553 cntl.pixel_clock = actual_pix_clk_khz; 554 cntl.lanes_number = LANE_COUNT_FOUR; 555 556 if (enc1->base.bp->funcs->encoder_control( 557 enc1->base.bp, &cntl) != BP_RESULT_OK) 558 return; 559 560 } else { 561 562 //Set pattern for clock channel, default vlue 0x63 does not work 563 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); 564 565 //DIG_BE_TMDS_HDMI_MODE : TMDS-HDMI mode is already set in link_encoder_setup 566 567 //DIG_SOURCE_SELECT is already set in dig_connect_to_otg 568 569 /* set DIG_START to 0x1 to reset FIFO */ 570 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); 571 udelay(1); 572 573 /* write 0 to take the FIFO out of reset */ 574 REG_UPDATE(DIG_FE_CNTL, DIG_START, 0); 575 udelay(1); 576 } 577 578 /* Configure pixel encoding */ 579 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); 580 581 /* setup HDMI engine */ 582 REG_UPDATE_6(HDMI_CONTROL, 583 HDMI_PACKET_GEN_VERSION, 1, 584 HDMI_KEEPOUT_MODE, 1, 585 HDMI_DEEP_COLOR_ENABLE, 0, 586 HDMI_DATA_SCRAMBLE_EN, 0, 587 HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1, 588 HDMI_CLOCK_CHANNEL_RATE, 0); 589 590 /* Configure color depth */ 591 switch (crtc_timing->display_color_depth) { 592 case COLOR_DEPTH_888: 593 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 594 break; 595 case COLOR_DEPTH_101010: 596 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 597 REG_UPDATE_2(HDMI_CONTROL, 598 HDMI_DEEP_COLOR_DEPTH, 1, 599 HDMI_DEEP_COLOR_ENABLE, 0); 600 } else { 601 REG_UPDATE_2(HDMI_CONTROL, 602 HDMI_DEEP_COLOR_DEPTH, 1, 603 HDMI_DEEP_COLOR_ENABLE, 1); 604 } 605 break; 606 case COLOR_DEPTH_121212: 607 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 608 REG_UPDATE_2(HDMI_CONTROL, 609 HDMI_DEEP_COLOR_DEPTH, 2, 610 HDMI_DEEP_COLOR_ENABLE, 0); 611 } else { 612 REG_UPDATE_2(HDMI_CONTROL, 613 HDMI_DEEP_COLOR_DEPTH, 2, 614 HDMI_DEEP_COLOR_ENABLE, 1); 615 } 616 break; 617 case COLOR_DEPTH_161616: 618 REG_UPDATE_2(HDMI_CONTROL, 619 HDMI_DEEP_COLOR_DEPTH, 3, 620 HDMI_DEEP_COLOR_ENABLE, 1); 621 break; 622 default: 623 break; 624 } 625 626 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { 627 /* enable HDMI data scrambler 628 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M 629 * Clock channel frequency is 1/4 of character rate. 630 */ 631 REG_UPDATE_2(HDMI_CONTROL, 632 HDMI_DATA_SCRAMBLE_EN, 1, 633 HDMI_CLOCK_CHANNEL_RATE, 1); 634 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { 635 636 /* TODO: New feature for DCE11, still need to implement */ 637 638 /* enable HDMI data scrambler 639 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE 640 * Clock channel frequency is the same 641 * as character rate 642 */ 643 REG_UPDATE_2(HDMI_CONTROL, 644 HDMI_DATA_SCRAMBLE_EN, 1, 645 HDMI_CLOCK_CHANNEL_RATE, 0); 646 } 647 648 649 /* Enable transmission of General Control packet on every frame */ 650 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, 651 HDMI_GC_CONT, 1, 652 HDMI_GC_SEND, 1, 653 HDMI_NULL_SEND, 1); 654 655 /* following belongs to audio */ 656 /* Enable Audio InfoFrame packet transmission. */ 657 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 658 659 /* update double-buffered AUDIO_INFO registers immediately */ 660 ASSERT (enc->afmt); 661 enc->afmt->funcs->audio_info_immediate_update(enc->afmt); 662 663 /* Select line number on which to send Audio InfoFrame packets */ 664 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 665 VBI_LINE_0 + 2); 666 667 /* set HDMI GC AVMUTE */ 668 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); 669 } 670 671 static void enc3_audio_mute_control( 672 struct stream_encoder *enc, 673 bool mute) 674 { 675 ASSERT (enc->afmt); 676 enc->afmt->funcs->audio_mute_control(enc->afmt, mute); 677 } 678 679 static void enc3_se_dp_audio_setup( 680 struct stream_encoder *enc, 681 unsigned int az_inst, 682 struct audio_info *info) 683 { 684 ASSERT (enc->afmt); 685 enc->afmt->funcs->se_audio_setup(enc->afmt, az_inst, info); 686 } 687 688 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 689 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 690 691 static void enc3_se_setup_dp_audio( 692 struct stream_encoder *enc) 693 { 694 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 695 696 /* --- DP Audio packet configurations --- */ 697 698 /* ATP Configuration */ 699 REG_SET(DP_SEC_AUD_N, 0, 700 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT); 701 702 /* Async/auto-calc timestamp mode */ 703 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, 704 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC); 705 706 ASSERT (enc->afmt); 707 enc->afmt->funcs->setup_dp_audio(enc->afmt); 708 } 709 710 static void enc3_se_dp_audio_enable( 711 struct stream_encoder *enc) 712 { 713 enc1_se_enable_audio_clock(enc, true); 714 enc3_se_setup_dp_audio(enc); 715 enc1_se_enable_dp_audio(enc); 716 } 717 718 static void enc3_se_setup_hdmi_audio( 719 struct stream_encoder *enc, 720 const struct audio_crtc_info *crtc_info) 721 { 722 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 723 724 struct audio_clock_info audio_clock_info = {0}; 725 726 /* Setup audio in AFMT - program AFMT block associated with DIO */ 727 ASSERT (enc->afmt); 728 enc->afmt->funcs->setup_hdmi_audio(enc->afmt); 729 730 /* HDMI_AUDIO_PACKET_CONTROL */ 731 REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL, 732 HDMI_AUDIO_DELAY_EN, 1); 733 734 /* HDMI_ACR_PACKET_CONTROL */ 735 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, 736 HDMI_ACR_AUTO_SEND, 1, 737 HDMI_ACR_SOURCE, 0, 738 HDMI_ACR_AUDIO_PRIORITY, 0); 739 740 /* Program audio clock sample/regeneration parameters */ 741 get_audio_clock_info(crtc_info->color_depth, 742 crtc_info->requested_pixel_clock_100Hz, 743 crtc_info->calculated_pixel_clock_100Hz, 744 &audio_clock_info); 745 DC_LOG_HW_AUDIO( 746 "\n%s:Input::requested_pixel_clock_100Hz = %d" \ 747 "calculated_pixel_clock_100Hz = %d \n", __func__, \ 748 crtc_info->requested_pixel_clock_100Hz, \ 749 crtc_info->calculated_pixel_clock_100Hz); 750 751 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ 752 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); 753 754 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ 755 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); 756 757 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ 758 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); 759 760 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ 761 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); 762 763 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ 764 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); 765 766 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ 767 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); 768 769 /* Video driver cannot know in advance which sample rate will 770 * be used by HD Audio driver 771 * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is 772 * programmed below in interruppt callback 773 */ 774 } 775 776 static void enc3_se_hdmi_audio_setup( 777 struct stream_encoder *enc, 778 unsigned int az_inst, 779 struct audio_info *info, 780 struct audio_crtc_info *audio_crtc_info) 781 { 782 enc1_se_enable_audio_clock(enc, true); 783 enc3_se_setup_hdmi_audio(enc, audio_crtc_info); 784 ASSERT (enc->afmt); 785 enc->afmt->funcs->se_audio_setup(enc->afmt, az_inst, info); 786 } 787 788 789 static const struct stream_encoder_funcs dcn30_str_enc_funcs = { 790 .dp_set_odm_combine = 791 enc3_dp_set_odm_combine, 792 .dp_set_stream_attribute = 793 enc2_stream_encoder_dp_set_stream_attribute, 794 .hdmi_set_stream_attribute = 795 enc3_stream_encoder_hdmi_set_stream_attribute, 796 .dvi_set_stream_attribute = 797 enc3_stream_encoder_dvi_set_stream_attribute, 798 .set_throttled_vcp_size = 799 enc1_stream_encoder_set_throttled_vcp_size, 800 .update_hdmi_info_packets = 801 enc3_stream_encoder_update_hdmi_info_packets, 802 .stop_hdmi_info_packets = 803 enc3_stream_encoder_stop_hdmi_info_packets, 804 .update_dp_info_packets = 805 enc3_stream_encoder_update_dp_info_packets, 806 .stop_dp_info_packets = 807 enc1_stream_encoder_stop_dp_info_packets, 808 .dp_blank = 809 enc1_stream_encoder_dp_blank, 810 .dp_unblank = 811 enc2_stream_encoder_dp_unblank, 812 .audio_mute_control = enc3_audio_mute_control, 813 814 .dp_audio_setup = enc3_se_dp_audio_setup, 815 .dp_audio_enable = enc3_se_dp_audio_enable, 816 .dp_audio_disable = enc1_se_dp_audio_disable, 817 818 .hdmi_audio_setup = enc3_se_hdmi_audio_setup, 819 .hdmi_audio_disable = enc1_se_hdmi_audio_disable, 820 .setup_stereo_sync = enc1_setup_stereo_sync, 821 .set_avmute = enc1_stream_encoder_set_avmute, 822 .dig_connect_to_otg = enc1_dig_connect_to_otg, 823 .dig_source_otg = enc1_dig_source_otg, 824 825 .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, 826 827 .enc_read_state = enc3_read_state, 828 .dp_set_dsc_config = enc3_dp_set_dsc_config, 829 .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, 830 .set_dynamic_metadata = enc2_set_dynamic_metadata, 831 .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, 832 833 .get_fifo_cal_average_level = enc2_get_fifo_cal_average_level, 834 }; 835 836 void dcn30_dio_stream_encoder_construct( 837 struct dcn10_stream_encoder *enc1, 838 struct dc_context *ctx, 839 struct dc_bios *bp, 840 enum engine_id eng_id, 841 struct vpg *vpg, 842 struct afmt *afmt, 843 const struct dcn10_stream_enc_registers *regs, 844 const struct dcn10_stream_encoder_shift *se_shift, 845 const struct dcn10_stream_encoder_mask *se_mask) 846 { 847 enc1->base.funcs = &dcn30_str_enc_funcs; 848 enc1->base.ctx = ctx; 849 enc1->base.id = eng_id; 850 enc1->base.bp = bp; 851 enc1->base.vpg = vpg; 852 enc1->base.afmt = afmt; 853 enc1->regs = regs; 854 enc1->se_shift = se_shift; 855 enc1->se_mask = se_mask; 856 enc1->base.stream_enc_inst = vpg->inst; 857 } 858 859