1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * Copyright 2019 Raptor Engineering, LLC 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 #include "dc.h" 31 32 #include "dcn21_init.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dcn20/dcn20_resource.h" 37 38 #include "clk_mgr.h" 39 #include "dcn10/dcn10_hubp.h" 40 #include "dcn10/dcn10_ipp.h" 41 #include "dcn20/dcn20_hubbub.h" 42 #include "dcn20/dcn20_mpc.h" 43 #include "dcn20/dcn20_hubp.h" 44 #include "dcn21_hubp.h" 45 #include "irq/dcn21/irq_service_dcn21.h" 46 #include "dcn20/dcn20_dpp.h" 47 #include "dcn20/dcn20_optc.h" 48 #include "dcn21/dcn21_hwseq.h" 49 #include "dce110/dce110_hw_sequencer.h" 50 #include "dcn20/dcn20_opp.h" 51 #include "dcn20/dcn20_dsc.h" 52 #include "dcn21/dcn21_link_encoder.h" 53 #include "dcn20/dcn20_stream_encoder.h" 54 #include "dce/dce_clock_source.h" 55 #include "dce/dce_audio.h" 56 #include "dce/dce_hwseq.h" 57 #include "virtual/virtual_stream_encoder.h" 58 #include "dml/display_mode_vba.h" 59 #include "dcn20/dcn20_dccg.h" 60 #include "dcn21/dcn21_dccg.h" 61 #include "dcn21_hubbub.h" 62 #include "dcn10/dcn10_resource.h" 63 #include "dce/dce_panel_cntl.h" 64 65 #include "dcn20/dcn20_dwb.h" 66 #include "dcn20/dcn20_mmhubbub.h" 67 #include "dpcs/dpcs_2_1_0_offset.h" 68 #include "dpcs/dpcs_2_1_0_sh_mask.h" 69 70 #include "renoir_ip_offset.h" 71 #include "dcn/dcn_2_1_0_offset.h" 72 #include "dcn/dcn_2_1_0_sh_mask.h" 73 74 #include "nbio/nbio_7_0_offset.h" 75 76 #include "mmhub/mmhub_2_0_0_offset.h" 77 #include "mmhub/mmhub_2_0_0_sh_mask.h" 78 79 #include "reg_helper.h" 80 #include "dce/dce_abm.h" 81 #include "dce/dce_dmcu.h" 82 #include "dce/dce_aux.h" 83 #include "dce/dce_i2c.h" 84 #include "dcn21_resource.h" 85 #include "vm_helper.h" 86 #include "dcn20/dcn20_vmid.h" 87 #include "dce/dmub_psr.h" 88 #include "dce/dmub_abm.h" 89 90 #define DC_LOGGER_INIT(logger) 91 92 93 struct _vcs_dpi_ip_params_st dcn2_1_ip = { 94 .odm_capable = 1, 95 .gpuvm_enable = 1, 96 .hostvm_enable = 1, 97 .gpuvm_max_page_table_levels = 1, 98 .hostvm_max_page_table_levels = 4, 99 .hostvm_cached_page_table_levels = 2, 100 .num_dsc = 3, 101 .rob_buffer_size_kbytes = 168, 102 .det_buffer_size_kbytes = 164, 103 .dpte_buffer_size_in_pte_reqs_luma = 44, 104 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo 105 .dpp_output_buffer_pixels = 2560, 106 .opp_output_buffer_lines = 1, 107 .pixel_chunk_size_kbytes = 8, 108 .pte_enable = 1, 109 .max_page_table_levels = 4, 110 .pte_chunk_size_kbytes = 2, 111 .meta_chunk_size_kbytes = 2, 112 .min_meta_chunk_size_bytes = 256, 113 .writeback_chunk_size_kbytes = 2, 114 .line_buffer_size_bits = 789504, 115 .is_line_buffer_bpp_fixed = 0, 116 .line_buffer_fixed_bpp = 0, 117 .dcc_supported = true, 118 .max_line_buffer_lines = 12, 119 .writeback_luma_buffer_size_kbytes = 12, 120 .writeback_chroma_buffer_size_kbytes = 8, 121 .writeback_chroma_line_buffer_width_pixels = 4, 122 .writeback_max_hscl_ratio = 1, 123 .writeback_max_vscl_ratio = 1, 124 .writeback_min_hscl_ratio = 1, 125 .writeback_min_vscl_ratio = 1, 126 .writeback_max_hscl_taps = 12, 127 .writeback_max_vscl_taps = 12, 128 .writeback_line_buffer_luma_buffer_size = 0, 129 .writeback_line_buffer_chroma_buffer_size = 14643, 130 .cursor_buffer_size = 8, 131 .cursor_chunk_size = 2, 132 .max_num_otg = 4, 133 .max_num_dpp = 4, 134 .max_num_wb = 1, 135 .max_dchub_pscl_bw_pix_per_clk = 4, 136 .max_pscl_lb_bw_pix_per_clk = 2, 137 .max_lb_vscl_bw_pix_per_clk = 4, 138 .max_vscl_hscl_bw_pix_per_clk = 4, 139 .max_hscl_ratio = 4, 140 .max_vscl_ratio = 4, 141 .hscl_mults = 4, 142 .vscl_mults = 4, 143 .max_hscl_taps = 8, 144 .max_vscl_taps = 8, 145 .dispclk_ramp_margin_percent = 1, 146 .underscan_factor = 1.10, 147 .min_vblank_lines = 32, // 148 .dppclk_delay_subtotal = 77, // 149 .dppclk_delay_scl_lb_only = 16, 150 .dppclk_delay_scl = 50, 151 .dppclk_delay_cnvc_formatter = 8, 152 .dppclk_delay_cnvc_cursor = 6, 153 .dispclk_delay_subtotal = 87, // 154 .dcfclk_cstate_latency = 10, // SRExitTime 155 .max_inter_dcn_tile_repeaters = 8, 156 157 .xfc_supported = false, 158 .xfc_fill_bw_overhead_percent = 10.0, 159 .xfc_fill_constant_bytes = 0, 160 .ptoi_supported = 0, 161 .number_of_cursors = 1, 162 }; 163 164 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { 165 .clock_limits = { 166 { 167 .state = 0, 168 .dcfclk_mhz = 400.0, 169 .fabricclk_mhz = 400.0, 170 .dispclk_mhz = 600.0, 171 .dppclk_mhz = 400.00, 172 .phyclk_mhz = 600.0, 173 .socclk_mhz = 278.0, 174 .dscclk_mhz = 205.67, 175 .dram_speed_mts = 1600.0, 176 }, 177 { 178 .state = 1, 179 .dcfclk_mhz = 464.52, 180 .fabricclk_mhz = 800.0, 181 .dispclk_mhz = 654.55, 182 .dppclk_mhz = 626.09, 183 .phyclk_mhz = 600.0, 184 .socclk_mhz = 278.0, 185 .dscclk_mhz = 205.67, 186 .dram_speed_mts = 1600.0, 187 }, 188 { 189 .state = 2, 190 .dcfclk_mhz = 514.29, 191 .fabricclk_mhz = 933.0, 192 .dispclk_mhz = 757.89, 193 .dppclk_mhz = 685.71, 194 .phyclk_mhz = 600.0, 195 .socclk_mhz = 278.0, 196 .dscclk_mhz = 287.67, 197 .dram_speed_mts = 1866.0, 198 }, 199 { 200 .state = 3, 201 .dcfclk_mhz = 576.00, 202 .fabricclk_mhz = 1067.0, 203 .dispclk_mhz = 847.06, 204 .dppclk_mhz = 757.89, 205 .phyclk_mhz = 600.0, 206 .socclk_mhz = 715.0, 207 .dscclk_mhz = 318.334, 208 .dram_speed_mts = 2134.0, 209 }, 210 { 211 .state = 4, 212 .dcfclk_mhz = 626.09, 213 .fabricclk_mhz = 1200.0, 214 .dispclk_mhz = 900.00, 215 .dppclk_mhz = 847.06, 216 .phyclk_mhz = 810.0, 217 .socclk_mhz = 953.0, 218 .dscclk_mhz = 489.0, 219 .dram_speed_mts = 2400.0, 220 }, 221 { 222 .state = 5, 223 .dcfclk_mhz = 685.71, 224 .fabricclk_mhz = 1333.0, 225 .dispclk_mhz = 1028.57, 226 .dppclk_mhz = 960.00, 227 .phyclk_mhz = 810.0, 228 .socclk_mhz = 278.0, 229 .dscclk_mhz = 287.67, 230 .dram_speed_mts = 2666.0, 231 }, 232 { 233 .state = 6, 234 .dcfclk_mhz = 757.89, 235 .fabricclk_mhz = 1467.0, 236 .dispclk_mhz = 1107.69, 237 .dppclk_mhz = 1028.57, 238 .phyclk_mhz = 810.0, 239 .socclk_mhz = 715.0, 240 .dscclk_mhz = 318.334, 241 .dram_speed_mts = 3200.0, 242 }, 243 { 244 .state = 7, 245 .dcfclk_mhz = 847.06, 246 .fabricclk_mhz = 1600.0, 247 .dispclk_mhz = 1395.0, 248 .dppclk_mhz = 1285.00, 249 .phyclk_mhz = 1325.0, 250 .socclk_mhz = 953.0, 251 .dscclk_mhz = 489.0, 252 .dram_speed_mts = 4266.0, 253 }, 254 /*Extra state, no dispclk ramping*/ 255 { 256 .state = 8, 257 .dcfclk_mhz = 847.06, 258 .fabricclk_mhz = 1600.0, 259 .dispclk_mhz = 1395.0, 260 .dppclk_mhz = 1285.0, 261 .phyclk_mhz = 1325.0, 262 .socclk_mhz = 953.0, 263 .dscclk_mhz = 489.0, 264 .dram_speed_mts = 4266.0, 265 }, 266 267 }, 268 269 .sr_exit_time_us = 12.5, 270 .sr_enter_plus_exit_time_us = 17.0, 271 .urgent_latency_us = 4.0, 272 .urgent_latency_pixel_data_only_us = 4.0, 273 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 274 .urgent_latency_vm_data_only_us = 4.0, 275 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 276 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 277 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 278 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 279 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0, 280 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 281 .max_avg_sdp_bw_use_normal_percent = 60.0, 282 .max_avg_dram_bw_use_normal_percent = 100.0, 283 .writeback_latency_us = 12.0, 284 .max_request_size_bytes = 256, 285 .dram_channel_width_bytes = 4, 286 .fabric_datapath_to_dcn_data_return_bytes = 32, 287 .dcn_downspread_percent = 0.5, 288 .downspread_percent = 0.38, 289 .dram_page_open_time_ns = 50.0, 290 .dram_rw_turnaround_time_ns = 17.5, 291 .dram_return_buffer_per_channel_bytes = 8192, 292 .round_trip_ping_latency_dcfclk_cycles = 128, 293 .urgent_out_of_order_return_per_channel_bytes = 4096, 294 .channel_interleave_bytes = 256, 295 .num_banks = 8, 296 .num_chans = 4, 297 .vmm_page_size_bytes = 4096, 298 .dram_clock_change_latency_us = 23.84, 299 .return_bus_width_bytes = 64, 300 .dispclk_dppclk_vco_speed_mhz = 3600, 301 .xfc_bus_transport_time_us = 4, 302 .xfc_xbuf_latency_tolerance_us = 4, 303 .use_urgent_burst_bw = 1, 304 .num_states = 8 305 }; 306 307 #ifndef MAX 308 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y)) 309 #endif 310 #ifndef MIN 311 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 312 #endif 313 314 /* begin ********************* 315 * macros to expend register list macro defined in HW object header file */ 316 317 /* DCN */ 318 /* TODO awful hack. fixup dcn20_dwb.h */ 319 #undef BASE_INNER 320 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg 321 322 #define BASE(seg) BASE_INNER(seg) 323 324 #define SR(reg_name)\ 325 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 326 mm ## reg_name 327 328 #define SRI(reg_name, block, id)\ 329 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 330 mm ## block ## id ## _ ## reg_name 331 332 #define SRIR(var_name, reg_name, block, id)\ 333 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 334 mm ## block ## id ## _ ## reg_name 335 336 #define SRII(reg_name, block, id)\ 337 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 338 mm ## block ## id ## _ ## reg_name 339 340 #define DCCG_SRII(reg_name, block, id)\ 341 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 342 mm ## block ## id ## _ ## reg_name 343 344 #define VUPDATE_SRII(reg_name, block, id)\ 345 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 346 mm ## reg_name ## _ ## block ## id 347 348 /* NBIO */ 349 #define NBIO_BASE_INNER(seg) \ 350 NBIF0_BASE__INST0_SEG ## seg 351 352 #define NBIO_BASE(seg) \ 353 NBIO_BASE_INNER(seg) 354 355 #define NBIO_SR(reg_name)\ 356 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 357 mm ## reg_name 358 359 /* MMHUB */ 360 #define MMHUB_BASE_INNER(seg) \ 361 MMHUB_BASE__INST0_SEG ## seg 362 363 #define MMHUB_BASE(seg) \ 364 MMHUB_BASE_INNER(seg) 365 366 #define MMHUB_SR(reg_name)\ 367 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 368 mmMM ## reg_name 369 370 #define clk_src_regs(index, pllid)\ 371 [index] = {\ 372 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\ 373 } 374 375 static const struct dce110_clk_src_regs clk_src_regs[] = { 376 clk_src_regs(0, A), 377 clk_src_regs(1, B), 378 clk_src_regs(2, C), 379 clk_src_regs(3, D), 380 clk_src_regs(4, E), 381 }; 382 383 static const struct dce110_clk_src_shift cs_shift = { 384 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 385 }; 386 387 static const struct dce110_clk_src_mask cs_mask = { 388 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 389 }; 390 391 static const struct bios_registers bios_regs = { 392 NBIO_SR(BIOS_SCRATCH_3), 393 NBIO_SR(BIOS_SCRATCH_6) 394 }; 395 396 static const struct dce_dmcu_registers dmcu_regs = { 397 DMCU_DCN20_REG_LIST() 398 }; 399 400 static const struct dce_dmcu_shift dmcu_shift = { 401 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 402 }; 403 404 static const struct dce_dmcu_mask dmcu_mask = { 405 DMCU_MASK_SH_LIST_DCN10(_MASK) 406 }; 407 408 static const struct dce_abm_registers abm_regs = { 409 ABM_DCN20_REG_LIST() 410 }; 411 412 static const struct dce_abm_shift abm_shift = { 413 ABM_MASK_SH_LIST_DCN20(__SHIFT) 414 }; 415 416 static const struct dce_abm_mask abm_mask = { 417 ABM_MASK_SH_LIST_DCN20(_MASK) 418 }; 419 420 #define audio_regs(id)\ 421 [id] = {\ 422 AUD_COMMON_REG_LIST(id)\ 423 } 424 425 static const struct dce_audio_registers audio_regs[] = { 426 audio_regs(0), 427 audio_regs(1), 428 audio_regs(2), 429 audio_regs(3), 430 audio_regs(4), 431 audio_regs(5), 432 }; 433 434 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 435 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 436 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 437 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 438 439 static const struct dce_audio_shift audio_shift = { 440 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 441 }; 442 443 static const struct dce_audio_mask audio_mask = { 444 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 445 }; 446 447 static const struct dccg_registers dccg_regs = { 448 DCCG_COMMON_REG_LIST_DCN_BASE() 449 }; 450 451 static const struct dccg_shift dccg_shift = { 452 DCCG_MASK_SH_LIST_DCN2_1(__SHIFT) 453 }; 454 455 static const struct dccg_mask dccg_mask = { 456 DCCG_MASK_SH_LIST_DCN2_1(_MASK) 457 }; 458 459 #define opp_regs(id)\ 460 [id] = {\ 461 OPP_REG_LIST_DCN20(id),\ 462 } 463 464 static const struct dcn20_opp_registers opp_regs[] = { 465 opp_regs(0), 466 opp_regs(1), 467 opp_regs(2), 468 opp_regs(3), 469 opp_regs(4), 470 opp_regs(5), 471 }; 472 473 static const struct dcn20_opp_shift opp_shift = { 474 OPP_MASK_SH_LIST_DCN20(__SHIFT) 475 }; 476 477 static const struct dcn20_opp_mask opp_mask = { 478 OPP_MASK_SH_LIST_DCN20(_MASK) 479 }; 480 481 #define tg_regs(id)\ 482 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)} 483 484 static const struct dcn_optc_registers tg_regs[] = { 485 tg_regs(0), 486 tg_regs(1), 487 tg_regs(2), 488 tg_regs(3) 489 }; 490 491 static const struct dcn_optc_shift tg_shift = { 492 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 493 }; 494 495 static const struct dcn_optc_mask tg_mask = { 496 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 497 }; 498 499 static const struct dcn20_mpc_registers mpc_regs = { 500 MPC_REG_LIST_DCN2_0(0), 501 MPC_REG_LIST_DCN2_0(1), 502 MPC_REG_LIST_DCN2_0(2), 503 MPC_REG_LIST_DCN2_0(3), 504 MPC_REG_LIST_DCN2_0(4), 505 MPC_REG_LIST_DCN2_0(5), 506 MPC_OUT_MUX_REG_LIST_DCN2_0(0), 507 MPC_OUT_MUX_REG_LIST_DCN2_0(1), 508 MPC_OUT_MUX_REG_LIST_DCN2_0(2), 509 MPC_OUT_MUX_REG_LIST_DCN2_0(3), 510 MPC_DBG_REG_LIST_DCN2_0() 511 }; 512 513 static const struct dcn20_mpc_shift mpc_shift = { 514 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT), 515 MPC_DEBUG_REG_LIST_SH_DCN20 516 }; 517 518 static const struct dcn20_mpc_mask mpc_mask = { 519 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK), 520 MPC_DEBUG_REG_LIST_MASK_DCN20 521 }; 522 523 #define hubp_regs(id)\ 524 [id] = {\ 525 HUBP_REG_LIST_DCN21(id)\ 526 } 527 528 static const struct dcn_hubp2_registers hubp_regs[] = { 529 hubp_regs(0), 530 hubp_regs(1), 531 hubp_regs(2), 532 hubp_regs(3) 533 }; 534 535 static const struct dcn_hubp2_shift hubp_shift = { 536 HUBP_MASK_SH_LIST_DCN21(__SHIFT) 537 }; 538 539 static const struct dcn_hubp2_mask hubp_mask = { 540 HUBP_MASK_SH_LIST_DCN21(_MASK) 541 }; 542 543 static const struct dcn_hubbub_registers hubbub_reg = { 544 HUBBUB_REG_LIST_DCN21() 545 }; 546 547 static const struct dcn_hubbub_shift hubbub_shift = { 548 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT) 549 }; 550 551 static const struct dcn_hubbub_mask hubbub_mask = { 552 HUBBUB_MASK_SH_LIST_DCN21(_MASK) 553 }; 554 555 556 #define vmid_regs(id)\ 557 [id] = {\ 558 DCN20_VMID_REG_LIST(id)\ 559 } 560 561 static const struct dcn_vmid_registers vmid_regs[] = { 562 vmid_regs(0), 563 vmid_regs(1), 564 vmid_regs(2), 565 vmid_regs(3), 566 vmid_regs(4), 567 vmid_regs(5), 568 vmid_regs(6), 569 vmid_regs(7), 570 vmid_regs(8), 571 vmid_regs(9), 572 vmid_regs(10), 573 vmid_regs(11), 574 vmid_regs(12), 575 vmid_regs(13), 576 vmid_regs(14), 577 vmid_regs(15) 578 }; 579 580 static const struct dcn20_vmid_shift vmid_shifts = { 581 DCN20_VMID_MASK_SH_LIST(__SHIFT) 582 }; 583 584 static const struct dcn20_vmid_mask vmid_masks = { 585 DCN20_VMID_MASK_SH_LIST(_MASK) 586 }; 587 588 #define dsc_regsDCN20(id)\ 589 [id] = {\ 590 DSC_REG_LIST_DCN20(id)\ 591 } 592 593 static const struct dcn20_dsc_registers dsc_regs[] = { 594 dsc_regsDCN20(0), 595 dsc_regsDCN20(1), 596 dsc_regsDCN20(2), 597 dsc_regsDCN20(3), 598 dsc_regsDCN20(4), 599 dsc_regsDCN20(5) 600 }; 601 602 static const struct dcn20_dsc_shift dsc_shift = { 603 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 604 }; 605 606 static const struct dcn20_dsc_mask dsc_mask = { 607 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 608 }; 609 610 #define ipp_regs(id)\ 611 [id] = {\ 612 IPP_REG_LIST_DCN20(id),\ 613 } 614 615 static const struct dcn10_ipp_registers ipp_regs[] = { 616 ipp_regs(0), 617 ipp_regs(1), 618 ipp_regs(2), 619 ipp_regs(3), 620 }; 621 622 static const struct dcn10_ipp_shift ipp_shift = { 623 IPP_MASK_SH_LIST_DCN20(__SHIFT) 624 }; 625 626 static const struct dcn10_ipp_mask ipp_mask = { 627 IPP_MASK_SH_LIST_DCN20(_MASK), 628 }; 629 630 #define opp_regs(id)\ 631 [id] = {\ 632 OPP_REG_LIST_DCN20(id),\ 633 } 634 635 636 #define aux_engine_regs(id)\ 637 [id] = {\ 638 AUX_COMMON_REG_LIST0(id), \ 639 .AUXN_IMPCAL = 0, \ 640 .AUXP_IMPCAL = 0, \ 641 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 642 } 643 644 static const struct dce110_aux_registers aux_engine_regs[] = { 645 aux_engine_regs(0), 646 aux_engine_regs(1), 647 aux_engine_regs(2), 648 aux_engine_regs(3), 649 aux_engine_regs(4), 650 }; 651 652 #define tf_regs(id)\ 653 [id] = {\ 654 TF_REG_LIST_DCN20(id),\ 655 TF_REG_LIST_DCN20_COMMON_APPEND(id),\ 656 } 657 658 static const struct dcn2_dpp_registers tf_regs[] = { 659 tf_regs(0), 660 tf_regs(1), 661 tf_regs(2), 662 tf_regs(3), 663 }; 664 665 static const struct dcn2_dpp_shift tf_shift = { 666 TF_REG_LIST_SH_MASK_DCN20(__SHIFT), 667 TF_DEBUG_REG_LIST_SH_DCN20 668 }; 669 670 static const struct dcn2_dpp_mask tf_mask = { 671 TF_REG_LIST_SH_MASK_DCN20(_MASK), 672 TF_DEBUG_REG_LIST_MASK_DCN20 673 }; 674 675 #define stream_enc_regs(id)\ 676 [id] = {\ 677 SE_DCN2_REG_LIST(id)\ 678 } 679 680 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 681 stream_enc_regs(0), 682 stream_enc_regs(1), 683 stream_enc_regs(2), 684 stream_enc_regs(3), 685 stream_enc_regs(4), 686 }; 687 688 static const struct dce110_aux_registers_shift aux_shift = { 689 DCN_AUX_MASK_SH_LIST(__SHIFT) 690 }; 691 692 static const struct dce110_aux_registers_mask aux_mask = { 693 DCN_AUX_MASK_SH_LIST(_MASK) 694 }; 695 696 static const struct dcn10_stream_encoder_shift se_shift = { 697 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) 698 }; 699 700 static const struct dcn10_stream_encoder_mask se_mask = { 701 SE_COMMON_MASK_SH_LIST_DCN20(_MASK) 702 }; 703 704 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu); 705 706 static int dcn21_populate_dml_pipes_from_context( 707 struct dc *dc, 708 struct dc_state *context, 709 display_e2e_pipe_params_st *pipes, 710 bool fast_validate); 711 712 static struct input_pixel_processor *dcn21_ipp_create( 713 struct dc_context *ctx, uint32_t inst) 714 { 715 struct dcn10_ipp *ipp = 716 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 717 718 if (!ipp) { 719 BREAK_TO_DEBUGGER(); 720 return NULL; 721 } 722 723 dcn20_ipp_construct(ipp, ctx, inst, 724 &ipp_regs[inst], &ipp_shift, &ipp_mask); 725 return &ipp->base; 726 } 727 728 static struct dpp *dcn21_dpp_create( 729 struct dc_context *ctx, 730 uint32_t inst) 731 { 732 struct dcn20_dpp *dpp = 733 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL); 734 735 if (!dpp) 736 return NULL; 737 738 if (dpp2_construct(dpp, ctx, inst, 739 &tf_regs[inst], &tf_shift, &tf_mask)) 740 return &dpp->base; 741 742 BREAK_TO_DEBUGGER(); 743 kfree(dpp); 744 return NULL; 745 } 746 747 static struct dce_aux *dcn21_aux_engine_create( 748 struct dc_context *ctx, 749 uint32_t inst) 750 { 751 struct aux_engine_dce110 *aux_engine = 752 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 753 754 if (!aux_engine) 755 return NULL; 756 757 dce110_aux_engine_construct(aux_engine, ctx, inst, 758 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 759 &aux_engine_regs[inst], 760 &aux_mask, 761 &aux_shift, 762 ctx->dc->caps.extended_aux_timeout_support); 763 764 return &aux_engine->base; 765 } 766 767 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 768 769 static const struct dce_i2c_registers i2c_hw_regs[] = { 770 i2c_inst_regs(1), 771 i2c_inst_regs(2), 772 i2c_inst_regs(3), 773 i2c_inst_regs(4), 774 i2c_inst_regs(5), 775 }; 776 777 static const struct dce_i2c_shift i2c_shifts = { 778 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 779 }; 780 781 static const struct dce_i2c_mask i2c_masks = { 782 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 783 }; 784 785 struct dce_i2c_hw *dcn21_i2c_hw_create( 786 struct dc_context *ctx, 787 uint32_t inst) 788 { 789 struct dce_i2c_hw *dce_i2c_hw = 790 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 791 792 if (!dce_i2c_hw) 793 return NULL; 794 795 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 796 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 797 798 return dce_i2c_hw; 799 } 800 801 static const struct resource_caps res_cap_rn = { 802 .num_timing_generator = 4, 803 .num_opp = 4, 804 .num_video_plane = 4, 805 .num_audio = 4, // 4 audio endpoints. 4 audio streams 806 .num_stream_encoder = 5, 807 .num_pll = 5, // maybe 3 because the last two used for USB-c 808 .num_dwb = 1, 809 .num_ddc = 5, 810 .num_vmid = 16, 811 .num_dsc = 3, 812 }; 813 814 #ifdef DIAGS_BUILD 815 static const struct resource_caps res_cap_rn_FPGA_4pipe = { 816 .num_timing_generator = 4, 817 .num_opp = 4, 818 .num_video_plane = 4, 819 .num_audio = 7, 820 .num_stream_encoder = 4, 821 .num_pll = 4, 822 .num_dwb = 1, 823 .num_ddc = 4, 824 .num_dsc = 0, 825 }; 826 827 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = { 828 .num_timing_generator = 2, 829 .num_opp = 2, 830 .num_video_plane = 2, 831 .num_audio = 7, 832 .num_stream_encoder = 2, 833 .num_pll = 4, 834 .num_dwb = 1, 835 .num_ddc = 4, 836 .num_dsc = 2, 837 }; 838 #endif 839 840 static const struct dc_plane_cap plane_cap = { 841 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 842 .blends_with_above = true, 843 .blends_with_below = true, 844 .per_pixel_alpha = true, 845 846 .pixel_format_support = { 847 .argb8888 = true, 848 .nv12 = true, 849 .fp16 = true, 850 .p010 = true 851 }, 852 853 .max_upscale_factor = { 854 .argb8888 = 16000, 855 .nv12 = 16000, 856 .fp16 = 16000 857 }, 858 859 .max_downscale_factor = { 860 .argb8888 = 250, 861 .nv12 = 250, 862 .fp16 = 250 863 }, 864 64, 865 64 866 }; 867 868 static const struct dc_debug_options debug_defaults_drv = { 869 .disable_dmcu = false, 870 .force_abm_enable = false, 871 .timing_trace = false, 872 .clock_trace = true, 873 .disable_pplib_clock_request = true, 874 .min_disp_clk_khz = 100000, 875 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 876 .force_single_disp_pipe_split = false, 877 .disable_dcc = DCC_ENABLE, 878 .vsr_support = true, 879 .performance_trace = false, 880 .max_downscale_src_width = 4096, 881 .disable_pplib_wm_range = false, 882 .scl_reset_length10 = true, 883 .sanity_checks = true, 884 .disable_48mhz_pwrdwn = false, 885 .usbc_combo_phy_reset_wa = true, 886 .dmub_command_table = true, 887 .use_max_lb = true, 888 .optimize_edp_link_rate = true 889 }; 890 891 static const struct dc_debug_options debug_defaults_diags = { 892 .disable_dmcu = false, 893 .force_abm_enable = false, 894 .timing_trace = true, 895 .clock_trace = true, 896 .disable_dpp_power_gate = true, 897 .disable_hubp_power_gate = true, 898 .disable_clock_gate = true, 899 .disable_pplib_clock_request = true, 900 .disable_pplib_wm_range = true, 901 .disable_stutter = true, 902 .disable_48mhz_pwrdwn = true, 903 .disable_psr = true, 904 .enable_tri_buf = true, 905 .use_max_lb = true 906 }; 907 908 enum dcn20_clk_src_array_id { 909 DCN20_CLK_SRC_PLL0, 910 DCN20_CLK_SRC_PLL1, 911 DCN20_CLK_SRC_PLL2, 912 DCN20_CLK_SRC_PLL3, 913 DCN20_CLK_SRC_PLL4, 914 DCN20_CLK_SRC_TOTAL_DCN21 915 }; 916 917 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) 918 { 919 unsigned int i; 920 921 for (i = 0; i < pool->base.stream_enc_count; i++) { 922 if (pool->base.stream_enc[i] != NULL) { 923 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 924 pool->base.stream_enc[i] = NULL; 925 } 926 } 927 928 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 929 if (pool->base.dscs[i] != NULL) 930 dcn20_dsc_destroy(&pool->base.dscs[i]); 931 } 932 933 if (pool->base.mpc != NULL) { 934 kfree(TO_DCN20_MPC(pool->base.mpc)); 935 pool->base.mpc = NULL; 936 } 937 if (pool->base.hubbub != NULL) { 938 kfree(pool->base.hubbub); 939 pool->base.hubbub = NULL; 940 } 941 for (i = 0; i < pool->base.pipe_count; i++) { 942 if (pool->base.dpps[i] != NULL) 943 dcn20_dpp_destroy(&pool->base.dpps[i]); 944 945 if (pool->base.ipps[i] != NULL) 946 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 947 948 if (pool->base.hubps[i] != NULL) { 949 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 950 pool->base.hubps[i] = NULL; 951 } 952 953 if (pool->base.irqs != NULL) { 954 dal_irq_service_destroy(&pool->base.irqs); 955 } 956 } 957 958 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 959 if (pool->base.engines[i] != NULL) 960 dce110_engine_destroy(&pool->base.engines[i]); 961 if (pool->base.hw_i2cs[i] != NULL) { 962 kfree(pool->base.hw_i2cs[i]); 963 pool->base.hw_i2cs[i] = NULL; 964 } 965 if (pool->base.sw_i2cs[i] != NULL) { 966 kfree(pool->base.sw_i2cs[i]); 967 pool->base.sw_i2cs[i] = NULL; 968 } 969 } 970 971 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 972 if (pool->base.opps[i] != NULL) 973 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 974 } 975 976 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 977 if (pool->base.timing_generators[i] != NULL) { 978 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 979 pool->base.timing_generators[i] = NULL; 980 } 981 } 982 983 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 984 if (pool->base.dwbc[i] != NULL) { 985 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); 986 pool->base.dwbc[i] = NULL; 987 } 988 if (pool->base.mcif_wb[i] != NULL) { 989 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); 990 pool->base.mcif_wb[i] = NULL; 991 } 992 } 993 994 for (i = 0; i < pool->base.audio_count; i++) { 995 if (pool->base.audios[i]) 996 dce_aud_destroy(&pool->base.audios[i]); 997 } 998 999 for (i = 0; i < pool->base.clk_src_count; i++) { 1000 if (pool->base.clock_sources[i] != NULL) { 1001 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1002 pool->base.clock_sources[i] = NULL; 1003 } 1004 } 1005 1006 if (pool->base.dp_clock_source != NULL) { 1007 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1008 pool->base.dp_clock_source = NULL; 1009 } 1010 1011 if (pool->base.abm != NULL) { 1012 if (pool->base.abm->ctx->dc->config.disable_dmcu) 1013 dmub_abm_destroy(&pool->base.abm); 1014 else 1015 dce_abm_destroy(&pool->base.abm); 1016 } 1017 1018 if (pool->base.dmcu != NULL) 1019 dce_dmcu_destroy(&pool->base.dmcu); 1020 1021 if (pool->base.psr != NULL) 1022 dmub_psr_destroy(&pool->base.psr); 1023 1024 if (pool->base.dccg != NULL) 1025 dcn_dccg_destroy(&pool->base.dccg); 1026 1027 if (pool->base.pp_smu != NULL) 1028 dcn21_pp_smu_destroy(&pool->base.pp_smu); 1029 } 1030 1031 1032 static void calculate_wm_set_for_vlevel( 1033 int vlevel, 1034 struct wm_range_table_entry *table_entry, 1035 struct dcn_watermarks *wm_set, 1036 struct display_mode_lib *dml, 1037 display_e2e_pipe_params_st *pipes, 1038 int pipe_cnt) 1039 { 1040 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; 1041 1042 ASSERT(vlevel < dml->soc.num_states); 1043 /* only pipe 0 is read for voltage and dcf/soc clocks */ 1044 pipes[0].clks_cfg.voltage = vlevel; 1045 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; 1046 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; 1047 1048 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; 1049 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; 1050 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; 1051 1052 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; 1053 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; 1054 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; 1055 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 1056 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; 1057 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; 1058 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; 1059 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000; 1060 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; 1061 1062 } 1063 1064 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) 1065 { 1066 int i; 1067 1068 if (dc->bb_overrides.sr_exit_time_ns) { 1069 for (i = 0; i < WM_SET_COUNT; i++) { 1070 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us = 1071 dc->bb_overrides.sr_exit_time_ns / 1000.0; 1072 } 1073 } 1074 1075 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) { 1076 for (i = 0; i < WM_SET_COUNT; i++) { 1077 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us = 1078 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 1079 } 1080 } 1081 1082 if (dc->bb_overrides.urgent_latency_ns) { 1083 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 1084 } 1085 1086 if (dc->bb_overrides.dram_clock_change_latency_ns) { 1087 for (i = 0; i < WM_SET_COUNT; i++) { 1088 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us = 1089 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 1090 } 1091 } 1092 } 1093 1094 void dcn21_calculate_wm( 1095 struct dc *dc, struct dc_state *context, 1096 display_e2e_pipe_params_st *pipes, 1097 int *out_pipe_cnt, 1098 int *pipe_split_from, 1099 int vlevel_req, 1100 bool fast_validate) 1101 { 1102 int pipe_cnt, i, pipe_idx; 1103 int vlevel, vlevel_max; 1104 struct wm_range_table_entry *table_entry; 1105 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; 1106 1107 ASSERT(bw_params); 1108 1109 patch_bounding_box(dc, &context->bw_ctx.dml.soc); 1110 1111 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1112 if (!context->res_ctx.pipe_ctx[i].stream) 1113 continue; 1114 1115 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 1116 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb]; 1117 1118 if (pipe_split_from[i] < 0) { 1119 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1120 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; 1121 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) 1122 pipes[pipe_cnt].pipe.dest.odm_combine = 1123 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx]; 1124 else 1125 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1126 pipe_idx++; 1127 } else { 1128 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1129 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; 1130 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) 1131 pipes[pipe_cnt].pipe.dest.odm_combine = 1132 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]]; 1133 else 1134 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1135 } 1136 pipe_cnt++; 1137 } 1138 1139 if (pipe_cnt != pipe_idx) { 1140 if (dc->res_pool->funcs->populate_dml_pipes) 1141 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, 1142 context, pipes, fast_validate); 1143 else 1144 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc, 1145 context, pipes, fast_validate); 1146 } 1147 1148 *out_pipe_cnt = pipe_cnt; 1149 1150 vlevel_max = bw_params->clk_table.num_entries - 1; 1151 1152 1153 /* WM Set D */ 1154 table_entry = &bw_params->wm_table.entries[WM_D]; 1155 if (table_entry->wm_type == WM_TYPE_RETRAINING) 1156 vlevel = 0; 1157 else 1158 vlevel = vlevel_max; 1159 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, 1160 &context->bw_ctx.dml, pipes, pipe_cnt); 1161 /* WM Set C */ 1162 table_entry = &bw_params->wm_table.entries[WM_C]; 1163 vlevel = MIN(MAX(vlevel_req, 3), vlevel_max); 1164 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, 1165 &context->bw_ctx.dml, pipes, pipe_cnt); 1166 /* WM Set B */ 1167 table_entry = &bw_params->wm_table.entries[WM_B]; 1168 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max); 1169 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, 1170 &context->bw_ctx.dml, pipes, pipe_cnt); 1171 1172 /* WM Set A */ 1173 table_entry = &bw_params->wm_table.entries[WM_A]; 1174 vlevel = MIN(vlevel_req, vlevel_max); 1175 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, 1176 &context->bw_ctx.dml, pipes, pipe_cnt); 1177 } 1178 1179 1180 static bool dcn21_fast_validate_bw( 1181 struct dc *dc, 1182 struct dc_state *context, 1183 display_e2e_pipe_params_st *pipes, 1184 int *pipe_cnt_out, 1185 int *pipe_split_from, 1186 int *vlevel_out, 1187 bool fast_validate) 1188 { 1189 bool out = false; 1190 int split[MAX_PIPES] = { 0 }; 1191 int pipe_cnt, i, pipe_idx, vlevel; 1192 1193 ASSERT(pipes); 1194 if (!pipes) 1195 return false; 1196 1197 dcn20_merge_pipes_for_validate(dc, context); 1198 1199 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 1200 1201 *pipe_cnt_out = pipe_cnt; 1202 1203 if (!pipe_cnt) { 1204 out = true; 1205 goto validate_out; 1206 } 1207 /* 1208 * DML favors voltage over p-state, but we're more interested in 1209 * supporting p-state over voltage. We can't support p-state in 1210 * prefetch mode > 0 so try capping the prefetch mode to start. 1211 */ 1212 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = 1213 dm_allow_self_refresh_and_mclk_switch; 1214 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1215 1216 if (vlevel > context->bw_ctx.dml.soc.num_states) { 1217 /* 1218 * If mode is unsupported or there's still no p-state support then 1219 * fall back to favoring voltage. 1220 * 1221 * We don't actually support prefetch mode 2, so require that we 1222 * at least support prefetch mode 1. 1223 */ 1224 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = 1225 dm_allow_self_refresh; 1226 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1227 if (vlevel > context->bw_ctx.dml.soc.num_states) 1228 goto validate_fail; 1229 } 1230 1231 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL); 1232 1233 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1234 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1235 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe; 1236 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 1237 1238 if (!pipe->stream) 1239 continue; 1240 1241 /* We only support full screen mpo with ODM */ 1242 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled 1243 && pipe->plane_state && mpo_pipe 1244 && memcmp(&mpo_pipe->plane_res.scl_data.recout, 1245 &pipe->plane_res.scl_data.recout, 1246 sizeof(struct rect)) != 0) { 1247 ASSERT(mpo_pipe->plane_state != pipe->plane_state); 1248 goto validate_fail; 1249 } 1250 pipe_idx++; 1251 } 1252 1253 /*initialize pipe_just_split_from to invalid idx*/ 1254 for (i = 0; i < MAX_PIPES; i++) 1255 pipe_split_from[i] = -1; 1256 1257 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { 1258 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1259 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 1260 1261 if (!pipe->stream || pipe_split_from[i] >= 0) 1262 continue; 1263 1264 pipe_idx++; 1265 1266 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 1267 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 1268 ASSERT(hsplit_pipe); 1269 if (!dcn20_split_stream_for_odm( 1270 dc, &context->res_ctx, 1271 pipe, hsplit_pipe)) 1272 goto validate_fail; 1273 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 1274 dcn20_build_mapped_resource(dc, context, pipe->stream); 1275 } 1276 1277 if (!pipe->plane_state) 1278 continue; 1279 /* Skip 2nd half of already split pipe */ 1280 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state) 1281 continue; 1282 1283 if (split[i] == 2) { 1284 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) { 1285 /* pipe not split previously needs split */ 1286 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 1287 ASSERT(hsplit_pipe); 1288 if (!hsplit_pipe) { 1289 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2; 1290 continue; 1291 } 1292 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 1293 if (!dcn20_split_stream_for_odm( 1294 dc, &context->res_ctx, 1295 pipe, hsplit_pipe)) 1296 goto validate_fail; 1297 dcn20_build_mapped_resource(dc, context, pipe->stream); 1298 } else { 1299 dcn20_split_stream_for_mpc( 1300 &context->res_ctx, dc->res_pool, 1301 pipe, hsplit_pipe); 1302 resource_build_scaling_params(pipe); 1303 resource_build_scaling_params(hsplit_pipe); 1304 } 1305 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 1306 } 1307 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { 1308 /* merge should already have been done */ 1309 ASSERT(0); 1310 } 1311 } 1312 /* Actual dsc count per stream dsc validation*/ 1313 if (!dcn20_validate_dsc(dc, context)) { 1314 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = 1315 DML_FAIL_DSC_VALIDATION_FAILURE; 1316 goto validate_fail; 1317 } 1318 1319 *vlevel_out = vlevel; 1320 1321 out = true; 1322 goto validate_out; 1323 1324 validate_fail: 1325 out = false; 1326 1327 validate_out: 1328 return out; 1329 } 1330 1331 static noinline bool dcn21_validate_bandwidth_fp(struct dc *dc, 1332 struct dc_state *context, bool fast_validate) 1333 { 1334 bool out = false; 1335 1336 BW_VAL_TRACE_SETUP(); 1337 1338 int vlevel = 0; 1339 int pipe_split_from[MAX_PIPES]; 1340 int pipe_cnt = 0; 1341 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC); 1342 DC_LOGGER_INIT(dc->ctx->logger); 1343 1344 BW_VAL_TRACE_COUNT(); 1345 1346 /*Unsafe due to current pipe merge and split logic*/ 1347 ASSERT(context != dc->current_state); 1348 1349 out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate); 1350 1351 if (pipe_cnt == 0) 1352 goto validate_out; 1353 1354 if (!out) 1355 goto validate_fail; 1356 1357 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1358 1359 if (fast_validate) { 1360 BW_VAL_TRACE_SKIP(fast); 1361 goto validate_out; 1362 } 1363 1364 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate); 1365 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 1366 1367 BW_VAL_TRACE_END_WATERMARKS(); 1368 1369 goto validate_out; 1370 1371 validate_fail: 1372 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1373 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1374 1375 BW_VAL_TRACE_SKIP(fail); 1376 out = false; 1377 1378 validate_out: 1379 kfree(pipes); 1380 1381 BW_VAL_TRACE_FINISH(); 1382 1383 return out; 1384 } 1385 1386 /* 1387 * Some of the functions further below use the FPU, so we need to wrap this 1388 * with DC_FP_START()/DC_FP_END(). Use the same approach as for 1389 * dcn20_validate_bandwidth in dcn20_resource.c. 1390 */ 1391 bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context, 1392 bool fast_validate) 1393 { 1394 bool voltage_supported; 1395 DC_FP_START(); 1396 voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate); 1397 DC_FP_END(); 1398 return voltage_supported; 1399 } 1400 1401 static void dcn21_destroy_resource_pool(struct resource_pool **pool) 1402 { 1403 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool); 1404 1405 dcn21_resource_destruct(dcn21_pool); 1406 kfree(dcn21_pool); 1407 *pool = NULL; 1408 } 1409 1410 static struct clock_source *dcn21_clock_source_create( 1411 struct dc_context *ctx, 1412 struct dc_bios *bios, 1413 enum clock_source_id id, 1414 const struct dce110_clk_src_regs *regs, 1415 bool dp_clk_src) 1416 { 1417 struct dce110_clk_src *clk_src = 1418 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1419 1420 if (!clk_src) 1421 return NULL; 1422 1423 if (dcn20_clk_src_construct(clk_src, ctx, bios, id, 1424 regs, &cs_shift, &cs_mask)) { 1425 clk_src->base.dp_clk_src = dp_clk_src; 1426 return &clk_src->base; 1427 } 1428 1429 BREAK_TO_DEBUGGER(); 1430 return NULL; 1431 } 1432 1433 static struct hubp *dcn21_hubp_create( 1434 struct dc_context *ctx, 1435 uint32_t inst) 1436 { 1437 struct dcn21_hubp *hubp21 = 1438 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL); 1439 1440 if (!hubp21) 1441 return NULL; 1442 1443 if (hubp21_construct(hubp21, ctx, inst, 1444 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1445 return &hubp21->base; 1446 1447 BREAK_TO_DEBUGGER(); 1448 kfree(hubp21); 1449 return NULL; 1450 } 1451 1452 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx) 1453 { 1454 int i; 1455 1456 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), 1457 GFP_KERNEL); 1458 1459 if (!hubbub) 1460 return NULL; 1461 1462 hubbub21_construct(hubbub, ctx, 1463 &hubbub_reg, 1464 &hubbub_shift, 1465 &hubbub_mask); 1466 1467 for (i = 0; i < res_cap_rn.num_vmid; i++) { 1468 struct dcn20_vmid *vmid = &hubbub->vmid[i]; 1469 1470 vmid->ctx = ctx; 1471 1472 vmid->regs = &vmid_regs[i]; 1473 vmid->shifts = &vmid_shifts; 1474 vmid->masks = &vmid_masks; 1475 } 1476 hubbub->num_vmid = res_cap_rn.num_vmid; 1477 1478 return &hubbub->base; 1479 } 1480 1481 struct output_pixel_processor *dcn21_opp_create( 1482 struct dc_context *ctx, uint32_t inst) 1483 { 1484 struct dcn20_opp *opp = 1485 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1486 1487 if (!opp) { 1488 BREAK_TO_DEBUGGER(); 1489 return NULL; 1490 } 1491 1492 dcn20_opp_construct(opp, ctx, inst, 1493 &opp_regs[inst], &opp_shift, &opp_mask); 1494 return &opp->base; 1495 } 1496 1497 struct timing_generator *dcn21_timing_generator_create( 1498 struct dc_context *ctx, 1499 uint32_t instance) 1500 { 1501 struct optc *tgn10 = 1502 kzalloc(sizeof(struct optc), GFP_KERNEL); 1503 1504 if (!tgn10) 1505 return NULL; 1506 1507 tgn10->base.inst = instance; 1508 tgn10->base.ctx = ctx; 1509 1510 tgn10->tg_regs = &tg_regs[instance]; 1511 tgn10->tg_shift = &tg_shift; 1512 tgn10->tg_mask = &tg_mask; 1513 1514 dcn20_timing_generator_init(tgn10); 1515 1516 return &tgn10->base; 1517 } 1518 1519 struct mpc *dcn21_mpc_create(struct dc_context *ctx) 1520 { 1521 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), 1522 GFP_KERNEL); 1523 1524 if (!mpc20) 1525 return NULL; 1526 1527 dcn20_mpc_construct(mpc20, ctx, 1528 &mpc_regs, 1529 &mpc_shift, 1530 &mpc_mask, 1531 6); 1532 1533 return &mpc20->base; 1534 } 1535 1536 static void read_dce_straps( 1537 struct dc_context *ctx, 1538 struct resource_straps *straps) 1539 { 1540 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1541 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1542 1543 } 1544 1545 1546 struct display_stream_compressor *dcn21_dsc_create( 1547 struct dc_context *ctx, uint32_t inst) 1548 { 1549 struct dcn20_dsc *dsc = 1550 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1551 1552 if (!dsc) { 1553 BREAK_TO_DEBUGGER(); 1554 return NULL; 1555 } 1556 1557 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1558 return &dsc->base; 1559 } 1560 1561 static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_limit_table *clk_table, unsigned int high_voltage_lvl) 1562 { 1563 struct _vcs_dpi_voltage_scaling_st low_pstate_lvl; 1564 int i; 1565 1566 low_pstate_lvl.state = 1; 1567 low_pstate_lvl.dcfclk_mhz = clk_table->entries[0].dcfclk_mhz; 1568 low_pstate_lvl.fabricclk_mhz = clk_table->entries[0].fclk_mhz; 1569 low_pstate_lvl.socclk_mhz = clk_table->entries[0].socclk_mhz; 1570 low_pstate_lvl.dram_speed_mts = clk_table->entries[0].memclk_mhz * 2; 1571 1572 low_pstate_lvl.dispclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dispclk_mhz; 1573 low_pstate_lvl.dppclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dppclk_mhz; 1574 low_pstate_lvl.dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[high_voltage_lvl].dram_bw_per_chan_gbps; 1575 low_pstate_lvl.dscclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dscclk_mhz; 1576 low_pstate_lvl.dtbclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dtbclk_mhz; 1577 low_pstate_lvl.phyclk_d18_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_d18_mhz; 1578 low_pstate_lvl.phyclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_mhz; 1579 1580 for (i = clk_table->num_entries; i > 1; i--) 1581 clk_table->entries[i] = clk_table->entries[i-1]; 1582 clk_table->entries[1] = clk_table->entries[0]; 1583 clk_table->num_entries++; 1584 1585 return low_pstate_lvl; 1586 } 1587 1588 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1589 { 1590 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool); 1591 struct clk_limit_table *clk_table = &bw_params->clk_table; 1592 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1593 unsigned int i, closest_clk_lvl = 0, k = 0; 1594 int j; 1595 1596 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator; 1597 dcn2_1_ip.max_num_dpp = pool->base.pipe_count; 1598 dcn2_1_soc.num_chans = bw_params->num_channels; 1599 1600 ASSERT(clk_table->num_entries); 1601 /* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */ 1602 for (i = 0; i < dcn2_1_soc.num_states + 1; i++) { 1603 clock_limits[i] = dcn2_1_soc.clock_limits[i]; 1604 } 1605 1606 for (i = 0; i < clk_table->num_entries; i++) { 1607 /* loop backwards*/ 1608 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) { 1609 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { 1610 closest_clk_lvl = j; 1611 break; 1612 } 1613 } 1614 1615 /* clk_table[1] is reserved for min DF PState. skip here to fill in later. */ 1616 if (i == 1) 1617 k++; 1618 1619 clock_limits[k].state = k; 1620 clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 1621 clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 1622 clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz; 1623 clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; 1624 1625 clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; 1626 clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; 1627 clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; 1628 clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; 1629 clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; 1630 clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; 1631 clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; 1632 1633 k++; 1634 } 1635 for (i = 0; i < clk_table->num_entries + 1; i++) 1636 dcn2_1_soc.clock_limits[i] = clock_limits[i]; 1637 if (clk_table->num_entries) { 1638 dcn2_1_soc.num_states = clk_table->num_entries + 1; 1639 /* fill in min DF PState */ 1640 dcn2_1_soc.clock_limits[1] = construct_low_pstate_lvl(clk_table, closest_clk_lvl); 1641 /* duplicate last level */ 1642 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1]; 1643 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states; 1644 } 1645 1646 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); 1647 } 1648 1649 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx) 1650 { 1651 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 1652 1653 if (!pp_smu) 1654 return pp_smu; 1655 1656 dm_pp_get_funcs(ctx, pp_smu); 1657 1658 if (pp_smu->ctx.ver != PP_SMU_VER_RN) 1659 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); 1660 1661 1662 return pp_smu; 1663 } 1664 1665 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu) 1666 { 1667 if (pp_smu && *pp_smu) { 1668 kfree(*pp_smu); 1669 *pp_smu = NULL; 1670 } 1671 } 1672 1673 static struct audio *dcn21_create_audio( 1674 struct dc_context *ctx, unsigned int inst) 1675 { 1676 return dce_audio_create(ctx, inst, 1677 &audio_regs[inst], &audio_shift, &audio_mask); 1678 } 1679 1680 static struct dc_cap_funcs cap_funcs = { 1681 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1682 }; 1683 1684 struct stream_encoder *dcn21_stream_encoder_create( 1685 enum engine_id eng_id, 1686 struct dc_context *ctx) 1687 { 1688 struct dcn10_stream_encoder *enc1 = 1689 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1690 1691 if (!enc1) 1692 return NULL; 1693 1694 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1695 &stream_enc_regs[eng_id], 1696 &se_shift, &se_mask); 1697 1698 return &enc1->base; 1699 } 1700 1701 static const struct dce_hwseq_registers hwseq_reg = { 1702 HWSEQ_DCN21_REG_LIST() 1703 }; 1704 1705 static const struct dce_hwseq_shift hwseq_shift = { 1706 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT) 1707 }; 1708 1709 static const struct dce_hwseq_mask hwseq_mask = { 1710 HWSEQ_DCN21_MASK_SH_LIST(_MASK) 1711 }; 1712 1713 static struct dce_hwseq *dcn21_hwseq_create( 1714 struct dc_context *ctx) 1715 { 1716 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1717 1718 if (hws) { 1719 hws->ctx = ctx; 1720 hws->regs = &hwseq_reg; 1721 hws->shifts = &hwseq_shift; 1722 hws->masks = &hwseq_mask; 1723 hws->wa.DEGVIDCN21 = true; 1724 hws->wa.disallow_self_refresh_during_multi_plane_transition = true; 1725 } 1726 return hws; 1727 } 1728 1729 static const struct resource_create_funcs res_create_funcs = { 1730 .read_dce_straps = read_dce_straps, 1731 .create_audio = dcn21_create_audio, 1732 .create_stream_encoder = dcn21_stream_encoder_create, 1733 .create_hwseq = dcn21_hwseq_create, 1734 }; 1735 1736 static const struct resource_create_funcs res_create_maximus_funcs = { 1737 .read_dce_straps = NULL, 1738 .create_audio = NULL, 1739 .create_stream_encoder = NULL, 1740 .create_hwseq = dcn21_hwseq_create, 1741 }; 1742 1743 static const struct encoder_feature_support link_enc_feature = { 1744 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1745 .max_hdmi_pixel_clock = 600000, 1746 .hdmi_ycbcr420_supported = true, 1747 .dp_ycbcr420_supported = true, 1748 .fec_supported = true, 1749 .flags.bits.IS_HBR2_CAPABLE = true, 1750 .flags.bits.IS_HBR3_CAPABLE = true, 1751 .flags.bits.IS_TPS3_CAPABLE = true, 1752 .flags.bits.IS_TPS4_CAPABLE = true 1753 }; 1754 1755 1756 #define link_regs(id, phyid)\ 1757 [id] = {\ 1758 LE_DCN2_REG_LIST(id), \ 1759 UNIPHY_DCN2_REG_LIST(phyid), \ 1760 DPCS_DCN21_REG_LIST(id), \ 1761 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 1762 } 1763 1764 static const struct dcn10_link_enc_registers link_enc_regs[] = { 1765 link_regs(0, A), 1766 link_regs(1, B), 1767 link_regs(2, C), 1768 link_regs(3, D), 1769 link_regs(4, E), 1770 }; 1771 1772 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 1773 { DCN_PANEL_CNTL_REG_LIST() } 1774 }; 1775 1776 static const struct dce_panel_cntl_shift panel_cntl_shift = { 1777 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 1778 }; 1779 1780 static const struct dce_panel_cntl_mask panel_cntl_mask = { 1781 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 1782 }; 1783 1784 #define aux_regs(id)\ 1785 [id] = {\ 1786 DCN2_AUX_REG_LIST(id)\ 1787 } 1788 1789 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 1790 aux_regs(0), 1791 aux_regs(1), 1792 aux_regs(2), 1793 aux_regs(3), 1794 aux_regs(4) 1795 }; 1796 1797 #define hpd_regs(id)\ 1798 [id] = {\ 1799 HPD_REG_LIST(id)\ 1800 } 1801 1802 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 1803 hpd_regs(0), 1804 hpd_regs(1), 1805 hpd_regs(2), 1806 hpd_regs(3), 1807 hpd_regs(4) 1808 }; 1809 1810 static const struct dcn10_link_enc_shift le_shift = { 1811 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\ 1812 DPCS_DCN21_MASK_SH_LIST(__SHIFT) 1813 }; 1814 1815 static const struct dcn10_link_enc_mask le_mask = { 1816 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\ 1817 DPCS_DCN21_MASK_SH_LIST(_MASK) 1818 }; 1819 1820 static int map_transmitter_id_to_phy_instance( 1821 enum transmitter transmitter) 1822 { 1823 switch (transmitter) { 1824 case TRANSMITTER_UNIPHY_A: 1825 return 0; 1826 break; 1827 case TRANSMITTER_UNIPHY_B: 1828 return 1; 1829 break; 1830 case TRANSMITTER_UNIPHY_C: 1831 return 2; 1832 break; 1833 case TRANSMITTER_UNIPHY_D: 1834 return 3; 1835 break; 1836 case TRANSMITTER_UNIPHY_E: 1837 return 4; 1838 break; 1839 default: 1840 ASSERT(0); 1841 return 0; 1842 } 1843 } 1844 1845 static struct link_encoder *dcn21_link_encoder_create( 1846 const struct encoder_init_data *enc_init_data) 1847 { 1848 struct dcn21_link_encoder *enc21 = 1849 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL); 1850 int link_regs_id; 1851 1852 if (!enc21) 1853 return NULL; 1854 1855 link_regs_id = 1856 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 1857 1858 dcn21_link_encoder_construct(enc21, 1859 enc_init_data, 1860 &link_enc_feature, 1861 &link_enc_regs[link_regs_id], 1862 &link_enc_aux_regs[enc_init_data->channel - 1], 1863 &link_enc_hpd_regs[enc_init_data->hpd_source], 1864 &le_shift, 1865 &le_mask); 1866 1867 return &enc21->enc10.base; 1868 } 1869 1870 static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1871 { 1872 struct dce_panel_cntl *panel_cntl = 1873 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 1874 1875 if (!panel_cntl) 1876 return NULL; 1877 1878 dce_panel_cntl_construct(panel_cntl, 1879 init_data, 1880 &panel_cntl_regs[init_data->inst], 1881 &panel_cntl_shift, 1882 &panel_cntl_mask); 1883 1884 return &panel_cntl->base; 1885 } 1886 1887 #define CTX ctx 1888 1889 #define REG(reg_name) \ 1890 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 1891 1892 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1893 { 1894 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 1895 /* RV1 support max 4 pipes */ 1896 value = value & 0xf; 1897 return value; 1898 } 1899 1900 static int dcn21_populate_dml_pipes_from_context( 1901 struct dc *dc, 1902 struct dc_state *context, 1903 display_e2e_pipe_params_st *pipes, 1904 bool fast_validate) 1905 { 1906 uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1907 int i; 1908 1909 for (i = 0; i < pipe_cnt; i++) { 1910 1911 pipes[i].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active; 1912 pipes[i].pipe.src.gpuvm = 1; 1913 } 1914 1915 return pipe_cnt; 1916 } 1917 1918 enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state) 1919 { 1920 enum dc_status result = DC_OK; 1921 1922 if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) { 1923 plane_state->dcc.enable = 1; 1924 /* align to our worst case block width */ 1925 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024; 1926 } 1927 result = dcn20_patch_unknown_plane_state(plane_state); 1928 return result; 1929 } 1930 1931 static const struct resource_funcs dcn21_res_pool_funcs = { 1932 .destroy = dcn21_destroy_resource_pool, 1933 .link_enc_create = dcn21_link_encoder_create, 1934 .panel_cntl_create = dcn21_panel_cntl_create, 1935 .validate_bandwidth = dcn21_validate_bandwidth, 1936 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context, 1937 .add_stream_to_ctx = dcn20_add_stream_to_ctx, 1938 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1939 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1940 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1941 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, 1942 .patch_unknown_plane_state = dcn21_patch_unknown_plane_state, 1943 .set_mcif_arb_params = dcn20_set_mcif_arb_params, 1944 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1945 .update_bw_bounding_box = update_bw_bounding_box 1946 }; 1947 1948 static bool dcn21_resource_construct( 1949 uint8_t num_virtual_links, 1950 struct dc *dc, 1951 struct dcn21_resource_pool *pool) 1952 { 1953 int i, j; 1954 struct dc_context *ctx = dc->ctx; 1955 struct irq_service_init_data init_data; 1956 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1957 uint32_t num_pipes; 1958 1959 ctx->dc_bios->regs = &bios_regs; 1960 1961 pool->base.res_cap = &res_cap_rn; 1962 #ifdef DIAGS_BUILD 1963 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1964 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc; 1965 pool->base.res_cap = &res_cap_rn_FPGA_4pipe; 1966 #endif 1967 1968 pool->base.funcs = &dcn21_res_pool_funcs; 1969 1970 /************************************************* 1971 * Resource + asic cap harcoding * 1972 *************************************************/ 1973 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1974 1975 /* max pipe num for ASIC before check pipe fuses */ 1976 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1977 1978 dc->caps.max_downscale_ratio = 200; 1979 dc->caps.i2c_speed_in_khz = 100; 1980 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/ 1981 dc->caps.max_cursor_size = 256; 1982 dc->caps.min_horizontal_blanking_period = 80; 1983 dc->caps.dmdata_alloc_size = 2048; 1984 1985 dc->caps.max_slave_planes = 1; 1986 dc->caps.max_slave_yuv_planes = 1; 1987 dc->caps.max_slave_rgb_planes = 1; 1988 dc->caps.post_blend_color_processing = true; 1989 dc->caps.force_dp_tps4_for_cp2520 = true; 1990 dc->caps.extended_aux_timeout_support = true; 1991 dc->caps.dmcub_support = true; 1992 dc->caps.is_apu = true; 1993 1994 /* Color pipeline capabilities */ 1995 dc->caps.color.dpp.dcn_arch = 1; 1996 dc->caps.color.dpp.input_lut_shared = 0; 1997 dc->caps.color.dpp.icsc = 1; 1998 dc->caps.color.dpp.dgam_ram = 1; 1999 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2000 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2001 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0; 2002 dc->caps.color.dpp.dgam_rom_caps.pq = 0; 2003 dc->caps.color.dpp.dgam_rom_caps.hlg = 0; 2004 dc->caps.color.dpp.post_csc = 0; 2005 dc->caps.color.dpp.gamma_corr = 0; 2006 dc->caps.color.dpp.dgam_rom_for_yuv = 1; 2007 2008 dc->caps.color.dpp.hw_3d_lut = 1; 2009 dc->caps.color.dpp.ogam_ram = 1; 2010 // no OGAM ROM on DCN2 2011 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2012 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2013 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2014 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2015 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2016 dc->caps.color.dpp.ocsc = 0; 2017 2018 dc->caps.color.mpc.gamut_remap = 0; 2019 dc->caps.color.mpc.num_3dluts = 0; 2020 dc->caps.color.mpc.shared_3d_lut = 0; 2021 dc->caps.color.mpc.ogam_ram = 1; 2022 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2023 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2024 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2025 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2026 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2027 dc->caps.color.mpc.ocsc = 1; 2028 2029 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2030 dc->debug = debug_defaults_drv; 2031 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 2032 pool->base.pipe_count = 4; 2033 dc->debug = debug_defaults_diags; 2034 } else 2035 dc->debug = debug_defaults_diags; 2036 2037 // Init the vm_helper 2038 if (dc->vm_helper) 2039 vm_helper_init(dc->vm_helper, 16); 2040 2041 /************************************************* 2042 * Create resources * 2043 *************************************************/ 2044 2045 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = 2046 dcn21_clock_source_create(ctx, ctx->dc_bios, 2047 CLOCK_SOURCE_COMBO_PHY_PLL0, 2048 &clk_src_regs[0], false); 2049 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = 2050 dcn21_clock_source_create(ctx, ctx->dc_bios, 2051 CLOCK_SOURCE_COMBO_PHY_PLL1, 2052 &clk_src_regs[1], false); 2053 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = 2054 dcn21_clock_source_create(ctx, ctx->dc_bios, 2055 CLOCK_SOURCE_COMBO_PHY_PLL2, 2056 &clk_src_regs[2], false); 2057 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] = 2058 dcn21_clock_source_create(ctx, ctx->dc_bios, 2059 CLOCK_SOURCE_COMBO_PHY_PLL3, 2060 &clk_src_regs[3], false); 2061 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] = 2062 dcn21_clock_source_create(ctx, ctx->dc_bios, 2063 CLOCK_SOURCE_COMBO_PHY_PLL4, 2064 &clk_src_regs[4], false); 2065 2066 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21; 2067 2068 /* todo: not reuse phy_pll registers */ 2069 pool->base.dp_clock_source = 2070 dcn21_clock_source_create(ctx, ctx->dc_bios, 2071 CLOCK_SOURCE_ID_DP_DTO, 2072 &clk_src_regs[0], true); 2073 2074 for (i = 0; i < pool->base.clk_src_count; i++) { 2075 if (pool->base.clock_sources[i] == NULL) { 2076 dm_error("DC: failed to create clock sources!\n"); 2077 BREAK_TO_DEBUGGER(); 2078 goto create_fail; 2079 } 2080 } 2081 2082 pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2083 if (pool->base.dccg == NULL) { 2084 dm_error("DC: failed to create dccg!\n"); 2085 BREAK_TO_DEBUGGER(); 2086 goto create_fail; 2087 } 2088 2089 if (!dc->config.disable_dmcu) { 2090 pool->base.dmcu = dcn21_dmcu_create(ctx, 2091 &dmcu_regs, 2092 &dmcu_shift, 2093 &dmcu_mask); 2094 if (pool->base.dmcu == NULL) { 2095 dm_error("DC: failed to create dmcu!\n"); 2096 BREAK_TO_DEBUGGER(); 2097 goto create_fail; 2098 } 2099 2100 dc->debug.dmub_command_table = false; 2101 } 2102 2103 if (dc->config.disable_dmcu) { 2104 pool->base.psr = dmub_psr_create(ctx); 2105 2106 if (pool->base.psr == NULL) { 2107 dm_error("DC: failed to create psr obj!\n"); 2108 BREAK_TO_DEBUGGER(); 2109 goto create_fail; 2110 } 2111 } 2112 2113 if (dc->config.disable_dmcu) 2114 pool->base.abm = dmub_abm_create(ctx, 2115 &abm_regs, 2116 &abm_shift, 2117 &abm_mask); 2118 else 2119 pool->base.abm = dce_abm_create(ctx, 2120 &abm_regs, 2121 &abm_shift, 2122 &abm_mask); 2123 2124 pool->base.pp_smu = dcn21_pp_smu_create(ctx); 2125 2126 num_pipes = dcn2_1_ip.max_num_dpp; 2127 2128 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++) 2129 if (pipe_fuses & 1 << i) 2130 num_pipes--; 2131 dcn2_1_ip.max_num_dpp = num_pipes; 2132 dcn2_1_ip.max_num_otg = num_pipes; 2133 2134 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); 2135 2136 init_data.ctx = dc->ctx; 2137 pool->base.irqs = dal_irq_service_dcn21_create(&init_data); 2138 if (!pool->base.irqs) 2139 goto create_fail; 2140 2141 j = 0; 2142 /* mem input -> ipp -> dpp -> opp -> TG */ 2143 for (i = 0; i < pool->base.pipe_count; i++) { 2144 /* if pipe is disabled, skip instance of HW pipe, 2145 * i.e, skip ASIC register instance 2146 */ 2147 if ((pipe_fuses & (1 << i)) != 0) 2148 continue; 2149 2150 pool->base.hubps[j] = dcn21_hubp_create(ctx, i); 2151 if (pool->base.hubps[j] == NULL) { 2152 BREAK_TO_DEBUGGER(); 2153 dm_error( 2154 "DC: failed to create memory input!\n"); 2155 goto create_fail; 2156 } 2157 2158 pool->base.ipps[j] = dcn21_ipp_create(ctx, i); 2159 if (pool->base.ipps[j] == NULL) { 2160 BREAK_TO_DEBUGGER(); 2161 dm_error( 2162 "DC: failed to create input pixel processor!\n"); 2163 goto create_fail; 2164 } 2165 2166 pool->base.dpps[j] = dcn21_dpp_create(ctx, i); 2167 if (pool->base.dpps[j] == NULL) { 2168 BREAK_TO_DEBUGGER(); 2169 dm_error( 2170 "DC: failed to create dpps!\n"); 2171 goto create_fail; 2172 } 2173 2174 pool->base.opps[j] = dcn21_opp_create(ctx, i); 2175 if (pool->base.opps[j] == NULL) { 2176 BREAK_TO_DEBUGGER(); 2177 dm_error( 2178 "DC: failed to create output pixel processor!\n"); 2179 goto create_fail; 2180 } 2181 2182 pool->base.timing_generators[j] = dcn21_timing_generator_create( 2183 ctx, i); 2184 if (pool->base.timing_generators[j] == NULL) { 2185 BREAK_TO_DEBUGGER(); 2186 dm_error("DC: failed to create tg!\n"); 2187 goto create_fail; 2188 } 2189 j++; 2190 } 2191 2192 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2193 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i); 2194 if (pool->base.engines[i] == NULL) { 2195 BREAK_TO_DEBUGGER(); 2196 dm_error( 2197 "DC:failed to create aux engine!!\n"); 2198 goto create_fail; 2199 } 2200 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i); 2201 if (pool->base.hw_i2cs[i] == NULL) { 2202 BREAK_TO_DEBUGGER(); 2203 dm_error( 2204 "DC:failed to create hw i2c!!\n"); 2205 goto create_fail; 2206 } 2207 pool->base.sw_i2cs[i] = NULL; 2208 } 2209 2210 pool->base.timing_generator_count = j; 2211 pool->base.pipe_count = j; 2212 pool->base.mpcc_count = j; 2213 2214 pool->base.mpc = dcn21_mpc_create(ctx); 2215 if (pool->base.mpc == NULL) { 2216 BREAK_TO_DEBUGGER(); 2217 dm_error("DC: failed to create mpc!\n"); 2218 goto create_fail; 2219 } 2220 2221 pool->base.hubbub = dcn21_hubbub_create(ctx); 2222 if (pool->base.hubbub == NULL) { 2223 BREAK_TO_DEBUGGER(); 2224 dm_error("DC: failed to create hubbub!\n"); 2225 goto create_fail; 2226 } 2227 2228 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2229 pool->base.dscs[i] = dcn21_dsc_create(ctx, i); 2230 if (pool->base.dscs[i] == NULL) { 2231 BREAK_TO_DEBUGGER(); 2232 dm_error("DC: failed to create display stream compressor %d!\n", i); 2233 goto create_fail; 2234 } 2235 } 2236 2237 if (!dcn20_dwbc_create(ctx, &pool->base)) { 2238 BREAK_TO_DEBUGGER(); 2239 dm_error("DC: failed to create dwbc!\n"); 2240 goto create_fail; 2241 } 2242 if (!dcn20_mmhubbub_create(ctx, &pool->base)) { 2243 BREAK_TO_DEBUGGER(); 2244 dm_error("DC: failed to create mcif_wb!\n"); 2245 goto create_fail; 2246 } 2247 2248 if (!resource_construct(num_virtual_links, dc, &pool->base, 2249 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2250 &res_create_funcs : &res_create_maximus_funcs))) 2251 goto create_fail; 2252 2253 dcn21_hw_sequencer_construct(dc); 2254 2255 dc->caps.max_planes = pool->base.pipe_count; 2256 2257 for (i = 0; i < dc->caps.max_planes; ++i) 2258 dc->caps.planes[i] = plane_cap; 2259 2260 dc->cap_funcs = cap_funcs; 2261 2262 return true; 2263 2264 create_fail: 2265 2266 dcn21_resource_destruct(pool); 2267 2268 return false; 2269 } 2270 2271 struct resource_pool *dcn21_create_resource_pool( 2272 const struct dc_init_data *init_data, 2273 struct dc *dc) 2274 { 2275 struct dcn21_resource_pool *pool = 2276 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL); 2277 2278 if (!pool) 2279 return NULL; 2280 2281 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool)) 2282 return &pool->base; 2283 2284 BREAK_TO_DEBUGGER(); 2285 kfree(pool); 2286 return NULL; 2287 } 2288