1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * Copyright 2019 Raptor Engineering, LLC 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 #include "dc.h" 31 32 #include "dcn21_init.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dcn20/dcn20_resource.h" 37 38 #include "clk_mgr.h" 39 #include "dcn10/dcn10_hubp.h" 40 #include "dcn10/dcn10_ipp.h" 41 #include "dcn20/dcn20_hubbub.h" 42 #include "dcn20/dcn20_mpc.h" 43 #include "dcn20/dcn20_hubp.h" 44 #include "dcn21_hubp.h" 45 #include "irq/dcn21/irq_service_dcn21.h" 46 #include "dcn20/dcn20_dpp.h" 47 #include "dcn20/dcn20_optc.h" 48 #include "dcn21/dcn21_hwseq.h" 49 #include "dce110/dce110_hw_sequencer.h" 50 #include "dcn20/dcn20_opp.h" 51 #include "dcn20/dcn20_dsc.h" 52 #include "dcn21/dcn21_link_encoder.h" 53 #include "dcn20/dcn20_stream_encoder.h" 54 #include "dce/dce_clock_source.h" 55 #include "dce/dce_audio.h" 56 #include "dce/dce_hwseq.h" 57 #include "virtual/virtual_stream_encoder.h" 58 #include "dce110/dce110_resource.h" 59 #include "dml/display_mode_vba.h" 60 #include "dcn20/dcn20_dccg.h" 61 #include "dcn21_hubbub.h" 62 #include "dcn10/dcn10_resource.h" 63 #include "dce110/dce110_resource.h" 64 65 #include "dcn20/dcn20_dwb.h" 66 #include "dcn20/dcn20_mmhubbub.h" 67 #include "dpcs/dpcs_2_1_0_offset.h" 68 #include "dpcs/dpcs_2_1_0_sh_mask.h" 69 70 #include "renoir_ip_offset.h" 71 #include "dcn/dcn_2_1_0_offset.h" 72 #include "dcn/dcn_2_1_0_sh_mask.h" 73 74 #include "nbio/nbio_7_0_offset.h" 75 76 #include "mmhub/mmhub_2_0_0_offset.h" 77 #include "mmhub/mmhub_2_0_0_sh_mask.h" 78 79 #include "reg_helper.h" 80 #include "dce/dce_abm.h" 81 #include "dce/dce_dmcu.h" 82 #include "dce/dce_aux.h" 83 #include "dce/dce_i2c.h" 84 #include "dcn21_resource.h" 85 #include "vm_helper.h" 86 #include "dcn20/dcn20_vmid.h" 87 #include "dce/dmub_psr.h" 88 89 #define SOC_BOUNDING_BOX_VALID false 90 #define DC_LOGGER_INIT(logger) 91 92 93 struct _vcs_dpi_ip_params_st dcn2_1_ip = { 94 .odm_capable = 1, 95 .gpuvm_enable = 1, 96 .hostvm_enable = 1, 97 .gpuvm_max_page_table_levels = 1, 98 .hostvm_max_page_table_levels = 4, 99 .hostvm_cached_page_table_levels = 2, 100 .num_dsc = 3, 101 .rob_buffer_size_kbytes = 168, 102 .det_buffer_size_kbytes = 164, 103 .dpte_buffer_size_in_pte_reqs_luma = 44, 104 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo 105 .dpp_output_buffer_pixels = 2560, 106 .opp_output_buffer_lines = 1, 107 .pixel_chunk_size_kbytes = 8, 108 .pte_enable = 1, 109 .max_page_table_levels = 4, 110 .pte_chunk_size_kbytes = 2, 111 .meta_chunk_size_kbytes = 2, 112 .writeback_chunk_size_kbytes = 2, 113 .line_buffer_size_bits = 789504, 114 .is_line_buffer_bpp_fixed = 0, 115 .line_buffer_fixed_bpp = 0, 116 .dcc_supported = true, 117 .max_line_buffer_lines = 12, 118 .writeback_luma_buffer_size_kbytes = 12, 119 .writeback_chroma_buffer_size_kbytes = 8, 120 .writeback_chroma_line_buffer_width_pixels = 4, 121 .writeback_max_hscl_ratio = 1, 122 .writeback_max_vscl_ratio = 1, 123 .writeback_min_hscl_ratio = 1, 124 .writeback_min_vscl_ratio = 1, 125 .writeback_max_hscl_taps = 12, 126 .writeback_max_vscl_taps = 12, 127 .writeback_line_buffer_luma_buffer_size = 0, 128 .writeback_line_buffer_chroma_buffer_size = 14643, 129 .cursor_buffer_size = 8, 130 .cursor_chunk_size = 2, 131 .max_num_otg = 4, 132 .max_num_dpp = 4, 133 .max_num_wb = 1, 134 .max_dchub_pscl_bw_pix_per_clk = 4, 135 .max_pscl_lb_bw_pix_per_clk = 2, 136 .max_lb_vscl_bw_pix_per_clk = 4, 137 .max_vscl_hscl_bw_pix_per_clk = 4, 138 .max_hscl_ratio = 4, 139 .max_vscl_ratio = 4, 140 .hscl_mults = 4, 141 .vscl_mults = 4, 142 .max_hscl_taps = 8, 143 .max_vscl_taps = 8, 144 .dispclk_ramp_margin_percent = 1, 145 .underscan_factor = 1.10, 146 .min_vblank_lines = 32, // 147 .dppclk_delay_subtotal = 77, // 148 .dppclk_delay_scl_lb_only = 16, 149 .dppclk_delay_scl = 50, 150 .dppclk_delay_cnvc_formatter = 8, 151 .dppclk_delay_cnvc_cursor = 6, 152 .dispclk_delay_subtotal = 87, // 153 .dcfclk_cstate_latency = 10, // SRExitTime 154 .max_inter_dcn_tile_repeaters = 8, 155 156 .xfc_supported = false, 157 .xfc_fill_bw_overhead_percent = 10.0, 158 .xfc_fill_constant_bytes = 0, 159 .ptoi_supported = 0, 160 .number_of_cursors = 1, 161 }; 162 163 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { 164 .clock_limits = { 165 { 166 .state = 0, 167 .dcfclk_mhz = 400.0, 168 .fabricclk_mhz = 400.0, 169 .dispclk_mhz = 600.0, 170 .dppclk_mhz = 400.00, 171 .phyclk_mhz = 600.0, 172 .socclk_mhz = 278.0, 173 .dscclk_mhz = 205.67, 174 .dram_speed_mts = 1600.0, 175 }, 176 { 177 .state = 1, 178 .dcfclk_mhz = 464.52, 179 .fabricclk_mhz = 800.0, 180 .dispclk_mhz = 654.55, 181 .dppclk_mhz = 626.09, 182 .phyclk_mhz = 600.0, 183 .socclk_mhz = 278.0, 184 .dscclk_mhz = 205.67, 185 .dram_speed_mts = 1600.0, 186 }, 187 { 188 .state = 2, 189 .dcfclk_mhz = 514.29, 190 .fabricclk_mhz = 933.0, 191 .dispclk_mhz = 757.89, 192 .dppclk_mhz = 685.71, 193 .phyclk_mhz = 600.0, 194 .socclk_mhz = 278.0, 195 .dscclk_mhz = 287.67, 196 .dram_speed_mts = 1866.0, 197 }, 198 { 199 .state = 3, 200 .dcfclk_mhz = 576.00, 201 .fabricclk_mhz = 1067.0, 202 .dispclk_mhz = 847.06, 203 .dppclk_mhz = 757.89, 204 .phyclk_mhz = 600.0, 205 .socclk_mhz = 715.0, 206 .dscclk_mhz = 318.334, 207 .dram_speed_mts = 2134.0, 208 }, 209 { 210 .state = 4, 211 .dcfclk_mhz = 626.09, 212 .fabricclk_mhz = 1200.0, 213 .dispclk_mhz = 900.00, 214 .dppclk_mhz = 847.06, 215 .phyclk_mhz = 810.0, 216 .socclk_mhz = 953.0, 217 .dscclk_mhz = 489.0, 218 .dram_speed_mts = 2400.0, 219 }, 220 { 221 .state = 5, 222 .dcfclk_mhz = 685.71, 223 .fabricclk_mhz = 1333.0, 224 .dispclk_mhz = 1028.57, 225 .dppclk_mhz = 960.00, 226 .phyclk_mhz = 810.0, 227 .socclk_mhz = 278.0, 228 .dscclk_mhz = 287.67, 229 .dram_speed_mts = 2666.0, 230 }, 231 { 232 .state = 6, 233 .dcfclk_mhz = 757.89, 234 .fabricclk_mhz = 1467.0, 235 .dispclk_mhz = 1107.69, 236 .dppclk_mhz = 1028.57, 237 .phyclk_mhz = 810.0, 238 .socclk_mhz = 715.0, 239 .dscclk_mhz = 318.334, 240 .dram_speed_mts = 3200.0, 241 }, 242 { 243 .state = 7, 244 .dcfclk_mhz = 847.06, 245 .fabricclk_mhz = 1600.0, 246 .dispclk_mhz = 1395.0, 247 .dppclk_mhz = 1285.00, 248 .phyclk_mhz = 1325.0, 249 .socclk_mhz = 953.0, 250 .dscclk_mhz = 489.0, 251 .dram_speed_mts = 4266.0, 252 }, 253 /*Extra state, no dispclk ramping*/ 254 { 255 .state = 8, 256 .dcfclk_mhz = 847.06, 257 .fabricclk_mhz = 1600.0, 258 .dispclk_mhz = 1395.0, 259 .dppclk_mhz = 1285.0, 260 .phyclk_mhz = 1325.0, 261 .socclk_mhz = 953.0, 262 .dscclk_mhz = 489.0, 263 .dram_speed_mts = 4266.0, 264 }, 265 266 }, 267 268 .sr_exit_time_us = 12.5, 269 .sr_enter_plus_exit_time_us = 17.0, 270 .urgent_latency_us = 4.0, 271 .urgent_latency_pixel_data_only_us = 4.0, 272 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 273 .urgent_latency_vm_data_only_us = 4.0, 274 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 275 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 276 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 277 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 278 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0, 279 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 280 .max_avg_sdp_bw_use_normal_percent = 60.0, 281 .max_avg_dram_bw_use_normal_percent = 100.0, 282 .writeback_latency_us = 12.0, 283 .max_request_size_bytes = 256, 284 .dram_channel_width_bytes = 4, 285 .fabric_datapath_to_dcn_data_return_bytes = 32, 286 .dcn_downspread_percent = 0.5, 287 .downspread_percent = 0.38, 288 .dram_page_open_time_ns = 50.0, 289 .dram_rw_turnaround_time_ns = 17.5, 290 .dram_return_buffer_per_channel_bytes = 8192, 291 .round_trip_ping_latency_dcfclk_cycles = 128, 292 .urgent_out_of_order_return_per_channel_bytes = 4096, 293 .channel_interleave_bytes = 256, 294 .num_banks = 8, 295 .num_chans = 4, 296 .vmm_page_size_bytes = 4096, 297 .dram_clock_change_latency_us = 23.84, 298 .return_bus_width_bytes = 64, 299 .dispclk_dppclk_vco_speed_mhz = 3600, 300 .xfc_bus_transport_time_us = 4, 301 .xfc_xbuf_latency_tolerance_us = 4, 302 .use_urgent_burst_bw = 1, 303 .num_states = 8 304 }; 305 306 #ifndef MAX 307 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y)) 308 #endif 309 #ifndef MIN 310 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 311 #endif 312 313 /* begin ********************* 314 * macros to expend register list macro defined in HW object header file */ 315 316 /* DCN */ 317 /* TODO awful hack. fixup dcn20_dwb.h */ 318 #undef BASE_INNER 319 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg 320 321 #define BASE(seg) BASE_INNER(seg) 322 323 #define SR(reg_name)\ 324 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 325 mm ## reg_name 326 327 #define SRI(reg_name, block, id)\ 328 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 329 mm ## block ## id ## _ ## reg_name 330 331 #define SRIR(var_name, reg_name, block, id)\ 332 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 333 mm ## block ## id ## _ ## reg_name 334 335 #define SRII(reg_name, block, id)\ 336 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 337 mm ## block ## id ## _ ## reg_name 338 339 #define DCCG_SRII(reg_name, block, id)\ 340 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 341 mm ## block ## id ## _ ## reg_name 342 343 #define VUPDATE_SRII(reg_name, block, id)\ 344 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 345 mm ## reg_name ## _ ## block ## id 346 347 /* NBIO */ 348 #define NBIO_BASE_INNER(seg) \ 349 NBIF0_BASE__INST0_SEG ## seg 350 351 #define NBIO_BASE(seg) \ 352 NBIO_BASE_INNER(seg) 353 354 #define NBIO_SR(reg_name)\ 355 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 356 mm ## reg_name 357 358 /* MMHUB */ 359 #define MMHUB_BASE_INNER(seg) \ 360 MMHUB_BASE__INST0_SEG ## seg 361 362 #define MMHUB_BASE(seg) \ 363 MMHUB_BASE_INNER(seg) 364 365 #define MMHUB_SR(reg_name)\ 366 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 367 mmMM ## reg_name 368 369 #define clk_src_regs(index, pllid)\ 370 [index] = {\ 371 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\ 372 } 373 374 static const struct dce110_clk_src_regs clk_src_regs[] = { 375 clk_src_regs(0, A), 376 clk_src_regs(1, B), 377 clk_src_regs(2, C), 378 clk_src_regs(3, D), 379 clk_src_regs(4, E), 380 }; 381 382 static const struct dce110_clk_src_shift cs_shift = { 383 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 384 }; 385 386 static const struct dce110_clk_src_mask cs_mask = { 387 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 388 }; 389 390 static const struct bios_registers bios_regs = { 391 NBIO_SR(BIOS_SCRATCH_3), 392 NBIO_SR(BIOS_SCRATCH_6) 393 }; 394 395 static const struct dce_dmcu_registers dmcu_regs = { 396 DMCU_DCN20_REG_LIST() 397 }; 398 399 static const struct dce_dmcu_shift dmcu_shift = { 400 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 401 }; 402 403 static const struct dce_dmcu_mask dmcu_mask = { 404 DMCU_MASK_SH_LIST_DCN10(_MASK) 405 }; 406 407 static const struct dce_abm_registers abm_regs = { 408 ABM_DCN20_REG_LIST() 409 }; 410 411 static const struct dce_abm_shift abm_shift = { 412 ABM_MASK_SH_LIST_DCN20(__SHIFT) 413 }; 414 415 static const struct dce_abm_mask abm_mask = { 416 ABM_MASK_SH_LIST_DCN20(_MASK) 417 }; 418 419 #define audio_regs(id)\ 420 [id] = {\ 421 AUD_COMMON_REG_LIST(id)\ 422 } 423 424 static const struct dce_audio_registers audio_regs[] = { 425 audio_regs(0), 426 audio_regs(1), 427 audio_regs(2), 428 audio_regs(3), 429 audio_regs(4), 430 audio_regs(5), 431 }; 432 433 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 434 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 435 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 436 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 437 438 static const struct dce_audio_shift audio_shift = { 439 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 440 }; 441 442 static const struct dce_audio_mask audio_mask = { 443 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 444 }; 445 446 static const struct dccg_registers dccg_regs = { 447 DCCG_COMMON_REG_LIST_DCN_BASE() 448 }; 449 450 static const struct dccg_shift dccg_shift = { 451 DCCG_MASK_SH_LIST_DCN2(__SHIFT) 452 }; 453 454 static const struct dccg_mask dccg_mask = { 455 DCCG_MASK_SH_LIST_DCN2(_MASK) 456 }; 457 458 #define opp_regs(id)\ 459 [id] = {\ 460 OPP_REG_LIST_DCN20(id),\ 461 } 462 463 static const struct dcn20_opp_registers opp_regs[] = { 464 opp_regs(0), 465 opp_regs(1), 466 opp_regs(2), 467 opp_regs(3), 468 opp_regs(4), 469 opp_regs(5), 470 }; 471 472 static const struct dcn20_opp_shift opp_shift = { 473 OPP_MASK_SH_LIST_DCN20(__SHIFT) 474 }; 475 476 static const struct dcn20_opp_mask opp_mask = { 477 OPP_MASK_SH_LIST_DCN20(_MASK) 478 }; 479 480 #define tg_regs(id)\ 481 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)} 482 483 static const struct dcn_optc_registers tg_regs[] = { 484 tg_regs(0), 485 tg_regs(1), 486 tg_regs(2), 487 tg_regs(3) 488 }; 489 490 static const struct dcn_optc_shift tg_shift = { 491 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 492 }; 493 494 static const struct dcn_optc_mask tg_mask = { 495 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 496 }; 497 498 static const struct dcn20_mpc_registers mpc_regs = { 499 MPC_REG_LIST_DCN2_0(0), 500 MPC_REG_LIST_DCN2_0(1), 501 MPC_REG_LIST_DCN2_0(2), 502 MPC_REG_LIST_DCN2_0(3), 503 MPC_REG_LIST_DCN2_0(4), 504 MPC_REG_LIST_DCN2_0(5), 505 MPC_OUT_MUX_REG_LIST_DCN2_0(0), 506 MPC_OUT_MUX_REG_LIST_DCN2_0(1), 507 MPC_OUT_MUX_REG_LIST_DCN2_0(2), 508 MPC_OUT_MUX_REG_LIST_DCN2_0(3), 509 MPC_DBG_REG_LIST_DCN2_0() 510 }; 511 512 static const struct dcn20_mpc_shift mpc_shift = { 513 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT), 514 MPC_DEBUG_REG_LIST_SH_DCN20 515 }; 516 517 static const struct dcn20_mpc_mask mpc_mask = { 518 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK), 519 MPC_DEBUG_REG_LIST_MASK_DCN20 520 }; 521 522 #define hubp_regs(id)\ 523 [id] = {\ 524 HUBP_REG_LIST_DCN21(id)\ 525 } 526 527 static const struct dcn_hubp2_registers hubp_regs[] = { 528 hubp_regs(0), 529 hubp_regs(1), 530 hubp_regs(2), 531 hubp_regs(3) 532 }; 533 534 static const struct dcn_hubp2_shift hubp_shift = { 535 HUBP_MASK_SH_LIST_DCN21(__SHIFT) 536 }; 537 538 static const struct dcn_hubp2_mask hubp_mask = { 539 HUBP_MASK_SH_LIST_DCN21(_MASK) 540 }; 541 542 static const struct dcn_hubbub_registers hubbub_reg = { 543 HUBBUB_REG_LIST_DCN21() 544 }; 545 546 static const struct dcn_hubbub_shift hubbub_shift = { 547 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT) 548 }; 549 550 static const struct dcn_hubbub_mask hubbub_mask = { 551 HUBBUB_MASK_SH_LIST_DCN21(_MASK) 552 }; 553 554 555 #define vmid_regs(id)\ 556 [id] = {\ 557 DCN20_VMID_REG_LIST(id)\ 558 } 559 560 static const struct dcn_vmid_registers vmid_regs[] = { 561 vmid_regs(0), 562 vmid_regs(1), 563 vmid_regs(2), 564 vmid_regs(3), 565 vmid_regs(4), 566 vmid_regs(5), 567 vmid_regs(6), 568 vmid_regs(7), 569 vmid_regs(8), 570 vmid_regs(9), 571 vmid_regs(10), 572 vmid_regs(11), 573 vmid_regs(12), 574 vmid_regs(13), 575 vmid_regs(14), 576 vmid_regs(15) 577 }; 578 579 static const struct dcn20_vmid_shift vmid_shifts = { 580 DCN20_VMID_MASK_SH_LIST(__SHIFT) 581 }; 582 583 static const struct dcn20_vmid_mask vmid_masks = { 584 DCN20_VMID_MASK_SH_LIST(_MASK) 585 }; 586 587 #define dsc_regsDCN20(id)\ 588 [id] = {\ 589 DSC_REG_LIST_DCN20(id)\ 590 } 591 592 static const struct dcn20_dsc_registers dsc_regs[] = { 593 dsc_regsDCN20(0), 594 dsc_regsDCN20(1), 595 dsc_regsDCN20(2), 596 dsc_regsDCN20(3), 597 dsc_regsDCN20(4), 598 dsc_regsDCN20(5) 599 }; 600 601 static const struct dcn20_dsc_shift dsc_shift = { 602 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 603 }; 604 605 static const struct dcn20_dsc_mask dsc_mask = { 606 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 607 }; 608 609 #define ipp_regs(id)\ 610 [id] = {\ 611 IPP_REG_LIST_DCN20(id),\ 612 } 613 614 static const struct dcn10_ipp_registers ipp_regs[] = { 615 ipp_regs(0), 616 ipp_regs(1), 617 ipp_regs(2), 618 ipp_regs(3), 619 }; 620 621 static const struct dcn10_ipp_shift ipp_shift = { 622 IPP_MASK_SH_LIST_DCN20(__SHIFT) 623 }; 624 625 static const struct dcn10_ipp_mask ipp_mask = { 626 IPP_MASK_SH_LIST_DCN20(_MASK), 627 }; 628 629 #define opp_regs(id)\ 630 [id] = {\ 631 OPP_REG_LIST_DCN20(id),\ 632 } 633 634 635 #define aux_engine_regs(id)\ 636 [id] = {\ 637 AUX_COMMON_REG_LIST0(id), \ 638 .AUXN_IMPCAL = 0, \ 639 .AUXP_IMPCAL = 0, \ 640 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 641 } 642 643 static const struct dce110_aux_registers aux_engine_regs[] = { 644 aux_engine_regs(0), 645 aux_engine_regs(1), 646 aux_engine_regs(2), 647 aux_engine_regs(3), 648 aux_engine_regs(4), 649 }; 650 651 #define tf_regs(id)\ 652 [id] = {\ 653 TF_REG_LIST_DCN20(id),\ 654 TF_REG_LIST_DCN20_COMMON_APPEND(id),\ 655 } 656 657 static const struct dcn2_dpp_registers tf_regs[] = { 658 tf_regs(0), 659 tf_regs(1), 660 tf_regs(2), 661 tf_regs(3), 662 }; 663 664 static const struct dcn2_dpp_shift tf_shift = { 665 TF_REG_LIST_SH_MASK_DCN20(__SHIFT), 666 TF_DEBUG_REG_LIST_SH_DCN20 667 }; 668 669 static const struct dcn2_dpp_mask tf_mask = { 670 TF_REG_LIST_SH_MASK_DCN20(_MASK), 671 TF_DEBUG_REG_LIST_MASK_DCN20 672 }; 673 674 #define stream_enc_regs(id)\ 675 [id] = {\ 676 SE_DCN2_REG_LIST(id)\ 677 } 678 679 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 680 stream_enc_regs(0), 681 stream_enc_regs(1), 682 stream_enc_regs(2), 683 stream_enc_regs(3), 684 stream_enc_regs(4), 685 }; 686 687 static const struct dce110_aux_registers_shift aux_shift = { 688 DCN_AUX_MASK_SH_LIST(__SHIFT) 689 }; 690 691 static const struct dce110_aux_registers_mask aux_mask = { 692 DCN_AUX_MASK_SH_LIST(_MASK) 693 }; 694 695 static const struct dcn10_stream_encoder_shift se_shift = { 696 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) 697 }; 698 699 static const struct dcn10_stream_encoder_mask se_mask = { 700 SE_COMMON_MASK_SH_LIST_DCN20(_MASK) 701 }; 702 703 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu); 704 705 static int dcn21_populate_dml_pipes_from_context( 706 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes); 707 708 static struct input_pixel_processor *dcn21_ipp_create( 709 struct dc_context *ctx, uint32_t inst) 710 { 711 struct dcn10_ipp *ipp = 712 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 713 714 if (!ipp) { 715 BREAK_TO_DEBUGGER(); 716 return NULL; 717 } 718 719 dcn20_ipp_construct(ipp, ctx, inst, 720 &ipp_regs[inst], &ipp_shift, &ipp_mask); 721 return &ipp->base; 722 } 723 724 static struct dpp *dcn21_dpp_create( 725 struct dc_context *ctx, 726 uint32_t inst) 727 { 728 struct dcn20_dpp *dpp = 729 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL); 730 731 if (!dpp) 732 return NULL; 733 734 if (dpp2_construct(dpp, ctx, inst, 735 &tf_regs[inst], &tf_shift, &tf_mask)) 736 return &dpp->base; 737 738 BREAK_TO_DEBUGGER(); 739 kfree(dpp); 740 return NULL; 741 } 742 743 static struct dce_aux *dcn21_aux_engine_create( 744 struct dc_context *ctx, 745 uint32_t inst) 746 { 747 struct aux_engine_dce110 *aux_engine = 748 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 749 750 if (!aux_engine) 751 return NULL; 752 753 dce110_aux_engine_construct(aux_engine, ctx, inst, 754 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 755 &aux_engine_regs[inst], 756 &aux_mask, 757 &aux_shift, 758 ctx->dc->caps.extended_aux_timeout_support); 759 760 return &aux_engine->base; 761 } 762 763 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 764 765 static const struct dce_i2c_registers i2c_hw_regs[] = { 766 i2c_inst_regs(1), 767 i2c_inst_regs(2), 768 i2c_inst_regs(3), 769 i2c_inst_regs(4), 770 i2c_inst_regs(5), 771 }; 772 773 static const struct dce_i2c_shift i2c_shifts = { 774 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 775 }; 776 777 static const struct dce_i2c_mask i2c_masks = { 778 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 779 }; 780 781 struct dce_i2c_hw *dcn21_i2c_hw_create( 782 struct dc_context *ctx, 783 uint32_t inst) 784 { 785 struct dce_i2c_hw *dce_i2c_hw = 786 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 787 788 if (!dce_i2c_hw) 789 return NULL; 790 791 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 792 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 793 794 return dce_i2c_hw; 795 } 796 797 static const struct resource_caps res_cap_rn = { 798 .num_timing_generator = 4, 799 .num_opp = 4, 800 .num_video_plane = 4, 801 .num_audio = 4, // 4 audio endpoints. 4 audio streams 802 .num_stream_encoder = 5, 803 .num_pll = 5, // maybe 3 because the last two used for USB-c 804 .num_dwb = 1, 805 .num_ddc = 5, 806 .num_vmid = 1, 807 .num_dsc = 3, 808 }; 809 810 #ifdef DIAGS_BUILD 811 static const struct resource_caps res_cap_rn_FPGA_4pipe = { 812 .num_timing_generator = 4, 813 .num_opp = 4, 814 .num_video_plane = 4, 815 .num_audio = 7, 816 .num_stream_encoder = 4, 817 .num_pll = 4, 818 .num_dwb = 1, 819 .num_ddc = 4, 820 .num_dsc = 0, 821 }; 822 823 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = { 824 .num_timing_generator = 2, 825 .num_opp = 2, 826 .num_video_plane = 2, 827 .num_audio = 7, 828 .num_stream_encoder = 2, 829 .num_pll = 4, 830 .num_dwb = 1, 831 .num_ddc = 4, 832 .num_dsc = 2, 833 }; 834 #endif 835 836 static const struct dc_plane_cap plane_cap = { 837 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 838 .blends_with_above = true, 839 .blends_with_below = true, 840 .per_pixel_alpha = true, 841 842 .pixel_format_support = { 843 .argb8888 = true, 844 .nv12 = true, 845 .fp16 = true, 846 .p010 = true 847 }, 848 849 .max_upscale_factor = { 850 .argb8888 = 16000, 851 .nv12 = 16000, 852 .fp16 = 16000 853 }, 854 855 .max_downscale_factor = { 856 .argb8888 = 250, 857 .nv12 = 250, 858 .fp16 = 250 859 } 860 }; 861 862 static const struct dc_debug_options debug_defaults_drv = { 863 .disable_dmcu = false, 864 .force_abm_enable = false, 865 .timing_trace = false, 866 .clock_trace = true, 867 .disable_pplib_clock_request = true, 868 .min_disp_clk_khz = 100000, 869 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 870 .force_single_disp_pipe_split = false, 871 .disable_dcc = DCC_ENABLE, 872 .vsr_support = true, 873 .performance_trace = false, 874 .max_downscale_src_width = 4096, 875 .disable_pplib_wm_range = false, 876 .scl_reset_length10 = true, 877 .sanity_checks = true, 878 .disable_48mhz_pwrdwn = false, 879 .nv12_iflip_vm_wa = true, 880 .usbc_combo_phy_reset_wa = true 881 }; 882 883 static const struct dc_debug_options debug_defaults_diags = { 884 .disable_dmcu = false, 885 .force_abm_enable = false, 886 .timing_trace = true, 887 .clock_trace = true, 888 .disable_dpp_power_gate = true, 889 .disable_hubp_power_gate = true, 890 .disable_clock_gate = true, 891 .disable_pplib_clock_request = true, 892 .disable_pplib_wm_range = true, 893 .disable_stutter = true, 894 .disable_48mhz_pwrdwn = true, 895 }; 896 897 enum dcn20_clk_src_array_id { 898 DCN20_CLK_SRC_PLL0, 899 DCN20_CLK_SRC_PLL1, 900 DCN20_CLK_SRC_PLL2, 901 DCN20_CLK_SRC_TOTAL_DCN21 902 }; 903 904 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) 905 { 906 unsigned int i; 907 908 for (i = 0; i < pool->base.stream_enc_count; i++) { 909 if (pool->base.stream_enc[i] != NULL) { 910 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 911 pool->base.stream_enc[i] = NULL; 912 } 913 } 914 915 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 916 if (pool->base.dscs[i] != NULL) 917 dcn20_dsc_destroy(&pool->base.dscs[i]); 918 } 919 920 if (pool->base.mpc != NULL) { 921 kfree(TO_DCN20_MPC(pool->base.mpc)); 922 pool->base.mpc = NULL; 923 } 924 if (pool->base.hubbub != NULL) { 925 kfree(pool->base.hubbub); 926 pool->base.hubbub = NULL; 927 } 928 for (i = 0; i < pool->base.pipe_count; i++) { 929 if (pool->base.dpps[i] != NULL) 930 dcn20_dpp_destroy(&pool->base.dpps[i]); 931 932 if (pool->base.ipps[i] != NULL) 933 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 934 935 if (pool->base.hubps[i] != NULL) { 936 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 937 pool->base.hubps[i] = NULL; 938 } 939 940 if (pool->base.irqs != NULL) { 941 dal_irq_service_destroy(&pool->base.irqs); 942 } 943 } 944 945 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 946 if (pool->base.engines[i] != NULL) 947 dce110_engine_destroy(&pool->base.engines[i]); 948 if (pool->base.hw_i2cs[i] != NULL) { 949 kfree(pool->base.hw_i2cs[i]); 950 pool->base.hw_i2cs[i] = NULL; 951 } 952 if (pool->base.sw_i2cs[i] != NULL) { 953 kfree(pool->base.sw_i2cs[i]); 954 pool->base.sw_i2cs[i] = NULL; 955 } 956 } 957 958 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 959 if (pool->base.opps[i] != NULL) 960 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 961 } 962 963 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 964 if (pool->base.timing_generators[i] != NULL) { 965 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 966 pool->base.timing_generators[i] = NULL; 967 } 968 } 969 970 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 971 if (pool->base.dwbc[i] != NULL) { 972 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); 973 pool->base.dwbc[i] = NULL; 974 } 975 if (pool->base.mcif_wb[i] != NULL) { 976 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); 977 pool->base.mcif_wb[i] = NULL; 978 } 979 } 980 981 for (i = 0; i < pool->base.audio_count; i++) { 982 if (pool->base.audios[i]) 983 dce_aud_destroy(&pool->base.audios[i]); 984 } 985 986 for (i = 0; i < pool->base.clk_src_count; i++) { 987 if (pool->base.clock_sources[i] != NULL) { 988 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 989 pool->base.clock_sources[i] = NULL; 990 } 991 } 992 993 if (pool->base.dp_clock_source != NULL) { 994 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 995 pool->base.dp_clock_source = NULL; 996 } 997 998 999 if (pool->base.abm != NULL) 1000 dce_abm_destroy(&pool->base.abm); 1001 1002 if (pool->base.dmcu != NULL) 1003 dce_dmcu_destroy(&pool->base.dmcu); 1004 1005 if (pool->base.psr != NULL) 1006 dmub_psr_destroy(&pool->base.psr); 1007 1008 if (pool->base.dccg != NULL) 1009 dcn_dccg_destroy(&pool->base.dccg); 1010 1011 if (pool->base.pp_smu != NULL) 1012 dcn21_pp_smu_destroy(&pool->base.pp_smu); 1013 } 1014 1015 1016 static void calculate_wm_set_for_vlevel( 1017 int vlevel, 1018 struct wm_range_table_entry *table_entry, 1019 struct dcn_watermarks *wm_set, 1020 struct display_mode_lib *dml, 1021 display_e2e_pipe_params_st *pipes, 1022 int pipe_cnt) 1023 { 1024 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; 1025 1026 ASSERT(vlevel < dml->soc.num_states); 1027 /* only pipe 0 is read for voltage and dcf/soc clocks */ 1028 pipes[0].clks_cfg.voltage = vlevel; 1029 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; 1030 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; 1031 1032 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; 1033 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; 1034 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; 1035 1036 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; 1037 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; 1038 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; 1039 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 1040 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; 1041 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; 1042 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; 1043 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000; 1044 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; 1045 1046 } 1047 1048 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) 1049 { 1050 int i; 1051 1052 DC_FP_START(); 1053 1054 if (dc->bb_overrides.sr_exit_time_ns) { 1055 for (i = 0; i < WM_SET_COUNT; i++) { 1056 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us = 1057 dc->bb_overrides.sr_exit_time_ns / 1000.0; 1058 } 1059 } 1060 1061 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) { 1062 for (i = 0; i < WM_SET_COUNT; i++) { 1063 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us = 1064 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 1065 } 1066 } 1067 1068 if (dc->bb_overrides.urgent_latency_ns) { 1069 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 1070 } 1071 1072 if (dc->bb_overrides.dram_clock_change_latency_ns) { 1073 for (i = 0; i < WM_SET_COUNT; i++) { 1074 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us = 1075 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 1076 } 1077 } 1078 1079 DC_FP_END(); 1080 } 1081 1082 void dcn21_calculate_wm( 1083 struct dc *dc, struct dc_state *context, 1084 display_e2e_pipe_params_st *pipes, 1085 int *out_pipe_cnt, 1086 int *pipe_split_from, 1087 int vlevel_req) 1088 { 1089 int pipe_cnt, i, pipe_idx; 1090 int vlevel, vlevel_max; 1091 struct wm_range_table_entry *table_entry; 1092 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; 1093 1094 ASSERT(bw_params); 1095 1096 patch_bounding_box(dc, &context->bw_ctx.dml.soc); 1097 1098 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1099 if (!context->res_ctx.pipe_ctx[i].stream) 1100 continue; 1101 1102 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 1103 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb]; 1104 1105 if (pipe_split_from[i] < 0) { 1106 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1107 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; 1108 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) 1109 pipes[pipe_cnt].pipe.dest.odm_combine = 1110 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx]; 1111 else 1112 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1113 pipe_idx++; 1114 } else { 1115 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1116 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; 1117 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) 1118 pipes[pipe_cnt].pipe.dest.odm_combine = 1119 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]]; 1120 else 1121 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1122 } 1123 pipe_cnt++; 1124 } 1125 1126 if (pipe_cnt != pipe_idx) { 1127 if (dc->res_pool->funcs->populate_dml_pipes) 1128 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, 1129 context, pipes); 1130 else 1131 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc, 1132 context, pipes); 1133 } 1134 1135 *out_pipe_cnt = pipe_cnt; 1136 1137 vlevel_max = bw_params->clk_table.num_entries - 1; 1138 1139 1140 /* WM Set D */ 1141 table_entry = &bw_params->wm_table.entries[WM_D]; 1142 if (table_entry->wm_type == WM_TYPE_RETRAINING) 1143 vlevel = 0; 1144 else 1145 vlevel = vlevel_max; 1146 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, 1147 &context->bw_ctx.dml, pipes, pipe_cnt); 1148 /* WM Set C */ 1149 table_entry = &bw_params->wm_table.entries[WM_C]; 1150 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max); 1151 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, 1152 &context->bw_ctx.dml, pipes, pipe_cnt); 1153 /* WM Set B */ 1154 table_entry = &bw_params->wm_table.entries[WM_B]; 1155 vlevel = MIN(MAX(vlevel_req, 1), vlevel_max); 1156 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, 1157 &context->bw_ctx.dml, pipes, pipe_cnt); 1158 1159 /* WM Set A */ 1160 table_entry = &bw_params->wm_table.entries[WM_A]; 1161 vlevel = MIN(vlevel_req, vlevel_max); 1162 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, 1163 &context->bw_ctx.dml, pipes, pipe_cnt); 1164 } 1165 1166 1167 bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context, 1168 bool fast_validate) 1169 { 1170 bool out = false; 1171 1172 BW_VAL_TRACE_SETUP(); 1173 1174 int vlevel = 0; 1175 int pipe_split_from[MAX_PIPES]; 1176 int pipe_cnt = 0; 1177 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1178 DC_LOGGER_INIT(dc->ctx->logger); 1179 1180 BW_VAL_TRACE_COUNT(); 1181 1182 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel); 1183 1184 if (pipe_cnt == 0) 1185 goto validate_out; 1186 1187 if (!out) 1188 goto validate_fail; 1189 1190 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1191 1192 if (fast_validate) { 1193 BW_VAL_TRACE_SKIP(fast); 1194 goto validate_out; 1195 } 1196 1197 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel); 1198 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 1199 1200 BW_VAL_TRACE_END_WATERMARKS(); 1201 1202 goto validate_out; 1203 1204 validate_fail: 1205 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1206 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1207 1208 BW_VAL_TRACE_SKIP(fail); 1209 out = false; 1210 1211 validate_out: 1212 kfree(pipes); 1213 1214 BW_VAL_TRACE_FINISH(); 1215 1216 return out; 1217 } 1218 static void dcn21_destroy_resource_pool(struct resource_pool **pool) 1219 { 1220 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool); 1221 1222 dcn21_resource_destruct(dcn21_pool); 1223 kfree(dcn21_pool); 1224 *pool = NULL; 1225 } 1226 1227 static struct clock_source *dcn21_clock_source_create( 1228 struct dc_context *ctx, 1229 struct dc_bios *bios, 1230 enum clock_source_id id, 1231 const struct dce110_clk_src_regs *regs, 1232 bool dp_clk_src) 1233 { 1234 struct dce110_clk_src *clk_src = 1235 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1236 1237 if (!clk_src) 1238 return NULL; 1239 1240 if (dcn20_clk_src_construct(clk_src, ctx, bios, id, 1241 regs, &cs_shift, &cs_mask)) { 1242 clk_src->base.dp_clk_src = dp_clk_src; 1243 return &clk_src->base; 1244 } 1245 1246 BREAK_TO_DEBUGGER(); 1247 return NULL; 1248 } 1249 1250 static struct hubp *dcn21_hubp_create( 1251 struct dc_context *ctx, 1252 uint32_t inst) 1253 { 1254 struct dcn21_hubp *hubp21 = 1255 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL); 1256 1257 if (!hubp21) 1258 return NULL; 1259 1260 if (hubp21_construct(hubp21, ctx, inst, 1261 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1262 return &hubp21->base; 1263 1264 BREAK_TO_DEBUGGER(); 1265 kfree(hubp21); 1266 return NULL; 1267 } 1268 1269 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx) 1270 { 1271 int i; 1272 1273 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), 1274 GFP_KERNEL); 1275 1276 if (!hubbub) 1277 return NULL; 1278 1279 hubbub21_construct(hubbub, ctx, 1280 &hubbub_reg, 1281 &hubbub_shift, 1282 &hubbub_mask); 1283 1284 for (i = 0; i < res_cap_rn.num_vmid; i++) { 1285 struct dcn20_vmid *vmid = &hubbub->vmid[i]; 1286 1287 vmid->ctx = ctx; 1288 1289 vmid->regs = &vmid_regs[i]; 1290 vmid->shifts = &vmid_shifts; 1291 vmid->masks = &vmid_masks; 1292 } 1293 1294 return &hubbub->base; 1295 } 1296 1297 struct output_pixel_processor *dcn21_opp_create( 1298 struct dc_context *ctx, uint32_t inst) 1299 { 1300 struct dcn20_opp *opp = 1301 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1302 1303 if (!opp) { 1304 BREAK_TO_DEBUGGER(); 1305 return NULL; 1306 } 1307 1308 dcn20_opp_construct(opp, ctx, inst, 1309 &opp_regs[inst], &opp_shift, &opp_mask); 1310 return &opp->base; 1311 } 1312 1313 struct timing_generator *dcn21_timing_generator_create( 1314 struct dc_context *ctx, 1315 uint32_t instance) 1316 { 1317 struct optc *tgn10 = 1318 kzalloc(sizeof(struct optc), GFP_KERNEL); 1319 1320 if (!tgn10) 1321 return NULL; 1322 1323 tgn10->base.inst = instance; 1324 tgn10->base.ctx = ctx; 1325 1326 tgn10->tg_regs = &tg_regs[instance]; 1327 tgn10->tg_shift = &tg_shift; 1328 tgn10->tg_mask = &tg_mask; 1329 1330 dcn20_timing_generator_init(tgn10); 1331 1332 return &tgn10->base; 1333 } 1334 1335 struct mpc *dcn21_mpc_create(struct dc_context *ctx) 1336 { 1337 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), 1338 GFP_KERNEL); 1339 1340 if (!mpc20) 1341 return NULL; 1342 1343 dcn20_mpc_construct(mpc20, ctx, 1344 &mpc_regs, 1345 &mpc_shift, 1346 &mpc_mask, 1347 6); 1348 1349 return &mpc20->base; 1350 } 1351 1352 static void read_dce_straps( 1353 struct dc_context *ctx, 1354 struct resource_straps *straps) 1355 { 1356 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1357 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1358 1359 } 1360 1361 1362 struct display_stream_compressor *dcn21_dsc_create( 1363 struct dc_context *ctx, uint32_t inst) 1364 { 1365 struct dcn20_dsc *dsc = 1366 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1367 1368 if (!dsc) { 1369 BREAK_TO_DEBUGGER(); 1370 return NULL; 1371 } 1372 1373 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1374 return &dsc->base; 1375 } 1376 1377 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1378 { 1379 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool); 1380 struct clk_limit_table *clk_table = &bw_params->clk_table; 1381 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1382 unsigned int i, j, closest_clk_lvl; 1383 1384 // Default clock levels are used for diags, which may lead to overclocking. 1385 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 1386 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator; 1387 dcn2_1_ip.max_num_dpp = pool->base.pipe_count; 1388 dcn2_1_soc.num_chans = bw_params->num_channels; 1389 1390 ASSERT(clk_table->num_entries); 1391 for (i = 0; i < clk_table->num_entries; i++) { 1392 /* loop backwards*/ 1393 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) { 1394 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { 1395 closest_clk_lvl = j; 1396 break; 1397 } 1398 } 1399 1400 clock_limits[i].state = i; 1401 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 1402 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 1403 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; 1404 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; 1405 1406 clock_limits[i].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; 1407 clock_limits[i].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; 1408 clock_limits[i].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; 1409 clock_limits[i].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; 1410 clock_limits[i].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; 1411 clock_limits[i].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; 1412 clock_limits[i].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; 1413 } 1414 for (i = 0; i < clk_table->num_entries; i++) 1415 dcn2_1_soc.clock_limits[i] = clock_limits[i]; 1416 if (clk_table->num_entries) { 1417 dcn2_1_soc.num_states = clk_table->num_entries; 1418 /* duplicate last level */ 1419 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1]; 1420 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states; 1421 } 1422 } 1423 1424 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); 1425 } 1426 1427 /* Temporary Place holder until we can get them from fuse */ 1428 static struct dpm_clocks dummy_clocks = { 1429 .DcfClocks = { 1430 {.Freq = 400, .Vol = 1}, 1431 {.Freq = 483, .Vol = 1}, 1432 {.Freq = 602, .Vol = 1}, 1433 {.Freq = 738, .Vol = 1} }, 1434 .SocClocks = { 1435 {.Freq = 300, .Vol = 1}, 1436 {.Freq = 400, .Vol = 1}, 1437 {.Freq = 400, .Vol = 1}, 1438 {.Freq = 400, .Vol = 1} }, 1439 .FClocks = { 1440 {.Freq = 400, .Vol = 1}, 1441 {.Freq = 800, .Vol = 1}, 1442 {.Freq = 1067, .Vol = 1}, 1443 {.Freq = 1600, .Vol = 1} }, 1444 .MemClocks = { 1445 {.Freq = 800, .Vol = 1}, 1446 {.Freq = 1600, .Vol = 1}, 1447 {.Freq = 1067, .Vol = 1}, 1448 {.Freq = 1600, .Vol = 1} }, 1449 1450 }; 1451 1452 static enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp, 1453 struct pp_smu_wm_range_sets *ranges) 1454 { 1455 return PP_SMU_RESULT_OK; 1456 } 1457 1458 static enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp, 1459 struct dpm_clocks *clock_table) 1460 { 1461 *clock_table = dummy_clocks; 1462 return PP_SMU_RESULT_OK; 1463 } 1464 1465 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx) 1466 { 1467 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 1468 1469 if (!pp_smu) 1470 return pp_smu; 1471 1472 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) { 1473 pp_smu->ctx.ver = PP_SMU_VER_RN; 1474 pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table; 1475 pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges; 1476 } else { 1477 1478 dm_pp_get_funcs(ctx, pp_smu); 1479 1480 if (pp_smu->ctx.ver != PP_SMU_VER_RN) 1481 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); 1482 } 1483 1484 return pp_smu; 1485 } 1486 1487 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu) 1488 { 1489 if (pp_smu && *pp_smu) { 1490 kfree(*pp_smu); 1491 *pp_smu = NULL; 1492 } 1493 } 1494 1495 static struct audio *dcn21_create_audio( 1496 struct dc_context *ctx, unsigned int inst) 1497 { 1498 return dce_audio_create(ctx, inst, 1499 &audio_regs[inst], &audio_shift, &audio_mask); 1500 } 1501 1502 static struct dc_cap_funcs cap_funcs = { 1503 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1504 }; 1505 1506 struct stream_encoder *dcn21_stream_encoder_create( 1507 enum engine_id eng_id, 1508 struct dc_context *ctx) 1509 { 1510 struct dcn10_stream_encoder *enc1 = 1511 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1512 1513 if (!enc1) 1514 return NULL; 1515 1516 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1517 &stream_enc_regs[eng_id], 1518 &se_shift, &se_mask); 1519 1520 return &enc1->base; 1521 } 1522 1523 static const struct dce_hwseq_registers hwseq_reg = { 1524 HWSEQ_DCN21_REG_LIST() 1525 }; 1526 1527 static const struct dce_hwseq_shift hwseq_shift = { 1528 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT) 1529 }; 1530 1531 static const struct dce_hwseq_mask hwseq_mask = { 1532 HWSEQ_DCN21_MASK_SH_LIST(_MASK) 1533 }; 1534 1535 static struct dce_hwseq *dcn21_hwseq_create( 1536 struct dc_context *ctx) 1537 { 1538 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1539 1540 if (hws) { 1541 hws->ctx = ctx; 1542 hws->regs = &hwseq_reg; 1543 hws->shifts = &hwseq_shift; 1544 hws->masks = &hwseq_mask; 1545 hws->wa.DEGVIDCN21 = true; 1546 hws->wa.disallow_self_refresh_during_multi_plane_transition = true; 1547 } 1548 return hws; 1549 } 1550 1551 static const struct resource_create_funcs res_create_funcs = { 1552 .read_dce_straps = read_dce_straps, 1553 .create_audio = dcn21_create_audio, 1554 .create_stream_encoder = dcn21_stream_encoder_create, 1555 .create_hwseq = dcn21_hwseq_create, 1556 }; 1557 1558 static const struct resource_create_funcs res_create_maximus_funcs = { 1559 .read_dce_straps = NULL, 1560 .create_audio = NULL, 1561 .create_stream_encoder = NULL, 1562 .create_hwseq = dcn21_hwseq_create, 1563 }; 1564 1565 static const struct encoder_feature_support link_enc_feature = { 1566 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1567 .max_hdmi_pixel_clock = 600000, 1568 .hdmi_ycbcr420_supported = true, 1569 .dp_ycbcr420_supported = true, 1570 .fec_supported = true, 1571 .flags.bits.IS_HBR2_CAPABLE = true, 1572 .flags.bits.IS_HBR3_CAPABLE = true, 1573 .flags.bits.IS_TPS3_CAPABLE = true, 1574 .flags.bits.IS_TPS4_CAPABLE = true 1575 }; 1576 1577 1578 #define link_regs(id, phyid)\ 1579 [id] = {\ 1580 LE_DCN2_REG_LIST(id), \ 1581 UNIPHY_DCN2_REG_LIST(phyid), \ 1582 DPCS_DCN21_REG_LIST(id), \ 1583 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 1584 } 1585 1586 static const struct dcn10_link_enc_registers link_enc_regs[] = { 1587 link_regs(0, A), 1588 link_regs(1, B), 1589 link_regs(2, C), 1590 link_regs(3, D), 1591 link_regs(4, E), 1592 }; 1593 1594 #define aux_regs(id)\ 1595 [id] = {\ 1596 DCN2_AUX_REG_LIST(id)\ 1597 } 1598 1599 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 1600 aux_regs(0), 1601 aux_regs(1), 1602 aux_regs(2), 1603 aux_regs(3), 1604 aux_regs(4) 1605 }; 1606 1607 #define hpd_regs(id)\ 1608 [id] = {\ 1609 HPD_REG_LIST(id)\ 1610 } 1611 1612 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 1613 hpd_regs(0), 1614 hpd_regs(1), 1615 hpd_regs(2), 1616 hpd_regs(3), 1617 hpd_regs(4) 1618 }; 1619 1620 static const struct dcn10_link_enc_shift le_shift = { 1621 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\ 1622 DPCS_DCN21_MASK_SH_LIST(__SHIFT) 1623 }; 1624 1625 static const struct dcn10_link_enc_mask le_mask = { 1626 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\ 1627 DPCS_DCN21_MASK_SH_LIST(_MASK) 1628 }; 1629 1630 static int map_transmitter_id_to_phy_instance( 1631 enum transmitter transmitter) 1632 { 1633 switch (transmitter) { 1634 case TRANSMITTER_UNIPHY_A: 1635 return 0; 1636 break; 1637 case TRANSMITTER_UNIPHY_B: 1638 return 1; 1639 break; 1640 case TRANSMITTER_UNIPHY_C: 1641 return 2; 1642 break; 1643 case TRANSMITTER_UNIPHY_D: 1644 return 3; 1645 break; 1646 case TRANSMITTER_UNIPHY_E: 1647 return 4; 1648 break; 1649 default: 1650 ASSERT(0); 1651 return 0; 1652 } 1653 } 1654 1655 static struct link_encoder *dcn21_link_encoder_create( 1656 const struct encoder_init_data *enc_init_data) 1657 { 1658 struct dcn21_link_encoder *enc21 = 1659 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL); 1660 int link_regs_id; 1661 1662 if (!enc21) 1663 return NULL; 1664 1665 link_regs_id = 1666 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 1667 1668 dcn21_link_encoder_construct(enc21, 1669 enc_init_data, 1670 &link_enc_feature, 1671 &link_enc_regs[link_regs_id], 1672 &link_enc_aux_regs[enc_init_data->channel - 1], 1673 &link_enc_hpd_regs[enc_init_data->hpd_source], 1674 &le_shift, 1675 &le_mask); 1676 1677 return &enc21->enc10.base; 1678 } 1679 #define CTX ctx 1680 1681 #define REG(reg_name) \ 1682 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 1683 1684 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1685 { 1686 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 1687 /* RV1 support max 4 pipes */ 1688 value = value & 0xf; 1689 return value; 1690 } 1691 1692 static int dcn21_populate_dml_pipes_from_context( 1693 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes) 1694 { 1695 uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes); 1696 int i; 1697 struct resource_context *res_ctx = &context->res_ctx; 1698 1699 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1700 1701 if (!res_ctx->pipe_ctx[i].stream) 1702 continue; 1703 1704 pipes[i].pipe.src.hostvm = 1; 1705 pipes[i].pipe.src.gpuvm = 1; 1706 } 1707 1708 return pipe_cnt; 1709 } 1710 1711 enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state) 1712 { 1713 enum dc_status result = DC_OK; 1714 1715 if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) { 1716 plane_state->dcc.enable = 1; 1717 /* align to our worst case block width */ 1718 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024; 1719 } 1720 result = dcn20_patch_unknown_plane_state(plane_state); 1721 return result; 1722 } 1723 1724 static struct resource_funcs dcn21_res_pool_funcs = { 1725 .destroy = dcn21_destroy_resource_pool, 1726 .link_enc_create = dcn21_link_encoder_create, 1727 .validate_bandwidth = dcn21_validate_bandwidth, 1728 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context, 1729 .add_stream_to_ctx = dcn20_add_stream_to_ctx, 1730 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1731 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1732 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, 1733 .patch_unknown_plane_state = dcn21_patch_unknown_plane_state, 1734 .set_mcif_arb_params = dcn20_set_mcif_arb_params, 1735 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1736 .update_bw_bounding_box = update_bw_bounding_box 1737 }; 1738 1739 static bool dcn21_resource_construct( 1740 uint8_t num_virtual_links, 1741 struct dc *dc, 1742 struct dcn21_resource_pool *pool) 1743 { 1744 int i, j; 1745 struct dc_context *ctx = dc->ctx; 1746 struct irq_service_init_data init_data; 1747 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1748 uint32_t num_pipes; 1749 1750 ctx->dc_bios->regs = &bios_regs; 1751 1752 pool->base.res_cap = &res_cap_rn; 1753 #ifdef DIAGS_BUILD 1754 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1755 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc; 1756 pool->base.res_cap = &res_cap_rn_FPGA_4pipe; 1757 #endif 1758 1759 pool->base.funcs = &dcn21_res_pool_funcs; 1760 1761 /************************************************* 1762 * Resource + asic cap harcoding * 1763 *************************************************/ 1764 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1765 1766 /* max pipe num for ASIC before check pipe fuses */ 1767 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1768 1769 dc->caps.max_downscale_ratio = 200; 1770 dc->caps.i2c_speed_in_khz = 100; 1771 dc->caps.max_cursor_size = 256; 1772 dc->caps.dmdata_alloc_size = 2048; 1773 dc->caps.hw_3d_lut = true; 1774 1775 dc->caps.max_slave_planes = 1; 1776 dc->caps.post_blend_color_processing = true; 1777 dc->caps.force_dp_tps4_for_cp2520 = true; 1778 dc->caps.extended_aux_timeout_support = true; 1779 dc->caps.dmcub_support = true; 1780 dc->caps.is_apu = true; 1781 1782 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1783 dc->debug = debug_defaults_drv; 1784 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1785 pool->base.pipe_count = 4; 1786 dc->debug = debug_defaults_diags; 1787 } else 1788 dc->debug = debug_defaults_diags; 1789 1790 // Init the vm_helper 1791 if (dc->vm_helper) 1792 vm_helper_init(dc->vm_helper, 16); 1793 1794 /************************************************* 1795 * Create resources * 1796 *************************************************/ 1797 1798 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = 1799 dcn21_clock_source_create(ctx, ctx->dc_bios, 1800 CLOCK_SOURCE_COMBO_PHY_PLL0, 1801 &clk_src_regs[0], false); 1802 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = 1803 dcn21_clock_source_create(ctx, ctx->dc_bios, 1804 CLOCK_SOURCE_COMBO_PHY_PLL1, 1805 &clk_src_regs[1], false); 1806 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = 1807 dcn21_clock_source_create(ctx, ctx->dc_bios, 1808 CLOCK_SOURCE_COMBO_PHY_PLL2, 1809 &clk_src_regs[2], false); 1810 1811 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21; 1812 1813 /* todo: not reuse phy_pll registers */ 1814 pool->base.dp_clock_source = 1815 dcn21_clock_source_create(ctx, ctx->dc_bios, 1816 CLOCK_SOURCE_ID_DP_DTO, 1817 &clk_src_regs[0], true); 1818 1819 for (i = 0; i < pool->base.clk_src_count; i++) { 1820 if (pool->base.clock_sources[i] == NULL) { 1821 dm_error("DC: failed to create clock sources!\n"); 1822 BREAK_TO_DEBUGGER(); 1823 goto create_fail; 1824 } 1825 } 1826 1827 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1828 if (pool->base.dccg == NULL) { 1829 dm_error("DC: failed to create dccg!\n"); 1830 BREAK_TO_DEBUGGER(); 1831 goto create_fail; 1832 } 1833 1834 pool->base.dmcu = dcn21_dmcu_create(ctx, 1835 &dmcu_regs, 1836 &dmcu_shift, 1837 &dmcu_mask); 1838 if (pool->base.dmcu == NULL) { 1839 dm_error("DC: failed to create dmcu!\n"); 1840 BREAK_TO_DEBUGGER(); 1841 goto create_fail; 1842 } 1843 1844 if (dc->debug.disable_dmcu) { 1845 pool->base.psr = dmub_psr_create(ctx); 1846 1847 if (pool->base.psr == NULL) { 1848 dm_error("DC: failed to create psr obj!\n"); 1849 BREAK_TO_DEBUGGER(); 1850 goto create_fail; 1851 } 1852 } 1853 1854 pool->base.abm = dce_abm_create(ctx, 1855 &abm_regs, 1856 &abm_shift, 1857 &abm_mask); 1858 if (pool->base.abm == NULL) { 1859 dm_error("DC: failed to create abm!\n"); 1860 BREAK_TO_DEBUGGER(); 1861 goto create_fail; 1862 } 1863 1864 pool->base.pp_smu = dcn21_pp_smu_create(ctx); 1865 1866 num_pipes = dcn2_1_ip.max_num_dpp; 1867 1868 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++) 1869 if (pipe_fuses & 1 << i) 1870 num_pipes--; 1871 dcn2_1_ip.max_num_dpp = num_pipes; 1872 dcn2_1_ip.max_num_otg = num_pipes; 1873 1874 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); 1875 1876 init_data.ctx = dc->ctx; 1877 pool->base.irqs = dal_irq_service_dcn21_create(&init_data); 1878 if (!pool->base.irqs) 1879 goto create_fail; 1880 1881 j = 0; 1882 /* mem input -> ipp -> dpp -> opp -> TG */ 1883 for (i = 0; i < pool->base.pipe_count; i++) { 1884 /* if pipe is disabled, skip instance of HW pipe, 1885 * i.e, skip ASIC register instance 1886 */ 1887 if ((pipe_fuses & (1 << i)) != 0) 1888 continue; 1889 1890 pool->base.hubps[j] = dcn21_hubp_create(ctx, i); 1891 if (pool->base.hubps[j] == NULL) { 1892 BREAK_TO_DEBUGGER(); 1893 dm_error( 1894 "DC: failed to create memory input!\n"); 1895 goto create_fail; 1896 } 1897 1898 pool->base.ipps[j] = dcn21_ipp_create(ctx, i); 1899 if (pool->base.ipps[j] == NULL) { 1900 BREAK_TO_DEBUGGER(); 1901 dm_error( 1902 "DC: failed to create input pixel processor!\n"); 1903 goto create_fail; 1904 } 1905 1906 pool->base.dpps[j] = dcn21_dpp_create(ctx, i); 1907 if (pool->base.dpps[j] == NULL) { 1908 BREAK_TO_DEBUGGER(); 1909 dm_error( 1910 "DC: failed to create dpps!\n"); 1911 goto create_fail; 1912 } 1913 1914 pool->base.opps[j] = dcn21_opp_create(ctx, i); 1915 if (pool->base.opps[j] == NULL) { 1916 BREAK_TO_DEBUGGER(); 1917 dm_error( 1918 "DC: failed to create output pixel processor!\n"); 1919 goto create_fail; 1920 } 1921 1922 pool->base.timing_generators[j] = dcn21_timing_generator_create( 1923 ctx, i); 1924 if (pool->base.timing_generators[j] == NULL) { 1925 BREAK_TO_DEBUGGER(); 1926 dm_error("DC: failed to create tg!\n"); 1927 goto create_fail; 1928 } 1929 j++; 1930 } 1931 1932 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1933 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i); 1934 if (pool->base.engines[i] == NULL) { 1935 BREAK_TO_DEBUGGER(); 1936 dm_error( 1937 "DC:failed to create aux engine!!\n"); 1938 goto create_fail; 1939 } 1940 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i); 1941 if (pool->base.hw_i2cs[i] == NULL) { 1942 BREAK_TO_DEBUGGER(); 1943 dm_error( 1944 "DC:failed to create hw i2c!!\n"); 1945 goto create_fail; 1946 } 1947 pool->base.sw_i2cs[i] = NULL; 1948 } 1949 1950 pool->base.timing_generator_count = j; 1951 pool->base.pipe_count = j; 1952 pool->base.mpcc_count = j; 1953 1954 pool->base.mpc = dcn21_mpc_create(ctx); 1955 if (pool->base.mpc == NULL) { 1956 BREAK_TO_DEBUGGER(); 1957 dm_error("DC: failed to create mpc!\n"); 1958 goto create_fail; 1959 } 1960 1961 pool->base.hubbub = dcn21_hubbub_create(ctx); 1962 if (pool->base.hubbub == NULL) { 1963 BREAK_TO_DEBUGGER(); 1964 dm_error("DC: failed to create hubbub!\n"); 1965 goto create_fail; 1966 } 1967 1968 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1969 pool->base.dscs[i] = dcn21_dsc_create(ctx, i); 1970 if (pool->base.dscs[i] == NULL) { 1971 BREAK_TO_DEBUGGER(); 1972 dm_error("DC: failed to create display stream compressor %d!\n", i); 1973 goto create_fail; 1974 } 1975 } 1976 1977 if (!dcn20_dwbc_create(ctx, &pool->base)) { 1978 BREAK_TO_DEBUGGER(); 1979 dm_error("DC: failed to create dwbc!\n"); 1980 goto create_fail; 1981 } 1982 if (!dcn20_mmhubbub_create(ctx, &pool->base)) { 1983 BREAK_TO_DEBUGGER(); 1984 dm_error("DC: failed to create mcif_wb!\n"); 1985 goto create_fail; 1986 } 1987 1988 if (!resource_construct(num_virtual_links, dc, &pool->base, 1989 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1990 &res_create_funcs : &res_create_maximus_funcs))) 1991 goto create_fail; 1992 1993 dcn21_hw_sequencer_construct(dc); 1994 1995 dc->caps.max_planes = pool->base.pipe_count; 1996 1997 for (i = 0; i < dc->caps.max_planes; ++i) 1998 dc->caps.planes[i] = plane_cap; 1999 2000 dc->cap_funcs = cap_funcs; 2001 2002 return true; 2003 2004 create_fail: 2005 2006 dcn21_resource_destruct(pool); 2007 2008 return false; 2009 } 2010 2011 struct resource_pool *dcn21_create_resource_pool( 2012 const struct dc_init_data *init_data, 2013 struct dc *dc) 2014 { 2015 struct dcn21_resource_pool *pool = 2016 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL); 2017 2018 if (!pool) 2019 return NULL; 2020 2021 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool)) 2022 return &pool->base; 2023 2024 BREAK_TO_DEBUGGER(); 2025 kfree(pool); 2026 return NULL; 2027 } 2028