1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * Copyright 2019 Raptor Engineering, LLC 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 #include "dc.h" 31 32 #include "dcn21_init.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dcn20/dcn20_resource.h" 37 38 #include "clk_mgr.h" 39 #include "dcn10/dcn10_hubp.h" 40 #include "dcn10/dcn10_ipp.h" 41 #include "dcn20/dcn20_hubbub.h" 42 #include "dcn20/dcn20_mpc.h" 43 #include "dcn20/dcn20_hubp.h" 44 #include "dcn21_hubp.h" 45 #include "irq/dcn21/irq_service_dcn21.h" 46 #include "dcn20/dcn20_dpp.h" 47 #include "dcn20/dcn20_optc.h" 48 #include "dcn21/dcn21_hwseq.h" 49 #include "dce110/dce110_hw_sequencer.h" 50 #include "dcn20/dcn20_opp.h" 51 #include "dcn20/dcn20_dsc.h" 52 #include "dcn21/dcn21_link_encoder.h" 53 #include "dcn20/dcn20_stream_encoder.h" 54 #include "dce/dce_clock_source.h" 55 #include "dce/dce_audio.h" 56 #include "dce/dce_hwseq.h" 57 #include "virtual/virtual_stream_encoder.h" 58 #include "dml/display_mode_vba.h" 59 #include "dcn20/dcn20_dccg.h" 60 #include "dcn21/dcn21_dccg.h" 61 #include "dcn21_hubbub.h" 62 #include "dcn10/dcn10_resource.h" 63 #include "dce/dce_panel_cntl.h" 64 65 #include "dcn20/dcn20_dwb.h" 66 #include "dcn20/dcn20_mmhubbub.h" 67 #include "dpcs/dpcs_2_1_0_offset.h" 68 #include "dpcs/dpcs_2_1_0_sh_mask.h" 69 70 #include "renoir_ip_offset.h" 71 #include "dcn/dcn_2_1_0_offset.h" 72 #include "dcn/dcn_2_1_0_sh_mask.h" 73 74 #include "nbio/nbio_7_0_offset.h" 75 76 #include "mmhub/mmhub_2_0_0_offset.h" 77 #include "mmhub/mmhub_2_0_0_sh_mask.h" 78 79 #include "reg_helper.h" 80 #include "dce/dce_abm.h" 81 #include "dce/dce_dmcu.h" 82 #include "dce/dce_aux.h" 83 #include "dce/dce_i2c.h" 84 #include "dcn21_resource.h" 85 #include "vm_helper.h" 86 #include "dcn20/dcn20_vmid.h" 87 #include "dce/dmub_psr.h" 88 #include "dce/dmub_abm.h" 89 90 #define DC_LOGGER_INIT(logger) 91 92 93 struct _vcs_dpi_ip_params_st dcn2_1_ip = { 94 .odm_capable = 1, 95 .gpuvm_enable = 1, 96 .hostvm_enable = 1, 97 .gpuvm_max_page_table_levels = 1, 98 .hostvm_max_page_table_levels = 4, 99 .hostvm_cached_page_table_levels = 2, 100 .num_dsc = 3, 101 .rob_buffer_size_kbytes = 168, 102 .det_buffer_size_kbytes = 164, 103 .dpte_buffer_size_in_pte_reqs_luma = 44, 104 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo 105 .dpp_output_buffer_pixels = 2560, 106 .opp_output_buffer_lines = 1, 107 .pixel_chunk_size_kbytes = 8, 108 .pte_enable = 1, 109 .max_page_table_levels = 4, 110 .pte_chunk_size_kbytes = 2, 111 .meta_chunk_size_kbytes = 2, 112 .min_meta_chunk_size_bytes = 256, 113 .writeback_chunk_size_kbytes = 2, 114 .line_buffer_size_bits = 789504, 115 .is_line_buffer_bpp_fixed = 0, 116 .line_buffer_fixed_bpp = 0, 117 .dcc_supported = true, 118 .max_line_buffer_lines = 12, 119 .writeback_luma_buffer_size_kbytes = 12, 120 .writeback_chroma_buffer_size_kbytes = 8, 121 .writeback_chroma_line_buffer_width_pixels = 4, 122 .writeback_max_hscl_ratio = 1, 123 .writeback_max_vscl_ratio = 1, 124 .writeback_min_hscl_ratio = 1, 125 .writeback_min_vscl_ratio = 1, 126 .writeback_max_hscl_taps = 12, 127 .writeback_max_vscl_taps = 12, 128 .writeback_line_buffer_luma_buffer_size = 0, 129 .writeback_line_buffer_chroma_buffer_size = 14643, 130 .cursor_buffer_size = 8, 131 .cursor_chunk_size = 2, 132 .max_num_otg = 4, 133 .max_num_dpp = 4, 134 .max_num_wb = 1, 135 .max_dchub_pscl_bw_pix_per_clk = 4, 136 .max_pscl_lb_bw_pix_per_clk = 2, 137 .max_lb_vscl_bw_pix_per_clk = 4, 138 .max_vscl_hscl_bw_pix_per_clk = 4, 139 .max_hscl_ratio = 4, 140 .max_vscl_ratio = 4, 141 .hscl_mults = 4, 142 .vscl_mults = 4, 143 .max_hscl_taps = 8, 144 .max_vscl_taps = 8, 145 .dispclk_ramp_margin_percent = 1, 146 .underscan_factor = 1.10, 147 .min_vblank_lines = 32, // 148 .dppclk_delay_subtotal = 77, // 149 .dppclk_delay_scl_lb_only = 16, 150 .dppclk_delay_scl = 50, 151 .dppclk_delay_cnvc_formatter = 8, 152 .dppclk_delay_cnvc_cursor = 6, 153 .dispclk_delay_subtotal = 87, // 154 .dcfclk_cstate_latency = 10, // SRExitTime 155 .max_inter_dcn_tile_repeaters = 8, 156 157 .xfc_supported = false, 158 .xfc_fill_bw_overhead_percent = 10.0, 159 .xfc_fill_constant_bytes = 0, 160 .ptoi_supported = 0, 161 .number_of_cursors = 1, 162 }; 163 164 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { 165 .clock_limits = { 166 { 167 .state = 0, 168 .dcfclk_mhz = 400.0, 169 .fabricclk_mhz = 400.0, 170 .dispclk_mhz = 600.0, 171 .dppclk_mhz = 400.00, 172 .phyclk_mhz = 600.0, 173 .socclk_mhz = 278.0, 174 .dscclk_mhz = 205.67, 175 .dram_speed_mts = 1600.0, 176 }, 177 { 178 .state = 1, 179 .dcfclk_mhz = 464.52, 180 .fabricclk_mhz = 800.0, 181 .dispclk_mhz = 654.55, 182 .dppclk_mhz = 626.09, 183 .phyclk_mhz = 600.0, 184 .socclk_mhz = 278.0, 185 .dscclk_mhz = 205.67, 186 .dram_speed_mts = 1600.0, 187 }, 188 { 189 .state = 2, 190 .dcfclk_mhz = 514.29, 191 .fabricclk_mhz = 933.0, 192 .dispclk_mhz = 757.89, 193 .dppclk_mhz = 685.71, 194 .phyclk_mhz = 600.0, 195 .socclk_mhz = 278.0, 196 .dscclk_mhz = 287.67, 197 .dram_speed_mts = 1866.0, 198 }, 199 { 200 .state = 3, 201 .dcfclk_mhz = 576.00, 202 .fabricclk_mhz = 1067.0, 203 .dispclk_mhz = 847.06, 204 .dppclk_mhz = 757.89, 205 .phyclk_mhz = 600.0, 206 .socclk_mhz = 715.0, 207 .dscclk_mhz = 318.334, 208 .dram_speed_mts = 2134.0, 209 }, 210 { 211 .state = 4, 212 .dcfclk_mhz = 626.09, 213 .fabricclk_mhz = 1200.0, 214 .dispclk_mhz = 900.00, 215 .dppclk_mhz = 847.06, 216 .phyclk_mhz = 810.0, 217 .socclk_mhz = 953.0, 218 .dscclk_mhz = 489.0, 219 .dram_speed_mts = 2400.0, 220 }, 221 { 222 .state = 5, 223 .dcfclk_mhz = 685.71, 224 .fabricclk_mhz = 1333.0, 225 .dispclk_mhz = 1028.57, 226 .dppclk_mhz = 960.00, 227 .phyclk_mhz = 810.0, 228 .socclk_mhz = 278.0, 229 .dscclk_mhz = 287.67, 230 .dram_speed_mts = 2666.0, 231 }, 232 { 233 .state = 6, 234 .dcfclk_mhz = 757.89, 235 .fabricclk_mhz = 1467.0, 236 .dispclk_mhz = 1107.69, 237 .dppclk_mhz = 1028.57, 238 .phyclk_mhz = 810.0, 239 .socclk_mhz = 715.0, 240 .dscclk_mhz = 318.334, 241 .dram_speed_mts = 3200.0, 242 }, 243 { 244 .state = 7, 245 .dcfclk_mhz = 847.06, 246 .fabricclk_mhz = 1600.0, 247 .dispclk_mhz = 1395.0, 248 .dppclk_mhz = 1285.00, 249 .phyclk_mhz = 1325.0, 250 .socclk_mhz = 953.0, 251 .dscclk_mhz = 489.0, 252 .dram_speed_mts = 4266.0, 253 }, 254 /*Extra state, no dispclk ramping*/ 255 { 256 .state = 8, 257 .dcfclk_mhz = 847.06, 258 .fabricclk_mhz = 1600.0, 259 .dispclk_mhz = 1395.0, 260 .dppclk_mhz = 1285.0, 261 .phyclk_mhz = 1325.0, 262 .socclk_mhz = 953.0, 263 .dscclk_mhz = 489.0, 264 .dram_speed_mts = 4266.0, 265 }, 266 267 }, 268 269 .sr_exit_time_us = 12.5, 270 .sr_enter_plus_exit_time_us = 17.0, 271 .urgent_latency_us = 4.0, 272 .urgent_latency_pixel_data_only_us = 4.0, 273 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 274 .urgent_latency_vm_data_only_us = 4.0, 275 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 276 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 277 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 278 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 279 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0, 280 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 281 .max_avg_sdp_bw_use_normal_percent = 60.0, 282 .max_avg_dram_bw_use_normal_percent = 100.0, 283 .writeback_latency_us = 12.0, 284 .max_request_size_bytes = 256, 285 .dram_channel_width_bytes = 4, 286 .fabric_datapath_to_dcn_data_return_bytes = 32, 287 .dcn_downspread_percent = 0.5, 288 .downspread_percent = 0.38, 289 .dram_page_open_time_ns = 50.0, 290 .dram_rw_turnaround_time_ns = 17.5, 291 .dram_return_buffer_per_channel_bytes = 8192, 292 .round_trip_ping_latency_dcfclk_cycles = 128, 293 .urgent_out_of_order_return_per_channel_bytes = 4096, 294 .channel_interleave_bytes = 256, 295 .num_banks = 8, 296 .num_chans = 4, 297 .vmm_page_size_bytes = 4096, 298 .dram_clock_change_latency_us = 23.84, 299 .return_bus_width_bytes = 64, 300 .dispclk_dppclk_vco_speed_mhz = 3600, 301 .xfc_bus_transport_time_us = 4, 302 .xfc_xbuf_latency_tolerance_us = 4, 303 .use_urgent_burst_bw = 1, 304 .num_states = 8 305 }; 306 307 #ifndef MAX 308 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y)) 309 #endif 310 #ifndef MIN 311 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 312 #endif 313 314 /* begin ********************* 315 * macros to expend register list macro defined in HW object header file */ 316 317 /* DCN */ 318 /* TODO awful hack. fixup dcn20_dwb.h */ 319 #undef BASE_INNER 320 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg 321 322 #define BASE(seg) BASE_INNER(seg) 323 324 #define SR(reg_name)\ 325 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 326 mm ## reg_name 327 328 #define SRI(reg_name, block, id)\ 329 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 330 mm ## block ## id ## _ ## reg_name 331 332 #define SRIR(var_name, reg_name, block, id)\ 333 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 334 mm ## block ## id ## _ ## reg_name 335 336 #define SRII(reg_name, block, id)\ 337 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 338 mm ## block ## id ## _ ## reg_name 339 340 #define DCCG_SRII(reg_name, block, id)\ 341 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 342 mm ## block ## id ## _ ## reg_name 343 344 #define VUPDATE_SRII(reg_name, block, id)\ 345 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 346 mm ## reg_name ## _ ## block ## id 347 348 /* NBIO */ 349 #define NBIO_BASE_INNER(seg) \ 350 NBIF0_BASE__INST0_SEG ## seg 351 352 #define NBIO_BASE(seg) \ 353 NBIO_BASE_INNER(seg) 354 355 #define NBIO_SR(reg_name)\ 356 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 357 mm ## reg_name 358 359 /* MMHUB */ 360 #define MMHUB_BASE_INNER(seg) \ 361 MMHUB_BASE__INST0_SEG ## seg 362 363 #define MMHUB_BASE(seg) \ 364 MMHUB_BASE_INNER(seg) 365 366 #define MMHUB_SR(reg_name)\ 367 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 368 mmMM ## reg_name 369 370 #define clk_src_regs(index, pllid)\ 371 [index] = {\ 372 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\ 373 } 374 375 static const struct dce110_clk_src_regs clk_src_regs[] = { 376 clk_src_regs(0, A), 377 clk_src_regs(1, B), 378 clk_src_regs(2, C), 379 clk_src_regs(3, D), 380 clk_src_regs(4, E), 381 }; 382 383 static const struct dce110_clk_src_shift cs_shift = { 384 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 385 }; 386 387 static const struct dce110_clk_src_mask cs_mask = { 388 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 389 }; 390 391 static const struct bios_registers bios_regs = { 392 NBIO_SR(BIOS_SCRATCH_3), 393 NBIO_SR(BIOS_SCRATCH_6) 394 }; 395 396 static const struct dce_dmcu_registers dmcu_regs = { 397 DMCU_DCN20_REG_LIST() 398 }; 399 400 static const struct dce_dmcu_shift dmcu_shift = { 401 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 402 }; 403 404 static const struct dce_dmcu_mask dmcu_mask = { 405 DMCU_MASK_SH_LIST_DCN10(_MASK) 406 }; 407 408 static const struct dce_abm_registers abm_regs = { 409 ABM_DCN20_REG_LIST() 410 }; 411 412 static const struct dce_abm_shift abm_shift = { 413 ABM_MASK_SH_LIST_DCN20(__SHIFT) 414 }; 415 416 static const struct dce_abm_mask abm_mask = { 417 ABM_MASK_SH_LIST_DCN20(_MASK) 418 }; 419 420 #define audio_regs(id)\ 421 [id] = {\ 422 AUD_COMMON_REG_LIST(id)\ 423 } 424 425 static const struct dce_audio_registers audio_regs[] = { 426 audio_regs(0), 427 audio_regs(1), 428 audio_regs(2), 429 audio_regs(3), 430 audio_regs(4), 431 audio_regs(5), 432 }; 433 434 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 435 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 436 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 437 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 438 439 static const struct dce_audio_shift audio_shift = { 440 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 441 }; 442 443 static const struct dce_audio_mask audio_mask = { 444 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 445 }; 446 447 static const struct dccg_registers dccg_regs = { 448 DCCG_COMMON_REG_LIST_DCN_BASE() 449 }; 450 451 static const struct dccg_shift dccg_shift = { 452 DCCG_MASK_SH_LIST_DCN2_1(__SHIFT) 453 }; 454 455 static const struct dccg_mask dccg_mask = { 456 DCCG_MASK_SH_LIST_DCN2_1(_MASK) 457 }; 458 459 #define opp_regs(id)\ 460 [id] = {\ 461 OPP_REG_LIST_DCN20(id),\ 462 } 463 464 static const struct dcn20_opp_registers opp_regs[] = { 465 opp_regs(0), 466 opp_regs(1), 467 opp_regs(2), 468 opp_regs(3), 469 opp_regs(4), 470 opp_regs(5), 471 }; 472 473 static const struct dcn20_opp_shift opp_shift = { 474 OPP_MASK_SH_LIST_DCN20(__SHIFT) 475 }; 476 477 static const struct dcn20_opp_mask opp_mask = { 478 OPP_MASK_SH_LIST_DCN20(_MASK) 479 }; 480 481 #define tg_regs(id)\ 482 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)} 483 484 static const struct dcn_optc_registers tg_regs[] = { 485 tg_regs(0), 486 tg_regs(1), 487 tg_regs(2), 488 tg_regs(3) 489 }; 490 491 static const struct dcn_optc_shift tg_shift = { 492 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 493 }; 494 495 static const struct dcn_optc_mask tg_mask = { 496 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 497 }; 498 499 static const struct dcn20_mpc_registers mpc_regs = { 500 MPC_REG_LIST_DCN2_0(0), 501 MPC_REG_LIST_DCN2_0(1), 502 MPC_REG_LIST_DCN2_0(2), 503 MPC_REG_LIST_DCN2_0(3), 504 MPC_REG_LIST_DCN2_0(4), 505 MPC_REG_LIST_DCN2_0(5), 506 MPC_OUT_MUX_REG_LIST_DCN2_0(0), 507 MPC_OUT_MUX_REG_LIST_DCN2_0(1), 508 MPC_OUT_MUX_REG_LIST_DCN2_0(2), 509 MPC_OUT_MUX_REG_LIST_DCN2_0(3), 510 MPC_DBG_REG_LIST_DCN2_0() 511 }; 512 513 static const struct dcn20_mpc_shift mpc_shift = { 514 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT), 515 MPC_DEBUG_REG_LIST_SH_DCN20 516 }; 517 518 static const struct dcn20_mpc_mask mpc_mask = { 519 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK), 520 MPC_DEBUG_REG_LIST_MASK_DCN20 521 }; 522 523 #define hubp_regs(id)\ 524 [id] = {\ 525 HUBP_REG_LIST_DCN21(id)\ 526 } 527 528 static const struct dcn_hubp2_registers hubp_regs[] = { 529 hubp_regs(0), 530 hubp_regs(1), 531 hubp_regs(2), 532 hubp_regs(3) 533 }; 534 535 static const struct dcn_hubp2_shift hubp_shift = { 536 HUBP_MASK_SH_LIST_DCN21(__SHIFT) 537 }; 538 539 static const struct dcn_hubp2_mask hubp_mask = { 540 HUBP_MASK_SH_LIST_DCN21(_MASK) 541 }; 542 543 static const struct dcn_hubbub_registers hubbub_reg = { 544 HUBBUB_REG_LIST_DCN21() 545 }; 546 547 static const struct dcn_hubbub_shift hubbub_shift = { 548 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT) 549 }; 550 551 static const struct dcn_hubbub_mask hubbub_mask = { 552 HUBBUB_MASK_SH_LIST_DCN21(_MASK) 553 }; 554 555 556 #define vmid_regs(id)\ 557 [id] = {\ 558 DCN20_VMID_REG_LIST(id)\ 559 } 560 561 static const struct dcn_vmid_registers vmid_regs[] = { 562 vmid_regs(0), 563 vmid_regs(1), 564 vmid_regs(2), 565 vmid_regs(3), 566 vmid_regs(4), 567 vmid_regs(5), 568 vmid_regs(6), 569 vmid_regs(7), 570 vmid_regs(8), 571 vmid_regs(9), 572 vmid_regs(10), 573 vmid_regs(11), 574 vmid_regs(12), 575 vmid_regs(13), 576 vmid_regs(14), 577 vmid_regs(15) 578 }; 579 580 static const struct dcn20_vmid_shift vmid_shifts = { 581 DCN20_VMID_MASK_SH_LIST(__SHIFT) 582 }; 583 584 static const struct dcn20_vmid_mask vmid_masks = { 585 DCN20_VMID_MASK_SH_LIST(_MASK) 586 }; 587 588 #define dsc_regsDCN20(id)\ 589 [id] = {\ 590 DSC_REG_LIST_DCN20(id)\ 591 } 592 593 static const struct dcn20_dsc_registers dsc_regs[] = { 594 dsc_regsDCN20(0), 595 dsc_regsDCN20(1), 596 dsc_regsDCN20(2), 597 dsc_regsDCN20(3), 598 dsc_regsDCN20(4), 599 dsc_regsDCN20(5) 600 }; 601 602 static const struct dcn20_dsc_shift dsc_shift = { 603 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 604 }; 605 606 static const struct dcn20_dsc_mask dsc_mask = { 607 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 608 }; 609 610 #define ipp_regs(id)\ 611 [id] = {\ 612 IPP_REG_LIST_DCN20(id),\ 613 } 614 615 static const struct dcn10_ipp_registers ipp_regs[] = { 616 ipp_regs(0), 617 ipp_regs(1), 618 ipp_regs(2), 619 ipp_regs(3), 620 }; 621 622 static const struct dcn10_ipp_shift ipp_shift = { 623 IPP_MASK_SH_LIST_DCN20(__SHIFT) 624 }; 625 626 static const struct dcn10_ipp_mask ipp_mask = { 627 IPP_MASK_SH_LIST_DCN20(_MASK), 628 }; 629 630 #define opp_regs(id)\ 631 [id] = {\ 632 OPP_REG_LIST_DCN20(id),\ 633 } 634 635 636 #define aux_engine_regs(id)\ 637 [id] = {\ 638 AUX_COMMON_REG_LIST0(id), \ 639 .AUXN_IMPCAL = 0, \ 640 .AUXP_IMPCAL = 0, \ 641 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 642 } 643 644 static const struct dce110_aux_registers aux_engine_regs[] = { 645 aux_engine_regs(0), 646 aux_engine_regs(1), 647 aux_engine_regs(2), 648 aux_engine_regs(3), 649 aux_engine_regs(4), 650 }; 651 652 #define tf_regs(id)\ 653 [id] = {\ 654 TF_REG_LIST_DCN20(id),\ 655 TF_REG_LIST_DCN20_COMMON_APPEND(id),\ 656 } 657 658 static const struct dcn2_dpp_registers tf_regs[] = { 659 tf_regs(0), 660 tf_regs(1), 661 tf_regs(2), 662 tf_regs(3), 663 }; 664 665 static const struct dcn2_dpp_shift tf_shift = { 666 TF_REG_LIST_SH_MASK_DCN20(__SHIFT), 667 TF_DEBUG_REG_LIST_SH_DCN20 668 }; 669 670 static const struct dcn2_dpp_mask tf_mask = { 671 TF_REG_LIST_SH_MASK_DCN20(_MASK), 672 TF_DEBUG_REG_LIST_MASK_DCN20 673 }; 674 675 #define stream_enc_regs(id)\ 676 [id] = {\ 677 SE_DCN2_REG_LIST(id)\ 678 } 679 680 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 681 stream_enc_regs(0), 682 stream_enc_regs(1), 683 stream_enc_regs(2), 684 stream_enc_regs(3), 685 stream_enc_regs(4), 686 }; 687 688 static const struct dce110_aux_registers_shift aux_shift = { 689 DCN_AUX_MASK_SH_LIST(__SHIFT) 690 }; 691 692 static const struct dce110_aux_registers_mask aux_mask = { 693 DCN_AUX_MASK_SH_LIST(_MASK) 694 }; 695 696 static const struct dcn10_stream_encoder_shift se_shift = { 697 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) 698 }; 699 700 static const struct dcn10_stream_encoder_mask se_mask = { 701 SE_COMMON_MASK_SH_LIST_DCN20(_MASK) 702 }; 703 704 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu); 705 706 static int dcn21_populate_dml_pipes_from_context( 707 struct dc *dc, 708 struct dc_state *context, 709 display_e2e_pipe_params_st *pipes, 710 bool fast_validate); 711 712 static struct input_pixel_processor *dcn21_ipp_create( 713 struct dc_context *ctx, uint32_t inst) 714 { 715 struct dcn10_ipp *ipp = 716 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 717 718 if (!ipp) { 719 BREAK_TO_DEBUGGER(); 720 return NULL; 721 } 722 723 dcn20_ipp_construct(ipp, ctx, inst, 724 &ipp_regs[inst], &ipp_shift, &ipp_mask); 725 return &ipp->base; 726 } 727 728 static struct dpp *dcn21_dpp_create( 729 struct dc_context *ctx, 730 uint32_t inst) 731 { 732 struct dcn20_dpp *dpp = 733 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL); 734 735 if (!dpp) 736 return NULL; 737 738 if (dpp2_construct(dpp, ctx, inst, 739 &tf_regs[inst], &tf_shift, &tf_mask)) 740 return &dpp->base; 741 742 BREAK_TO_DEBUGGER(); 743 kfree(dpp); 744 return NULL; 745 } 746 747 static struct dce_aux *dcn21_aux_engine_create( 748 struct dc_context *ctx, 749 uint32_t inst) 750 { 751 struct aux_engine_dce110 *aux_engine = 752 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 753 754 if (!aux_engine) 755 return NULL; 756 757 dce110_aux_engine_construct(aux_engine, ctx, inst, 758 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 759 &aux_engine_regs[inst], 760 &aux_mask, 761 &aux_shift, 762 ctx->dc->caps.extended_aux_timeout_support); 763 764 return &aux_engine->base; 765 } 766 767 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 768 769 static const struct dce_i2c_registers i2c_hw_regs[] = { 770 i2c_inst_regs(1), 771 i2c_inst_regs(2), 772 i2c_inst_regs(3), 773 i2c_inst_regs(4), 774 i2c_inst_regs(5), 775 }; 776 777 static const struct dce_i2c_shift i2c_shifts = { 778 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 779 }; 780 781 static const struct dce_i2c_mask i2c_masks = { 782 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 783 }; 784 785 struct dce_i2c_hw *dcn21_i2c_hw_create( 786 struct dc_context *ctx, 787 uint32_t inst) 788 { 789 struct dce_i2c_hw *dce_i2c_hw = 790 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 791 792 if (!dce_i2c_hw) 793 return NULL; 794 795 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 796 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 797 798 return dce_i2c_hw; 799 } 800 801 static const struct resource_caps res_cap_rn = { 802 .num_timing_generator = 4, 803 .num_opp = 4, 804 .num_video_plane = 4, 805 .num_audio = 4, // 4 audio endpoints. 4 audio streams 806 .num_stream_encoder = 5, 807 .num_pll = 5, // maybe 3 because the last two used for USB-c 808 .num_dwb = 1, 809 .num_ddc = 5, 810 .num_vmid = 16, 811 .num_dsc = 3, 812 }; 813 814 #ifdef DIAGS_BUILD 815 static const struct resource_caps res_cap_rn_FPGA_4pipe = { 816 .num_timing_generator = 4, 817 .num_opp = 4, 818 .num_video_plane = 4, 819 .num_audio = 7, 820 .num_stream_encoder = 4, 821 .num_pll = 4, 822 .num_dwb = 1, 823 .num_ddc = 4, 824 .num_dsc = 0, 825 }; 826 827 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = { 828 .num_timing_generator = 2, 829 .num_opp = 2, 830 .num_video_plane = 2, 831 .num_audio = 7, 832 .num_stream_encoder = 2, 833 .num_pll = 4, 834 .num_dwb = 1, 835 .num_ddc = 4, 836 .num_dsc = 2, 837 }; 838 #endif 839 840 static const struct dc_plane_cap plane_cap = { 841 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 842 .blends_with_above = true, 843 .blends_with_below = true, 844 .per_pixel_alpha = true, 845 846 .pixel_format_support = { 847 .argb8888 = true, 848 .nv12 = true, 849 .fp16 = true, 850 .p010 = true 851 }, 852 853 .max_upscale_factor = { 854 .argb8888 = 16000, 855 .nv12 = 16000, 856 .fp16 = 16000 857 }, 858 859 .max_downscale_factor = { 860 .argb8888 = 250, 861 .nv12 = 250, 862 .fp16 = 250 863 }, 864 64, 865 64 866 }; 867 868 static const struct dc_debug_options debug_defaults_drv = { 869 .disable_dmcu = false, 870 .force_abm_enable = false, 871 .timing_trace = false, 872 .clock_trace = true, 873 .disable_pplib_clock_request = true, 874 .min_disp_clk_khz = 100000, 875 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 876 .force_single_disp_pipe_split = false, 877 .disable_dcc = DCC_ENABLE, 878 .vsr_support = true, 879 .performance_trace = false, 880 .max_downscale_src_width = 4096, 881 .disable_pplib_wm_range = false, 882 .scl_reset_length10 = true, 883 .sanity_checks = true, 884 .disable_48mhz_pwrdwn = false, 885 .usbc_combo_phy_reset_wa = true, 886 .dmub_command_table = true, 887 .use_max_lb = true 888 }; 889 890 static const struct dc_debug_options debug_defaults_diags = { 891 .disable_dmcu = false, 892 .force_abm_enable = false, 893 .timing_trace = true, 894 .clock_trace = true, 895 .disable_dpp_power_gate = true, 896 .disable_hubp_power_gate = true, 897 .disable_clock_gate = true, 898 .disable_pplib_clock_request = true, 899 .disable_pplib_wm_range = true, 900 .disable_stutter = true, 901 .disable_48mhz_pwrdwn = true, 902 .disable_psr = true, 903 .enable_tri_buf = true, 904 .use_max_lb = true 905 }; 906 907 enum dcn20_clk_src_array_id { 908 DCN20_CLK_SRC_PLL0, 909 DCN20_CLK_SRC_PLL1, 910 DCN20_CLK_SRC_PLL2, 911 DCN20_CLK_SRC_PLL3, 912 DCN20_CLK_SRC_PLL4, 913 DCN20_CLK_SRC_TOTAL_DCN21 914 }; 915 916 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) 917 { 918 unsigned int i; 919 920 for (i = 0; i < pool->base.stream_enc_count; i++) { 921 if (pool->base.stream_enc[i] != NULL) { 922 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 923 pool->base.stream_enc[i] = NULL; 924 } 925 } 926 927 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 928 if (pool->base.dscs[i] != NULL) 929 dcn20_dsc_destroy(&pool->base.dscs[i]); 930 } 931 932 if (pool->base.mpc != NULL) { 933 kfree(TO_DCN20_MPC(pool->base.mpc)); 934 pool->base.mpc = NULL; 935 } 936 if (pool->base.hubbub != NULL) { 937 kfree(pool->base.hubbub); 938 pool->base.hubbub = NULL; 939 } 940 for (i = 0; i < pool->base.pipe_count; i++) { 941 if (pool->base.dpps[i] != NULL) 942 dcn20_dpp_destroy(&pool->base.dpps[i]); 943 944 if (pool->base.ipps[i] != NULL) 945 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 946 947 if (pool->base.hubps[i] != NULL) { 948 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 949 pool->base.hubps[i] = NULL; 950 } 951 952 if (pool->base.irqs != NULL) { 953 dal_irq_service_destroy(&pool->base.irqs); 954 } 955 } 956 957 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 958 if (pool->base.engines[i] != NULL) 959 dce110_engine_destroy(&pool->base.engines[i]); 960 if (pool->base.hw_i2cs[i] != NULL) { 961 kfree(pool->base.hw_i2cs[i]); 962 pool->base.hw_i2cs[i] = NULL; 963 } 964 if (pool->base.sw_i2cs[i] != NULL) { 965 kfree(pool->base.sw_i2cs[i]); 966 pool->base.sw_i2cs[i] = NULL; 967 } 968 } 969 970 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 971 if (pool->base.opps[i] != NULL) 972 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 973 } 974 975 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 976 if (pool->base.timing_generators[i] != NULL) { 977 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 978 pool->base.timing_generators[i] = NULL; 979 } 980 } 981 982 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 983 if (pool->base.dwbc[i] != NULL) { 984 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); 985 pool->base.dwbc[i] = NULL; 986 } 987 if (pool->base.mcif_wb[i] != NULL) { 988 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); 989 pool->base.mcif_wb[i] = NULL; 990 } 991 } 992 993 for (i = 0; i < pool->base.audio_count; i++) { 994 if (pool->base.audios[i]) 995 dce_aud_destroy(&pool->base.audios[i]); 996 } 997 998 for (i = 0; i < pool->base.clk_src_count; i++) { 999 if (pool->base.clock_sources[i] != NULL) { 1000 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1001 pool->base.clock_sources[i] = NULL; 1002 } 1003 } 1004 1005 if (pool->base.dp_clock_source != NULL) { 1006 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1007 pool->base.dp_clock_source = NULL; 1008 } 1009 1010 if (pool->base.abm != NULL) { 1011 if (pool->base.abm->ctx->dc->config.disable_dmcu) 1012 dmub_abm_destroy(&pool->base.abm); 1013 else 1014 dce_abm_destroy(&pool->base.abm); 1015 } 1016 1017 if (pool->base.dmcu != NULL) 1018 dce_dmcu_destroy(&pool->base.dmcu); 1019 1020 if (pool->base.psr != NULL) 1021 dmub_psr_destroy(&pool->base.psr); 1022 1023 if (pool->base.dccg != NULL) 1024 dcn_dccg_destroy(&pool->base.dccg); 1025 1026 if (pool->base.pp_smu != NULL) 1027 dcn21_pp_smu_destroy(&pool->base.pp_smu); 1028 } 1029 1030 1031 static void calculate_wm_set_for_vlevel( 1032 int vlevel, 1033 struct wm_range_table_entry *table_entry, 1034 struct dcn_watermarks *wm_set, 1035 struct display_mode_lib *dml, 1036 display_e2e_pipe_params_st *pipes, 1037 int pipe_cnt) 1038 { 1039 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; 1040 1041 ASSERT(vlevel < dml->soc.num_states); 1042 /* only pipe 0 is read for voltage and dcf/soc clocks */ 1043 pipes[0].clks_cfg.voltage = vlevel; 1044 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; 1045 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; 1046 1047 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; 1048 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; 1049 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; 1050 1051 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; 1052 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; 1053 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; 1054 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 1055 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; 1056 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; 1057 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; 1058 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000; 1059 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; 1060 1061 } 1062 1063 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) 1064 { 1065 int i; 1066 1067 if (dc->bb_overrides.sr_exit_time_ns) { 1068 for (i = 0; i < WM_SET_COUNT; i++) { 1069 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us = 1070 dc->bb_overrides.sr_exit_time_ns / 1000.0; 1071 } 1072 } 1073 1074 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) { 1075 for (i = 0; i < WM_SET_COUNT; i++) { 1076 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us = 1077 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 1078 } 1079 } 1080 1081 if (dc->bb_overrides.urgent_latency_ns) { 1082 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 1083 } 1084 1085 if (dc->bb_overrides.dram_clock_change_latency_ns) { 1086 for (i = 0; i < WM_SET_COUNT; i++) { 1087 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us = 1088 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 1089 } 1090 } 1091 } 1092 1093 void dcn21_calculate_wm( 1094 struct dc *dc, struct dc_state *context, 1095 display_e2e_pipe_params_st *pipes, 1096 int *out_pipe_cnt, 1097 int *pipe_split_from, 1098 int vlevel_req, 1099 bool fast_validate) 1100 { 1101 int pipe_cnt, i, pipe_idx; 1102 int vlevel, vlevel_max; 1103 struct wm_range_table_entry *table_entry; 1104 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; 1105 1106 ASSERT(bw_params); 1107 1108 patch_bounding_box(dc, &context->bw_ctx.dml.soc); 1109 1110 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1111 if (!context->res_ctx.pipe_ctx[i].stream) 1112 continue; 1113 1114 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 1115 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb]; 1116 1117 if (pipe_split_from[i] < 0) { 1118 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1119 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; 1120 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) 1121 pipes[pipe_cnt].pipe.dest.odm_combine = 1122 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx]; 1123 else 1124 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1125 pipe_idx++; 1126 } else { 1127 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1128 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; 1129 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) 1130 pipes[pipe_cnt].pipe.dest.odm_combine = 1131 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]]; 1132 else 1133 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1134 } 1135 pipe_cnt++; 1136 } 1137 1138 if (pipe_cnt != pipe_idx) { 1139 if (dc->res_pool->funcs->populate_dml_pipes) 1140 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, 1141 context, pipes, fast_validate); 1142 else 1143 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc, 1144 context, pipes, fast_validate); 1145 } 1146 1147 *out_pipe_cnt = pipe_cnt; 1148 1149 vlevel_max = bw_params->clk_table.num_entries - 1; 1150 1151 1152 /* WM Set D */ 1153 table_entry = &bw_params->wm_table.entries[WM_D]; 1154 if (table_entry->wm_type == WM_TYPE_RETRAINING) 1155 vlevel = 0; 1156 else 1157 vlevel = vlevel_max; 1158 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, 1159 &context->bw_ctx.dml, pipes, pipe_cnt); 1160 /* WM Set C */ 1161 table_entry = &bw_params->wm_table.entries[WM_C]; 1162 vlevel = MIN(MAX(vlevel_req, 3), vlevel_max); 1163 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, 1164 &context->bw_ctx.dml, pipes, pipe_cnt); 1165 /* WM Set B */ 1166 table_entry = &bw_params->wm_table.entries[WM_B]; 1167 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max); 1168 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, 1169 &context->bw_ctx.dml, pipes, pipe_cnt); 1170 1171 /* WM Set A */ 1172 table_entry = &bw_params->wm_table.entries[WM_A]; 1173 vlevel = MIN(vlevel_req, vlevel_max); 1174 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, 1175 &context->bw_ctx.dml, pipes, pipe_cnt); 1176 } 1177 1178 1179 static bool dcn21_fast_validate_bw( 1180 struct dc *dc, 1181 struct dc_state *context, 1182 display_e2e_pipe_params_st *pipes, 1183 int *pipe_cnt_out, 1184 int *pipe_split_from, 1185 int *vlevel_out, 1186 bool fast_validate) 1187 { 1188 bool out = false; 1189 int split[MAX_PIPES] = { 0 }; 1190 int pipe_cnt, i, pipe_idx, vlevel; 1191 1192 ASSERT(pipes); 1193 if (!pipes) 1194 return false; 1195 1196 dcn20_merge_pipes_for_validate(dc, context); 1197 1198 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 1199 1200 *pipe_cnt_out = pipe_cnt; 1201 1202 if (!pipe_cnt) { 1203 out = true; 1204 goto validate_out; 1205 } 1206 /* 1207 * DML favors voltage over p-state, but we're more interested in 1208 * supporting p-state over voltage. We can't support p-state in 1209 * prefetch mode > 0 so try capping the prefetch mode to start. 1210 */ 1211 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = 1212 dm_allow_self_refresh_and_mclk_switch; 1213 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1214 1215 if (vlevel > context->bw_ctx.dml.soc.num_states) { 1216 /* 1217 * If mode is unsupported or there's still no p-state support then 1218 * fall back to favoring voltage. 1219 * 1220 * We don't actually support prefetch mode 2, so require that we 1221 * at least support prefetch mode 1. 1222 */ 1223 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = 1224 dm_allow_self_refresh; 1225 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1226 if (vlevel > context->bw_ctx.dml.soc.num_states) 1227 goto validate_fail; 1228 } 1229 1230 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL); 1231 1232 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1233 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1234 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe; 1235 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 1236 1237 if (!pipe->stream) 1238 continue; 1239 1240 /* We only support full screen mpo with ODM */ 1241 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled 1242 && pipe->plane_state && mpo_pipe 1243 && memcmp(&mpo_pipe->plane_res.scl_data.recout, 1244 &pipe->plane_res.scl_data.recout, 1245 sizeof(struct rect)) != 0) { 1246 ASSERT(mpo_pipe->plane_state != pipe->plane_state); 1247 goto validate_fail; 1248 } 1249 pipe_idx++; 1250 } 1251 1252 /*initialize pipe_just_split_from to invalid idx*/ 1253 for (i = 0; i < MAX_PIPES; i++) 1254 pipe_split_from[i] = -1; 1255 1256 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { 1257 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1258 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 1259 1260 if (!pipe->stream || pipe_split_from[i] >= 0) 1261 continue; 1262 1263 pipe_idx++; 1264 1265 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 1266 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 1267 ASSERT(hsplit_pipe); 1268 if (!dcn20_split_stream_for_odm( 1269 dc, &context->res_ctx, 1270 pipe, hsplit_pipe)) 1271 goto validate_fail; 1272 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 1273 dcn20_build_mapped_resource(dc, context, pipe->stream); 1274 } 1275 1276 if (!pipe->plane_state) 1277 continue; 1278 /* Skip 2nd half of already split pipe */ 1279 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state) 1280 continue; 1281 1282 if (split[i] == 2) { 1283 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) { 1284 /* pipe not split previously needs split */ 1285 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 1286 ASSERT(hsplit_pipe); 1287 if (!hsplit_pipe) { 1288 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2; 1289 continue; 1290 } 1291 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 1292 if (!dcn20_split_stream_for_odm( 1293 dc, &context->res_ctx, 1294 pipe, hsplit_pipe)) 1295 goto validate_fail; 1296 dcn20_build_mapped_resource(dc, context, pipe->stream); 1297 } else { 1298 dcn20_split_stream_for_mpc( 1299 &context->res_ctx, dc->res_pool, 1300 pipe, hsplit_pipe); 1301 resource_build_scaling_params(pipe); 1302 resource_build_scaling_params(hsplit_pipe); 1303 } 1304 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 1305 } 1306 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { 1307 /* merge should already have been done */ 1308 ASSERT(0); 1309 } 1310 } 1311 /* Actual dsc count per stream dsc validation*/ 1312 if (!dcn20_validate_dsc(dc, context)) { 1313 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = 1314 DML_FAIL_DSC_VALIDATION_FAILURE; 1315 goto validate_fail; 1316 } 1317 1318 *vlevel_out = vlevel; 1319 1320 out = true; 1321 goto validate_out; 1322 1323 validate_fail: 1324 out = false; 1325 1326 validate_out: 1327 return out; 1328 } 1329 1330 static noinline bool dcn21_validate_bandwidth_fp(struct dc *dc, 1331 struct dc_state *context, bool fast_validate) 1332 { 1333 bool out = false; 1334 1335 BW_VAL_TRACE_SETUP(); 1336 1337 int vlevel = 0; 1338 int pipe_split_from[MAX_PIPES]; 1339 int pipe_cnt = 0; 1340 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC); 1341 DC_LOGGER_INIT(dc->ctx->logger); 1342 1343 BW_VAL_TRACE_COUNT(); 1344 1345 /*Unsafe due to current pipe merge and split logic*/ 1346 ASSERT(context != dc->current_state); 1347 1348 out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate); 1349 1350 if (pipe_cnt == 0) 1351 goto validate_out; 1352 1353 if (!out) 1354 goto validate_fail; 1355 1356 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1357 1358 if (fast_validate) { 1359 BW_VAL_TRACE_SKIP(fast); 1360 goto validate_out; 1361 } 1362 1363 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate); 1364 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 1365 1366 BW_VAL_TRACE_END_WATERMARKS(); 1367 1368 goto validate_out; 1369 1370 validate_fail: 1371 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1372 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1373 1374 BW_VAL_TRACE_SKIP(fail); 1375 out = false; 1376 1377 validate_out: 1378 kfree(pipes); 1379 1380 BW_VAL_TRACE_FINISH(); 1381 1382 return out; 1383 } 1384 1385 /* 1386 * Some of the functions further below use the FPU, so we need to wrap this 1387 * with DC_FP_START()/DC_FP_END(). Use the same approach as for 1388 * dcn20_validate_bandwidth in dcn20_resource.c. 1389 */ 1390 bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context, 1391 bool fast_validate) 1392 { 1393 bool voltage_supported; 1394 DC_FP_START(); 1395 voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate); 1396 DC_FP_END(); 1397 return voltage_supported; 1398 } 1399 1400 static void dcn21_destroy_resource_pool(struct resource_pool **pool) 1401 { 1402 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool); 1403 1404 dcn21_resource_destruct(dcn21_pool); 1405 kfree(dcn21_pool); 1406 *pool = NULL; 1407 } 1408 1409 static struct clock_source *dcn21_clock_source_create( 1410 struct dc_context *ctx, 1411 struct dc_bios *bios, 1412 enum clock_source_id id, 1413 const struct dce110_clk_src_regs *regs, 1414 bool dp_clk_src) 1415 { 1416 struct dce110_clk_src *clk_src = 1417 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1418 1419 if (!clk_src) 1420 return NULL; 1421 1422 if (dcn20_clk_src_construct(clk_src, ctx, bios, id, 1423 regs, &cs_shift, &cs_mask)) { 1424 clk_src->base.dp_clk_src = dp_clk_src; 1425 return &clk_src->base; 1426 } 1427 1428 BREAK_TO_DEBUGGER(); 1429 return NULL; 1430 } 1431 1432 static struct hubp *dcn21_hubp_create( 1433 struct dc_context *ctx, 1434 uint32_t inst) 1435 { 1436 struct dcn21_hubp *hubp21 = 1437 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL); 1438 1439 if (!hubp21) 1440 return NULL; 1441 1442 if (hubp21_construct(hubp21, ctx, inst, 1443 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1444 return &hubp21->base; 1445 1446 BREAK_TO_DEBUGGER(); 1447 kfree(hubp21); 1448 return NULL; 1449 } 1450 1451 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx) 1452 { 1453 int i; 1454 1455 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), 1456 GFP_KERNEL); 1457 1458 if (!hubbub) 1459 return NULL; 1460 1461 hubbub21_construct(hubbub, ctx, 1462 &hubbub_reg, 1463 &hubbub_shift, 1464 &hubbub_mask); 1465 1466 for (i = 0; i < res_cap_rn.num_vmid; i++) { 1467 struct dcn20_vmid *vmid = &hubbub->vmid[i]; 1468 1469 vmid->ctx = ctx; 1470 1471 vmid->regs = &vmid_regs[i]; 1472 vmid->shifts = &vmid_shifts; 1473 vmid->masks = &vmid_masks; 1474 } 1475 hubbub->num_vmid = res_cap_rn.num_vmid; 1476 1477 return &hubbub->base; 1478 } 1479 1480 struct output_pixel_processor *dcn21_opp_create( 1481 struct dc_context *ctx, uint32_t inst) 1482 { 1483 struct dcn20_opp *opp = 1484 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1485 1486 if (!opp) { 1487 BREAK_TO_DEBUGGER(); 1488 return NULL; 1489 } 1490 1491 dcn20_opp_construct(opp, ctx, inst, 1492 &opp_regs[inst], &opp_shift, &opp_mask); 1493 return &opp->base; 1494 } 1495 1496 struct timing_generator *dcn21_timing_generator_create( 1497 struct dc_context *ctx, 1498 uint32_t instance) 1499 { 1500 struct optc *tgn10 = 1501 kzalloc(sizeof(struct optc), GFP_KERNEL); 1502 1503 if (!tgn10) 1504 return NULL; 1505 1506 tgn10->base.inst = instance; 1507 tgn10->base.ctx = ctx; 1508 1509 tgn10->tg_regs = &tg_regs[instance]; 1510 tgn10->tg_shift = &tg_shift; 1511 tgn10->tg_mask = &tg_mask; 1512 1513 dcn20_timing_generator_init(tgn10); 1514 1515 return &tgn10->base; 1516 } 1517 1518 struct mpc *dcn21_mpc_create(struct dc_context *ctx) 1519 { 1520 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), 1521 GFP_KERNEL); 1522 1523 if (!mpc20) 1524 return NULL; 1525 1526 dcn20_mpc_construct(mpc20, ctx, 1527 &mpc_regs, 1528 &mpc_shift, 1529 &mpc_mask, 1530 6); 1531 1532 return &mpc20->base; 1533 } 1534 1535 static void read_dce_straps( 1536 struct dc_context *ctx, 1537 struct resource_straps *straps) 1538 { 1539 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1540 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1541 1542 } 1543 1544 1545 struct display_stream_compressor *dcn21_dsc_create( 1546 struct dc_context *ctx, uint32_t inst) 1547 { 1548 struct dcn20_dsc *dsc = 1549 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1550 1551 if (!dsc) { 1552 BREAK_TO_DEBUGGER(); 1553 return NULL; 1554 } 1555 1556 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1557 return &dsc->base; 1558 } 1559 1560 static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_limit_table *clk_table, unsigned int high_voltage_lvl) 1561 { 1562 struct _vcs_dpi_voltage_scaling_st low_pstate_lvl; 1563 int i; 1564 1565 low_pstate_lvl.state = 1; 1566 low_pstate_lvl.dcfclk_mhz = clk_table->entries[0].dcfclk_mhz; 1567 low_pstate_lvl.fabricclk_mhz = clk_table->entries[0].fclk_mhz; 1568 low_pstate_lvl.socclk_mhz = clk_table->entries[0].socclk_mhz; 1569 low_pstate_lvl.dram_speed_mts = clk_table->entries[0].memclk_mhz * 2; 1570 1571 low_pstate_lvl.dispclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dispclk_mhz; 1572 low_pstate_lvl.dppclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dppclk_mhz; 1573 low_pstate_lvl.dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[high_voltage_lvl].dram_bw_per_chan_gbps; 1574 low_pstate_lvl.dscclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dscclk_mhz; 1575 low_pstate_lvl.dtbclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dtbclk_mhz; 1576 low_pstate_lvl.phyclk_d18_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_d18_mhz; 1577 low_pstate_lvl.phyclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_mhz; 1578 1579 for (i = clk_table->num_entries; i > 1; i--) 1580 clk_table->entries[i] = clk_table->entries[i-1]; 1581 clk_table->entries[1] = clk_table->entries[0]; 1582 clk_table->num_entries++; 1583 1584 return low_pstate_lvl; 1585 } 1586 1587 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1588 { 1589 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool); 1590 struct clk_limit_table *clk_table = &bw_params->clk_table; 1591 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1592 unsigned int i, closest_clk_lvl = 0, k = 0; 1593 int j; 1594 1595 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator; 1596 dcn2_1_ip.max_num_dpp = pool->base.pipe_count; 1597 dcn2_1_soc.num_chans = bw_params->num_channels; 1598 1599 ASSERT(clk_table->num_entries); 1600 /* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */ 1601 for (i = 0; i < dcn2_1_soc.num_states + 1; i++) { 1602 clock_limits[i] = dcn2_1_soc.clock_limits[i]; 1603 } 1604 1605 for (i = 0; i < clk_table->num_entries; i++) { 1606 /* loop backwards*/ 1607 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) { 1608 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { 1609 closest_clk_lvl = j; 1610 break; 1611 } 1612 } 1613 1614 /* clk_table[1] is reserved for min DF PState. skip here to fill in later. */ 1615 if (i == 1) 1616 k++; 1617 1618 clock_limits[k].state = k; 1619 clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 1620 clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 1621 clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz; 1622 clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; 1623 1624 clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; 1625 clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; 1626 clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; 1627 clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; 1628 clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; 1629 clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; 1630 clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; 1631 1632 k++; 1633 } 1634 for (i = 0; i < clk_table->num_entries + 1; i++) 1635 dcn2_1_soc.clock_limits[i] = clock_limits[i]; 1636 if (clk_table->num_entries) { 1637 dcn2_1_soc.num_states = clk_table->num_entries + 1; 1638 /* fill in min DF PState */ 1639 dcn2_1_soc.clock_limits[1] = construct_low_pstate_lvl(clk_table, closest_clk_lvl); 1640 /* duplicate last level */ 1641 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1]; 1642 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states; 1643 } 1644 1645 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); 1646 } 1647 1648 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx) 1649 { 1650 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 1651 1652 if (!pp_smu) 1653 return pp_smu; 1654 1655 dm_pp_get_funcs(ctx, pp_smu); 1656 1657 if (pp_smu->ctx.ver != PP_SMU_VER_RN) 1658 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); 1659 1660 1661 return pp_smu; 1662 } 1663 1664 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu) 1665 { 1666 if (pp_smu && *pp_smu) { 1667 kfree(*pp_smu); 1668 *pp_smu = NULL; 1669 } 1670 } 1671 1672 static struct audio *dcn21_create_audio( 1673 struct dc_context *ctx, unsigned int inst) 1674 { 1675 return dce_audio_create(ctx, inst, 1676 &audio_regs[inst], &audio_shift, &audio_mask); 1677 } 1678 1679 static struct dc_cap_funcs cap_funcs = { 1680 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1681 }; 1682 1683 struct stream_encoder *dcn21_stream_encoder_create( 1684 enum engine_id eng_id, 1685 struct dc_context *ctx) 1686 { 1687 struct dcn10_stream_encoder *enc1 = 1688 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1689 1690 if (!enc1) 1691 return NULL; 1692 1693 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1694 &stream_enc_regs[eng_id], 1695 &se_shift, &se_mask); 1696 1697 return &enc1->base; 1698 } 1699 1700 static const struct dce_hwseq_registers hwseq_reg = { 1701 HWSEQ_DCN21_REG_LIST() 1702 }; 1703 1704 static const struct dce_hwseq_shift hwseq_shift = { 1705 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT) 1706 }; 1707 1708 static const struct dce_hwseq_mask hwseq_mask = { 1709 HWSEQ_DCN21_MASK_SH_LIST(_MASK) 1710 }; 1711 1712 static struct dce_hwseq *dcn21_hwseq_create( 1713 struct dc_context *ctx) 1714 { 1715 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1716 1717 if (hws) { 1718 hws->ctx = ctx; 1719 hws->regs = &hwseq_reg; 1720 hws->shifts = &hwseq_shift; 1721 hws->masks = &hwseq_mask; 1722 hws->wa.DEGVIDCN21 = true; 1723 hws->wa.disallow_self_refresh_during_multi_plane_transition = true; 1724 } 1725 return hws; 1726 } 1727 1728 static const struct resource_create_funcs res_create_funcs = { 1729 .read_dce_straps = read_dce_straps, 1730 .create_audio = dcn21_create_audio, 1731 .create_stream_encoder = dcn21_stream_encoder_create, 1732 .create_hwseq = dcn21_hwseq_create, 1733 }; 1734 1735 static const struct resource_create_funcs res_create_maximus_funcs = { 1736 .read_dce_straps = NULL, 1737 .create_audio = NULL, 1738 .create_stream_encoder = NULL, 1739 .create_hwseq = dcn21_hwseq_create, 1740 }; 1741 1742 static const struct encoder_feature_support link_enc_feature = { 1743 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1744 .max_hdmi_pixel_clock = 600000, 1745 .hdmi_ycbcr420_supported = true, 1746 .dp_ycbcr420_supported = true, 1747 .fec_supported = true, 1748 .flags.bits.IS_HBR2_CAPABLE = true, 1749 .flags.bits.IS_HBR3_CAPABLE = true, 1750 .flags.bits.IS_TPS3_CAPABLE = true, 1751 .flags.bits.IS_TPS4_CAPABLE = true 1752 }; 1753 1754 1755 #define link_regs(id, phyid)\ 1756 [id] = {\ 1757 LE_DCN2_REG_LIST(id), \ 1758 UNIPHY_DCN2_REG_LIST(phyid), \ 1759 DPCS_DCN21_REG_LIST(id), \ 1760 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 1761 } 1762 1763 static const struct dcn10_link_enc_registers link_enc_regs[] = { 1764 link_regs(0, A), 1765 link_regs(1, B), 1766 link_regs(2, C), 1767 link_regs(3, D), 1768 link_regs(4, E), 1769 }; 1770 1771 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 1772 { DCN_PANEL_CNTL_REG_LIST() } 1773 }; 1774 1775 static const struct dce_panel_cntl_shift panel_cntl_shift = { 1776 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 1777 }; 1778 1779 static const struct dce_panel_cntl_mask panel_cntl_mask = { 1780 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 1781 }; 1782 1783 #define aux_regs(id)\ 1784 [id] = {\ 1785 DCN2_AUX_REG_LIST(id)\ 1786 } 1787 1788 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 1789 aux_regs(0), 1790 aux_regs(1), 1791 aux_regs(2), 1792 aux_regs(3), 1793 aux_regs(4) 1794 }; 1795 1796 #define hpd_regs(id)\ 1797 [id] = {\ 1798 HPD_REG_LIST(id)\ 1799 } 1800 1801 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 1802 hpd_regs(0), 1803 hpd_regs(1), 1804 hpd_regs(2), 1805 hpd_regs(3), 1806 hpd_regs(4) 1807 }; 1808 1809 static const struct dcn10_link_enc_shift le_shift = { 1810 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\ 1811 DPCS_DCN21_MASK_SH_LIST(__SHIFT) 1812 }; 1813 1814 static const struct dcn10_link_enc_mask le_mask = { 1815 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\ 1816 DPCS_DCN21_MASK_SH_LIST(_MASK) 1817 }; 1818 1819 static int map_transmitter_id_to_phy_instance( 1820 enum transmitter transmitter) 1821 { 1822 switch (transmitter) { 1823 case TRANSMITTER_UNIPHY_A: 1824 return 0; 1825 break; 1826 case TRANSMITTER_UNIPHY_B: 1827 return 1; 1828 break; 1829 case TRANSMITTER_UNIPHY_C: 1830 return 2; 1831 break; 1832 case TRANSMITTER_UNIPHY_D: 1833 return 3; 1834 break; 1835 case TRANSMITTER_UNIPHY_E: 1836 return 4; 1837 break; 1838 default: 1839 ASSERT(0); 1840 return 0; 1841 } 1842 } 1843 1844 static struct link_encoder *dcn21_link_encoder_create( 1845 const struct encoder_init_data *enc_init_data) 1846 { 1847 struct dcn21_link_encoder *enc21 = 1848 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL); 1849 int link_regs_id; 1850 1851 if (!enc21) 1852 return NULL; 1853 1854 link_regs_id = 1855 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 1856 1857 dcn21_link_encoder_construct(enc21, 1858 enc_init_data, 1859 &link_enc_feature, 1860 &link_enc_regs[link_regs_id], 1861 &link_enc_aux_regs[enc_init_data->channel - 1], 1862 &link_enc_hpd_regs[enc_init_data->hpd_source], 1863 &le_shift, 1864 &le_mask); 1865 1866 return &enc21->enc10.base; 1867 } 1868 1869 static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1870 { 1871 struct dce_panel_cntl *panel_cntl = 1872 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 1873 1874 if (!panel_cntl) 1875 return NULL; 1876 1877 dce_panel_cntl_construct(panel_cntl, 1878 init_data, 1879 &panel_cntl_regs[init_data->inst], 1880 &panel_cntl_shift, 1881 &panel_cntl_mask); 1882 1883 return &panel_cntl->base; 1884 } 1885 1886 #define CTX ctx 1887 1888 #define REG(reg_name) \ 1889 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 1890 1891 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1892 { 1893 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 1894 /* RV1 support max 4 pipes */ 1895 value = value & 0xf; 1896 return value; 1897 } 1898 1899 static int dcn21_populate_dml_pipes_from_context( 1900 struct dc *dc, 1901 struct dc_state *context, 1902 display_e2e_pipe_params_st *pipes, 1903 bool fast_validate) 1904 { 1905 uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1906 int i; 1907 1908 for (i = 0; i < pipe_cnt; i++) { 1909 1910 pipes[i].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active; 1911 pipes[i].pipe.src.gpuvm = 1; 1912 } 1913 1914 return pipe_cnt; 1915 } 1916 1917 enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state) 1918 { 1919 enum dc_status result = DC_OK; 1920 1921 if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) { 1922 plane_state->dcc.enable = 1; 1923 /* align to our worst case block width */ 1924 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024; 1925 } 1926 result = dcn20_patch_unknown_plane_state(plane_state); 1927 return result; 1928 } 1929 1930 static const struct resource_funcs dcn21_res_pool_funcs = { 1931 .destroy = dcn21_destroy_resource_pool, 1932 .link_enc_create = dcn21_link_encoder_create, 1933 .panel_cntl_create = dcn21_panel_cntl_create, 1934 .validate_bandwidth = dcn21_validate_bandwidth, 1935 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context, 1936 .add_stream_to_ctx = dcn20_add_stream_to_ctx, 1937 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1938 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1939 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1940 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, 1941 .patch_unknown_plane_state = dcn21_patch_unknown_plane_state, 1942 .set_mcif_arb_params = dcn20_set_mcif_arb_params, 1943 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1944 .update_bw_bounding_box = update_bw_bounding_box 1945 }; 1946 1947 static bool dcn21_resource_construct( 1948 uint8_t num_virtual_links, 1949 struct dc *dc, 1950 struct dcn21_resource_pool *pool) 1951 { 1952 int i, j; 1953 struct dc_context *ctx = dc->ctx; 1954 struct irq_service_init_data init_data; 1955 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1956 uint32_t num_pipes; 1957 1958 ctx->dc_bios->regs = &bios_regs; 1959 1960 pool->base.res_cap = &res_cap_rn; 1961 #ifdef DIAGS_BUILD 1962 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1963 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc; 1964 pool->base.res_cap = &res_cap_rn_FPGA_4pipe; 1965 #endif 1966 1967 pool->base.funcs = &dcn21_res_pool_funcs; 1968 1969 /************************************************* 1970 * Resource + asic cap harcoding * 1971 *************************************************/ 1972 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1973 1974 /* max pipe num for ASIC before check pipe fuses */ 1975 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1976 1977 dc->caps.max_downscale_ratio = 200; 1978 dc->caps.i2c_speed_in_khz = 100; 1979 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/ 1980 dc->caps.max_cursor_size = 256; 1981 dc->caps.min_horizontal_blanking_period = 80; 1982 dc->caps.dmdata_alloc_size = 2048; 1983 1984 dc->caps.max_slave_planes = 1; 1985 dc->caps.max_slave_yuv_planes = 1; 1986 dc->caps.max_slave_rgb_planes = 1; 1987 dc->caps.post_blend_color_processing = true; 1988 dc->caps.force_dp_tps4_for_cp2520 = true; 1989 dc->caps.extended_aux_timeout_support = true; 1990 dc->caps.dmcub_support = true; 1991 dc->caps.is_apu = true; 1992 1993 /* Color pipeline capabilities */ 1994 dc->caps.color.dpp.dcn_arch = 1; 1995 dc->caps.color.dpp.input_lut_shared = 0; 1996 dc->caps.color.dpp.icsc = 1; 1997 dc->caps.color.dpp.dgam_ram = 1; 1998 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1999 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2000 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0; 2001 dc->caps.color.dpp.dgam_rom_caps.pq = 0; 2002 dc->caps.color.dpp.dgam_rom_caps.hlg = 0; 2003 dc->caps.color.dpp.post_csc = 0; 2004 dc->caps.color.dpp.gamma_corr = 0; 2005 dc->caps.color.dpp.dgam_rom_for_yuv = 1; 2006 2007 dc->caps.color.dpp.hw_3d_lut = 1; 2008 dc->caps.color.dpp.ogam_ram = 1; 2009 // no OGAM ROM on DCN2 2010 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2011 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2012 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2013 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2014 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2015 dc->caps.color.dpp.ocsc = 0; 2016 2017 dc->caps.color.mpc.gamut_remap = 0; 2018 dc->caps.color.mpc.num_3dluts = 0; 2019 dc->caps.color.mpc.shared_3d_lut = 0; 2020 dc->caps.color.mpc.ogam_ram = 1; 2021 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2022 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2023 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2024 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2025 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2026 dc->caps.color.mpc.ocsc = 1; 2027 2028 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2029 dc->debug = debug_defaults_drv; 2030 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 2031 pool->base.pipe_count = 4; 2032 dc->debug = debug_defaults_diags; 2033 } else 2034 dc->debug = debug_defaults_diags; 2035 2036 // Init the vm_helper 2037 if (dc->vm_helper) 2038 vm_helper_init(dc->vm_helper, 16); 2039 2040 /************************************************* 2041 * Create resources * 2042 *************************************************/ 2043 2044 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = 2045 dcn21_clock_source_create(ctx, ctx->dc_bios, 2046 CLOCK_SOURCE_COMBO_PHY_PLL0, 2047 &clk_src_regs[0], false); 2048 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = 2049 dcn21_clock_source_create(ctx, ctx->dc_bios, 2050 CLOCK_SOURCE_COMBO_PHY_PLL1, 2051 &clk_src_regs[1], false); 2052 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = 2053 dcn21_clock_source_create(ctx, ctx->dc_bios, 2054 CLOCK_SOURCE_COMBO_PHY_PLL2, 2055 &clk_src_regs[2], false); 2056 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] = 2057 dcn21_clock_source_create(ctx, ctx->dc_bios, 2058 CLOCK_SOURCE_COMBO_PHY_PLL3, 2059 &clk_src_regs[3], false); 2060 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] = 2061 dcn21_clock_source_create(ctx, ctx->dc_bios, 2062 CLOCK_SOURCE_COMBO_PHY_PLL4, 2063 &clk_src_regs[4], false); 2064 2065 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21; 2066 2067 /* todo: not reuse phy_pll registers */ 2068 pool->base.dp_clock_source = 2069 dcn21_clock_source_create(ctx, ctx->dc_bios, 2070 CLOCK_SOURCE_ID_DP_DTO, 2071 &clk_src_regs[0], true); 2072 2073 for (i = 0; i < pool->base.clk_src_count; i++) { 2074 if (pool->base.clock_sources[i] == NULL) { 2075 dm_error("DC: failed to create clock sources!\n"); 2076 BREAK_TO_DEBUGGER(); 2077 goto create_fail; 2078 } 2079 } 2080 2081 pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2082 if (pool->base.dccg == NULL) { 2083 dm_error("DC: failed to create dccg!\n"); 2084 BREAK_TO_DEBUGGER(); 2085 goto create_fail; 2086 } 2087 2088 if (!dc->config.disable_dmcu) { 2089 pool->base.dmcu = dcn21_dmcu_create(ctx, 2090 &dmcu_regs, 2091 &dmcu_shift, 2092 &dmcu_mask); 2093 if (pool->base.dmcu == NULL) { 2094 dm_error("DC: failed to create dmcu!\n"); 2095 BREAK_TO_DEBUGGER(); 2096 goto create_fail; 2097 } 2098 2099 dc->debug.dmub_command_table = false; 2100 } 2101 2102 if (dc->config.disable_dmcu) { 2103 pool->base.psr = dmub_psr_create(ctx); 2104 2105 if (pool->base.psr == NULL) { 2106 dm_error("DC: failed to create psr obj!\n"); 2107 BREAK_TO_DEBUGGER(); 2108 goto create_fail; 2109 } 2110 } 2111 2112 if (dc->config.disable_dmcu) 2113 pool->base.abm = dmub_abm_create(ctx, 2114 &abm_regs, 2115 &abm_shift, 2116 &abm_mask); 2117 else 2118 pool->base.abm = dce_abm_create(ctx, 2119 &abm_regs, 2120 &abm_shift, 2121 &abm_mask); 2122 2123 pool->base.pp_smu = dcn21_pp_smu_create(ctx); 2124 2125 num_pipes = dcn2_1_ip.max_num_dpp; 2126 2127 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++) 2128 if (pipe_fuses & 1 << i) 2129 num_pipes--; 2130 dcn2_1_ip.max_num_dpp = num_pipes; 2131 dcn2_1_ip.max_num_otg = num_pipes; 2132 2133 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); 2134 2135 init_data.ctx = dc->ctx; 2136 pool->base.irqs = dal_irq_service_dcn21_create(&init_data); 2137 if (!pool->base.irqs) 2138 goto create_fail; 2139 2140 j = 0; 2141 /* mem input -> ipp -> dpp -> opp -> TG */ 2142 for (i = 0; i < pool->base.pipe_count; i++) { 2143 /* if pipe is disabled, skip instance of HW pipe, 2144 * i.e, skip ASIC register instance 2145 */ 2146 if ((pipe_fuses & (1 << i)) != 0) 2147 continue; 2148 2149 pool->base.hubps[j] = dcn21_hubp_create(ctx, i); 2150 if (pool->base.hubps[j] == NULL) { 2151 BREAK_TO_DEBUGGER(); 2152 dm_error( 2153 "DC: failed to create memory input!\n"); 2154 goto create_fail; 2155 } 2156 2157 pool->base.ipps[j] = dcn21_ipp_create(ctx, i); 2158 if (pool->base.ipps[j] == NULL) { 2159 BREAK_TO_DEBUGGER(); 2160 dm_error( 2161 "DC: failed to create input pixel processor!\n"); 2162 goto create_fail; 2163 } 2164 2165 pool->base.dpps[j] = dcn21_dpp_create(ctx, i); 2166 if (pool->base.dpps[j] == NULL) { 2167 BREAK_TO_DEBUGGER(); 2168 dm_error( 2169 "DC: failed to create dpps!\n"); 2170 goto create_fail; 2171 } 2172 2173 pool->base.opps[j] = dcn21_opp_create(ctx, i); 2174 if (pool->base.opps[j] == NULL) { 2175 BREAK_TO_DEBUGGER(); 2176 dm_error( 2177 "DC: failed to create output pixel processor!\n"); 2178 goto create_fail; 2179 } 2180 2181 pool->base.timing_generators[j] = dcn21_timing_generator_create( 2182 ctx, i); 2183 if (pool->base.timing_generators[j] == NULL) { 2184 BREAK_TO_DEBUGGER(); 2185 dm_error("DC: failed to create tg!\n"); 2186 goto create_fail; 2187 } 2188 j++; 2189 } 2190 2191 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2192 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i); 2193 if (pool->base.engines[i] == NULL) { 2194 BREAK_TO_DEBUGGER(); 2195 dm_error( 2196 "DC:failed to create aux engine!!\n"); 2197 goto create_fail; 2198 } 2199 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i); 2200 if (pool->base.hw_i2cs[i] == NULL) { 2201 BREAK_TO_DEBUGGER(); 2202 dm_error( 2203 "DC:failed to create hw i2c!!\n"); 2204 goto create_fail; 2205 } 2206 pool->base.sw_i2cs[i] = NULL; 2207 } 2208 2209 pool->base.timing_generator_count = j; 2210 pool->base.pipe_count = j; 2211 pool->base.mpcc_count = j; 2212 2213 pool->base.mpc = dcn21_mpc_create(ctx); 2214 if (pool->base.mpc == NULL) { 2215 BREAK_TO_DEBUGGER(); 2216 dm_error("DC: failed to create mpc!\n"); 2217 goto create_fail; 2218 } 2219 2220 pool->base.hubbub = dcn21_hubbub_create(ctx); 2221 if (pool->base.hubbub == NULL) { 2222 BREAK_TO_DEBUGGER(); 2223 dm_error("DC: failed to create hubbub!\n"); 2224 goto create_fail; 2225 } 2226 2227 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2228 pool->base.dscs[i] = dcn21_dsc_create(ctx, i); 2229 if (pool->base.dscs[i] == NULL) { 2230 BREAK_TO_DEBUGGER(); 2231 dm_error("DC: failed to create display stream compressor %d!\n", i); 2232 goto create_fail; 2233 } 2234 } 2235 2236 if (!dcn20_dwbc_create(ctx, &pool->base)) { 2237 BREAK_TO_DEBUGGER(); 2238 dm_error("DC: failed to create dwbc!\n"); 2239 goto create_fail; 2240 } 2241 if (!dcn20_mmhubbub_create(ctx, &pool->base)) { 2242 BREAK_TO_DEBUGGER(); 2243 dm_error("DC: failed to create mcif_wb!\n"); 2244 goto create_fail; 2245 } 2246 2247 if (!resource_construct(num_virtual_links, dc, &pool->base, 2248 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2249 &res_create_funcs : &res_create_maximus_funcs))) 2250 goto create_fail; 2251 2252 dcn21_hw_sequencer_construct(dc); 2253 2254 dc->caps.max_planes = pool->base.pipe_count; 2255 2256 for (i = 0; i < dc->caps.max_planes; ++i) 2257 dc->caps.planes[i] = plane_cap; 2258 2259 dc->cap_funcs = cap_funcs; 2260 2261 return true; 2262 2263 create_fail: 2264 2265 dcn21_resource_destruct(pool); 2266 2267 return false; 2268 } 2269 2270 struct resource_pool *dcn21_create_resource_pool( 2271 const struct dc_init_data *init_data, 2272 struct dc *dc) 2273 { 2274 struct dcn21_resource_pool *pool = 2275 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL); 2276 2277 if (!pool) 2278 return NULL; 2279 2280 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool)) 2281 return &pool->base; 2282 2283 BREAK_TO_DEBUGGER(); 2284 kfree(pool); 2285 return NULL; 2286 } 2287