1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 #include "dc.h" 30 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dcn20/dcn20_resource.h" 34 35 #include "clk_mgr.h" 36 #include "dcn10/dcn10_hubp.h" 37 #include "dcn10/dcn10_ipp.h" 38 #include "dcn20/dcn20_hubbub.h" 39 #include "dcn20/dcn20_mpc.h" 40 #include "dcn20/dcn20_hubp.h" 41 #include "dcn21_hubp.h" 42 #include "irq/dcn21/irq_service_dcn21.h" 43 #include "dcn20/dcn20_dpp.h" 44 #include "dcn20/dcn20_optc.h" 45 #include "dcn20/dcn20_hwseq.h" 46 #include "dce110/dce110_hw_sequencer.h" 47 #include "dcn20/dcn20_opp.h" 48 #include "dcn20/dcn20_dsc.h" 49 #include "dcn20/dcn20_link_encoder.h" 50 #include "dcn20/dcn20_stream_encoder.h" 51 #include "dce/dce_clock_source.h" 52 #include "dce/dce_audio.h" 53 #include "dce/dce_hwseq.h" 54 #include "virtual/virtual_stream_encoder.h" 55 #include "dce110/dce110_resource.h" 56 #include "dml/display_mode_vba.h" 57 #include "dcn20/dcn20_dccg.h" 58 #include "dcn21_hubbub.h" 59 #include "dcn10/dcn10_resource.h" 60 61 #include "dcn20/dcn20_dwb.h" 62 #include "dcn20/dcn20_mmhubbub.h" 63 64 #include "renoir_ip_offset.h" 65 #include "dcn/dcn_2_1_0_offset.h" 66 #include "dcn/dcn_2_1_0_sh_mask.h" 67 68 #include "nbio/nbio_7_0_offset.h" 69 70 #include "mmhub/mmhub_2_0_0_offset.h" 71 #include "mmhub/mmhub_2_0_0_sh_mask.h" 72 73 #include "reg_helper.h" 74 #include "dce/dce_abm.h" 75 #include "dce/dce_dmcu.h" 76 #include "dce/dce_aux.h" 77 #include "dce/dce_i2c.h" 78 #include "dcn21_resource.h" 79 #include "vm_helper.h" 80 #include "dcn20/dcn20_vmid.h" 81 82 #define SOC_BOUNDING_BOX_VALID false 83 #define DC_LOGGER_INIT(logger) 84 85 86 struct _vcs_dpi_ip_params_st dcn2_1_ip = { 87 .gpuvm_enable = 0, 88 .hostvm_enable = 0, 89 .gpuvm_max_page_table_levels = 1, 90 .hostvm_max_page_table_levels = 4, 91 .hostvm_cached_page_table_levels = 2, 92 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 93 .num_dsc = 3, 94 #else 95 .num_dsc = 0, 96 #endif 97 .rob_buffer_size_kbytes = 168, 98 .det_buffer_size_kbytes = 164, 99 .dpte_buffer_size_in_pte_reqs_luma = 44, 100 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo 101 .dpp_output_buffer_pixels = 2560, 102 .opp_output_buffer_lines = 1, 103 .pixel_chunk_size_kbytes = 8, 104 .pte_enable = 1, 105 .max_page_table_levels = 4, 106 .pte_chunk_size_kbytes = 2, 107 .meta_chunk_size_kbytes = 2, 108 .writeback_chunk_size_kbytes = 2, 109 .line_buffer_size_bits = 789504, 110 .is_line_buffer_bpp_fixed = 0, 111 .line_buffer_fixed_bpp = 0, 112 .dcc_supported = true, 113 .max_line_buffer_lines = 12, 114 .writeback_luma_buffer_size_kbytes = 12, 115 .writeback_chroma_buffer_size_kbytes = 8, 116 .writeback_chroma_line_buffer_width_pixels = 4, 117 .writeback_max_hscl_ratio = 1, 118 .writeback_max_vscl_ratio = 1, 119 .writeback_min_hscl_ratio = 1, 120 .writeback_min_vscl_ratio = 1, 121 .writeback_max_hscl_taps = 12, 122 .writeback_max_vscl_taps = 12, 123 .writeback_line_buffer_luma_buffer_size = 0, 124 .writeback_line_buffer_chroma_buffer_size = 14643, 125 .cursor_buffer_size = 8, 126 .cursor_chunk_size = 2, 127 .max_num_otg = 4, 128 .max_num_dpp = 4, 129 .max_num_wb = 1, 130 .max_dchub_pscl_bw_pix_per_clk = 4, 131 .max_pscl_lb_bw_pix_per_clk = 2, 132 .max_lb_vscl_bw_pix_per_clk = 4, 133 .max_vscl_hscl_bw_pix_per_clk = 4, 134 .max_hscl_ratio = 4, 135 .max_vscl_ratio = 4, 136 .hscl_mults = 4, 137 .vscl_mults = 4, 138 .max_hscl_taps = 8, 139 .max_vscl_taps = 8, 140 .dispclk_ramp_margin_percent = 1, 141 .underscan_factor = 1.10, 142 .min_vblank_lines = 32, // 143 .dppclk_delay_subtotal = 77, // 144 .dppclk_delay_scl_lb_only = 16, 145 .dppclk_delay_scl = 50, 146 .dppclk_delay_cnvc_formatter = 8, 147 .dppclk_delay_cnvc_cursor = 6, 148 .dispclk_delay_subtotal = 87, // 149 .dcfclk_cstate_latency = 10, // SRExitTime 150 .max_inter_dcn_tile_repeaters = 8, 151 152 .xfc_supported = false, 153 .xfc_fill_bw_overhead_percent = 10.0, 154 .xfc_fill_constant_bytes = 0, 155 .ptoi_supported = 0 156 }; 157 158 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { 159 .clock_limits = { 160 { 161 .state = 0, 162 .dcfclk_mhz = 304.0, 163 .fabricclk_mhz = 600.0, 164 .dispclk_mhz = 618.0, 165 .dppclk_mhz = 440.0, 166 .phyclk_mhz = 600.0, 167 .socclk_mhz = 278.0, 168 .dscclk_mhz = 205.67, 169 .dram_speed_mts = 1600.0, 170 }, 171 { 172 .state = 1, 173 .dcfclk_mhz = 304.0, 174 .fabricclk_mhz = 600.0, 175 .dispclk_mhz = 618.0, 176 .dppclk_mhz = 618.0, 177 .phyclk_mhz = 600.0, 178 .socclk_mhz = 278.0, 179 .dscclk_mhz = 205.67, 180 .dram_speed_mts = 1600.0, 181 }, 182 { 183 .state = 2, 184 .dcfclk_mhz = 608.0, 185 .fabricclk_mhz = 1066.0, 186 .dispclk_mhz = 888.0, 187 .dppclk_mhz = 888.0, 188 .phyclk_mhz = 810.0, 189 .socclk_mhz = 278.0, 190 .dscclk_mhz = 287.67, 191 .dram_speed_mts = 2133.0, 192 }, 193 { 194 .state = 3, 195 .dcfclk_mhz = 676.0, 196 .fabricclk_mhz = 1600.0, 197 .dispclk_mhz = 1015.0, 198 .dppclk_mhz = 1015.0, 199 .phyclk_mhz = 810.0, 200 .socclk_mhz = 715.0, 201 .dscclk_mhz = 318.334, 202 .dram_speed_mts = 4266.0, 203 }, 204 { 205 .state = 4, 206 .dcfclk_mhz = 810.0, 207 .fabricclk_mhz = 1600.0, 208 .dispclk_mhz = 1015.0, 209 .dppclk_mhz = 1015.0, 210 .phyclk_mhz = 810.0, 211 .socclk_mhz = 953.0, 212 .dscclk_mhz = 318.334, 213 .dram_speed_mts = 4266.0, 214 }, 215 /*Extra state, no dispclk ramping*/ 216 { 217 .state = 5, 218 .dcfclk_mhz = 810.0, 219 .fabricclk_mhz = 1600.0, 220 .dispclk_mhz = 1015.0, 221 .dppclk_mhz = 1015.0, 222 .phyclk_mhz = 810.0, 223 .socclk_mhz = 953.0, 224 .dscclk_mhz = 318.334, 225 .dram_speed_mts = 4266.0, 226 }, 227 228 }, 229 230 .sr_exit_time_us = 9.0, 231 .sr_enter_plus_exit_time_us = 11.0, 232 .urgent_latency_us = 4.0, 233 .urgent_latency_pixel_data_only_us = 4.0, 234 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 235 .urgent_latency_vm_data_only_us = 4.0, 236 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 237 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 238 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 239 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 240 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0, 241 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 242 .max_avg_sdp_bw_use_normal_percent = 60.0, 243 .max_avg_dram_bw_use_normal_percent = 100.0, 244 .writeback_latency_us = 12.0, 245 .max_request_size_bytes = 256, 246 .dram_channel_width_bytes = 4, 247 .fabric_datapath_to_dcn_data_return_bytes = 32, 248 .dcn_downspread_percent = 0.5, 249 .downspread_percent = 0.5, 250 .dram_page_open_time_ns = 50.0, 251 .dram_rw_turnaround_time_ns = 17.5, 252 .dram_return_buffer_per_channel_bytes = 8192, 253 .round_trip_ping_latency_dcfclk_cycles = 128, 254 .urgent_out_of_order_return_per_channel_bytes = 4096, 255 .channel_interleave_bytes = 256, 256 .num_banks = 8, 257 .num_chans = 4, 258 .vmm_page_size_bytes = 4096, 259 .dram_clock_change_latency_us = 23.84, 260 .return_bus_width_bytes = 64, 261 .dispclk_dppclk_vco_speed_mhz = 3550, 262 .xfc_bus_transport_time_us = 4, 263 .xfc_xbuf_latency_tolerance_us = 4, 264 .use_urgent_burst_bw = 1, 265 .num_states = 5 266 }; 267 268 #ifndef MAX 269 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y)) 270 #endif 271 #ifndef MIN 272 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 273 #endif 274 275 /* begin ********************* 276 * macros to expend register list macro defined in HW object header file */ 277 278 /* DCN */ 279 /* TODO awful hack. fixup dcn20_dwb.h */ 280 #undef BASE_INNER 281 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg 282 283 #define BASE(seg) BASE_INNER(seg) 284 285 #define SR(reg_name)\ 286 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 287 mm ## reg_name 288 289 #define SRI(reg_name, block, id)\ 290 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 291 mm ## block ## id ## _ ## reg_name 292 293 #define SRIR(var_name, reg_name, block, id)\ 294 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 295 mm ## block ## id ## _ ## reg_name 296 297 #define SRII(reg_name, block, id)\ 298 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 299 mm ## block ## id ## _ ## reg_name 300 301 #define DCCG_SRII(reg_name, block, id)\ 302 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 303 mm ## block ## id ## _ ## reg_name 304 305 /* NBIO */ 306 #define NBIO_BASE_INNER(seg) \ 307 NBIF0_BASE__INST0_SEG ## seg 308 309 #define NBIO_BASE(seg) \ 310 NBIO_BASE_INNER(seg) 311 312 #define NBIO_SR(reg_name)\ 313 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 314 mm ## reg_name 315 316 /* MMHUB */ 317 #define MMHUB_BASE_INNER(seg) \ 318 MMHUB_BASE__INST0_SEG ## seg 319 320 #define MMHUB_BASE(seg) \ 321 MMHUB_BASE_INNER(seg) 322 323 #define MMHUB_SR(reg_name)\ 324 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 325 mmMM ## reg_name 326 327 #define clk_src_regs(index, pllid)\ 328 [index] = {\ 329 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\ 330 } 331 332 static const struct dce110_clk_src_regs clk_src_regs[] = { 333 clk_src_regs(0, A), 334 clk_src_regs(1, B), 335 clk_src_regs(2, C), 336 clk_src_regs(3, D), 337 clk_src_regs(4, E), 338 }; 339 340 static const struct dce110_clk_src_shift cs_shift = { 341 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 342 }; 343 344 static const struct dce110_clk_src_mask cs_mask = { 345 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 346 }; 347 348 static const struct bios_registers bios_regs = { 349 NBIO_SR(BIOS_SCRATCH_3), 350 NBIO_SR(BIOS_SCRATCH_6) 351 }; 352 353 #ifdef CONFIG_DRM_AMD_DC_DMUB 354 static const struct dcn21_dmcub_registers dmcub_regs = { 355 DMCUB_REG_LIST_DCN() 356 }; 357 358 static const struct dcn21_dmcub_shift dmcub_shift = { 359 DMCUB_COMMON_MASK_SH_LIST_BASE(__SHIFT) 360 }; 361 362 static const struct dcn21_dmcub_mask dmcub_mask = { 363 DMCUB_COMMON_MASK_SH_LIST_BASE(_MASK) 364 }; 365 #endif 366 367 #define audio_regs(id)\ 368 [id] = {\ 369 AUD_COMMON_REG_LIST(id)\ 370 } 371 372 static const struct dce_audio_registers audio_regs[] = { 373 audio_regs(0), 374 audio_regs(1), 375 audio_regs(2), 376 audio_regs(3), 377 audio_regs(4), 378 audio_regs(5), 379 }; 380 381 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 382 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 383 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 384 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 385 386 static const struct dce_audio_shift audio_shift = { 387 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 388 }; 389 390 static const struct dce_audio_mask audio_mask = { 391 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 392 }; 393 394 static const struct dccg_registers dccg_regs = { 395 DCCG_COMMON_REG_LIST_DCN_BASE() 396 }; 397 398 static const struct dccg_shift dccg_shift = { 399 DCCG_MASK_SH_LIST_DCN2(__SHIFT) 400 }; 401 402 static const struct dccg_mask dccg_mask = { 403 DCCG_MASK_SH_LIST_DCN2(_MASK) 404 }; 405 406 #define opp_regs(id)\ 407 [id] = {\ 408 OPP_REG_LIST_DCN20(id),\ 409 } 410 411 static const struct dcn20_opp_registers opp_regs[] = { 412 opp_regs(0), 413 opp_regs(1), 414 opp_regs(2), 415 opp_regs(3), 416 opp_regs(4), 417 opp_regs(5), 418 }; 419 420 static const struct dcn20_opp_shift opp_shift = { 421 OPP_MASK_SH_LIST_DCN20(__SHIFT) 422 }; 423 424 static const struct dcn20_opp_mask opp_mask = { 425 OPP_MASK_SH_LIST_DCN20(_MASK) 426 }; 427 428 #define tg_regs(id)\ 429 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)} 430 431 static const struct dcn_optc_registers tg_regs[] = { 432 tg_regs(0), 433 tg_regs(1), 434 tg_regs(2), 435 tg_regs(3) 436 }; 437 438 static const struct dcn_optc_shift tg_shift = { 439 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 440 }; 441 442 static const struct dcn_optc_mask tg_mask = { 443 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 444 }; 445 446 static const struct dcn20_mpc_registers mpc_regs = { 447 MPC_REG_LIST_DCN2_0(0), 448 MPC_REG_LIST_DCN2_0(1), 449 MPC_REG_LIST_DCN2_0(2), 450 MPC_REG_LIST_DCN2_0(3), 451 MPC_REG_LIST_DCN2_0(4), 452 MPC_REG_LIST_DCN2_0(5), 453 MPC_OUT_MUX_REG_LIST_DCN2_0(0), 454 MPC_OUT_MUX_REG_LIST_DCN2_0(1), 455 MPC_OUT_MUX_REG_LIST_DCN2_0(2), 456 MPC_OUT_MUX_REG_LIST_DCN2_0(3) 457 }; 458 459 static const struct dcn20_mpc_shift mpc_shift = { 460 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 461 }; 462 463 static const struct dcn20_mpc_mask mpc_mask = { 464 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 465 }; 466 467 #define hubp_regs(id)\ 468 [id] = {\ 469 HUBP_REG_LIST_DCN21(id)\ 470 } 471 472 static const struct dcn_hubp2_registers hubp_regs[] = { 473 hubp_regs(0), 474 hubp_regs(1), 475 hubp_regs(2), 476 hubp_regs(3) 477 }; 478 479 static const struct dcn_hubp2_shift hubp_shift = { 480 HUBP_MASK_SH_LIST_DCN21(__SHIFT) 481 }; 482 483 static const struct dcn_hubp2_mask hubp_mask = { 484 HUBP_MASK_SH_LIST_DCN21(_MASK) 485 }; 486 487 static const struct dcn_hubbub_registers hubbub_reg = { 488 HUBBUB_REG_LIST_DCN21() 489 }; 490 491 static const struct dcn_hubbub_shift hubbub_shift = { 492 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT) 493 }; 494 495 static const struct dcn_hubbub_mask hubbub_mask = { 496 HUBBUB_MASK_SH_LIST_DCN21(_MASK) 497 }; 498 499 500 #define vmid_regs(id)\ 501 [id] = {\ 502 DCN20_VMID_REG_LIST(id)\ 503 } 504 505 static const struct dcn_vmid_registers vmid_regs[] = { 506 vmid_regs(0), 507 vmid_regs(1), 508 vmid_regs(2), 509 vmid_regs(3), 510 vmid_regs(4), 511 vmid_regs(5), 512 vmid_regs(6), 513 vmid_regs(7), 514 vmid_regs(8), 515 vmid_regs(9), 516 vmid_regs(10), 517 vmid_regs(11), 518 vmid_regs(12), 519 vmid_regs(13), 520 vmid_regs(14), 521 vmid_regs(15) 522 }; 523 524 static const struct dcn20_vmid_shift vmid_shifts = { 525 DCN20_VMID_MASK_SH_LIST(__SHIFT) 526 }; 527 528 static const struct dcn20_vmid_mask vmid_masks = { 529 DCN20_VMID_MASK_SH_LIST(_MASK) 530 }; 531 532 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 533 #define dsc_regsDCN20(id)\ 534 [id] = {\ 535 DSC_REG_LIST_DCN20(id)\ 536 } 537 538 static const struct dcn20_dsc_registers dsc_regs[] = { 539 dsc_regsDCN20(0), 540 dsc_regsDCN20(1), 541 dsc_regsDCN20(2), 542 dsc_regsDCN20(3), 543 dsc_regsDCN20(4), 544 dsc_regsDCN20(5) 545 }; 546 547 static const struct dcn20_dsc_shift dsc_shift = { 548 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 549 }; 550 551 static const struct dcn20_dsc_mask dsc_mask = { 552 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 553 }; 554 #endif 555 556 #define ipp_regs(id)\ 557 [id] = {\ 558 IPP_REG_LIST_DCN20(id),\ 559 } 560 561 static const struct dcn10_ipp_registers ipp_regs[] = { 562 ipp_regs(0), 563 ipp_regs(1), 564 ipp_regs(2), 565 ipp_regs(3), 566 }; 567 568 static const struct dcn10_ipp_shift ipp_shift = { 569 IPP_MASK_SH_LIST_DCN20(__SHIFT) 570 }; 571 572 static const struct dcn10_ipp_mask ipp_mask = { 573 IPP_MASK_SH_LIST_DCN20(_MASK), 574 }; 575 576 #define opp_regs(id)\ 577 [id] = {\ 578 OPP_REG_LIST_DCN20(id),\ 579 } 580 581 582 #define aux_engine_regs(id)\ 583 [id] = {\ 584 AUX_COMMON_REG_LIST0(id), \ 585 .AUXN_IMPCAL = 0, \ 586 .AUXP_IMPCAL = 0, \ 587 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 588 } 589 590 static const struct dce110_aux_registers aux_engine_regs[] = { 591 aux_engine_regs(0), 592 aux_engine_regs(1), 593 aux_engine_regs(2), 594 aux_engine_regs(3), 595 aux_engine_regs(4), 596 }; 597 598 #define tf_regs(id)\ 599 [id] = {\ 600 TF_REG_LIST_DCN20(id),\ 601 } 602 603 static const struct dcn2_dpp_registers tf_regs[] = { 604 tf_regs(0), 605 tf_regs(1), 606 tf_regs(2), 607 tf_regs(3), 608 }; 609 610 static const struct dcn2_dpp_shift tf_shift = { 611 TF_REG_LIST_SH_MASK_DCN20(__SHIFT) 612 }; 613 614 static const struct dcn2_dpp_mask tf_mask = { 615 TF_REG_LIST_SH_MASK_DCN20(_MASK) 616 }; 617 618 #define stream_enc_regs(id)\ 619 [id] = {\ 620 SE_DCN2_REG_LIST(id)\ 621 } 622 623 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 624 stream_enc_regs(0), 625 stream_enc_regs(1), 626 stream_enc_regs(2), 627 stream_enc_regs(3), 628 stream_enc_regs(4), 629 }; 630 631 static const struct dcn10_stream_encoder_shift se_shift = { 632 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) 633 }; 634 635 static const struct dcn10_stream_encoder_mask se_mask = { 636 SE_COMMON_MASK_SH_LIST_DCN20(_MASK) 637 }; 638 639 static struct input_pixel_processor *dcn21_ipp_create( 640 struct dc_context *ctx, uint32_t inst) 641 { 642 struct dcn10_ipp *ipp = 643 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 644 645 if (!ipp) { 646 BREAK_TO_DEBUGGER(); 647 return NULL; 648 } 649 650 dcn20_ipp_construct(ipp, ctx, inst, 651 &ipp_regs[inst], &ipp_shift, &ipp_mask); 652 return &ipp->base; 653 } 654 655 static struct dpp *dcn21_dpp_create( 656 struct dc_context *ctx, 657 uint32_t inst) 658 { 659 struct dcn20_dpp *dpp = 660 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL); 661 662 if (!dpp) 663 return NULL; 664 665 if (dpp2_construct(dpp, ctx, inst, 666 &tf_regs[inst], &tf_shift, &tf_mask)) 667 return &dpp->base; 668 669 BREAK_TO_DEBUGGER(); 670 kfree(dpp); 671 return NULL; 672 } 673 674 static struct dce_aux *dcn21_aux_engine_create( 675 struct dc_context *ctx, 676 uint32_t inst) 677 { 678 struct aux_engine_dce110 *aux_engine = 679 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 680 681 if (!aux_engine) 682 return NULL; 683 684 dce110_aux_engine_construct(aux_engine, ctx, inst, 685 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 686 &aux_engine_regs[inst]); 687 688 return &aux_engine->base; 689 } 690 691 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 692 693 static const struct dce_i2c_registers i2c_hw_regs[] = { 694 i2c_inst_regs(1), 695 i2c_inst_regs(2), 696 i2c_inst_regs(3), 697 i2c_inst_regs(4), 698 i2c_inst_regs(5), 699 }; 700 701 static const struct dce_i2c_shift i2c_shifts = { 702 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 703 }; 704 705 static const struct dce_i2c_mask i2c_masks = { 706 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 707 }; 708 709 struct dce_i2c_hw *dcn21_i2c_hw_create( 710 struct dc_context *ctx, 711 uint32_t inst) 712 { 713 struct dce_i2c_hw *dce_i2c_hw = 714 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 715 716 if (!dce_i2c_hw) 717 return NULL; 718 719 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 720 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 721 722 return dce_i2c_hw; 723 } 724 725 static const struct resource_caps res_cap_rn = { 726 .num_timing_generator = 4, 727 .num_opp = 4, 728 .num_video_plane = 4, 729 .num_audio = 6, // 6 audio endpoints. 4 audio streams 730 .num_stream_encoder = 5, 731 .num_pll = 5, // maybe 3 because the last two used for USB-c 732 .num_dwb = 1, 733 .num_ddc = 5, 734 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 735 .num_dsc = 3, 736 #endif 737 }; 738 739 #ifdef DIAGS_BUILD 740 static const struct resource_caps res_cap_rn_FPGA_4pipe = { 741 .num_timing_generator = 4, 742 .num_opp = 4, 743 .num_video_plane = 4, 744 .num_audio = 7, 745 .num_stream_encoder = 4, 746 .num_pll = 4, 747 .num_dwb = 1, 748 .num_ddc = 4, 749 .num_dsc = 0, 750 }; 751 752 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = { 753 .num_timing_generator = 2, 754 .num_opp = 2, 755 .num_video_plane = 2, 756 .num_audio = 7, 757 .num_stream_encoder = 2, 758 .num_pll = 4, 759 .num_dwb = 1, 760 .num_ddc = 4, 761 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 762 .num_dsc = 2, 763 #endif 764 }; 765 #endif 766 767 static const struct dc_plane_cap plane_cap = { 768 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 769 .blends_with_above = true, 770 .blends_with_below = true, 771 .per_pixel_alpha = true, 772 773 .pixel_format_support = { 774 .argb8888 = true, 775 .nv12 = true, 776 .fp16 = true 777 }, 778 779 .max_upscale_factor = { 780 .argb8888 = 16000, 781 .nv12 = 16000, 782 .fp16 = 16000 783 }, 784 785 .max_downscale_factor = { 786 .argb8888 = 250, 787 .nv12 = 250, 788 .fp16 = 250 789 } 790 }; 791 792 static const struct dc_debug_options debug_defaults_drv = { 793 .disable_dmcu = true, 794 .force_abm_enable = false, 795 .timing_trace = false, 796 .clock_trace = true, 797 .disable_pplib_clock_request = true, 798 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 799 .force_single_disp_pipe_split = true, 800 .disable_dcc = DCC_ENABLE, 801 .vsr_support = true, 802 .performance_trace = false, 803 .max_downscale_src_width = 5120,/*upto 5K*/ 804 .disable_pplib_wm_range = false, 805 .scl_reset_length10 = true, 806 .sanity_checks = true, 807 .disable_48mhz_pwrdwn = true, 808 }; 809 810 static const struct dc_debug_options debug_defaults_diags = { 811 .disable_dmcu = true, 812 .force_abm_enable = false, 813 .timing_trace = true, 814 .clock_trace = true, 815 .disable_dpp_power_gate = true, 816 .disable_hubp_power_gate = true, 817 .disable_clock_gate = true, 818 .disable_pplib_clock_request = true, 819 .disable_pplib_wm_range = true, 820 .disable_stutter = true, 821 .disable_48mhz_pwrdwn = true, 822 }; 823 824 enum dcn20_clk_src_array_id { 825 DCN20_CLK_SRC_PLL0, 826 DCN20_CLK_SRC_PLL1, 827 DCN20_CLK_SRC_TOTAL_DCN21 828 }; 829 830 static void destruct(struct dcn21_resource_pool *pool) 831 { 832 unsigned int i; 833 834 for (i = 0; i < pool->base.stream_enc_count; i++) { 835 if (pool->base.stream_enc[i] != NULL) { 836 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 837 pool->base.stream_enc[i] = NULL; 838 } 839 } 840 841 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 842 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 843 if (pool->base.dscs[i] != NULL) 844 dcn20_dsc_destroy(&pool->base.dscs[i]); 845 } 846 #endif 847 848 if (pool->base.mpc != NULL) { 849 kfree(TO_DCN20_MPC(pool->base.mpc)); 850 pool->base.mpc = NULL; 851 } 852 if (pool->base.hubbub != NULL) { 853 kfree(pool->base.hubbub); 854 pool->base.hubbub = NULL; 855 } 856 for (i = 0; i < pool->base.pipe_count; i++) { 857 if (pool->base.dpps[i] != NULL) 858 dcn20_dpp_destroy(&pool->base.dpps[i]); 859 860 if (pool->base.ipps[i] != NULL) 861 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 862 863 if (pool->base.hubps[i] != NULL) { 864 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 865 pool->base.hubps[i] = NULL; 866 } 867 868 if (pool->base.irqs != NULL) { 869 dal_irq_service_destroy(&pool->base.irqs); 870 } 871 } 872 873 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 874 if (pool->base.engines[i] != NULL) 875 dce110_engine_destroy(&pool->base.engines[i]); 876 if (pool->base.hw_i2cs[i] != NULL) { 877 kfree(pool->base.hw_i2cs[i]); 878 pool->base.hw_i2cs[i] = NULL; 879 } 880 if (pool->base.sw_i2cs[i] != NULL) { 881 kfree(pool->base.sw_i2cs[i]); 882 pool->base.sw_i2cs[i] = NULL; 883 } 884 } 885 886 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 887 if (pool->base.opps[i] != NULL) 888 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 889 } 890 891 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 892 if (pool->base.timing_generators[i] != NULL) { 893 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 894 pool->base.timing_generators[i] = NULL; 895 } 896 } 897 898 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 899 if (pool->base.dwbc[i] != NULL) { 900 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); 901 pool->base.dwbc[i] = NULL; 902 } 903 if (pool->base.mcif_wb[i] != NULL) { 904 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); 905 pool->base.mcif_wb[i] = NULL; 906 } 907 } 908 909 for (i = 0; i < pool->base.audio_count; i++) { 910 if (pool->base.audios[i]) 911 dce_aud_destroy(&pool->base.audios[i]); 912 } 913 914 for (i = 0; i < pool->base.clk_src_count; i++) { 915 if (pool->base.clock_sources[i] != NULL) { 916 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 917 pool->base.clock_sources[i] = NULL; 918 } 919 } 920 921 if (pool->base.dp_clock_source != NULL) { 922 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 923 pool->base.dp_clock_source = NULL; 924 } 925 926 927 if (pool->base.abm != NULL) 928 dce_abm_destroy(&pool->base.abm); 929 930 if (pool->base.dmcu != NULL) 931 dce_dmcu_destroy(&pool->base.dmcu); 932 933 #ifdef CONFIG_DRM_AMD_DC_DMUB 934 if (pool->base.dmcub != NULL) 935 dcn21_dmcub_destroy(&pool->base.dmcub); 936 #endif 937 938 if (pool->base.dccg != NULL) 939 dcn_dccg_destroy(&pool->base.dccg); 940 941 if (pool->base.pp_smu != NULL) 942 dcn20_pp_smu_destroy(&pool->base.pp_smu); 943 } 944 945 946 static void calculate_wm_set_for_vlevel( 947 int vlevel, 948 struct wm_range_table_entry *table_entry, 949 struct dcn_watermarks *wm_set, 950 struct display_mode_lib *dml, 951 display_e2e_pipe_params_st *pipes, 952 int pipe_cnt) 953 { 954 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; 955 956 ASSERT(vlevel < dml->soc.num_states); 957 /* only pipe 0 is read for voltage and dcf/soc clocks */ 958 pipes[0].clks_cfg.voltage = vlevel; 959 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; 960 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; 961 962 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; 963 964 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; 965 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; 966 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; 967 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 968 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; 969 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 970 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; 971 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; 972 #endif 973 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; 974 975 } 976 977 void dcn21_calculate_wm( 978 struct dc *dc, struct dc_state *context, 979 display_e2e_pipe_params_st *pipes, 980 int *out_pipe_cnt, 981 int *pipe_split_from, 982 int vlevel_req) 983 { 984 int pipe_cnt, i, pipe_idx; 985 int vlevel, vlevel_max; 986 struct wm_range_table_entry *table_entry; 987 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; 988 989 ASSERT(bw_params); 990 991 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 992 if (!context->res_ctx.pipe_ctx[i].stream) 993 continue; 994 995 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 996 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb]; 997 998 if (pipe_split_from[i] < 0) { 999 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1000 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; 1001 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) 1002 pipes[pipe_cnt].pipe.dest.odm_combine = 1003 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx]; 1004 else 1005 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1006 pipe_idx++; 1007 } else { 1008 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1009 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; 1010 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) 1011 pipes[pipe_cnt].pipe.dest.odm_combine = 1012 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]]; 1013 else 1014 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1015 } 1016 pipe_cnt++; 1017 } 1018 1019 if (pipe_cnt != pipe_idx) { 1020 if (dc->res_pool->funcs->populate_dml_pipes) 1021 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, 1022 &context->res_ctx, pipes); 1023 else 1024 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, 1025 &context->res_ctx, pipes); 1026 } 1027 1028 *out_pipe_cnt = pipe_cnt; 1029 1030 vlevel_max = bw_params->clk_table.num_entries - 1; 1031 1032 1033 /* WM Set D */ 1034 table_entry = &bw_params->wm_table.entries[WM_D]; 1035 if (table_entry->wm_type == WM_TYPE_RETRAINING) 1036 vlevel = 0; 1037 else 1038 vlevel = vlevel_max; 1039 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, 1040 &context->bw_ctx.dml, pipes, pipe_cnt); 1041 /* WM Set C */ 1042 table_entry = &bw_params->wm_table.entries[WM_C]; 1043 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max); 1044 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, 1045 &context->bw_ctx.dml, pipes, pipe_cnt); 1046 /* WM Set B */ 1047 table_entry = &bw_params->wm_table.entries[WM_B]; 1048 vlevel = MIN(MAX(vlevel_req, 1), vlevel_max); 1049 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, 1050 &context->bw_ctx.dml, pipes, pipe_cnt); 1051 1052 /* WM Set A */ 1053 table_entry = &bw_params->wm_table.entries[WM_A]; 1054 vlevel = MIN(vlevel_req, vlevel_max); 1055 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, 1056 &context->bw_ctx.dml, pipes, pipe_cnt); 1057 } 1058 1059 1060 bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context, 1061 bool fast_validate) 1062 { 1063 bool out = false; 1064 1065 BW_VAL_TRACE_SETUP(); 1066 1067 int vlevel = 0; 1068 int pipe_split_from[MAX_PIPES]; 1069 int pipe_cnt = 0; 1070 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1071 DC_LOGGER_INIT(dc->ctx->logger); 1072 1073 BW_VAL_TRACE_COUNT(); 1074 1075 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel); 1076 1077 if (pipe_cnt == 0) 1078 goto validate_out; 1079 1080 if (!out) 1081 goto validate_fail; 1082 1083 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1084 1085 if (fast_validate) { 1086 BW_VAL_TRACE_SKIP(fast); 1087 goto validate_out; 1088 } 1089 1090 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel); 1091 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 1092 1093 BW_VAL_TRACE_END_WATERMARKS(); 1094 1095 goto validate_out; 1096 1097 validate_fail: 1098 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1099 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1100 1101 BW_VAL_TRACE_SKIP(fail); 1102 out = false; 1103 1104 validate_out: 1105 kfree(pipes); 1106 1107 BW_VAL_TRACE_FINISH(); 1108 1109 return out; 1110 } 1111 static void dcn21_destroy_resource_pool(struct resource_pool **pool) 1112 { 1113 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool); 1114 1115 destruct(dcn21_pool); 1116 kfree(dcn21_pool); 1117 *pool = NULL; 1118 } 1119 1120 static struct clock_source *dcn21_clock_source_create( 1121 struct dc_context *ctx, 1122 struct dc_bios *bios, 1123 enum clock_source_id id, 1124 const struct dce110_clk_src_regs *regs, 1125 bool dp_clk_src) 1126 { 1127 struct dce110_clk_src *clk_src = 1128 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1129 1130 if (!clk_src) 1131 return NULL; 1132 1133 if (dcn20_clk_src_construct(clk_src, ctx, bios, id, 1134 regs, &cs_shift, &cs_mask)) { 1135 clk_src->base.dp_clk_src = dp_clk_src; 1136 return &clk_src->base; 1137 } 1138 1139 BREAK_TO_DEBUGGER(); 1140 return NULL; 1141 } 1142 1143 static struct hubp *dcn21_hubp_create( 1144 struct dc_context *ctx, 1145 uint32_t inst) 1146 { 1147 struct dcn21_hubp *hubp21 = 1148 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL); 1149 1150 if (!hubp21) 1151 return NULL; 1152 1153 if (hubp21_construct(hubp21, ctx, inst, 1154 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1155 return &hubp21->base; 1156 1157 BREAK_TO_DEBUGGER(); 1158 kfree(hubp21); 1159 return NULL; 1160 } 1161 1162 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx) 1163 { 1164 int i; 1165 1166 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), 1167 GFP_KERNEL); 1168 1169 if (!hubbub) 1170 return NULL; 1171 1172 hubbub21_construct(hubbub, ctx, 1173 &hubbub_reg, 1174 &hubbub_shift, 1175 &hubbub_mask); 1176 1177 for (i = 0; i < res_cap_rn.num_vmid; i++) { 1178 struct dcn20_vmid *vmid = &hubbub->vmid[i]; 1179 1180 vmid->ctx = ctx; 1181 1182 vmid->regs = &vmid_regs[i]; 1183 vmid->shifts = &vmid_shifts; 1184 vmid->masks = &vmid_masks; 1185 } 1186 1187 return &hubbub->base; 1188 } 1189 1190 struct output_pixel_processor *dcn21_opp_create( 1191 struct dc_context *ctx, uint32_t inst) 1192 { 1193 struct dcn20_opp *opp = 1194 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1195 1196 if (!opp) { 1197 BREAK_TO_DEBUGGER(); 1198 return NULL; 1199 } 1200 1201 dcn20_opp_construct(opp, ctx, inst, 1202 &opp_regs[inst], &opp_shift, &opp_mask); 1203 return &opp->base; 1204 } 1205 1206 struct timing_generator *dcn21_timing_generator_create( 1207 struct dc_context *ctx, 1208 uint32_t instance) 1209 { 1210 struct optc *tgn10 = 1211 kzalloc(sizeof(struct optc), GFP_KERNEL); 1212 1213 if (!tgn10) 1214 return NULL; 1215 1216 tgn10->base.inst = instance; 1217 tgn10->base.ctx = ctx; 1218 1219 tgn10->tg_regs = &tg_regs[instance]; 1220 tgn10->tg_shift = &tg_shift; 1221 tgn10->tg_mask = &tg_mask; 1222 1223 dcn20_timing_generator_init(tgn10); 1224 1225 return &tgn10->base; 1226 } 1227 1228 struct mpc *dcn21_mpc_create(struct dc_context *ctx) 1229 { 1230 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), 1231 GFP_KERNEL); 1232 1233 if (!mpc20) 1234 return NULL; 1235 1236 dcn20_mpc_construct(mpc20, ctx, 1237 &mpc_regs, 1238 &mpc_shift, 1239 &mpc_mask, 1240 6); 1241 1242 return &mpc20->base; 1243 } 1244 1245 static void read_dce_straps( 1246 struct dc_context *ctx, 1247 struct resource_straps *straps) 1248 { 1249 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1250 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1251 1252 } 1253 1254 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1255 1256 struct display_stream_compressor *dcn21_dsc_create( 1257 struct dc_context *ctx, uint32_t inst) 1258 { 1259 struct dcn20_dsc *dsc = 1260 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1261 1262 if (!dsc) { 1263 BREAK_TO_DEBUGGER(); 1264 return NULL; 1265 } 1266 1267 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1268 return &dsc->base; 1269 } 1270 #endif 1271 1272 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1273 { 1274 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool); 1275 struct clk_limit_table *clk_table = &bw_params->clk_table; 1276 int i; 1277 1278 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator; 1279 dcn2_1_ip.max_num_dpp = pool->base.pipe_count; 1280 dcn2_1_soc.num_chans = bw_params->num_channels; 1281 dcn2_1_soc.num_states = 0; 1282 1283 for (i = 0; i < clk_table->num_entries; i++) { 1284 1285 dcn2_1_soc.clock_limits[i].state = i; 1286 dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 1287 dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 1288 dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; 1289 /* This is probably wrong, TODO: find correct calculation */ 1290 dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 16 / 1000; 1291 dcn2_1_soc.num_states++; 1292 } 1293 } 1294 1295 /* Temporary Place holder until we can get them from fuse */ 1296 static struct dpm_clocks dummy_clocks = { 1297 .DcfClocks = { 1298 {.Freq = 400, .Vol = 1}, 1299 {.Freq = 483, .Vol = 1}, 1300 {.Freq = 602, .Vol = 1}, 1301 {.Freq = 738, .Vol = 1} }, 1302 .SocClocks = { 1303 {.Freq = 300, .Vol = 1}, 1304 {.Freq = 400, .Vol = 1}, 1305 {.Freq = 400, .Vol = 1}, 1306 {.Freq = 400, .Vol = 1} }, 1307 .FClocks = { 1308 {.Freq = 400, .Vol = 1}, 1309 {.Freq = 800, .Vol = 1}, 1310 {.Freq = 1067, .Vol = 1}, 1311 {.Freq = 1600, .Vol = 1} }, 1312 .MemClocks = { 1313 {.Freq = 800, .Vol = 1}, 1314 {.Freq = 1600, .Vol = 1}, 1315 {.Freq = 1067, .Vol = 1}, 1316 {.Freq = 1600, .Vol = 1} }, 1317 1318 }; 1319 1320 enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp, 1321 struct pp_smu_wm_range_sets *ranges) 1322 { 1323 return PP_SMU_RESULT_OK; 1324 } 1325 1326 enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp, 1327 struct dpm_clocks *clock_table) 1328 { 1329 *clock_table = dummy_clocks; 1330 return PP_SMU_RESULT_OK; 1331 } 1332 1333 struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx) 1334 { 1335 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 1336 1337 pp_smu->ctx.ver = PP_SMU_VER_RN; 1338 1339 pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table; 1340 pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges; 1341 1342 return pp_smu; 1343 } 1344 1345 void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu) 1346 { 1347 if (pp_smu && *pp_smu) { 1348 kfree(*pp_smu); 1349 *pp_smu = NULL; 1350 } 1351 } 1352 1353 static struct audio *dcn21_create_audio( 1354 struct dc_context *ctx, unsigned int inst) 1355 { 1356 return dce_audio_create(ctx, inst, 1357 &audio_regs[inst], &audio_shift, &audio_mask); 1358 } 1359 1360 static struct dc_cap_funcs cap_funcs = { 1361 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1362 }; 1363 1364 struct stream_encoder *dcn21_stream_encoder_create( 1365 enum engine_id eng_id, 1366 struct dc_context *ctx) 1367 { 1368 struct dcn10_stream_encoder *enc1 = 1369 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1370 1371 if (!enc1) 1372 return NULL; 1373 1374 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1375 &stream_enc_regs[eng_id], 1376 &se_shift, &se_mask); 1377 1378 return &enc1->base; 1379 } 1380 1381 static const struct dce_hwseq_registers hwseq_reg = { 1382 HWSEQ_DCN21_REG_LIST() 1383 }; 1384 1385 static const struct dce_hwseq_shift hwseq_shift = { 1386 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT) 1387 }; 1388 1389 static const struct dce_hwseq_mask hwseq_mask = { 1390 HWSEQ_DCN21_MASK_SH_LIST(_MASK) 1391 }; 1392 1393 static struct dce_hwseq *dcn21_hwseq_create( 1394 struct dc_context *ctx) 1395 { 1396 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1397 1398 if (hws) { 1399 hws->ctx = ctx; 1400 hws->regs = &hwseq_reg; 1401 hws->shifts = &hwseq_shift; 1402 hws->masks = &hwseq_mask; 1403 } 1404 return hws; 1405 } 1406 1407 static const struct resource_create_funcs res_create_funcs = { 1408 .read_dce_straps = read_dce_straps, 1409 .create_audio = dcn21_create_audio, 1410 .create_stream_encoder = dcn21_stream_encoder_create, 1411 .create_hwseq = dcn21_hwseq_create, 1412 }; 1413 1414 static const struct resource_create_funcs res_create_maximus_funcs = { 1415 .read_dce_straps = NULL, 1416 .create_audio = NULL, 1417 .create_stream_encoder = NULL, 1418 .create_hwseq = dcn21_hwseq_create, 1419 }; 1420 1421 static struct resource_funcs dcn21_res_pool_funcs = { 1422 .destroy = dcn21_destroy_resource_pool, 1423 .link_enc_create = dcn20_link_encoder_create, 1424 .validate_bandwidth = dcn21_validate_bandwidth, 1425 .add_stream_to_ctx = dcn20_add_stream_to_ctx, 1426 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1427 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1428 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, 1429 .get_default_swizzle_mode = dcn20_get_default_swizzle_mode, 1430 .set_mcif_arb_params = dcn20_set_mcif_arb_params, 1431 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1432 .update_bw_bounding_box = update_bw_bounding_box 1433 }; 1434 1435 static bool construct( 1436 uint8_t num_virtual_links, 1437 struct dc *dc, 1438 struct dcn21_resource_pool *pool) 1439 { 1440 int i; 1441 struct dc_context *ctx = dc->ctx; 1442 struct irq_service_init_data init_data; 1443 1444 ctx->dc_bios->regs = &bios_regs; 1445 1446 pool->base.res_cap = &res_cap_rn; 1447 #ifdef DIAGS_BUILD 1448 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1449 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc; 1450 pool->base.res_cap = &res_cap_rn_FPGA_4pipe; 1451 #endif 1452 1453 pool->base.funcs = &dcn21_res_pool_funcs; 1454 1455 /************************************************* 1456 * Resource + asic cap harcoding * 1457 *************************************************/ 1458 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1459 1460 pool->base.pipe_count = 4; 1461 dc->caps.max_downscale_ratio = 200; 1462 dc->caps.i2c_speed_in_khz = 100; 1463 dc->caps.max_cursor_size = 256; 1464 dc->caps.dmdata_alloc_size = 2048; 1465 dc->caps.hw_3d_lut = true; 1466 1467 dc->caps.max_slave_planes = 1; 1468 dc->caps.post_blend_color_processing = true; 1469 dc->caps.force_dp_tps4_for_cp2520 = true; 1470 1471 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1472 dc->debug = debug_defaults_drv; 1473 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1474 pool->base.pipe_count = 4; 1475 dc->debug = debug_defaults_diags; 1476 } else 1477 dc->debug = debug_defaults_diags; 1478 1479 // Init the vm_helper 1480 if (dc->vm_helper) 1481 vm_helper_init(dc->vm_helper, 16); 1482 1483 /************************************************* 1484 * Create resources * 1485 *************************************************/ 1486 1487 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = 1488 dcn21_clock_source_create(ctx, ctx->dc_bios, 1489 CLOCK_SOURCE_COMBO_PHY_PLL0, 1490 &clk_src_regs[0], false); 1491 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = 1492 dcn21_clock_source_create(ctx, ctx->dc_bios, 1493 CLOCK_SOURCE_COMBO_PHY_PLL1, 1494 &clk_src_regs[1], false); 1495 1496 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21; 1497 1498 /* todo: not reuse phy_pll registers */ 1499 pool->base.dp_clock_source = 1500 dcn21_clock_source_create(ctx, ctx->dc_bios, 1501 CLOCK_SOURCE_ID_DP_DTO, 1502 &clk_src_regs[0], true); 1503 1504 for (i = 0; i < pool->base.clk_src_count; i++) { 1505 if (pool->base.clock_sources[i] == NULL) { 1506 dm_error("DC: failed to create clock sources!\n"); 1507 BREAK_TO_DEBUGGER(); 1508 goto create_fail; 1509 } 1510 } 1511 1512 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1513 if (pool->base.dccg == NULL) { 1514 dm_error("DC: failed to create dccg!\n"); 1515 BREAK_TO_DEBUGGER(); 1516 goto create_fail; 1517 } 1518 1519 #ifdef CONFIG_DRM_AMD_DC_DMUB 1520 pool->base.dmcub = dcn21_dmcub_create(ctx, 1521 &dmcub_regs, 1522 &dmcub_shift, 1523 &dmcub_mask); 1524 if (pool->base.dmcub == NULL) { 1525 dm_error("DC: failed to create dmcub!\n"); 1526 BREAK_TO_DEBUGGER(); 1527 goto create_fail; 1528 } 1529 #endif 1530 1531 pool->base.pp_smu = dcn21_pp_smu_create(ctx); 1532 1533 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); 1534 1535 init_data.ctx = dc->ctx; 1536 pool->base.irqs = dal_irq_service_dcn21_create(&init_data); 1537 if (!pool->base.irqs) 1538 goto create_fail; 1539 1540 /* mem input -> ipp -> dpp -> opp -> TG */ 1541 for (i = 0; i < pool->base.pipe_count; i++) { 1542 pool->base.hubps[i] = dcn21_hubp_create(ctx, i); 1543 if (pool->base.hubps[i] == NULL) { 1544 BREAK_TO_DEBUGGER(); 1545 dm_error( 1546 "DC: failed to create memory input!\n"); 1547 goto create_fail; 1548 } 1549 1550 pool->base.ipps[i] = dcn21_ipp_create(ctx, i); 1551 if (pool->base.ipps[i] == NULL) { 1552 BREAK_TO_DEBUGGER(); 1553 dm_error( 1554 "DC: failed to create input pixel processor!\n"); 1555 goto create_fail; 1556 } 1557 1558 pool->base.dpps[i] = dcn21_dpp_create(ctx, i); 1559 if (pool->base.dpps[i] == NULL) { 1560 BREAK_TO_DEBUGGER(); 1561 dm_error( 1562 "DC: failed to create dpps!\n"); 1563 goto create_fail; 1564 } 1565 } 1566 1567 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1568 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i); 1569 if (pool->base.engines[i] == NULL) { 1570 BREAK_TO_DEBUGGER(); 1571 dm_error( 1572 "DC:failed to create aux engine!!\n"); 1573 goto create_fail; 1574 } 1575 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i); 1576 if (pool->base.hw_i2cs[i] == NULL) { 1577 BREAK_TO_DEBUGGER(); 1578 dm_error( 1579 "DC:failed to create hw i2c!!\n"); 1580 goto create_fail; 1581 } 1582 pool->base.sw_i2cs[i] = NULL; 1583 } 1584 1585 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1586 pool->base.opps[i] = dcn21_opp_create(ctx, i); 1587 if (pool->base.opps[i] == NULL) { 1588 BREAK_TO_DEBUGGER(); 1589 dm_error( 1590 "DC: failed to create output pixel processor!\n"); 1591 goto create_fail; 1592 } 1593 } 1594 1595 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1596 pool->base.timing_generators[i] = dcn21_timing_generator_create( 1597 ctx, i); 1598 if (pool->base.timing_generators[i] == NULL) { 1599 BREAK_TO_DEBUGGER(); 1600 dm_error("DC: failed to create tg!\n"); 1601 goto create_fail; 1602 } 1603 } 1604 1605 pool->base.timing_generator_count = i; 1606 1607 pool->base.mpc = dcn21_mpc_create(ctx); 1608 if (pool->base.mpc == NULL) { 1609 BREAK_TO_DEBUGGER(); 1610 dm_error("DC: failed to create mpc!\n"); 1611 goto create_fail; 1612 } 1613 1614 pool->base.hubbub = dcn21_hubbub_create(ctx); 1615 if (pool->base.hubbub == NULL) { 1616 BREAK_TO_DEBUGGER(); 1617 dm_error("DC: failed to create hubbub!\n"); 1618 goto create_fail; 1619 } 1620 1621 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1622 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1623 pool->base.dscs[i] = dcn21_dsc_create(ctx, i); 1624 if (pool->base.dscs[i] == NULL) { 1625 BREAK_TO_DEBUGGER(); 1626 dm_error("DC: failed to create display stream compressor %d!\n", i); 1627 goto create_fail; 1628 } 1629 } 1630 #endif 1631 1632 if (!dcn20_dwbc_create(ctx, &pool->base)) { 1633 BREAK_TO_DEBUGGER(); 1634 dm_error("DC: failed to create dwbc!\n"); 1635 goto create_fail; 1636 } 1637 if (!dcn20_mmhubbub_create(ctx, &pool->base)) { 1638 BREAK_TO_DEBUGGER(); 1639 dm_error("DC: failed to create mcif_wb!\n"); 1640 goto create_fail; 1641 } 1642 1643 if (!resource_construct(num_virtual_links, dc, &pool->base, 1644 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1645 &res_create_funcs : &res_create_maximus_funcs))) 1646 goto create_fail; 1647 1648 dcn20_hw_sequencer_construct(dc); 1649 1650 dc->caps.max_planes = pool->base.pipe_count; 1651 1652 for (i = 0; i < dc->caps.max_planes; ++i) 1653 dc->caps.planes[i] = plane_cap; 1654 1655 dc->cap_funcs = cap_funcs; 1656 1657 return true; 1658 1659 create_fail: 1660 1661 destruct(pool); 1662 1663 return false; 1664 } 1665 1666 struct resource_pool *dcn21_create_resource_pool( 1667 const struct dc_init_data *init_data, 1668 struct dc *dc) 1669 { 1670 struct dcn21_resource_pool *pool = 1671 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL); 1672 1673 if (!pool) 1674 return NULL; 1675 1676 if (construct(init_data->num_virtual_links, dc, pool)) 1677 return &pool->base; 1678 1679 BREAK_TO_DEBUGGER(); 1680 kfree(pool); 1681 return NULL; 1682 } 1683