1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * Copyright 2019 Raptor Engineering, LLC 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 #include "dc.h" 31 32 #include "dcn21_init.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dcn20/dcn20_resource.h" 37 38 #include "clk_mgr.h" 39 #include "dcn10/dcn10_hubp.h" 40 #include "dcn10/dcn10_ipp.h" 41 #include "dcn20/dcn20_hubbub.h" 42 #include "dcn20/dcn20_mpc.h" 43 #include "dcn20/dcn20_hubp.h" 44 #include "dcn21_hubp.h" 45 #include "irq/dcn21/irq_service_dcn21.h" 46 #include "dcn20/dcn20_dpp.h" 47 #include "dcn20/dcn20_optc.h" 48 #include "dcn21/dcn21_hwseq.h" 49 #include "dce110/dce110_hw_sequencer.h" 50 #include "dcn20/dcn20_opp.h" 51 #include "dcn20/dcn20_dsc.h" 52 #include "dcn21/dcn21_link_encoder.h" 53 #include "dcn20/dcn20_stream_encoder.h" 54 #include "dce/dce_clock_source.h" 55 #include "dce/dce_audio.h" 56 #include "dce/dce_hwseq.h" 57 #include "virtual/virtual_stream_encoder.h" 58 #include "dce110/dce110_resource.h" 59 #include "dml/display_mode_vba.h" 60 #include "dcn20/dcn20_dccg.h" 61 #include "dcn21_hubbub.h" 62 #include "dcn10/dcn10_resource.h" 63 #include "dce110/dce110_resource.h" 64 65 #include "dcn20/dcn20_dwb.h" 66 #include "dcn20/dcn20_mmhubbub.h" 67 #include "dpcs/dpcs_2_1_0_offset.h" 68 #include "dpcs/dpcs_2_1_0_sh_mask.h" 69 70 #include "renoir_ip_offset.h" 71 #include "dcn/dcn_2_1_0_offset.h" 72 #include "dcn/dcn_2_1_0_sh_mask.h" 73 74 #include "nbio/nbio_7_0_offset.h" 75 76 #include "mmhub/mmhub_2_0_0_offset.h" 77 #include "mmhub/mmhub_2_0_0_sh_mask.h" 78 79 #include "reg_helper.h" 80 #include "dce/dce_abm.h" 81 #include "dce/dce_dmcu.h" 82 #include "dce/dce_aux.h" 83 #include "dce/dce_i2c.h" 84 #include "dcn21_resource.h" 85 #include "vm_helper.h" 86 #include "dcn20/dcn20_vmid.h" 87 #include "../dce/dmub_psr.h" 88 89 #define SOC_BOUNDING_BOX_VALID false 90 #define DC_LOGGER_INIT(logger) 91 92 93 struct _vcs_dpi_ip_params_st dcn2_1_ip = { 94 .odm_capable = 1, 95 .gpuvm_enable = 1, 96 .hostvm_enable = 1, 97 .gpuvm_max_page_table_levels = 1, 98 .hostvm_max_page_table_levels = 4, 99 .hostvm_cached_page_table_levels = 2, 100 .num_dsc = 3, 101 .rob_buffer_size_kbytes = 168, 102 .det_buffer_size_kbytes = 164, 103 .dpte_buffer_size_in_pte_reqs_luma = 44, 104 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo 105 .dpp_output_buffer_pixels = 2560, 106 .opp_output_buffer_lines = 1, 107 .pixel_chunk_size_kbytes = 8, 108 .pte_enable = 1, 109 .max_page_table_levels = 4, 110 .pte_chunk_size_kbytes = 2, 111 .meta_chunk_size_kbytes = 2, 112 .writeback_chunk_size_kbytes = 2, 113 .line_buffer_size_bits = 789504, 114 .is_line_buffer_bpp_fixed = 0, 115 .line_buffer_fixed_bpp = 0, 116 .dcc_supported = true, 117 .max_line_buffer_lines = 12, 118 .writeback_luma_buffer_size_kbytes = 12, 119 .writeback_chroma_buffer_size_kbytes = 8, 120 .writeback_chroma_line_buffer_width_pixels = 4, 121 .writeback_max_hscl_ratio = 1, 122 .writeback_max_vscl_ratio = 1, 123 .writeback_min_hscl_ratio = 1, 124 .writeback_min_vscl_ratio = 1, 125 .writeback_max_hscl_taps = 12, 126 .writeback_max_vscl_taps = 12, 127 .writeback_line_buffer_luma_buffer_size = 0, 128 .writeback_line_buffer_chroma_buffer_size = 14643, 129 .cursor_buffer_size = 8, 130 .cursor_chunk_size = 2, 131 .max_num_otg = 4, 132 .max_num_dpp = 4, 133 .max_num_wb = 1, 134 .max_dchub_pscl_bw_pix_per_clk = 4, 135 .max_pscl_lb_bw_pix_per_clk = 2, 136 .max_lb_vscl_bw_pix_per_clk = 4, 137 .max_vscl_hscl_bw_pix_per_clk = 4, 138 .max_hscl_ratio = 4, 139 .max_vscl_ratio = 4, 140 .hscl_mults = 4, 141 .vscl_mults = 4, 142 .max_hscl_taps = 8, 143 .max_vscl_taps = 8, 144 .dispclk_ramp_margin_percent = 1, 145 .underscan_factor = 1.10, 146 .min_vblank_lines = 32, // 147 .dppclk_delay_subtotal = 77, // 148 .dppclk_delay_scl_lb_only = 16, 149 .dppclk_delay_scl = 50, 150 .dppclk_delay_cnvc_formatter = 8, 151 .dppclk_delay_cnvc_cursor = 6, 152 .dispclk_delay_subtotal = 87, // 153 .dcfclk_cstate_latency = 10, // SRExitTime 154 .max_inter_dcn_tile_repeaters = 8, 155 156 .xfc_supported = false, 157 .xfc_fill_bw_overhead_percent = 10.0, 158 .xfc_fill_constant_bytes = 0, 159 .ptoi_supported = 0 160 }; 161 162 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { 163 .clock_limits = { 164 { 165 .state = 0, 166 .dcfclk_mhz = 304.0, 167 .fabricclk_mhz = 600.0, 168 .dispclk_mhz = 618.0, 169 .dppclk_mhz = 440.0, 170 .phyclk_mhz = 600.0, 171 .socclk_mhz = 278.0, 172 .dscclk_mhz = 205.67, 173 .dram_speed_mts = 1600.0, 174 }, 175 { 176 .state = 1, 177 .dcfclk_mhz = 304.0, 178 .fabricclk_mhz = 600.0, 179 .dispclk_mhz = 618.0, 180 .dppclk_mhz = 618.0, 181 .phyclk_mhz = 600.0, 182 .socclk_mhz = 278.0, 183 .dscclk_mhz = 205.67, 184 .dram_speed_mts = 1600.0, 185 }, 186 { 187 .state = 2, 188 .dcfclk_mhz = 608.0, 189 .fabricclk_mhz = 1066.0, 190 .dispclk_mhz = 888.0, 191 .dppclk_mhz = 888.0, 192 .phyclk_mhz = 810.0, 193 .socclk_mhz = 278.0, 194 .dscclk_mhz = 287.67, 195 .dram_speed_mts = 2133.0, 196 }, 197 { 198 .state = 3, 199 .dcfclk_mhz = 676.0, 200 .fabricclk_mhz = 1600.0, 201 .dispclk_mhz = 1015.0, 202 .dppclk_mhz = 1015.0, 203 .phyclk_mhz = 810.0, 204 .socclk_mhz = 715.0, 205 .dscclk_mhz = 318.334, 206 .dram_speed_mts = 4266.0, 207 }, 208 { 209 .state = 4, 210 .dcfclk_mhz = 810.0, 211 .fabricclk_mhz = 1600.0, 212 .dispclk_mhz = 1395.0, 213 .dppclk_mhz = 1285.0, 214 .phyclk_mhz = 1325.0, 215 .socclk_mhz = 953.0, 216 .dscclk_mhz = 489.0, 217 .dram_speed_mts = 4266.0, 218 }, 219 /*Extra state, no dispclk ramping*/ 220 { 221 .state = 5, 222 .dcfclk_mhz = 810.0, 223 .fabricclk_mhz = 1600.0, 224 .dispclk_mhz = 1395.0, 225 .dppclk_mhz = 1285.0, 226 .phyclk_mhz = 1325.0, 227 .socclk_mhz = 953.0, 228 .dscclk_mhz = 489.0, 229 .dram_speed_mts = 4266.0, 230 }, 231 232 }, 233 234 .sr_exit_time_us = 12.5, 235 .sr_enter_plus_exit_time_us = 17.0, 236 .urgent_latency_us = 4.0, 237 .urgent_latency_pixel_data_only_us = 4.0, 238 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 239 .urgent_latency_vm_data_only_us = 4.0, 240 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 241 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 242 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 243 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 244 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0, 245 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 246 .max_avg_sdp_bw_use_normal_percent = 60.0, 247 .max_avg_dram_bw_use_normal_percent = 100.0, 248 .writeback_latency_us = 12.0, 249 .max_request_size_bytes = 256, 250 .dram_channel_width_bytes = 4, 251 .fabric_datapath_to_dcn_data_return_bytes = 32, 252 .dcn_downspread_percent = 0.5, 253 .downspread_percent = 0.5, 254 .dram_page_open_time_ns = 50.0, 255 .dram_rw_turnaround_time_ns = 17.5, 256 .dram_return_buffer_per_channel_bytes = 8192, 257 .round_trip_ping_latency_dcfclk_cycles = 128, 258 .urgent_out_of_order_return_per_channel_bytes = 4096, 259 .channel_interleave_bytes = 256, 260 .num_banks = 8, 261 .num_chans = 4, 262 .vmm_page_size_bytes = 4096, 263 .dram_clock_change_latency_us = 23.84, 264 .return_bus_width_bytes = 64, 265 .dispclk_dppclk_vco_speed_mhz = 3600, 266 .xfc_bus_transport_time_us = 4, 267 .xfc_xbuf_latency_tolerance_us = 4, 268 .use_urgent_burst_bw = 1, 269 .num_states = 5 270 }; 271 272 #ifndef MAX 273 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y)) 274 #endif 275 #ifndef MIN 276 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 277 #endif 278 279 /* begin ********************* 280 * macros to expend register list macro defined in HW object header file */ 281 282 /* DCN */ 283 /* TODO awful hack. fixup dcn20_dwb.h */ 284 #undef BASE_INNER 285 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg 286 287 #define BASE(seg) BASE_INNER(seg) 288 289 #define SR(reg_name)\ 290 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 291 mm ## reg_name 292 293 #define SRI(reg_name, block, id)\ 294 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 295 mm ## block ## id ## _ ## reg_name 296 297 #define SRIR(var_name, reg_name, block, id)\ 298 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 299 mm ## block ## id ## _ ## reg_name 300 301 #define SRII(reg_name, block, id)\ 302 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 303 mm ## block ## id ## _ ## reg_name 304 305 #define DCCG_SRII(reg_name, block, id)\ 306 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 307 mm ## block ## id ## _ ## reg_name 308 309 /* NBIO */ 310 #define NBIO_BASE_INNER(seg) \ 311 NBIF0_BASE__INST0_SEG ## seg 312 313 #define NBIO_BASE(seg) \ 314 NBIO_BASE_INNER(seg) 315 316 #define NBIO_SR(reg_name)\ 317 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 318 mm ## reg_name 319 320 /* MMHUB */ 321 #define MMHUB_BASE_INNER(seg) \ 322 MMHUB_BASE__INST0_SEG ## seg 323 324 #define MMHUB_BASE(seg) \ 325 MMHUB_BASE_INNER(seg) 326 327 #define MMHUB_SR(reg_name)\ 328 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 329 mmMM ## reg_name 330 331 #define clk_src_regs(index, pllid)\ 332 [index] = {\ 333 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\ 334 } 335 336 static const struct dce110_clk_src_regs clk_src_regs[] = { 337 clk_src_regs(0, A), 338 clk_src_regs(1, B), 339 clk_src_regs(2, C), 340 clk_src_regs(3, D), 341 clk_src_regs(4, E), 342 }; 343 344 static const struct dce110_clk_src_shift cs_shift = { 345 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 346 }; 347 348 static const struct dce110_clk_src_mask cs_mask = { 349 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 350 }; 351 352 static const struct bios_registers bios_regs = { 353 NBIO_SR(BIOS_SCRATCH_3), 354 NBIO_SR(BIOS_SCRATCH_6) 355 }; 356 357 static const struct dce_dmcu_registers dmcu_regs = { 358 DMCU_DCN20_REG_LIST() 359 }; 360 361 static const struct dce_dmcu_shift dmcu_shift = { 362 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 363 }; 364 365 static const struct dce_dmcu_mask dmcu_mask = { 366 DMCU_MASK_SH_LIST_DCN10(_MASK) 367 }; 368 369 static const struct dce_abm_registers abm_regs = { 370 ABM_DCN20_REG_LIST() 371 }; 372 373 static const struct dce_abm_shift abm_shift = { 374 ABM_MASK_SH_LIST_DCN20(__SHIFT) 375 }; 376 377 static const struct dce_abm_mask abm_mask = { 378 ABM_MASK_SH_LIST_DCN20(_MASK) 379 }; 380 381 #define audio_regs(id)\ 382 [id] = {\ 383 AUD_COMMON_REG_LIST(id)\ 384 } 385 386 static const struct dce_audio_registers audio_regs[] = { 387 audio_regs(0), 388 audio_regs(1), 389 audio_regs(2), 390 audio_regs(3), 391 audio_regs(4), 392 audio_regs(5), 393 }; 394 395 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 396 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 397 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 398 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 399 400 static const struct dce_audio_shift audio_shift = { 401 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 402 }; 403 404 static const struct dce_audio_mask audio_mask = { 405 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 406 }; 407 408 static const struct dccg_registers dccg_regs = { 409 DCCG_COMMON_REG_LIST_DCN_BASE() 410 }; 411 412 static const struct dccg_shift dccg_shift = { 413 DCCG_MASK_SH_LIST_DCN2(__SHIFT) 414 }; 415 416 static const struct dccg_mask dccg_mask = { 417 DCCG_MASK_SH_LIST_DCN2(_MASK) 418 }; 419 420 #define opp_regs(id)\ 421 [id] = {\ 422 OPP_REG_LIST_DCN20(id),\ 423 } 424 425 static const struct dcn20_opp_registers opp_regs[] = { 426 opp_regs(0), 427 opp_regs(1), 428 opp_regs(2), 429 opp_regs(3), 430 opp_regs(4), 431 opp_regs(5), 432 }; 433 434 static const struct dcn20_opp_shift opp_shift = { 435 OPP_MASK_SH_LIST_DCN20(__SHIFT) 436 }; 437 438 static const struct dcn20_opp_mask opp_mask = { 439 OPP_MASK_SH_LIST_DCN20(_MASK) 440 }; 441 442 #define tg_regs(id)\ 443 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)} 444 445 static const struct dcn_optc_registers tg_regs[] = { 446 tg_regs(0), 447 tg_regs(1), 448 tg_regs(2), 449 tg_regs(3) 450 }; 451 452 static const struct dcn_optc_shift tg_shift = { 453 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 454 }; 455 456 static const struct dcn_optc_mask tg_mask = { 457 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 458 }; 459 460 static const struct dcn20_mpc_registers mpc_regs = { 461 MPC_REG_LIST_DCN2_0(0), 462 MPC_REG_LIST_DCN2_0(1), 463 MPC_REG_LIST_DCN2_0(2), 464 MPC_REG_LIST_DCN2_0(3), 465 MPC_REG_LIST_DCN2_0(4), 466 MPC_REG_LIST_DCN2_0(5), 467 MPC_OUT_MUX_REG_LIST_DCN2_0(0), 468 MPC_OUT_MUX_REG_LIST_DCN2_0(1), 469 MPC_OUT_MUX_REG_LIST_DCN2_0(2), 470 MPC_OUT_MUX_REG_LIST_DCN2_0(3), 471 MPC_DBG_REG_LIST_DCN2_0() 472 }; 473 474 static const struct dcn20_mpc_shift mpc_shift = { 475 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT), 476 MPC_DEBUG_REG_LIST_SH_DCN20 477 }; 478 479 static const struct dcn20_mpc_mask mpc_mask = { 480 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK), 481 MPC_DEBUG_REG_LIST_MASK_DCN20 482 }; 483 484 #define hubp_regs(id)\ 485 [id] = {\ 486 HUBP_REG_LIST_DCN21(id)\ 487 } 488 489 static const struct dcn_hubp2_registers hubp_regs[] = { 490 hubp_regs(0), 491 hubp_regs(1), 492 hubp_regs(2), 493 hubp_regs(3) 494 }; 495 496 static const struct dcn_hubp2_shift hubp_shift = { 497 HUBP_MASK_SH_LIST_DCN21(__SHIFT) 498 }; 499 500 static const struct dcn_hubp2_mask hubp_mask = { 501 HUBP_MASK_SH_LIST_DCN21(_MASK) 502 }; 503 504 static const struct dcn_hubbub_registers hubbub_reg = { 505 HUBBUB_REG_LIST_DCN21() 506 }; 507 508 static const struct dcn_hubbub_shift hubbub_shift = { 509 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT) 510 }; 511 512 static const struct dcn_hubbub_mask hubbub_mask = { 513 HUBBUB_MASK_SH_LIST_DCN21(_MASK) 514 }; 515 516 517 #define vmid_regs(id)\ 518 [id] = {\ 519 DCN20_VMID_REG_LIST(id)\ 520 } 521 522 static const struct dcn_vmid_registers vmid_regs[] = { 523 vmid_regs(0), 524 vmid_regs(1), 525 vmid_regs(2), 526 vmid_regs(3), 527 vmid_regs(4), 528 vmid_regs(5), 529 vmid_regs(6), 530 vmid_regs(7), 531 vmid_regs(8), 532 vmid_regs(9), 533 vmid_regs(10), 534 vmid_regs(11), 535 vmid_regs(12), 536 vmid_regs(13), 537 vmid_regs(14), 538 vmid_regs(15) 539 }; 540 541 static const struct dcn20_vmid_shift vmid_shifts = { 542 DCN20_VMID_MASK_SH_LIST(__SHIFT) 543 }; 544 545 static const struct dcn20_vmid_mask vmid_masks = { 546 DCN20_VMID_MASK_SH_LIST(_MASK) 547 }; 548 549 #define dsc_regsDCN20(id)\ 550 [id] = {\ 551 DSC_REG_LIST_DCN20(id)\ 552 } 553 554 static const struct dcn20_dsc_registers dsc_regs[] = { 555 dsc_regsDCN20(0), 556 dsc_regsDCN20(1), 557 dsc_regsDCN20(2), 558 dsc_regsDCN20(3), 559 dsc_regsDCN20(4), 560 dsc_regsDCN20(5) 561 }; 562 563 static const struct dcn20_dsc_shift dsc_shift = { 564 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 565 }; 566 567 static const struct dcn20_dsc_mask dsc_mask = { 568 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 569 }; 570 571 #define ipp_regs(id)\ 572 [id] = {\ 573 IPP_REG_LIST_DCN20(id),\ 574 } 575 576 static const struct dcn10_ipp_registers ipp_regs[] = { 577 ipp_regs(0), 578 ipp_regs(1), 579 ipp_regs(2), 580 ipp_regs(3), 581 }; 582 583 static const struct dcn10_ipp_shift ipp_shift = { 584 IPP_MASK_SH_LIST_DCN20(__SHIFT) 585 }; 586 587 static const struct dcn10_ipp_mask ipp_mask = { 588 IPP_MASK_SH_LIST_DCN20(_MASK), 589 }; 590 591 #define opp_regs(id)\ 592 [id] = {\ 593 OPP_REG_LIST_DCN20(id),\ 594 } 595 596 597 #define aux_engine_regs(id)\ 598 [id] = {\ 599 AUX_COMMON_REG_LIST0(id), \ 600 .AUXN_IMPCAL = 0, \ 601 .AUXP_IMPCAL = 0, \ 602 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 603 } 604 605 static const struct dce110_aux_registers aux_engine_regs[] = { 606 aux_engine_regs(0), 607 aux_engine_regs(1), 608 aux_engine_regs(2), 609 aux_engine_regs(3), 610 aux_engine_regs(4), 611 }; 612 613 #define tf_regs(id)\ 614 [id] = {\ 615 TF_REG_LIST_DCN20(id),\ 616 TF_REG_LIST_DCN20_COMMON_APPEND(id),\ 617 } 618 619 static const struct dcn2_dpp_registers tf_regs[] = { 620 tf_regs(0), 621 tf_regs(1), 622 tf_regs(2), 623 tf_regs(3), 624 }; 625 626 static const struct dcn2_dpp_shift tf_shift = { 627 TF_REG_LIST_SH_MASK_DCN20(__SHIFT), 628 TF_DEBUG_REG_LIST_SH_DCN20 629 }; 630 631 static const struct dcn2_dpp_mask tf_mask = { 632 TF_REG_LIST_SH_MASK_DCN20(_MASK), 633 TF_DEBUG_REG_LIST_MASK_DCN20 634 }; 635 636 #define stream_enc_regs(id)\ 637 [id] = {\ 638 SE_DCN2_REG_LIST(id)\ 639 } 640 641 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 642 stream_enc_regs(0), 643 stream_enc_regs(1), 644 stream_enc_regs(2), 645 stream_enc_regs(3), 646 stream_enc_regs(4), 647 }; 648 649 static const struct dce110_aux_registers_shift aux_shift = { 650 DCN_AUX_MASK_SH_LIST(__SHIFT) 651 }; 652 653 static const struct dce110_aux_registers_mask aux_mask = { 654 DCN_AUX_MASK_SH_LIST(_MASK) 655 }; 656 657 static const struct dcn10_stream_encoder_shift se_shift = { 658 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) 659 }; 660 661 static const struct dcn10_stream_encoder_mask se_mask = { 662 SE_COMMON_MASK_SH_LIST_DCN20(_MASK) 663 }; 664 665 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu); 666 667 static int dcn21_populate_dml_pipes_from_context( 668 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes); 669 670 static struct input_pixel_processor *dcn21_ipp_create( 671 struct dc_context *ctx, uint32_t inst) 672 { 673 struct dcn10_ipp *ipp = 674 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 675 676 if (!ipp) { 677 BREAK_TO_DEBUGGER(); 678 return NULL; 679 } 680 681 dcn20_ipp_construct(ipp, ctx, inst, 682 &ipp_regs[inst], &ipp_shift, &ipp_mask); 683 return &ipp->base; 684 } 685 686 static struct dpp *dcn21_dpp_create( 687 struct dc_context *ctx, 688 uint32_t inst) 689 { 690 struct dcn20_dpp *dpp = 691 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL); 692 693 if (!dpp) 694 return NULL; 695 696 if (dpp2_construct(dpp, ctx, inst, 697 &tf_regs[inst], &tf_shift, &tf_mask)) 698 return &dpp->base; 699 700 BREAK_TO_DEBUGGER(); 701 kfree(dpp); 702 return NULL; 703 } 704 705 static struct dce_aux *dcn21_aux_engine_create( 706 struct dc_context *ctx, 707 uint32_t inst) 708 { 709 struct aux_engine_dce110 *aux_engine = 710 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 711 712 if (!aux_engine) 713 return NULL; 714 715 dce110_aux_engine_construct(aux_engine, ctx, inst, 716 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 717 &aux_engine_regs[inst], 718 &aux_mask, 719 &aux_shift, 720 ctx->dc->caps.extended_aux_timeout_support); 721 722 return &aux_engine->base; 723 } 724 725 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 726 727 static const struct dce_i2c_registers i2c_hw_regs[] = { 728 i2c_inst_regs(1), 729 i2c_inst_regs(2), 730 i2c_inst_regs(3), 731 i2c_inst_regs(4), 732 i2c_inst_regs(5), 733 }; 734 735 static const struct dce_i2c_shift i2c_shifts = { 736 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 737 }; 738 739 static const struct dce_i2c_mask i2c_masks = { 740 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 741 }; 742 743 struct dce_i2c_hw *dcn21_i2c_hw_create( 744 struct dc_context *ctx, 745 uint32_t inst) 746 { 747 struct dce_i2c_hw *dce_i2c_hw = 748 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 749 750 if (!dce_i2c_hw) 751 return NULL; 752 753 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 754 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 755 756 return dce_i2c_hw; 757 } 758 759 static const struct resource_caps res_cap_rn = { 760 .num_timing_generator = 4, 761 .num_opp = 4, 762 .num_video_plane = 4, 763 .num_audio = 4, // 4 audio endpoints. 4 audio streams 764 .num_stream_encoder = 5, 765 .num_pll = 5, // maybe 3 because the last two used for USB-c 766 .num_dwb = 1, 767 .num_ddc = 5, 768 .num_vmid = 1, 769 .num_dsc = 3, 770 }; 771 772 #ifdef DIAGS_BUILD 773 static const struct resource_caps res_cap_rn_FPGA_4pipe = { 774 .num_timing_generator = 4, 775 .num_opp = 4, 776 .num_video_plane = 4, 777 .num_audio = 7, 778 .num_stream_encoder = 4, 779 .num_pll = 4, 780 .num_dwb = 1, 781 .num_ddc = 4, 782 .num_dsc = 0, 783 }; 784 785 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = { 786 .num_timing_generator = 2, 787 .num_opp = 2, 788 .num_video_plane = 2, 789 .num_audio = 7, 790 .num_stream_encoder = 2, 791 .num_pll = 4, 792 .num_dwb = 1, 793 .num_ddc = 4, 794 .num_dsc = 2, 795 }; 796 #endif 797 798 static const struct dc_plane_cap plane_cap = { 799 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 800 .blends_with_above = true, 801 .blends_with_below = true, 802 .per_pixel_alpha = true, 803 804 .pixel_format_support = { 805 .argb8888 = true, 806 .nv12 = true, 807 .fp16 = true 808 }, 809 810 .max_upscale_factor = { 811 .argb8888 = 16000, 812 .nv12 = 16000, 813 .fp16 = 16000 814 }, 815 816 .max_downscale_factor = { 817 .argb8888 = 250, 818 .nv12 = 250, 819 .fp16 = 250 820 } 821 }; 822 823 static const struct dc_debug_options debug_defaults_drv = { 824 .disable_dmcu = true, 825 .force_abm_enable = false, 826 .timing_trace = false, 827 .clock_trace = true, 828 .disable_pplib_clock_request = true, 829 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 830 .force_single_disp_pipe_split = false, 831 .disable_dcc = DCC_ENABLE, 832 .vsr_support = true, 833 .performance_trace = false, 834 .max_downscale_src_width = 4096, 835 .disable_pplib_wm_range = false, 836 .scl_reset_length10 = true, 837 .sanity_checks = true, 838 .disable_48mhz_pwrdwn = false, 839 .nv12_iflip_vm_wa = true, 840 .usbc_combo_phy_reset_wa = true 841 }; 842 843 static const struct dc_debug_options debug_defaults_diags = { 844 .disable_dmcu = true, 845 .force_abm_enable = false, 846 .timing_trace = true, 847 .clock_trace = true, 848 .disable_dpp_power_gate = true, 849 .disable_hubp_power_gate = true, 850 .disable_clock_gate = true, 851 .disable_pplib_clock_request = true, 852 .disable_pplib_wm_range = true, 853 .disable_stutter = true, 854 .disable_48mhz_pwrdwn = true, 855 }; 856 857 enum dcn20_clk_src_array_id { 858 DCN20_CLK_SRC_PLL0, 859 DCN20_CLK_SRC_PLL1, 860 DCN20_CLK_SRC_PLL2, 861 DCN20_CLK_SRC_TOTAL_DCN21 862 }; 863 864 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) 865 { 866 unsigned int i; 867 868 for (i = 0; i < pool->base.stream_enc_count; i++) { 869 if (pool->base.stream_enc[i] != NULL) { 870 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 871 pool->base.stream_enc[i] = NULL; 872 } 873 } 874 875 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 876 if (pool->base.dscs[i] != NULL) 877 dcn20_dsc_destroy(&pool->base.dscs[i]); 878 } 879 880 if (pool->base.mpc != NULL) { 881 kfree(TO_DCN20_MPC(pool->base.mpc)); 882 pool->base.mpc = NULL; 883 } 884 if (pool->base.hubbub != NULL) { 885 kfree(pool->base.hubbub); 886 pool->base.hubbub = NULL; 887 } 888 for (i = 0; i < pool->base.pipe_count; i++) { 889 if (pool->base.dpps[i] != NULL) 890 dcn20_dpp_destroy(&pool->base.dpps[i]); 891 892 if (pool->base.ipps[i] != NULL) 893 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 894 895 if (pool->base.hubps[i] != NULL) { 896 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 897 pool->base.hubps[i] = NULL; 898 } 899 900 if (pool->base.irqs != NULL) { 901 dal_irq_service_destroy(&pool->base.irqs); 902 } 903 } 904 905 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 906 if (pool->base.engines[i] != NULL) 907 dce110_engine_destroy(&pool->base.engines[i]); 908 if (pool->base.hw_i2cs[i] != NULL) { 909 kfree(pool->base.hw_i2cs[i]); 910 pool->base.hw_i2cs[i] = NULL; 911 } 912 if (pool->base.sw_i2cs[i] != NULL) { 913 kfree(pool->base.sw_i2cs[i]); 914 pool->base.sw_i2cs[i] = NULL; 915 } 916 } 917 918 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 919 if (pool->base.opps[i] != NULL) 920 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 921 } 922 923 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 924 if (pool->base.timing_generators[i] != NULL) { 925 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 926 pool->base.timing_generators[i] = NULL; 927 } 928 } 929 930 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 931 if (pool->base.dwbc[i] != NULL) { 932 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); 933 pool->base.dwbc[i] = NULL; 934 } 935 if (pool->base.mcif_wb[i] != NULL) { 936 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); 937 pool->base.mcif_wb[i] = NULL; 938 } 939 } 940 941 for (i = 0; i < pool->base.audio_count; i++) { 942 if (pool->base.audios[i]) 943 dce_aud_destroy(&pool->base.audios[i]); 944 } 945 946 for (i = 0; i < pool->base.clk_src_count; i++) { 947 if (pool->base.clock_sources[i] != NULL) { 948 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 949 pool->base.clock_sources[i] = NULL; 950 } 951 } 952 953 if (pool->base.dp_clock_source != NULL) { 954 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 955 pool->base.dp_clock_source = NULL; 956 } 957 958 959 if (pool->base.abm != NULL) 960 dce_abm_destroy(&pool->base.abm); 961 962 if (pool->base.dmcu != NULL) 963 dce_dmcu_destroy(&pool->base.dmcu); 964 965 if (pool->base.dccg != NULL) 966 dcn_dccg_destroy(&pool->base.dccg); 967 968 if (pool->base.pp_smu != NULL) 969 dcn21_pp_smu_destroy(&pool->base.pp_smu); 970 } 971 972 973 static void calculate_wm_set_for_vlevel( 974 int vlevel, 975 struct wm_range_table_entry *table_entry, 976 struct dcn_watermarks *wm_set, 977 struct display_mode_lib *dml, 978 display_e2e_pipe_params_st *pipes, 979 int pipe_cnt) 980 { 981 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; 982 983 ASSERT(vlevel < dml->soc.num_states); 984 /* only pipe 0 is read for voltage and dcf/soc clocks */ 985 pipes[0].clks_cfg.voltage = vlevel; 986 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; 987 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; 988 989 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; 990 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; 991 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; 992 993 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; 994 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; 995 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; 996 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 997 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; 998 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; 999 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; 1000 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000; 1001 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; 1002 1003 } 1004 1005 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) 1006 { 1007 int i; 1008 1009 DC_FP_START(); 1010 1011 if (dc->bb_overrides.sr_exit_time_ns) { 1012 for (i = 0; i < WM_SET_COUNT; i++) { 1013 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us = 1014 dc->bb_overrides.sr_exit_time_ns / 1000.0; 1015 } 1016 } 1017 1018 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) { 1019 for (i = 0; i < WM_SET_COUNT; i++) { 1020 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us = 1021 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 1022 } 1023 } 1024 1025 if (dc->bb_overrides.urgent_latency_ns) { 1026 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 1027 } 1028 1029 if (dc->bb_overrides.dram_clock_change_latency_ns) { 1030 for (i = 0; i < WM_SET_COUNT; i++) { 1031 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us = 1032 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 1033 } 1034 } 1035 1036 DC_FP_END(); 1037 } 1038 1039 void dcn21_calculate_wm( 1040 struct dc *dc, struct dc_state *context, 1041 display_e2e_pipe_params_st *pipes, 1042 int *out_pipe_cnt, 1043 int *pipe_split_from, 1044 int vlevel_req) 1045 { 1046 int pipe_cnt, i, pipe_idx; 1047 int vlevel, vlevel_max; 1048 struct wm_range_table_entry *table_entry; 1049 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; 1050 1051 ASSERT(bw_params); 1052 1053 patch_bounding_box(dc, &context->bw_ctx.dml.soc); 1054 1055 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1056 if (!context->res_ctx.pipe_ctx[i].stream) 1057 continue; 1058 1059 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 1060 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb]; 1061 1062 if (pipe_split_from[i] < 0) { 1063 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1064 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; 1065 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) 1066 pipes[pipe_cnt].pipe.dest.odm_combine = 1067 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx]; 1068 else 1069 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1070 pipe_idx++; 1071 } else { 1072 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1073 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; 1074 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) 1075 pipes[pipe_cnt].pipe.dest.odm_combine = 1076 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]]; 1077 else 1078 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1079 } 1080 pipe_cnt++; 1081 } 1082 1083 if (pipe_cnt != pipe_idx) { 1084 if (dc->res_pool->funcs->populate_dml_pipes) 1085 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, 1086 context, pipes); 1087 else 1088 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc, 1089 context, pipes); 1090 } 1091 1092 *out_pipe_cnt = pipe_cnt; 1093 1094 vlevel_max = bw_params->clk_table.num_entries - 1; 1095 1096 1097 /* WM Set D */ 1098 table_entry = &bw_params->wm_table.entries[WM_D]; 1099 if (table_entry->wm_type == WM_TYPE_RETRAINING) 1100 vlevel = 0; 1101 else 1102 vlevel = vlevel_max; 1103 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, 1104 &context->bw_ctx.dml, pipes, pipe_cnt); 1105 /* WM Set C */ 1106 table_entry = &bw_params->wm_table.entries[WM_C]; 1107 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max); 1108 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, 1109 &context->bw_ctx.dml, pipes, pipe_cnt); 1110 /* WM Set B */ 1111 table_entry = &bw_params->wm_table.entries[WM_B]; 1112 vlevel = MIN(MAX(vlevel_req, 1), vlevel_max); 1113 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, 1114 &context->bw_ctx.dml, pipes, pipe_cnt); 1115 1116 /* WM Set A */ 1117 table_entry = &bw_params->wm_table.entries[WM_A]; 1118 vlevel = MIN(vlevel_req, vlevel_max); 1119 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, 1120 &context->bw_ctx.dml, pipes, pipe_cnt); 1121 } 1122 1123 1124 bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context, 1125 bool fast_validate) 1126 { 1127 bool out = false; 1128 1129 BW_VAL_TRACE_SETUP(); 1130 1131 int vlevel = 0; 1132 int pipe_split_from[MAX_PIPES]; 1133 int pipe_cnt = 0; 1134 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1135 DC_LOGGER_INIT(dc->ctx->logger); 1136 1137 BW_VAL_TRACE_COUNT(); 1138 1139 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel); 1140 1141 if (pipe_cnt == 0) 1142 goto validate_out; 1143 1144 if (!out) 1145 goto validate_fail; 1146 1147 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1148 1149 if (fast_validate) { 1150 BW_VAL_TRACE_SKIP(fast); 1151 goto validate_out; 1152 } 1153 1154 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel); 1155 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 1156 1157 BW_VAL_TRACE_END_WATERMARKS(); 1158 1159 goto validate_out; 1160 1161 validate_fail: 1162 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1163 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1164 1165 BW_VAL_TRACE_SKIP(fail); 1166 out = false; 1167 1168 validate_out: 1169 kfree(pipes); 1170 1171 BW_VAL_TRACE_FINISH(); 1172 1173 return out; 1174 } 1175 static void dcn21_destroy_resource_pool(struct resource_pool **pool) 1176 { 1177 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool); 1178 1179 dcn21_resource_destruct(dcn21_pool); 1180 kfree(dcn21_pool); 1181 *pool = NULL; 1182 } 1183 1184 static struct clock_source *dcn21_clock_source_create( 1185 struct dc_context *ctx, 1186 struct dc_bios *bios, 1187 enum clock_source_id id, 1188 const struct dce110_clk_src_regs *regs, 1189 bool dp_clk_src) 1190 { 1191 struct dce110_clk_src *clk_src = 1192 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1193 1194 if (!clk_src) 1195 return NULL; 1196 1197 if (dcn20_clk_src_construct(clk_src, ctx, bios, id, 1198 regs, &cs_shift, &cs_mask)) { 1199 clk_src->base.dp_clk_src = dp_clk_src; 1200 return &clk_src->base; 1201 } 1202 1203 BREAK_TO_DEBUGGER(); 1204 return NULL; 1205 } 1206 1207 static struct hubp *dcn21_hubp_create( 1208 struct dc_context *ctx, 1209 uint32_t inst) 1210 { 1211 struct dcn21_hubp *hubp21 = 1212 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL); 1213 1214 if (!hubp21) 1215 return NULL; 1216 1217 if (hubp21_construct(hubp21, ctx, inst, 1218 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1219 return &hubp21->base; 1220 1221 BREAK_TO_DEBUGGER(); 1222 kfree(hubp21); 1223 return NULL; 1224 } 1225 1226 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx) 1227 { 1228 int i; 1229 1230 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), 1231 GFP_KERNEL); 1232 1233 if (!hubbub) 1234 return NULL; 1235 1236 hubbub21_construct(hubbub, ctx, 1237 &hubbub_reg, 1238 &hubbub_shift, 1239 &hubbub_mask); 1240 1241 for (i = 0; i < res_cap_rn.num_vmid; i++) { 1242 struct dcn20_vmid *vmid = &hubbub->vmid[i]; 1243 1244 vmid->ctx = ctx; 1245 1246 vmid->regs = &vmid_regs[i]; 1247 vmid->shifts = &vmid_shifts; 1248 vmid->masks = &vmid_masks; 1249 } 1250 1251 return &hubbub->base; 1252 } 1253 1254 struct output_pixel_processor *dcn21_opp_create( 1255 struct dc_context *ctx, uint32_t inst) 1256 { 1257 struct dcn20_opp *opp = 1258 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1259 1260 if (!opp) { 1261 BREAK_TO_DEBUGGER(); 1262 return NULL; 1263 } 1264 1265 dcn20_opp_construct(opp, ctx, inst, 1266 &opp_regs[inst], &opp_shift, &opp_mask); 1267 return &opp->base; 1268 } 1269 1270 struct timing_generator *dcn21_timing_generator_create( 1271 struct dc_context *ctx, 1272 uint32_t instance) 1273 { 1274 struct optc *tgn10 = 1275 kzalloc(sizeof(struct optc), GFP_KERNEL); 1276 1277 if (!tgn10) 1278 return NULL; 1279 1280 tgn10->base.inst = instance; 1281 tgn10->base.ctx = ctx; 1282 1283 tgn10->tg_regs = &tg_regs[instance]; 1284 tgn10->tg_shift = &tg_shift; 1285 tgn10->tg_mask = &tg_mask; 1286 1287 dcn20_timing_generator_init(tgn10); 1288 1289 return &tgn10->base; 1290 } 1291 1292 struct mpc *dcn21_mpc_create(struct dc_context *ctx) 1293 { 1294 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), 1295 GFP_KERNEL); 1296 1297 if (!mpc20) 1298 return NULL; 1299 1300 dcn20_mpc_construct(mpc20, ctx, 1301 &mpc_regs, 1302 &mpc_shift, 1303 &mpc_mask, 1304 6); 1305 1306 return &mpc20->base; 1307 } 1308 1309 static void read_dce_straps( 1310 struct dc_context *ctx, 1311 struct resource_straps *straps) 1312 { 1313 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1314 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1315 1316 } 1317 1318 1319 struct display_stream_compressor *dcn21_dsc_create( 1320 struct dc_context *ctx, uint32_t inst) 1321 { 1322 struct dcn20_dsc *dsc = 1323 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1324 1325 if (!dsc) { 1326 BREAK_TO_DEBUGGER(); 1327 return NULL; 1328 } 1329 1330 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1331 return &dsc->base; 1332 } 1333 1334 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1335 { 1336 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool); 1337 struct clk_limit_table *clk_table = &bw_params->clk_table; 1338 int i; 1339 1340 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator; 1341 dcn2_1_ip.max_num_dpp = pool->base.pipe_count; 1342 dcn2_1_soc.num_chans = bw_params->num_channels; 1343 1344 for (i = 0; i < clk_table->num_entries; i++) { 1345 1346 dcn2_1_soc.clock_limits[i].state = i; 1347 dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 1348 dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 1349 dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; 1350 dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; 1351 } 1352 dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i - 1]; 1353 dcn2_1_soc.num_states = i; 1354 1355 // diags does not retrieve proper values from SMU, do not update DML instance for diags 1356 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) && !IS_DIAG_DC(dc->ctx->dce_environment)) 1357 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); 1358 } 1359 1360 /* Temporary Place holder until we can get them from fuse */ 1361 static struct dpm_clocks dummy_clocks = { 1362 .DcfClocks = { 1363 {.Freq = 400, .Vol = 1}, 1364 {.Freq = 483, .Vol = 1}, 1365 {.Freq = 602, .Vol = 1}, 1366 {.Freq = 738, .Vol = 1} }, 1367 .SocClocks = { 1368 {.Freq = 300, .Vol = 1}, 1369 {.Freq = 400, .Vol = 1}, 1370 {.Freq = 400, .Vol = 1}, 1371 {.Freq = 400, .Vol = 1} }, 1372 .FClocks = { 1373 {.Freq = 400, .Vol = 1}, 1374 {.Freq = 800, .Vol = 1}, 1375 {.Freq = 1067, .Vol = 1}, 1376 {.Freq = 1600, .Vol = 1} }, 1377 .MemClocks = { 1378 {.Freq = 800, .Vol = 1}, 1379 {.Freq = 1600, .Vol = 1}, 1380 {.Freq = 1067, .Vol = 1}, 1381 {.Freq = 1600, .Vol = 1} }, 1382 1383 }; 1384 1385 static enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp, 1386 struct pp_smu_wm_range_sets *ranges) 1387 { 1388 return PP_SMU_RESULT_OK; 1389 } 1390 1391 static enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp, 1392 struct dpm_clocks *clock_table) 1393 { 1394 *clock_table = dummy_clocks; 1395 return PP_SMU_RESULT_OK; 1396 } 1397 1398 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx) 1399 { 1400 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 1401 1402 if (!pp_smu) 1403 return pp_smu; 1404 1405 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) { 1406 pp_smu->ctx.ver = PP_SMU_VER_RN; 1407 pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table; 1408 pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges; 1409 } else { 1410 1411 dm_pp_get_funcs(ctx, pp_smu); 1412 1413 if (pp_smu->ctx.ver != PP_SMU_VER_RN) 1414 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); 1415 } 1416 1417 return pp_smu; 1418 } 1419 1420 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu) 1421 { 1422 if (pp_smu && *pp_smu) { 1423 kfree(*pp_smu); 1424 *pp_smu = NULL; 1425 } 1426 } 1427 1428 static struct audio *dcn21_create_audio( 1429 struct dc_context *ctx, unsigned int inst) 1430 { 1431 return dce_audio_create(ctx, inst, 1432 &audio_regs[inst], &audio_shift, &audio_mask); 1433 } 1434 1435 static struct dc_cap_funcs cap_funcs = { 1436 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1437 }; 1438 1439 struct stream_encoder *dcn21_stream_encoder_create( 1440 enum engine_id eng_id, 1441 struct dc_context *ctx) 1442 { 1443 struct dcn10_stream_encoder *enc1 = 1444 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1445 1446 if (!enc1) 1447 return NULL; 1448 1449 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1450 &stream_enc_regs[eng_id], 1451 &se_shift, &se_mask); 1452 1453 return &enc1->base; 1454 } 1455 1456 static const struct dce_hwseq_registers hwseq_reg = { 1457 HWSEQ_DCN21_REG_LIST() 1458 }; 1459 1460 static const struct dce_hwseq_shift hwseq_shift = { 1461 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT) 1462 }; 1463 1464 static const struct dce_hwseq_mask hwseq_mask = { 1465 HWSEQ_DCN21_MASK_SH_LIST(_MASK) 1466 }; 1467 1468 static struct dce_hwseq *dcn21_hwseq_create( 1469 struct dc_context *ctx) 1470 { 1471 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1472 1473 if (hws) { 1474 hws->ctx = ctx; 1475 hws->regs = &hwseq_reg; 1476 hws->shifts = &hwseq_shift; 1477 hws->masks = &hwseq_mask; 1478 hws->wa.DEGVIDCN21 = true; 1479 } 1480 return hws; 1481 } 1482 1483 static const struct resource_create_funcs res_create_funcs = { 1484 .read_dce_straps = read_dce_straps, 1485 .create_audio = dcn21_create_audio, 1486 .create_stream_encoder = dcn21_stream_encoder_create, 1487 .create_hwseq = dcn21_hwseq_create, 1488 }; 1489 1490 static const struct resource_create_funcs res_create_maximus_funcs = { 1491 .read_dce_straps = NULL, 1492 .create_audio = NULL, 1493 .create_stream_encoder = NULL, 1494 .create_hwseq = dcn21_hwseq_create, 1495 }; 1496 1497 static const struct encoder_feature_support link_enc_feature = { 1498 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1499 .max_hdmi_pixel_clock = 600000, 1500 .hdmi_ycbcr420_supported = true, 1501 .dp_ycbcr420_supported = true, 1502 .flags.bits.IS_HBR2_CAPABLE = true, 1503 .flags.bits.IS_HBR3_CAPABLE = true, 1504 .flags.bits.IS_TPS3_CAPABLE = true, 1505 .flags.bits.IS_TPS4_CAPABLE = true 1506 }; 1507 1508 1509 #define link_regs(id, phyid)\ 1510 [id] = {\ 1511 LE_DCN2_REG_LIST(id), \ 1512 UNIPHY_DCN2_REG_LIST(phyid), \ 1513 DPCS_DCN21_REG_LIST(id), \ 1514 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 1515 } 1516 1517 static const struct dcn10_link_enc_registers link_enc_regs[] = { 1518 link_regs(0, A), 1519 link_regs(1, B), 1520 link_regs(2, C), 1521 link_regs(3, D), 1522 link_regs(4, E), 1523 }; 1524 1525 #define aux_regs(id)\ 1526 [id] = {\ 1527 DCN2_AUX_REG_LIST(id)\ 1528 } 1529 1530 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 1531 aux_regs(0), 1532 aux_regs(1), 1533 aux_regs(2), 1534 aux_regs(3), 1535 aux_regs(4) 1536 }; 1537 1538 #define hpd_regs(id)\ 1539 [id] = {\ 1540 HPD_REG_LIST(id)\ 1541 } 1542 1543 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 1544 hpd_regs(0), 1545 hpd_regs(1), 1546 hpd_regs(2), 1547 hpd_regs(3), 1548 hpd_regs(4) 1549 }; 1550 1551 static const struct dcn10_link_enc_shift le_shift = { 1552 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\ 1553 DPCS_DCN21_MASK_SH_LIST(__SHIFT) 1554 }; 1555 1556 static const struct dcn10_link_enc_mask le_mask = { 1557 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\ 1558 DPCS_DCN21_MASK_SH_LIST(_MASK) 1559 }; 1560 1561 static int map_transmitter_id_to_phy_instance( 1562 enum transmitter transmitter) 1563 { 1564 switch (transmitter) { 1565 case TRANSMITTER_UNIPHY_A: 1566 return 0; 1567 break; 1568 case TRANSMITTER_UNIPHY_B: 1569 return 1; 1570 break; 1571 case TRANSMITTER_UNIPHY_C: 1572 return 2; 1573 break; 1574 case TRANSMITTER_UNIPHY_D: 1575 return 3; 1576 break; 1577 case TRANSMITTER_UNIPHY_E: 1578 return 4; 1579 break; 1580 default: 1581 ASSERT(0); 1582 return 0; 1583 } 1584 } 1585 1586 static struct link_encoder *dcn21_link_encoder_create( 1587 const struct encoder_init_data *enc_init_data) 1588 { 1589 struct dcn21_link_encoder *enc21 = 1590 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL); 1591 int link_regs_id; 1592 1593 if (!enc21) 1594 return NULL; 1595 1596 link_regs_id = 1597 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 1598 1599 dcn21_link_encoder_construct(enc21, 1600 enc_init_data, 1601 &link_enc_feature, 1602 &link_enc_regs[link_regs_id], 1603 &link_enc_aux_regs[enc_init_data->channel - 1], 1604 &link_enc_hpd_regs[enc_init_data->hpd_source], 1605 &le_shift, 1606 &le_mask); 1607 1608 return &enc21->enc10.base; 1609 } 1610 #define CTX ctx 1611 1612 #define REG(reg_name) \ 1613 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 1614 1615 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1616 { 1617 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 1618 /* RV1 support max 4 pipes */ 1619 value = value & 0xf; 1620 return value; 1621 } 1622 1623 static int dcn21_populate_dml_pipes_from_context( 1624 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes) 1625 { 1626 uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes); 1627 int i; 1628 struct resource_context *res_ctx = &context->res_ctx; 1629 1630 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1631 1632 if (!res_ctx->pipe_ctx[i].stream) 1633 continue; 1634 1635 pipes[i].pipe.src.hostvm = 1; 1636 pipes[i].pipe.src.gpuvm = 1; 1637 } 1638 1639 return pipe_cnt; 1640 } 1641 1642 static struct resource_funcs dcn21_res_pool_funcs = { 1643 .destroy = dcn21_destroy_resource_pool, 1644 .link_enc_create = dcn21_link_encoder_create, 1645 .validate_bandwidth = dcn21_validate_bandwidth, 1646 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context, 1647 .add_stream_to_ctx = dcn20_add_stream_to_ctx, 1648 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1649 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1650 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, 1651 .get_default_swizzle_mode = dcn20_get_default_swizzle_mode, 1652 .set_mcif_arb_params = dcn20_set_mcif_arb_params, 1653 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1654 .update_bw_bounding_box = update_bw_bounding_box 1655 }; 1656 1657 static bool dcn21_resource_construct( 1658 uint8_t num_virtual_links, 1659 struct dc *dc, 1660 struct dcn21_resource_pool *pool) 1661 { 1662 int i, j; 1663 struct dc_context *ctx = dc->ctx; 1664 struct irq_service_init_data init_data; 1665 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1666 uint32_t num_pipes; 1667 1668 ctx->dc_bios->regs = &bios_regs; 1669 1670 pool->base.res_cap = &res_cap_rn; 1671 #ifdef DIAGS_BUILD 1672 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1673 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc; 1674 pool->base.res_cap = &res_cap_rn_FPGA_4pipe; 1675 #endif 1676 1677 pool->base.funcs = &dcn21_res_pool_funcs; 1678 1679 /************************************************* 1680 * Resource + asic cap harcoding * 1681 *************************************************/ 1682 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1683 1684 /* max pipe num for ASIC before check pipe fuses */ 1685 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1686 1687 dc->caps.max_downscale_ratio = 200; 1688 dc->caps.i2c_speed_in_khz = 100; 1689 dc->caps.max_cursor_size = 256; 1690 dc->caps.dmdata_alloc_size = 2048; 1691 dc->caps.hw_3d_lut = true; 1692 1693 dc->caps.max_slave_planes = 1; 1694 dc->caps.post_blend_color_processing = true; 1695 dc->caps.force_dp_tps4_for_cp2520 = true; 1696 dc->caps.extended_aux_timeout_support = true; 1697 dc->caps.dmcub_support = true; 1698 1699 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1700 dc->debug = debug_defaults_drv; 1701 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1702 pool->base.pipe_count = 4; 1703 dc->debug = debug_defaults_diags; 1704 } else 1705 dc->debug = debug_defaults_diags; 1706 1707 // Init the vm_helper 1708 if (dc->vm_helper) 1709 vm_helper_init(dc->vm_helper, 16); 1710 1711 /************************************************* 1712 * Create resources * 1713 *************************************************/ 1714 1715 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = 1716 dcn21_clock_source_create(ctx, ctx->dc_bios, 1717 CLOCK_SOURCE_COMBO_PHY_PLL0, 1718 &clk_src_regs[0], false); 1719 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = 1720 dcn21_clock_source_create(ctx, ctx->dc_bios, 1721 CLOCK_SOURCE_COMBO_PHY_PLL1, 1722 &clk_src_regs[1], false); 1723 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = 1724 dcn21_clock_source_create(ctx, ctx->dc_bios, 1725 CLOCK_SOURCE_COMBO_PHY_PLL2, 1726 &clk_src_regs[2], false); 1727 1728 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21; 1729 1730 /* todo: not reuse phy_pll registers */ 1731 pool->base.dp_clock_source = 1732 dcn21_clock_source_create(ctx, ctx->dc_bios, 1733 CLOCK_SOURCE_ID_DP_DTO, 1734 &clk_src_regs[0], true); 1735 1736 for (i = 0; i < pool->base.clk_src_count; i++) { 1737 if (pool->base.clock_sources[i] == NULL) { 1738 dm_error("DC: failed to create clock sources!\n"); 1739 BREAK_TO_DEBUGGER(); 1740 goto create_fail; 1741 } 1742 } 1743 1744 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1745 if (pool->base.dccg == NULL) { 1746 dm_error("DC: failed to create dccg!\n"); 1747 BREAK_TO_DEBUGGER(); 1748 goto create_fail; 1749 } 1750 1751 pool->base.dmcu = dcn21_dmcu_create(ctx, 1752 &dmcu_regs, 1753 &dmcu_shift, 1754 &dmcu_mask); 1755 if (pool->base.dmcu == NULL) { 1756 dm_error("DC: failed to create dmcu!\n"); 1757 BREAK_TO_DEBUGGER(); 1758 goto create_fail; 1759 } 1760 1761 // Leave as NULL to not affect current dmcu psr programming sequence 1762 // Will be uncommented when functionality is confirmed to be working 1763 pool->base.psr = NULL; 1764 1765 pool->base.abm = dce_abm_create(ctx, 1766 &abm_regs, 1767 &abm_shift, 1768 &abm_mask); 1769 if (pool->base.abm == NULL) { 1770 dm_error("DC: failed to create abm!\n"); 1771 BREAK_TO_DEBUGGER(); 1772 goto create_fail; 1773 } 1774 1775 pool->base.pp_smu = dcn21_pp_smu_create(ctx); 1776 1777 num_pipes = dcn2_1_ip.max_num_dpp; 1778 1779 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++) 1780 if (pipe_fuses & 1 << i) 1781 num_pipes--; 1782 dcn2_1_ip.max_num_dpp = num_pipes; 1783 dcn2_1_ip.max_num_otg = num_pipes; 1784 1785 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); 1786 1787 init_data.ctx = dc->ctx; 1788 pool->base.irqs = dal_irq_service_dcn21_create(&init_data); 1789 if (!pool->base.irqs) 1790 goto create_fail; 1791 1792 j = 0; 1793 /* mem input -> ipp -> dpp -> opp -> TG */ 1794 for (i = 0; i < pool->base.pipe_count; i++) { 1795 /* if pipe is disabled, skip instance of HW pipe, 1796 * i.e, skip ASIC register instance 1797 */ 1798 if ((pipe_fuses & (1 << i)) != 0) 1799 continue; 1800 1801 pool->base.hubps[j] = dcn21_hubp_create(ctx, i); 1802 if (pool->base.hubps[j] == NULL) { 1803 BREAK_TO_DEBUGGER(); 1804 dm_error( 1805 "DC: failed to create memory input!\n"); 1806 goto create_fail; 1807 } 1808 1809 pool->base.ipps[j] = dcn21_ipp_create(ctx, i); 1810 if (pool->base.ipps[j] == NULL) { 1811 BREAK_TO_DEBUGGER(); 1812 dm_error( 1813 "DC: failed to create input pixel processor!\n"); 1814 goto create_fail; 1815 } 1816 1817 pool->base.dpps[j] = dcn21_dpp_create(ctx, i); 1818 if (pool->base.dpps[j] == NULL) { 1819 BREAK_TO_DEBUGGER(); 1820 dm_error( 1821 "DC: failed to create dpps!\n"); 1822 goto create_fail; 1823 } 1824 1825 pool->base.opps[j] = dcn21_opp_create(ctx, i); 1826 if (pool->base.opps[j] == NULL) { 1827 BREAK_TO_DEBUGGER(); 1828 dm_error( 1829 "DC: failed to create output pixel processor!\n"); 1830 goto create_fail; 1831 } 1832 1833 pool->base.timing_generators[j] = dcn21_timing_generator_create( 1834 ctx, i); 1835 if (pool->base.timing_generators[j] == NULL) { 1836 BREAK_TO_DEBUGGER(); 1837 dm_error("DC: failed to create tg!\n"); 1838 goto create_fail; 1839 } 1840 j++; 1841 } 1842 1843 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1844 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i); 1845 if (pool->base.engines[i] == NULL) { 1846 BREAK_TO_DEBUGGER(); 1847 dm_error( 1848 "DC:failed to create aux engine!!\n"); 1849 goto create_fail; 1850 } 1851 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i); 1852 if (pool->base.hw_i2cs[i] == NULL) { 1853 BREAK_TO_DEBUGGER(); 1854 dm_error( 1855 "DC:failed to create hw i2c!!\n"); 1856 goto create_fail; 1857 } 1858 pool->base.sw_i2cs[i] = NULL; 1859 } 1860 1861 pool->base.timing_generator_count = j; 1862 pool->base.pipe_count = j; 1863 pool->base.mpcc_count = j; 1864 1865 pool->base.mpc = dcn21_mpc_create(ctx); 1866 if (pool->base.mpc == NULL) { 1867 BREAK_TO_DEBUGGER(); 1868 dm_error("DC: failed to create mpc!\n"); 1869 goto create_fail; 1870 } 1871 1872 pool->base.hubbub = dcn21_hubbub_create(ctx); 1873 if (pool->base.hubbub == NULL) { 1874 BREAK_TO_DEBUGGER(); 1875 dm_error("DC: failed to create hubbub!\n"); 1876 goto create_fail; 1877 } 1878 1879 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1880 pool->base.dscs[i] = dcn21_dsc_create(ctx, i); 1881 if (pool->base.dscs[i] == NULL) { 1882 BREAK_TO_DEBUGGER(); 1883 dm_error("DC: failed to create display stream compressor %d!\n", i); 1884 goto create_fail; 1885 } 1886 } 1887 1888 if (!dcn20_dwbc_create(ctx, &pool->base)) { 1889 BREAK_TO_DEBUGGER(); 1890 dm_error("DC: failed to create dwbc!\n"); 1891 goto create_fail; 1892 } 1893 if (!dcn20_mmhubbub_create(ctx, &pool->base)) { 1894 BREAK_TO_DEBUGGER(); 1895 dm_error("DC: failed to create mcif_wb!\n"); 1896 goto create_fail; 1897 } 1898 1899 if (!resource_construct(num_virtual_links, dc, &pool->base, 1900 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1901 &res_create_funcs : &res_create_maximus_funcs))) 1902 goto create_fail; 1903 1904 dcn21_hw_sequencer_construct(dc); 1905 1906 dc->caps.max_planes = pool->base.pipe_count; 1907 1908 for (i = 0; i < dc->caps.max_planes; ++i) 1909 dc->caps.planes[i] = plane_cap; 1910 1911 dc->cap_funcs = cap_funcs; 1912 1913 return true; 1914 1915 create_fail: 1916 1917 dcn21_resource_destruct(pool); 1918 1919 return false; 1920 } 1921 1922 struct resource_pool *dcn21_create_resource_pool( 1923 const struct dc_init_data *init_data, 1924 struct dc *dc) 1925 { 1926 struct dcn21_resource_pool *pool = 1927 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL); 1928 1929 if (!pool) 1930 return NULL; 1931 1932 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool)) 1933 return &pool->base; 1934 1935 BREAK_TO_DEBUGGER(); 1936 kfree(pool); 1937 return NULL; 1938 } 1939