1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * Copyright 2019 Raptor Engineering, LLC 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 #include "dc.h" 31 32 #include "dcn21_init.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dcn20/dcn20_resource.h" 37 38 #include "dml/dcn20/dcn20_fpu.h" 39 40 #include "clk_mgr.h" 41 #include "dcn10/dcn10_hubp.h" 42 #include "dcn10/dcn10_ipp.h" 43 #include "dcn20/dcn20_hubbub.h" 44 #include "dcn20/dcn20_mpc.h" 45 #include "dcn20/dcn20_hubp.h" 46 #include "dcn21_hubp.h" 47 #include "irq/dcn21/irq_service_dcn21.h" 48 #include "dcn20/dcn20_dpp.h" 49 #include "dcn20/dcn20_optc.h" 50 #include "dcn21/dcn21_hwseq.h" 51 #include "dce110/dce110_hw_sequencer.h" 52 #include "dcn20/dcn20_opp.h" 53 #include "dcn20/dcn20_dsc.h" 54 #include "dcn21/dcn21_link_encoder.h" 55 #include "dcn20/dcn20_stream_encoder.h" 56 #include "dce/dce_clock_source.h" 57 #include "dce/dce_audio.h" 58 #include "dce/dce_hwseq.h" 59 #include "virtual/virtual_stream_encoder.h" 60 #include "dml/display_mode_vba.h" 61 #include "dcn20/dcn20_dccg.h" 62 #include "dcn21/dcn21_dccg.h" 63 #include "dcn21_hubbub.h" 64 #include "dcn10/dcn10_resource.h" 65 #include "dce/dce_panel_cntl.h" 66 67 #include "dcn20/dcn20_dwb.h" 68 #include "dcn20/dcn20_mmhubbub.h" 69 #include "dpcs/dpcs_2_1_0_offset.h" 70 #include "dpcs/dpcs_2_1_0_sh_mask.h" 71 72 #include "renoir_ip_offset.h" 73 #include "dcn/dcn_2_1_0_offset.h" 74 #include "dcn/dcn_2_1_0_sh_mask.h" 75 76 #include "nbio/nbio_7_0_offset.h" 77 78 #include "mmhub/mmhub_2_0_0_offset.h" 79 #include "mmhub/mmhub_2_0_0_sh_mask.h" 80 81 #include "reg_helper.h" 82 #include "dce/dce_abm.h" 83 #include "dce/dce_dmcu.h" 84 #include "dce/dce_aux.h" 85 #include "dce/dce_i2c.h" 86 #include "dcn21_resource.h" 87 #include "vm_helper.h" 88 #include "dcn20/dcn20_vmid.h" 89 #include "dce/dmub_psr.h" 90 #include "dce/dmub_abm.h" 91 92 #define DC_LOGGER_INIT(logger) 93 94 95 struct _vcs_dpi_ip_params_st dcn2_1_ip = { 96 .odm_capable = 1, 97 .gpuvm_enable = 1, 98 .hostvm_enable = 1, 99 .gpuvm_max_page_table_levels = 1, 100 .hostvm_max_page_table_levels = 4, 101 .hostvm_cached_page_table_levels = 2, 102 .num_dsc = 3, 103 .rob_buffer_size_kbytes = 168, 104 .det_buffer_size_kbytes = 164, 105 .dpte_buffer_size_in_pte_reqs_luma = 44, 106 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo 107 .dpp_output_buffer_pixels = 2560, 108 .opp_output_buffer_lines = 1, 109 .pixel_chunk_size_kbytes = 8, 110 .pte_enable = 1, 111 .max_page_table_levels = 4, 112 .pte_chunk_size_kbytes = 2, 113 .meta_chunk_size_kbytes = 2, 114 .min_meta_chunk_size_bytes = 256, 115 .writeback_chunk_size_kbytes = 2, 116 .line_buffer_size_bits = 789504, 117 .is_line_buffer_bpp_fixed = 0, 118 .line_buffer_fixed_bpp = 0, 119 .dcc_supported = true, 120 .max_line_buffer_lines = 12, 121 .writeback_luma_buffer_size_kbytes = 12, 122 .writeback_chroma_buffer_size_kbytes = 8, 123 .writeback_chroma_line_buffer_width_pixels = 4, 124 .writeback_max_hscl_ratio = 1, 125 .writeback_max_vscl_ratio = 1, 126 .writeback_min_hscl_ratio = 1, 127 .writeback_min_vscl_ratio = 1, 128 .writeback_max_hscl_taps = 12, 129 .writeback_max_vscl_taps = 12, 130 .writeback_line_buffer_luma_buffer_size = 0, 131 .writeback_line_buffer_chroma_buffer_size = 14643, 132 .cursor_buffer_size = 8, 133 .cursor_chunk_size = 2, 134 .max_num_otg = 4, 135 .max_num_dpp = 4, 136 .max_num_wb = 1, 137 .max_dchub_pscl_bw_pix_per_clk = 4, 138 .max_pscl_lb_bw_pix_per_clk = 2, 139 .max_lb_vscl_bw_pix_per_clk = 4, 140 .max_vscl_hscl_bw_pix_per_clk = 4, 141 .max_hscl_ratio = 4, 142 .max_vscl_ratio = 4, 143 .hscl_mults = 4, 144 .vscl_mults = 4, 145 .max_hscl_taps = 8, 146 .max_vscl_taps = 8, 147 .dispclk_ramp_margin_percent = 1, 148 .underscan_factor = 1.10, 149 .min_vblank_lines = 32, // 150 .dppclk_delay_subtotal = 77, // 151 .dppclk_delay_scl_lb_only = 16, 152 .dppclk_delay_scl = 50, 153 .dppclk_delay_cnvc_formatter = 8, 154 .dppclk_delay_cnvc_cursor = 6, 155 .dispclk_delay_subtotal = 87, // 156 .dcfclk_cstate_latency = 10, // SRExitTime 157 .max_inter_dcn_tile_repeaters = 8, 158 159 .xfc_supported = false, 160 .xfc_fill_bw_overhead_percent = 10.0, 161 .xfc_fill_constant_bytes = 0, 162 .ptoi_supported = 0, 163 .number_of_cursors = 1, 164 }; 165 166 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { 167 .clock_limits = { 168 { 169 .state = 0, 170 .dcfclk_mhz = 400.0, 171 .fabricclk_mhz = 400.0, 172 .dispclk_mhz = 600.0, 173 .dppclk_mhz = 400.00, 174 .phyclk_mhz = 600.0, 175 .socclk_mhz = 278.0, 176 .dscclk_mhz = 205.67, 177 .dram_speed_mts = 1600.0, 178 }, 179 { 180 .state = 1, 181 .dcfclk_mhz = 464.52, 182 .fabricclk_mhz = 800.0, 183 .dispclk_mhz = 654.55, 184 .dppclk_mhz = 626.09, 185 .phyclk_mhz = 600.0, 186 .socclk_mhz = 278.0, 187 .dscclk_mhz = 205.67, 188 .dram_speed_mts = 1600.0, 189 }, 190 { 191 .state = 2, 192 .dcfclk_mhz = 514.29, 193 .fabricclk_mhz = 933.0, 194 .dispclk_mhz = 757.89, 195 .dppclk_mhz = 685.71, 196 .phyclk_mhz = 600.0, 197 .socclk_mhz = 278.0, 198 .dscclk_mhz = 287.67, 199 .dram_speed_mts = 1866.0, 200 }, 201 { 202 .state = 3, 203 .dcfclk_mhz = 576.00, 204 .fabricclk_mhz = 1067.0, 205 .dispclk_mhz = 847.06, 206 .dppclk_mhz = 757.89, 207 .phyclk_mhz = 600.0, 208 .socclk_mhz = 715.0, 209 .dscclk_mhz = 318.334, 210 .dram_speed_mts = 2134.0, 211 }, 212 { 213 .state = 4, 214 .dcfclk_mhz = 626.09, 215 .fabricclk_mhz = 1200.0, 216 .dispclk_mhz = 900.00, 217 .dppclk_mhz = 847.06, 218 .phyclk_mhz = 810.0, 219 .socclk_mhz = 953.0, 220 .dscclk_mhz = 489.0, 221 .dram_speed_mts = 2400.0, 222 }, 223 { 224 .state = 5, 225 .dcfclk_mhz = 685.71, 226 .fabricclk_mhz = 1333.0, 227 .dispclk_mhz = 1028.57, 228 .dppclk_mhz = 960.00, 229 .phyclk_mhz = 810.0, 230 .socclk_mhz = 278.0, 231 .dscclk_mhz = 287.67, 232 .dram_speed_mts = 2666.0, 233 }, 234 { 235 .state = 6, 236 .dcfclk_mhz = 757.89, 237 .fabricclk_mhz = 1467.0, 238 .dispclk_mhz = 1107.69, 239 .dppclk_mhz = 1028.57, 240 .phyclk_mhz = 810.0, 241 .socclk_mhz = 715.0, 242 .dscclk_mhz = 318.334, 243 .dram_speed_mts = 3200.0, 244 }, 245 { 246 .state = 7, 247 .dcfclk_mhz = 847.06, 248 .fabricclk_mhz = 1600.0, 249 .dispclk_mhz = 1395.0, 250 .dppclk_mhz = 1285.00, 251 .phyclk_mhz = 1325.0, 252 .socclk_mhz = 953.0, 253 .dscclk_mhz = 489.0, 254 .dram_speed_mts = 4266.0, 255 }, 256 /*Extra state, no dispclk ramping*/ 257 { 258 .state = 8, 259 .dcfclk_mhz = 847.06, 260 .fabricclk_mhz = 1600.0, 261 .dispclk_mhz = 1395.0, 262 .dppclk_mhz = 1285.0, 263 .phyclk_mhz = 1325.0, 264 .socclk_mhz = 953.0, 265 .dscclk_mhz = 489.0, 266 .dram_speed_mts = 4266.0, 267 }, 268 269 }, 270 271 .sr_exit_time_us = 12.5, 272 .sr_enter_plus_exit_time_us = 17.0, 273 .urgent_latency_us = 4.0, 274 .urgent_latency_pixel_data_only_us = 4.0, 275 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 276 .urgent_latency_vm_data_only_us = 4.0, 277 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 278 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 279 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 280 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 281 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0, 282 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 283 .max_avg_sdp_bw_use_normal_percent = 60.0, 284 .max_avg_dram_bw_use_normal_percent = 100.0, 285 .writeback_latency_us = 12.0, 286 .max_request_size_bytes = 256, 287 .dram_channel_width_bytes = 4, 288 .fabric_datapath_to_dcn_data_return_bytes = 32, 289 .dcn_downspread_percent = 0.5, 290 .downspread_percent = 0.38, 291 .dram_page_open_time_ns = 50.0, 292 .dram_rw_turnaround_time_ns = 17.5, 293 .dram_return_buffer_per_channel_bytes = 8192, 294 .round_trip_ping_latency_dcfclk_cycles = 128, 295 .urgent_out_of_order_return_per_channel_bytes = 4096, 296 .channel_interleave_bytes = 256, 297 .num_banks = 8, 298 .num_chans = 4, 299 .vmm_page_size_bytes = 4096, 300 .dram_clock_change_latency_us = 23.84, 301 .return_bus_width_bytes = 64, 302 .dispclk_dppclk_vco_speed_mhz = 3600, 303 .xfc_bus_transport_time_us = 4, 304 .xfc_xbuf_latency_tolerance_us = 4, 305 .use_urgent_burst_bw = 1, 306 .num_states = 8 307 }; 308 309 #ifndef MAX 310 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y)) 311 #endif 312 #ifndef MIN 313 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 314 #endif 315 316 /* begin ********************* 317 * macros to expend register list macro defined in HW object header file */ 318 319 /* DCN */ 320 /* TODO awful hack. fixup dcn20_dwb.h */ 321 #undef BASE_INNER 322 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg 323 324 #define BASE(seg) BASE_INNER(seg) 325 326 #define SR(reg_name)\ 327 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 328 mm ## reg_name 329 330 #define SRI(reg_name, block, id)\ 331 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 332 mm ## block ## id ## _ ## reg_name 333 334 #define SRIR(var_name, reg_name, block, id)\ 335 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 336 mm ## block ## id ## _ ## reg_name 337 338 #define SRII(reg_name, block, id)\ 339 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 340 mm ## block ## id ## _ ## reg_name 341 342 #define DCCG_SRII(reg_name, block, id)\ 343 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 344 mm ## block ## id ## _ ## reg_name 345 346 #define VUPDATE_SRII(reg_name, block, id)\ 347 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 348 mm ## reg_name ## _ ## block ## id 349 350 /* NBIO */ 351 #define NBIO_BASE_INNER(seg) \ 352 NBIF0_BASE__INST0_SEG ## seg 353 354 #define NBIO_BASE(seg) \ 355 NBIO_BASE_INNER(seg) 356 357 #define NBIO_SR(reg_name)\ 358 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 359 mm ## reg_name 360 361 /* MMHUB */ 362 #define MMHUB_BASE_INNER(seg) \ 363 MMHUB_BASE__INST0_SEG ## seg 364 365 #define MMHUB_BASE(seg) \ 366 MMHUB_BASE_INNER(seg) 367 368 #define MMHUB_SR(reg_name)\ 369 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 370 mmMM ## reg_name 371 372 #define clk_src_regs(index, pllid)\ 373 [index] = {\ 374 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\ 375 } 376 377 static const struct dce110_clk_src_regs clk_src_regs[] = { 378 clk_src_regs(0, A), 379 clk_src_regs(1, B), 380 clk_src_regs(2, C), 381 clk_src_regs(3, D), 382 clk_src_regs(4, E), 383 }; 384 385 static const struct dce110_clk_src_shift cs_shift = { 386 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 387 }; 388 389 static const struct dce110_clk_src_mask cs_mask = { 390 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 391 }; 392 393 static const struct bios_registers bios_regs = { 394 NBIO_SR(BIOS_SCRATCH_3), 395 NBIO_SR(BIOS_SCRATCH_6) 396 }; 397 398 static const struct dce_dmcu_registers dmcu_regs = { 399 DMCU_DCN20_REG_LIST() 400 }; 401 402 static const struct dce_dmcu_shift dmcu_shift = { 403 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 404 }; 405 406 static const struct dce_dmcu_mask dmcu_mask = { 407 DMCU_MASK_SH_LIST_DCN10(_MASK) 408 }; 409 410 static const struct dce_abm_registers abm_regs = { 411 ABM_DCN20_REG_LIST() 412 }; 413 414 static const struct dce_abm_shift abm_shift = { 415 ABM_MASK_SH_LIST_DCN20(__SHIFT) 416 }; 417 418 static const struct dce_abm_mask abm_mask = { 419 ABM_MASK_SH_LIST_DCN20(_MASK) 420 }; 421 422 #define audio_regs(id)\ 423 [id] = {\ 424 AUD_COMMON_REG_LIST(id)\ 425 } 426 427 static const struct dce_audio_registers audio_regs[] = { 428 audio_regs(0), 429 audio_regs(1), 430 audio_regs(2), 431 audio_regs(3), 432 audio_regs(4), 433 audio_regs(5), 434 }; 435 436 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 437 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 438 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 439 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 440 441 static const struct dce_audio_shift audio_shift = { 442 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 443 }; 444 445 static const struct dce_audio_mask audio_mask = { 446 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 447 }; 448 449 static const struct dccg_registers dccg_regs = { 450 DCCG_COMMON_REG_LIST_DCN_BASE() 451 }; 452 453 static const struct dccg_shift dccg_shift = { 454 DCCG_MASK_SH_LIST_DCN2_1(__SHIFT) 455 }; 456 457 static const struct dccg_mask dccg_mask = { 458 DCCG_MASK_SH_LIST_DCN2_1(_MASK) 459 }; 460 461 #define opp_regs(id)\ 462 [id] = {\ 463 OPP_REG_LIST_DCN20(id),\ 464 } 465 466 static const struct dcn20_opp_registers opp_regs[] = { 467 opp_regs(0), 468 opp_regs(1), 469 opp_regs(2), 470 opp_regs(3), 471 opp_regs(4), 472 opp_regs(5), 473 }; 474 475 static const struct dcn20_opp_shift opp_shift = { 476 OPP_MASK_SH_LIST_DCN20(__SHIFT) 477 }; 478 479 static const struct dcn20_opp_mask opp_mask = { 480 OPP_MASK_SH_LIST_DCN20(_MASK) 481 }; 482 483 #define tg_regs(id)\ 484 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)} 485 486 static const struct dcn_optc_registers tg_regs[] = { 487 tg_regs(0), 488 tg_regs(1), 489 tg_regs(2), 490 tg_regs(3) 491 }; 492 493 static const struct dcn_optc_shift tg_shift = { 494 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 495 }; 496 497 static const struct dcn_optc_mask tg_mask = { 498 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 499 }; 500 501 static const struct dcn20_mpc_registers mpc_regs = { 502 MPC_REG_LIST_DCN2_0(0), 503 MPC_REG_LIST_DCN2_0(1), 504 MPC_REG_LIST_DCN2_0(2), 505 MPC_REG_LIST_DCN2_0(3), 506 MPC_REG_LIST_DCN2_0(4), 507 MPC_REG_LIST_DCN2_0(5), 508 MPC_OUT_MUX_REG_LIST_DCN2_0(0), 509 MPC_OUT_MUX_REG_LIST_DCN2_0(1), 510 MPC_OUT_MUX_REG_LIST_DCN2_0(2), 511 MPC_OUT_MUX_REG_LIST_DCN2_0(3), 512 MPC_DBG_REG_LIST_DCN2_0() 513 }; 514 515 static const struct dcn20_mpc_shift mpc_shift = { 516 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT), 517 MPC_DEBUG_REG_LIST_SH_DCN20 518 }; 519 520 static const struct dcn20_mpc_mask mpc_mask = { 521 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK), 522 MPC_DEBUG_REG_LIST_MASK_DCN20 523 }; 524 525 #define hubp_regs(id)\ 526 [id] = {\ 527 HUBP_REG_LIST_DCN21(id)\ 528 } 529 530 static const struct dcn_hubp2_registers hubp_regs[] = { 531 hubp_regs(0), 532 hubp_regs(1), 533 hubp_regs(2), 534 hubp_regs(3) 535 }; 536 537 static const struct dcn_hubp2_shift hubp_shift = { 538 HUBP_MASK_SH_LIST_DCN21(__SHIFT) 539 }; 540 541 static const struct dcn_hubp2_mask hubp_mask = { 542 HUBP_MASK_SH_LIST_DCN21(_MASK) 543 }; 544 545 static const struct dcn_hubbub_registers hubbub_reg = { 546 HUBBUB_REG_LIST_DCN21() 547 }; 548 549 static const struct dcn_hubbub_shift hubbub_shift = { 550 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT) 551 }; 552 553 static const struct dcn_hubbub_mask hubbub_mask = { 554 HUBBUB_MASK_SH_LIST_DCN21(_MASK) 555 }; 556 557 558 #define vmid_regs(id)\ 559 [id] = {\ 560 DCN20_VMID_REG_LIST(id)\ 561 } 562 563 static const struct dcn_vmid_registers vmid_regs[] = { 564 vmid_regs(0), 565 vmid_regs(1), 566 vmid_regs(2), 567 vmid_regs(3), 568 vmid_regs(4), 569 vmid_regs(5), 570 vmid_regs(6), 571 vmid_regs(7), 572 vmid_regs(8), 573 vmid_regs(9), 574 vmid_regs(10), 575 vmid_regs(11), 576 vmid_regs(12), 577 vmid_regs(13), 578 vmid_regs(14), 579 vmid_regs(15) 580 }; 581 582 static const struct dcn20_vmid_shift vmid_shifts = { 583 DCN20_VMID_MASK_SH_LIST(__SHIFT) 584 }; 585 586 static const struct dcn20_vmid_mask vmid_masks = { 587 DCN20_VMID_MASK_SH_LIST(_MASK) 588 }; 589 590 #define dsc_regsDCN20(id)\ 591 [id] = {\ 592 DSC_REG_LIST_DCN20(id)\ 593 } 594 595 static const struct dcn20_dsc_registers dsc_regs[] = { 596 dsc_regsDCN20(0), 597 dsc_regsDCN20(1), 598 dsc_regsDCN20(2), 599 dsc_regsDCN20(3), 600 dsc_regsDCN20(4), 601 dsc_regsDCN20(5) 602 }; 603 604 static const struct dcn20_dsc_shift dsc_shift = { 605 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 606 }; 607 608 static const struct dcn20_dsc_mask dsc_mask = { 609 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 610 }; 611 612 #define ipp_regs(id)\ 613 [id] = {\ 614 IPP_REG_LIST_DCN20(id),\ 615 } 616 617 static const struct dcn10_ipp_registers ipp_regs[] = { 618 ipp_regs(0), 619 ipp_regs(1), 620 ipp_regs(2), 621 ipp_regs(3), 622 }; 623 624 static const struct dcn10_ipp_shift ipp_shift = { 625 IPP_MASK_SH_LIST_DCN20(__SHIFT) 626 }; 627 628 static const struct dcn10_ipp_mask ipp_mask = { 629 IPP_MASK_SH_LIST_DCN20(_MASK), 630 }; 631 632 #define opp_regs(id)\ 633 [id] = {\ 634 OPP_REG_LIST_DCN20(id),\ 635 } 636 637 638 #define aux_engine_regs(id)\ 639 [id] = {\ 640 AUX_COMMON_REG_LIST0(id), \ 641 .AUXN_IMPCAL = 0, \ 642 .AUXP_IMPCAL = 0, \ 643 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 644 } 645 646 static const struct dce110_aux_registers aux_engine_regs[] = { 647 aux_engine_regs(0), 648 aux_engine_regs(1), 649 aux_engine_regs(2), 650 aux_engine_regs(3), 651 aux_engine_regs(4), 652 }; 653 654 #define tf_regs(id)\ 655 [id] = {\ 656 TF_REG_LIST_DCN20(id),\ 657 TF_REG_LIST_DCN20_COMMON_APPEND(id),\ 658 } 659 660 static const struct dcn2_dpp_registers tf_regs[] = { 661 tf_regs(0), 662 tf_regs(1), 663 tf_regs(2), 664 tf_regs(3), 665 }; 666 667 static const struct dcn2_dpp_shift tf_shift = { 668 TF_REG_LIST_SH_MASK_DCN20(__SHIFT), 669 TF_DEBUG_REG_LIST_SH_DCN20 670 }; 671 672 static const struct dcn2_dpp_mask tf_mask = { 673 TF_REG_LIST_SH_MASK_DCN20(_MASK), 674 TF_DEBUG_REG_LIST_MASK_DCN20 675 }; 676 677 #define stream_enc_regs(id)\ 678 [id] = {\ 679 SE_DCN2_REG_LIST(id)\ 680 } 681 682 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 683 stream_enc_regs(0), 684 stream_enc_regs(1), 685 stream_enc_regs(2), 686 stream_enc_regs(3), 687 stream_enc_regs(4), 688 }; 689 690 static const struct dce110_aux_registers_shift aux_shift = { 691 DCN_AUX_MASK_SH_LIST(__SHIFT) 692 }; 693 694 static const struct dce110_aux_registers_mask aux_mask = { 695 DCN_AUX_MASK_SH_LIST(_MASK) 696 }; 697 698 static const struct dcn10_stream_encoder_shift se_shift = { 699 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) 700 }; 701 702 static const struct dcn10_stream_encoder_mask se_mask = { 703 SE_COMMON_MASK_SH_LIST_DCN20(_MASK) 704 }; 705 706 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu); 707 708 static int dcn21_populate_dml_pipes_from_context( 709 struct dc *dc, 710 struct dc_state *context, 711 display_e2e_pipe_params_st *pipes, 712 bool fast_validate); 713 714 static struct input_pixel_processor *dcn21_ipp_create( 715 struct dc_context *ctx, uint32_t inst) 716 { 717 struct dcn10_ipp *ipp = 718 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 719 720 if (!ipp) { 721 BREAK_TO_DEBUGGER(); 722 return NULL; 723 } 724 725 dcn20_ipp_construct(ipp, ctx, inst, 726 &ipp_regs[inst], &ipp_shift, &ipp_mask); 727 return &ipp->base; 728 } 729 730 static struct dpp *dcn21_dpp_create( 731 struct dc_context *ctx, 732 uint32_t inst) 733 { 734 struct dcn20_dpp *dpp = 735 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL); 736 737 if (!dpp) 738 return NULL; 739 740 if (dpp2_construct(dpp, ctx, inst, 741 &tf_regs[inst], &tf_shift, &tf_mask)) 742 return &dpp->base; 743 744 BREAK_TO_DEBUGGER(); 745 kfree(dpp); 746 return NULL; 747 } 748 749 static struct dce_aux *dcn21_aux_engine_create( 750 struct dc_context *ctx, 751 uint32_t inst) 752 { 753 struct aux_engine_dce110 *aux_engine = 754 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 755 756 if (!aux_engine) 757 return NULL; 758 759 dce110_aux_engine_construct(aux_engine, ctx, inst, 760 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 761 &aux_engine_regs[inst], 762 &aux_mask, 763 &aux_shift, 764 ctx->dc->caps.extended_aux_timeout_support); 765 766 return &aux_engine->base; 767 } 768 769 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 770 771 static const struct dce_i2c_registers i2c_hw_regs[] = { 772 i2c_inst_regs(1), 773 i2c_inst_regs(2), 774 i2c_inst_regs(3), 775 i2c_inst_regs(4), 776 i2c_inst_regs(5), 777 }; 778 779 static const struct dce_i2c_shift i2c_shifts = { 780 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 781 }; 782 783 static const struct dce_i2c_mask i2c_masks = { 784 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 785 }; 786 787 static struct dce_i2c_hw *dcn21_i2c_hw_create(struct dc_context *ctx, 788 uint32_t inst) 789 { 790 struct dce_i2c_hw *dce_i2c_hw = 791 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 792 793 if (!dce_i2c_hw) 794 return NULL; 795 796 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 797 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 798 799 return dce_i2c_hw; 800 } 801 802 static const struct resource_caps res_cap_rn = { 803 .num_timing_generator = 4, 804 .num_opp = 4, 805 .num_video_plane = 4, 806 .num_audio = 4, // 4 audio endpoints. 4 audio streams 807 .num_stream_encoder = 5, 808 .num_pll = 5, // maybe 3 because the last two used for USB-c 809 .num_dwb = 1, 810 .num_ddc = 5, 811 .num_vmid = 16, 812 .num_dsc = 3, 813 }; 814 815 #ifdef DIAGS_BUILD 816 static const struct resource_caps res_cap_rn_FPGA_4pipe = { 817 .num_timing_generator = 4, 818 .num_opp = 4, 819 .num_video_plane = 4, 820 .num_audio = 7, 821 .num_stream_encoder = 4, 822 .num_pll = 4, 823 .num_dwb = 1, 824 .num_ddc = 4, 825 .num_dsc = 0, 826 }; 827 828 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = { 829 .num_timing_generator = 2, 830 .num_opp = 2, 831 .num_video_plane = 2, 832 .num_audio = 7, 833 .num_stream_encoder = 2, 834 .num_pll = 4, 835 .num_dwb = 1, 836 .num_ddc = 4, 837 .num_dsc = 2, 838 }; 839 #endif 840 841 static const struct dc_plane_cap plane_cap = { 842 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 843 .blends_with_above = true, 844 .blends_with_below = true, 845 .per_pixel_alpha = true, 846 847 .pixel_format_support = { 848 .argb8888 = true, 849 .nv12 = true, 850 .fp16 = true, 851 .p010 = true 852 }, 853 854 .max_upscale_factor = { 855 .argb8888 = 16000, 856 .nv12 = 16000, 857 .fp16 = 16000 858 }, 859 860 .max_downscale_factor = { 861 .argb8888 = 250, 862 .nv12 = 250, 863 .fp16 = 250 864 }, 865 64, 866 64 867 }; 868 869 static const struct dc_debug_options debug_defaults_drv = { 870 .disable_dmcu = false, 871 .force_abm_enable = false, 872 .timing_trace = false, 873 .clock_trace = true, 874 .disable_pplib_clock_request = true, 875 .min_disp_clk_khz = 100000, 876 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 877 .force_single_disp_pipe_split = false, 878 .disable_dcc = DCC_ENABLE, 879 .vsr_support = true, 880 .performance_trace = false, 881 .max_downscale_src_width = 4096, 882 .disable_pplib_wm_range = false, 883 .scl_reset_length10 = true, 884 .sanity_checks = true, 885 .disable_48mhz_pwrdwn = false, 886 .usbc_combo_phy_reset_wa = true, 887 .dmub_command_table = true, 888 .use_max_lb = true, 889 .optimize_edp_link_rate = true 890 }; 891 892 static const struct dc_debug_options debug_defaults_diags = { 893 .disable_dmcu = false, 894 .force_abm_enable = false, 895 .timing_trace = true, 896 .clock_trace = true, 897 .disable_dpp_power_gate = true, 898 .disable_hubp_power_gate = true, 899 .disable_clock_gate = true, 900 .disable_pplib_clock_request = true, 901 .disable_pplib_wm_range = true, 902 .disable_stutter = true, 903 .disable_48mhz_pwrdwn = true, 904 .disable_psr = true, 905 .enable_tri_buf = true, 906 .use_max_lb = true 907 }; 908 909 enum dcn20_clk_src_array_id { 910 DCN20_CLK_SRC_PLL0, 911 DCN20_CLK_SRC_PLL1, 912 DCN20_CLK_SRC_PLL2, 913 DCN20_CLK_SRC_PLL3, 914 DCN20_CLK_SRC_PLL4, 915 DCN20_CLK_SRC_TOTAL_DCN21 916 }; 917 918 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) 919 { 920 unsigned int i; 921 922 for (i = 0; i < pool->base.stream_enc_count; i++) { 923 if (pool->base.stream_enc[i] != NULL) { 924 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 925 pool->base.stream_enc[i] = NULL; 926 } 927 } 928 929 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 930 if (pool->base.dscs[i] != NULL) 931 dcn20_dsc_destroy(&pool->base.dscs[i]); 932 } 933 934 if (pool->base.mpc != NULL) { 935 kfree(TO_DCN20_MPC(pool->base.mpc)); 936 pool->base.mpc = NULL; 937 } 938 if (pool->base.hubbub != NULL) { 939 kfree(pool->base.hubbub); 940 pool->base.hubbub = NULL; 941 } 942 for (i = 0; i < pool->base.pipe_count; i++) { 943 if (pool->base.dpps[i] != NULL) 944 dcn20_dpp_destroy(&pool->base.dpps[i]); 945 946 if (pool->base.ipps[i] != NULL) 947 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 948 949 if (pool->base.hubps[i] != NULL) { 950 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 951 pool->base.hubps[i] = NULL; 952 } 953 954 if (pool->base.irqs != NULL) { 955 dal_irq_service_destroy(&pool->base.irqs); 956 } 957 } 958 959 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 960 if (pool->base.engines[i] != NULL) 961 dce110_engine_destroy(&pool->base.engines[i]); 962 if (pool->base.hw_i2cs[i] != NULL) { 963 kfree(pool->base.hw_i2cs[i]); 964 pool->base.hw_i2cs[i] = NULL; 965 } 966 if (pool->base.sw_i2cs[i] != NULL) { 967 kfree(pool->base.sw_i2cs[i]); 968 pool->base.sw_i2cs[i] = NULL; 969 } 970 } 971 972 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 973 if (pool->base.opps[i] != NULL) 974 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 975 } 976 977 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 978 if (pool->base.timing_generators[i] != NULL) { 979 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 980 pool->base.timing_generators[i] = NULL; 981 } 982 } 983 984 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 985 if (pool->base.dwbc[i] != NULL) { 986 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); 987 pool->base.dwbc[i] = NULL; 988 } 989 if (pool->base.mcif_wb[i] != NULL) { 990 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); 991 pool->base.mcif_wb[i] = NULL; 992 } 993 } 994 995 for (i = 0; i < pool->base.audio_count; i++) { 996 if (pool->base.audios[i]) 997 dce_aud_destroy(&pool->base.audios[i]); 998 } 999 1000 for (i = 0; i < pool->base.clk_src_count; i++) { 1001 if (pool->base.clock_sources[i] != NULL) { 1002 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1003 pool->base.clock_sources[i] = NULL; 1004 } 1005 } 1006 1007 if (pool->base.dp_clock_source != NULL) { 1008 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1009 pool->base.dp_clock_source = NULL; 1010 } 1011 1012 if (pool->base.abm != NULL) { 1013 if (pool->base.abm->ctx->dc->config.disable_dmcu) 1014 dmub_abm_destroy(&pool->base.abm); 1015 else 1016 dce_abm_destroy(&pool->base.abm); 1017 } 1018 1019 if (pool->base.dmcu != NULL) 1020 dce_dmcu_destroy(&pool->base.dmcu); 1021 1022 if (pool->base.psr != NULL) 1023 dmub_psr_destroy(&pool->base.psr); 1024 1025 if (pool->base.dccg != NULL) 1026 dcn_dccg_destroy(&pool->base.dccg); 1027 1028 if (pool->base.pp_smu != NULL) 1029 dcn21_pp_smu_destroy(&pool->base.pp_smu); 1030 } 1031 1032 1033 static void calculate_wm_set_for_vlevel( 1034 int vlevel, 1035 struct wm_range_table_entry *table_entry, 1036 struct dcn_watermarks *wm_set, 1037 struct display_mode_lib *dml, 1038 display_e2e_pipe_params_st *pipes, 1039 int pipe_cnt) 1040 { 1041 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; 1042 1043 ASSERT(vlevel < dml->soc.num_states); 1044 /* only pipe 0 is read for voltage and dcf/soc clocks */ 1045 pipes[0].clks_cfg.voltage = vlevel; 1046 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; 1047 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; 1048 1049 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; 1050 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; 1051 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; 1052 1053 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; 1054 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; 1055 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; 1056 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 1057 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; 1058 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; 1059 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; 1060 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000; 1061 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; 1062 1063 } 1064 1065 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) 1066 { 1067 int i; 1068 1069 if (dc->bb_overrides.sr_exit_time_ns) { 1070 for (i = 0; i < WM_SET_COUNT; i++) { 1071 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us = 1072 dc->bb_overrides.sr_exit_time_ns / 1000.0; 1073 } 1074 } 1075 1076 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) { 1077 for (i = 0; i < WM_SET_COUNT; i++) { 1078 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us = 1079 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 1080 } 1081 } 1082 1083 if (dc->bb_overrides.urgent_latency_ns) { 1084 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 1085 } 1086 1087 if (dc->bb_overrides.dram_clock_change_latency_ns) { 1088 for (i = 0; i < WM_SET_COUNT; i++) { 1089 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us = 1090 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 1091 } 1092 } 1093 } 1094 1095 static void dcn21_calculate_wm( 1096 struct dc *dc, struct dc_state *context, 1097 display_e2e_pipe_params_st *pipes, 1098 int *out_pipe_cnt, 1099 int *pipe_split_from, 1100 int vlevel_req, 1101 bool fast_validate) 1102 { 1103 int pipe_cnt, i, pipe_idx; 1104 int vlevel, vlevel_max; 1105 struct wm_range_table_entry *table_entry; 1106 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; 1107 1108 ASSERT(bw_params); 1109 1110 patch_bounding_box(dc, &context->bw_ctx.dml.soc); 1111 1112 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1113 if (!context->res_ctx.pipe_ctx[i].stream) 1114 continue; 1115 1116 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 1117 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb]; 1118 1119 if (pipe_split_from[i] < 0) { 1120 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1121 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; 1122 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) 1123 pipes[pipe_cnt].pipe.dest.odm_combine = 1124 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx]; 1125 else 1126 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1127 pipe_idx++; 1128 } else { 1129 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1130 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; 1131 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) 1132 pipes[pipe_cnt].pipe.dest.odm_combine = 1133 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]]; 1134 else 1135 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1136 } 1137 pipe_cnt++; 1138 } 1139 1140 if (pipe_cnt != pipe_idx) { 1141 if (dc->res_pool->funcs->populate_dml_pipes) 1142 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, 1143 context, pipes, fast_validate); 1144 else 1145 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc, 1146 context, pipes, fast_validate); 1147 } 1148 1149 *out_pipe_cnt = pipe_cnt; 1150 1151 vlevel_max = bw_params->clk_table.num_entries - 1; 1152 1153 1154 /* WM Set D */ 1155 table_entry = &bw_params->wm_table.entries[WM_D]; 1156 if (table_entry->wm_type == WM_TYPE_RETRAINING) 1157 vlevel = 0; 1158 else 1159 vlevel = vlevel_max; 1160 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, 1161 &context->bw_ctx.dml, pipes, pipe_cnt); 1162 /* WM Set C */ 1163 table_entry = &bw_params->wm_table.entries[WM_C]; 1164 vlevel = MIN(MAX(vlevel_req, 3), vlevel_max); 1165 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, 1166 &context->bw_ctx.dml, pipes, pipe_cnt); 1167 /* WM Set B */ 1168 table_entry = &bw_params->wm_table.entries[WM_B]; 1169 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max); 1170 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, 1171 &context->bw_ctx.dml, pipes, pipe_cnt); 1172 1173 /* WM Set A */ 1174 table_entry = &bw_params->wm_table.entries[WM_A]; 1175 vlevel = MIN(vlevel_req, vlevel_max); 1176 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, 1177 &context->bw_ctx.dml, pipes, pipe_cnt); 1178 } 1179 1180 1181 static bool dcn21_fast_validate_bw( 1182 struct dc *dc, 1183 struct dc_state *context, 1184 display_e2e_pipe_params_st *pipes, 1185 int *pipe_cnt_out, 1186 int *pipe_split_from, 1187 int *vlevel_out, 1188 bool fast_validate) 1189 { 1190 bool out = false; 1191 int split[MAX_PIPES] = { 0 }; 1192 int pipe_cnt, i, pipe_idx, vlevel; 1193 1194 ASSERT(pipes); 1195 if (!pipes) 1196 return false; 1197 1198 dcn20_merge_pipes_for_validate(dc, context); 1199 1200 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 1201 1202 *pipe_cnt_out = pipe_cnt; 1203 1204 if (!pipe_cnt) { 1205 out = true; 1206 goto validate_out; 1207 } 1208 /* 1209 * DML favors voltage over p-state, but we're more interested in 1210 * supporting p-state over voltage. We can't support p-state in 1211 * prefetch mode > 0 so try capping the prefetch mode to start. 1212 */ 1213 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = 1214 dm_allow_self_refresh_and_mclk_switch; 1215 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1216 1217 if (vlevel > context->bw_ctx.dml.soc.num_states) { 1218 /* 1219 * If mode is unsupported or there's still no p-state support then 1220 * fall back to favoring voltage. 1221 * 1222 * We don't actually support prefetch mode 2, so require that we 1223 * at least support prefetch mode 1. 1224 */ 1225 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = 1226 dm_allow_self_refresh; 1227 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1228 if (vlevel > context->bw_ctx.dml.soc.num_states) 1229 goto validate_fail; 1230 } 1231 1232 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL); 1233 1234 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1235 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1236 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe; 1237 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 1238 1239 if (!pipe->stream) 1240 continue; 1241 1242 /* We only support full screen mpo with ODM */ 1243 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled 1244 && pipe->plane_state && mpo_pipe 1245 && memcmp(&mpo_pipe->plane_res.scl_data.recout, 1246 &pipe->plane_res.scl_data.recout, 1247 sizeof(struct rect)) != 0) { 1248 ASSERT(mpo_pipe->plane_state != pipe->plane_state); 1249 goto validate_fail; 1250 } 1251 pipe_idx++; 1252 } 1253 1254 /*initialize pipe_just_split_from to invalid idx*/ 1255 for (i = 0; i < MAX_PIPES; i++) 1256 pipe_split_from[i] = -1; 1257 1258 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { 1259 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1260 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 1261 1262 if (!pipe->stream || pipe_split_from[i] >= 0) 1263 continue; 1264 1265 pipe_idx++; 1266 1267 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 1268 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 1269 ASSERT(hsplit_pipe); 1270 if (!dcn20_split_stream_for_odm( 1271 dc, &context->res_ctx, 1272 pipe, hsplit_pipe)) 1273 goto validate_fail; 1274 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 1275 dcn20_build_mapped_resource(dc, context, pipe->stream); 1276 } 1277 1278 if (!pipe->plane_state) 1279 continue; 1280 /* Skip 2nd half of already split pipe */ 1281 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state) 1282 continue; 1283 1284 if (split[i] == 2) { 1285 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) { 1286 /* pipe not split previously needs split */ 1287 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 1288 ASSERT(hsplit_pipe); 1289 if (!hsplit_pipe) { 1290 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2; 1291 continue; 1292 } 1293 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 1294 if (!dcn20_split_stream_for_odm( 1295 dc, &context->res_ctx, 1296 pipe, hsplit_pipe)) 1297 goto validate_fail; 1298 dcn20_build_mapped_resource(dc, context, pipe->stream); 1299 } else { 1300 dcn20_split_stream_for_mpc( 1301 &context->res_ctx, dc->res_pool, 1302 pipe, hsplit_pipe); 1303 resource_build_scaling_params(pipe); 1304 resource_build_scaling_params(hsplit_pipe); 1305 } 1306 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 1307 } 1308 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { 1309 /* merge should already have been done */ 1310 ASSERT(0); 1311 } 1312 } 1313 /* Actual dsc count per stream dsc validation*/ 1314 if (!dcn20_validate_dsc(dc, context)) { 1315 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = 1316 DML_FAIL_DSC_VALIDATION_FAILURE; 1317 goto validate_fail; 1318 } 1319 1320 *vlevel_out = vlevel; 1321 1322 out = true; 1323 goto validate_out; 1324 1325 validate_fail: 1326 out = false; 1327 1328 validate_out: 1329 return out; 1330 } 1331 1332 static noinline bool dcn21_validate_bandwidth_fp(struct dc *dc, 1333 struct dc_state *context, bool fast_validate) 1334 { 1335 bool out = false; 1336 1337 BW_VAL_TRACE_SETUP(); 1338 1339 int vlevel = 0; 1340 int pipe_split_from[MAX_PIPES]; 1341 int pipe_cnt = 0; 1342 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC); 1343 DC_LOGGER_INIT(dc->ctx->logger); 1344 1345 BW_VAL_TRACE_COUNT(); 1346 1347 /*Unsafe due to current pipe merge and split logic*/ 1348 ASSERT(context != dc->current_state); 1349 1350 out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate); 1351 1352 if (pipe_cnt == 0) 1353 goto validate_out; 1354 1355 if (!out) 1356 goto validate_fail; 1357 1358 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1359 1360 if (fast_validate) { 1361 BW_VAL_TRACE_SKIP(fast); 1362 goto validate_out; 1363 } 1364 1365 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate); 1366 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 1367 1368 BW_VAL_TRACE_END_WATERMARKS(); 1369 1370 goto validate_out; 1371 1372 validate_fail: 1373 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1374 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1375 1376 BW_VAL_TRACE_SKIP(fail); 1377 out = false; 1378 1379 validate_out: 1380 kfree(pipes); 1381 1382 BW_VAL_TRACE_FINISH(); 1383 1384 return out; 1385 } 1386 1387 /* 1388 * Some of the functions further below use the FPU, so we need to wrap this 1389 * with DC_FP_START()/DC_FP_END(). Use the same approach as for 1390 * dcn20_validate_bandwidth in dcn20_resource.c. 1391 */ 1392 static bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context, 1393 bool fast_validate) 1394 { 1395 bool voltage_supported; 1396 DC_FP_START(); 1397 voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate); 1398 DC_FP_END(); 1399 return voltage_supported; 1400 } 1401 1402 static void dcn21_destroy_resource_pool(struct resource_pool **pool) 1403 { 1404 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool); 1405 1406 dcn21_resource_destruct(dcn21_pool); 1407 kfree(dcn21_pool); 1408 *pool = NULL; 1409 } 1410 1411 static struct clock_source *dcn21_clock_source_create( 1412 struct dc_context *ctx, 1413 struct dc_bios *bios, 1414 enum clock_source_id id, 1415 const struct dce110_clk_src_regs *regs, 1416 bool dp_clk_src) 1417 { 1418 struct dce110_clk_src *clk_src = 1419 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1420 1421 if (!clk_src) 1422 return NULL; 1423 1424 if (dcn20_clk_src_construct(clk_src, ctx, bios, id, 1425 regs, &cs_shift, &cs_mask)) { 1426 clk_src->base.dp_clk_src = dp_clk_src; 1427 return &clk_src->base; 1428 } 1429 1430 BREAK_TO_DEBUGGER(); 1431 return NULL; 1432 } 1433 1434 static struct hubp *dcn21_hubp_create( 1435 struct dc_context *ctx, 1436 uint32_t inst) 1437 { 1438 struct dcn21_hubp *hubp21 = 1439 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL); 1440 1441 if (!hubp21) 1442 return NULL; 1443 1444 if (hubp21_construct(hubp21, ctx, inst, 1445 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1446 return &hubp21->base; 1447 1448 BREAK_TO_DEBUGGER(); 1449 kfree(hubp21); 1450 return NULL; 1451 } 1452 1453 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx) 1454 { 1455 int i; 1456 1457 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), 1458 GFP_KERNEL); 1459 1460 if (!hubbub) 1461 return NULL; 1462 1463 hubbub21_construct(hubbub, ctx, 1464 &hubbub_reg, 1465 &hubbub_shift, 1466 &hubbub_mask); 1467 1468 for (i = 0; i < res_cap_rn.num_vmid; i++) { 1469 struct dcn20_vmid *vmid = &hubbub->vmid[i]; 1470 1471 vmid->ctx = ctx; 1472 1473 vmid->regs = &vmid_regs[i]; 1474 vmid->shifts = &vmid_shifts; 1475 vmid->masks = &vmid_masks; 1476 } 1477 hubbub->num_vmid = res_cap_rn.num_vmid; 1478 1479 return &hubbub->base; 1480 } 1481 1482 static struct output_pixel_processor *dcn21_opp_create(struct dc_context *ctx, 1483 uint32_t inst) 1484 { 1485 struct dcn20_opp *opp = 1486 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1487 1488 if (!opp) { 1489 BREAK_TO_DEBUGGER(); 1490 return NULL; 1491 } 1492 1493 dcn20_opp_construct(opp, ctx, inst, 1494 &opp_regs[inst], &opp_shift, &opp_mask); 1495 return &opp->base; 1496 } 1497 1498 static struct timing_generator *dcn21_timing_generator_create(struct dc_context *ctx, 1499 uint32_t instance) 1500 { 1501 struct optc *tgn10 = 1502 kzalloc(sizeof(struct optc), GFP_KERNEL); 1503 1504 if (!tgn10) 1505 return NULL; 1506 1507 tgn10->base.inst = instance; 1508 tgn10->base.ctx = ctx; 1509 1510 tgn10->tg_regs = &tg_regs[instance]; 1511 tgn10->tg_shift = &tg_shift; 1512 tgn10->tg_mask = &tg_mask; 1513 1514 dcn20_timing_generator_init(tgn10); 1515 1516 return &tgn10->base; 1517 } 1518 1519 static struct mpc *dcn21_mpc_create(struct dc_context *ctx) 1520 { 1521 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), 1522 GFP_KERNEL); 1523 1524 if (!mpc20) 1525 return NULL; 1526 1527 dcn20_mpc_construct(mpc20, ctx, 1528 &mpc_regs, 1529 &mpc_shift, 1530 &mpc_mask, 1531 6); 1532 1533 return &mpc20->base; 1534 } 1535 1536 static void read_dce_straps( 1537 struct dc_context *ctx, 1538 struct resource_straps *straps) 1539 { 1540 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1541 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1542 1543 } 1544 1545 1546 static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx, 1547 uint32_t inst) 1548 { 1549 struct dcn20_dsc *dsc = 1550 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1551 1552 if (!dsc) { 1553 BREAK_TO_DEBUGGER(); 1554 return NULL; 1555 } 1556 1557 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1558 return &dsc->base; 1559 } 1560 1561 static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_limit_table *clk_table, unsigned int high_voltage_lvl) 1562 { 1563 struct _vcs_dpi_voltage_scaling_st low_pstate_lvl; 1564 int i; 1565 1566 low_pstate_lvl.state = 1; 1567 low_pstate_lvl.dcfclk_mhz = clk_table->entries[0].dcfclk_mhz; 1568 low_pstate_lvl.fabricclk_mhz = clk_table->entries[0].fclk_mhz; 1569 low_pstate_lvl.socclk_mhz = clk_table->entries[0].socclk_mhz; 1570 low_pstate_lvl.dram_speed_mts = clk_table->entries[0].memclk_mhz * 2; 1571 1572 low_pstate_lvl.dispclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dispclk_mhz; 1573 low_pstate_lvl.dppclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dppclk_mhz; 1574 low_pstate_lvl.dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[high_voltage_lvl].dram_bw_per_chan_gbps; 1575 low_pstate_lvl.dscclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dscclk_mhz; 1576 low_pstate_lvl.dtbclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dtbclk_mhz; 1577 low_pstate_lvl.phyclk_d18_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_d18_mhz; 1578 low_pstate_lvl.phyclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_mhz; 1579 1580 for (i = clk_table->num_entries; i > 1; i--) 1581 clk_table->entries[i] = clk_table->entries[i-1]; 1582 clk_table->entries[1] = clk_table->entries[0]; 1583 clk_table->num_entries++; 1584 1585 return low_pstate_lvl; 1586 } 1587 1588 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1589 { 1590 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool); 1591 struct clk_limit_table *clk_table = &bw_params->clk_table; 1592 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1593 unsigned int i, closest_clk_lvl = 0, k = 0; 1594 int j; 1595 1596 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator; 1597 dcn2_1_ip.max_num_dpp = pool->base.pipe_count; 1598 dcn2_1_soc.num_chans = bw_params->num_channels; 1599 1600 ASSERT(clk_table->num_entries); 1601 /* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */ 1602 for (i = 0; i < dcn2_1_soc.num_states + 1; i++) { 1603 clock_limits[i] = dcn2_1_soc.clock_limits[i]; 1604 } 1605 1606 for (i = 0; i < clk_table->num_entries; i++) { 1607 /* loop backwards*/ 1608 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) { 1609 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { 1610 closest_clk_lvl = j; 1611 break; 1612 } 1613 } 1614 1615 /* clk_table[1] is reserved for min DF PState. skip here to fill in later. */ 1616 if (i == 1) 1617 k++; 1618 1619 clock_limits[k].state = k; 1620 clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 1621 clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 1622 clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz; 1623 clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; 1624 1625 clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; 1626 clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; 1627 clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; 1628 clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; 1629 clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; 1630 clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; 1631 clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; 1632 1633 k++; 1634 } 1635 for (i = 0; i < clk_table->num_entries + 1; i++) 1636 dcn2_1_soc.clock_limits[i] = clock_limits[i]; 1637 if (clk_table->num_entries) { 1638 dcn2_1_soc.num_states = clk_table->num_entries + 1; 1639 /* fill in min DF PState */ 1640 dcn2_1_soc.clock_limits[1] = construct_low_pstate_lvl(clk_table, closest_clk_lvl); 1641 /* duplicate last level */ 1642 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1]; 1643 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states; 1644 } 1645 1646 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); 1647 } 1648 1649 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx) 1650 { 1651 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 1652 1653 if (!pp_smu) 1654 return pp_smu; 1655 1656 dm_pp_get_funcs(ctx, pp_smu); 1657 1658 if (pp_smu->ctx.ver != PP_SMU_VER_RN) 1659 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); 1660 1661 1662 return pp_smu; 1663 } 1664 1665 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu) 1666 { 1667 if (pp_smu && *pp_smu) { 1668 kfree(*pp_smu); 1669 *pp_smu = NULL; 1670 } 1671 } 1672 1673 static struct audio *dcn21_create_audio( 1674 struct dc_context *ctx, unsigned int inst) 1675 { 1676 return dce_audio_create(ctx, inst, 1677 &audio_regs[inst], &audio_shift, &audio_mask); 1678 } 1679 1680 static struct dc_cap_funcs cap_funcs = { 1681 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1682 }; 1683 1684 static struct stream_encoder *dcn21_stream_encoder_create(enum engine_id eng_id, 1685 struct dc_context *ctx) 1686 { 1687 struct dcn10_stream_encoder *enc1 = 1688 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1689 1690 if (!enc1) 1691 return NULL; 1692 1693 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1694 &stream_enc_regs[eng_id], 1695 &se_shift, &se_mask); 1696 1697 return &enc1->base; 1698 } 1699 1700 static const struct dce_hwseq_registers hwseq_reg = { 1701 HWSEQ_DCN21_REG_LIST() 1702 }; 1703 1704 static const struct dce_hwseq_shift hwseq_shift = { 1705 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT) 1706 }; 1707 1708 static const struct dce_hwseq_mask hwseq_mask = { 1709 HWSEQ_DCN21_MASK_SH_LIST(_MASK) 1710 }; 1711 1712 static struct dce_hwseq *dcn21_hwseq_create( 1713 struct dc_context *ctx) 1714 { 1715 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1716 1717 if (hws) { 1718 hws->ctx = ctx; 1719 hws->regs = &hwseq_reg; 1720 hws->shifts = &hwseq_shift; 1721 hws->masks = &hwseq_mask; 1722 hws->wa.DEGVIDCN21 = true; 1723 hws->wa.disallow_self_refresh_during_multi_plane_transition = true; 1724 } 1725 return hws; 1726 } 1727 1728 static const struct resource_create_funcs res_create_funcs = { 1729 .read_dce_straps = read_dce_straps, 1730 .create_audio = dcn21_create_audio, 1731 .create_stream_encoder = dcn21_stream_encoder_create, 1732 .create_hwseq = dcn21_hwseq_create, 1733 }; 1734 1735 static const struct resource_create_funcs res_create_maximus_funcs = { 1736 .read_dce_straps = NULL, 1737 .create_audio = NULL, 1738 .create_stream_encoder = NULL, 1739 .create_hwseq = dcn21_hwseq_create, 1740 }; 1741 1742 static const struct encoder_feature_support link_enc_feature = { 1743 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1744 .max_hdmi_pixel_clock = 600000, 1745 .hdmi_ycbcr420_supported = true, 1746 .dp_ycbcr420_supported = true, 1747 .fec_supported = true, 1748 .flags.bits.IS_HBR2_CAPABLE = true, 1749 .flags.bits.IS_HBR3_CAPABLE = true, 1750 .flags.bits.IS_TPS3_CAPABLE = true, 1751 .flags.bits.IS_TPS4_CAPABLE = true 1752 }; 1753 1754 1755 #define link_regs(id, phyid)\ 1756 [id] = {\ 1757 LE_DCN2_REG_LIST(id), \ 1758 UNIPHY_DCN2_REG_LIST(phyid), \ 1759 DPCS_DCN21_REG_LIST(id), \ 1760 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 1761 } 1762 1763 static const struct dcn10_link_enc_registers link_enc_regs[] = { 1764 link_regs(0, A), 1765 link_regs(1, B), 1766 link_regs(2, C), 1767 link_regs(3, D), 1768 link_regs(4, E), 1769 }; 1770 1771 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 1772 { DCN_PANEL_CNTL_REG_LIST() } 1773 }; 1774 1775 static const struct dce_panel_cntl_shift panel_cntl_shift = { 1776 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 1777 }; 1778 1779 static const struct dce_panel_cntl_mask panel_cntl_mask = { 1780 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 1781 }; 1782 1783 #define aux_regs(id)\ 1784 [id] = {\ 1785 DCN2_AUX_REG_LIST(id)\ 1786 } 1787 1788 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 1789 aux_regs(0), 1790 aux_regs(1), 1791 aux_regs(2), 1792 aux_regs(3), 1793 aux_regs(4) 1794 }; 1795 1796 #define hpd_regs(id)\ 1797 [id] = {\ 1798 HPD_REG_LIST(id)\ 1799 } 1800 1801 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 1802 hpd_regs(0), 1803 hpd_regs(1), 1804 hpd_regs(2), 1805 hpd_regs(3), 1806 hpd_regs(4) 1807 }; 1808 1809 static const struct dcn10_link_enc_shift le_shift = { 1810 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\ 1811 DPCS_DCN21_MASK_SH_LIST(__SHIFT) 1812 }; 1813 1814 static const struct dcn10_link_enc_mask le_mask = { 1815 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\ 1816 DPCS_DCN21_MASK_SH_LIST(_MASK) 1817 }; 1818 1819 static int map_transmitter_id_to_phy_instance( 1820 enum transmitter transmitter) 1821 { 1822 switch (transmitter) { 1823 case TRANSMITTER_UNIPHY_A: 1824 return 0; 1825 break; 1826 case TRANSMITTER_UNIPHY_B: 1827 return 1; 1828 break; 1829 case TRANSMITTER_UNIPHY_C: 1830 return 2; 1831 break; 1832 case TRANSMITTER_UNIPHY_D: 1833 return 3; 1834 break; 1835 case TRANSMITTER_UNIPHY_E: 1836 return 4; 1837 break; 1838 default: 1839 ASSERT(0); 1840 return 0; 1841 } 1842 } 1843 1844 static struct link_encoder *dcn21_link_encoder_create( 1845 const struct encoder_init_data *enc_init_data) 1846 { 1847 struct dcn21_link_encoder *enc21 = 1848 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL); 1849 int link_regs_id; 1850 1851 if (!enc21) 1852 return NULL; 1853 1854 link_regs_id = 1855 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 1856 1857 dcn21_link_encoder_construct(enc21, 1858 enc_init_data, 1859 &link_enc_feature, 1860 &link_enc_regs[link_regs_id], 1861 &link_enc_aux_regs[enc_init_data->channel - 1], 1862 &link_enc_hpd_regs[enc_init_data->hpd_source], 1863 &le_shift, 1864 &le_mask); 1865 1866 return &enc21->enc10.base; 1867 } 1868 1869 static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1870 { 1871 struct dce_panel_cntl *panel_cntl = 1872 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 1873 1874 if (!panel_cntl) 1875 return NULL; 1876 1877 dce_panel_cntl_construct(panel_cntl, 1878 init_data, 1879 &panel_cntl_regs[init_data->inst], 1880 &panel_cntl_shift, 1881 &panel_cntl_mask); 1882 1883 return &panel_cntl->base; 1884 } 1885 1886 #define CTX ctx 1887 1888 #define REG(reg_name) \ 1889 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 1890 1891 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1892 { 1893 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 1894 /* RV1 support max 4 pipes */ 1895 value = value & 0xf; 1896 return value; 1897 } 1898 1899 static int dcn21_populate_dml_pipes_from_context( 1900 struct dc *dc, 1901 struct dc_state *context, 1902 display_e2e_pipe_params_st *pipes, 1903 bool fast_validate) 1904 { 1905 uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1906 int i; 1907 1908 for (i = 0; i < pipe_cnt; i++) { 1909 1910 pipes[i].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active; 1911 pipes[i].pipe.src.gpuvm = 1; 1912 } 1913 1914 return pipe_cnt; 1915 } 1916 1917 static enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state) 1918 { 1919 enum dc_status result = DC_OK; 1920 1921 if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) { 1922 plane_state->dcc.enable = 1; 1923 /* align to our worst case block width */ 1924 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024; 1925 } 1926 result = dcn20_patch_unknown_plane_state(plane_state); 1927 return result; 1928 } 1929 1930 static const struct resource_funcs dcn21_res_pool_funcs = { 1931 .destroy = dcn21_destroy_resource_pool, 1932 .link_enc_create = dcn21_link_encoder_create, 1933 .panel_cntl_create = dcn21_panel_cntl_create, 1934 .validate_bandwidth = dcn21_validate_bandwidth, 1935 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context, 1936 .add_stream_to_ctx = dcn20_add_stream_to_ctx, 1937 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1938 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1939 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1940 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, 1941 .patch_unknown_plane_state = dcn21_patch_unknown_plane_state, 1942 .set_mcif_arb_params = dcn20_set_mcif_arb_params, 1943 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1944 .update_bw_bounding_box = update_bw_bounding_box 1945 }; 1946 1947 static bool dcn21_resource_construct( 1948 uint8_t num_virtual_links, 1949 struct dc *dc, 1950 struct dcn21_resource_pool *pool) 1951 { 1952 int i, j; 1953 struct dc_context *ctx = dc->ctx; 1954 struct irq_service_init_data init_data; 1955 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1956 uint32_t num_pipes; 1957 1958 ctx->dc_bios->regs = &bios_regs; 1959 1960 pool->base.res_cap = &res_cap_rn; 1961 #ifdef DIAGS_BUILD 1962 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1963 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc; 1964 pool->base.res_cap = &res_cap_rn_FPGA_4pipe; 1965 #endif 1966 1967 pool->base.funcs = &dcn21_res_pool_funcs; 1968 1969 /************************************************* 1970 * Resource + asic cap harcoding * 1971 *************************************************/ 1972 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1973 1974 /* max pipe num for ASIC before check pipe fuses */ 1975 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1976 1977 dc->caps.max_downscale_ratio = 200; 1978 dc->caps.i2c_speed_in_khz = 100; 1979 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/ 1980 dc->caps.max_cursor_size = 256; 1981 dc->caps.min_horizontal_blanking_period = 80; 1982 dc->caps.dmdata_alloc_size = 2048; 1983 1984 dc->caps.max_slave_planes = 1; 1985 dc->caps.max_slave_yuv_planes = 1; 1986 dc->caps.max_slave_rgb_planes = 1; 1987 dc->caps.post_blend_color_processing = true; 1988 dc->caps.force_dp_tps4_for_cp2520 = true; 1989 dc->caps.extended_aux_timeout_support = true; 1990 dc->caps.dmcub_support = true; 1991 dc->caps.is_apu = true; 1992 1993 /* Color pipeline capabilities */ 1994 dc->caps.color.dpp.dcn_arch = 1; 1995 dc->caps.color.dpp.input_lut_shared = 0; 1996 dc->caps.color.dpp.icsc = 1; 1997 dc->caps.color.dpp.dgam_ram = 1; 1998 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1999 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2000 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0; 2001 dc->caps.color.dpp.dgam_rom_caps.pq = 0; 2002 dc->caps.color.dpp.dgam_rom_caps.hlg = 0; 2003 dc->caps.color.dpp.post_csc = 0; 2004 dc->caps.color.dpp.gamma_corr = 0; 2005 dc->caps.color.dpp.dgam_rom_for_yuv = 1; 2006 2007 dc->caps.color.dpp.hw_3d_lut = 1; 2008 dc->caps.color.dpp.ogam_ram = 1; 2009 // no OGAM ROM on DCN2 2010 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2011 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2012 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2013 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2014 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2015 dc->caps.color.dpp.ocsc = 0; 2016 2017 dc->caps.color.mpc.gamut_remap = 0; 2018 dc->caps.color.mpc.num_3dluts = 0; 2019 dc->caps.color.mpc.shared_3d_lut = 0; 2020 dc->caps.color.mpc.ogam_ram = 1; 2021 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2022 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2023 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2024 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2025 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2026 dc->caps.color.mpc.ocsc = 1; 2027 2028 dc->caps.hdmi_frl_pcon_support = true; 2029 2030 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2031 dc->debug = debug_defaults_drv; 2032 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 2033 pool->base.pipe_count = 4; 2034 dc->debug = debug_defaults_diags; 2035 } else 2036 dc->debug = debug_defaults_diags; 2037 2038 // Init the vm_helper 2039 if (dc->vm_helper) 2040 vm_helper_init(dc->vm_helper, 16); 2041 2042 /************************************************* 2043 * Create resources * 2044 *************************************************/ 2045 2046 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = 2047 dcn21_clock_source_create(ctx, ctx->dc_bios, 2048 CLOCK_SOURCE_COMBO_PHY_PLL0, 2049 &clk_src_regs[0], false); 2050 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = 2051 dcn21_clock_source_create(ctx, ctx->dc_bios, 2052 CLOCK_SOURCE_COMBO_PHY_PLL1, 2053 &clk_src_regs[1], false); 2054 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = 2055 dcn21_clock_source_create(ctx, ctx->dc_bios, 2056 CLOCK_SOURCE_COMBO_PHY_PLL2, 2057 &clk_src_regs[2], false); 2058 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] = 2059 dcn21_clock_source_create(ctx, ctx->dc_bios, 2060 CLOCK_SOURCE_COMBO_PHY_PLL3, 2061 &clk_src_regs[3], false); 2062 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] = 2063 dcn21_clock_source_create(ctx, ctx->dc_bios, 2064 CLOCK_SOURCE_COMBO_PHY_PLL4, 2065 &clk_src_regs[4], false); 2066 2067 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21; 2068 2069 /* todo: not reuse phy_pll registers */ 2070 pool->base.dp_clock_source = 2071 dcn21_clock_source_create(ctx, ctx->dc_bios, 2072 CLOCK_SOURCE_ID_DP_DTO, 2073 &clk_src_regs[0], true); 2074 2075 for (i = 0; i < pool->base.clk_src_count; i++) { 2076 if (pool->base.clock_sources[i] == NULL) { 2077 dm_error("DC: failed to create clock sources!\n"); 2078 BREAK_TO_DEBUGGER(); 2079 goto create_fail; 2080 } 2081 } 2082 2083 pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2084 if (pool->base.dccg == NULL) { 2085 dm_error("DC: failed to create dccg!\n"); 2086 BREAK_TO_DEBUGGER(); 2087 goto create_fail; 2088 } 2089 2090 if (!dc->config.disable_dmcu) { 2091 pool->base.dmcu = dcn21_dmcu_create(ctx, 2092 &dmcu_regs, 2093 &dmcu_shift, 2094 &dmcu_mask); 2095 if (pool->base.dmcu == NULL) { 2096 dm_error("DC: failed to create dmcu!\n"); 2097 BREAK_TO_DEBUGGER(); 2098 goto create_fail; 2099 } 2100 2101 dc->debug.dmub_command_table = false; 2102 } 2103 2104 if (dc->config.disable_dmcu) { 2105 pool->base.psr = dmub_psr_create(ctx); 2106 2107 if (pool->base.psr == NULL) { 2108 dm_error("DC: failed to create psr obj!\n"); 2109 BREAK_TO_DEBUGGER(); 2110 goto create_fail; 2111 } 2112 } 2113 2114 if (dc->config.disable_dmcu) 2115 pool->base.abm = dmub_abm_create(ctx, 2116 &abm_regs, 2117 &abm_shift, 2118 &abm_mask); 2119 else 2120 pool->base.abm = dce_abm_create(ctx, 2121 &abm_regs, 2122 &abm_shift, 2123 &abm_mask); 2124 2125 pool->base.pp_smu = dcn21_pp_smu_create(ctx); 2126 2127 num_pipes = dcn2_1_ip.max_num_dpp; 2128 2129 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++) 2130 if (pipe_fuses & 1 << i) 2131 num_pipes--; 2132 dcn2_1_ip.max_num_dpp = num_pipes; 2133 dcn2_1_ip.max_num_otg = num_pipes; 2134 2135 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); 2136 2137 init_data.ctx = dc->ctx; 2138 pool->base.irqs = dal_irq_service_dcn21_create(&init_data); 2139 if (!pool->base.irqs) 2140 goto create_fail; 2141 2142 j = 0; 2143 /* mem input -> ipp -> dpp -> opp -> TG */ 2144 for (i = 0; i < pool->base.pipe_count; i++) { 2145 /* if pipe is disabled, skip instance of HW pipe, 2146 * i.e, skip ASIC register instance 2147 */ 2148 if ((pipe_fuses & (1 << i)) != 0) 2149 continue; 2150 2151 pool->base.hubps[j] = dcn21_hubp_create(ctx, i); 2152 if (pool->base.hubps[j] == NULL) { 2153 BREAK_TO_DEBUGGER(); 2154 dm_error( 2155 "DC: failed to create memory input!\n"); 2156 goto create_fail; 2157 } 2158 2159 pool->base.ipps[j] = dcn21_ipp_create(ctx, i); 2160 if (pool->base.ipps[j] == NULL) { 2161 BREAK_TO_DEBUGGER(); 2162 dm_error( 2163 "DC: failed to create input pixel processor!\n"); 2164 goto create_fail; 2165 } 2166 2167 pool->base.dpps[j] = dcn21_dpp_create(ctx, i); 2168 if (pool->base.dpps[j] == NULL) { 2169 BREAK_TO_DEBUGGER(); 2170 dm_error( 2171 "DC: failed to create dpps!\n"); 2172 goto create_fail; 2173 } 2174 2175 pool->base.opps[j] = dcn21_opp_create(ctx, i); 2176 if (pool->base.opps[j] == NULL) { 2177 BREAK_TO_DEBUGGER(); 2178 dm_error( 2179 "DC: failed to create output pixel processor!\n"); 2180 goto create_fail; 2181 } 2182 2183 pool->base.timing_generators[j] = dcn21_timing_generator_create( 2184 ctx, i); 2185 if (pool->base.timing_generators[j] == NULL) { 2186 BREAK_TO_DEBUGGER(); 2187 dm_error("DC: failed to create tg!\n"); 2188 goto create_fail; 2189 } 2190 j++; 2191 } 2192 2193 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2194 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i); 2195 if (pool->base.engines[i] == NULL) { 2196 BREAK_TO_DEBUGGER(); 2197 dm_error( 2198 "DC:failed to create aux engine!!\n"); 2199 goto create_fail; 2200 } 2201 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i); 2202 if (pool->base.hw_i2cs[i] == NULL) { 2203 BREAK_TO_DEBUGGER(); 2204 dm_error( 2205 "DC:failed to create hw i2c!!\n"); 2206 goto create_fail; 2207 } 2208 pool->base.sw_i2cs[i] = NULL; 2209 } 2210 2211 pool->base.timing_generator_count = j; 2212 pool->base.pipe_count = j; 2213 pool->base.mpcc_count = j; 2214 2215 pool->base.mpc = dcn21_mpc_create(ctx); 2216 if (pool->base.mpc == NULL) { 2217 BREAK_TO_DEBUGGER(); 2218 dm_error("DC: failed to create mpc!\n"); 2219 goto create_fail; 2220 } 2221 2222 pool->base.hubbub = dcn21_hubbub_create(ctx); 2223 if (pool->base.hubbub == NULL) { 2224 BREAK_TO_DEBUGGER(); 2225 dm_error("DC: failed to create hubbub!\n"); 2226 goto create_fail; 2227 } 2228 2229 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2230 pool->base.dscs[i] = dcn21_dsc_create(ctx, i); 2231 if (pool->base.dscs[i] == NULL) { 2232 BREAK_TO_DEBUGGER(); 2233 dm_error("DC: failed to create display stream compressor %d!\n", i); 2234 goto create_fail; 2235 } 2236 } 2237 2238 if (!dcn20_dwbc_create(ctx, &pool->base)) { 2239 BREAK_TO_DEBUGGER(); 2240 dm_error("DC: failed to create dwbc!\n"); 2241 goto create_fail; 2242 } 2243 if (!dcn20_mmhubbub_create(ctx, &pool->base)) { 2244 BREAK_TO_DEBUGGER(); 2245 dm_error("DC: failed to create mcif_wb!\n"); 2246 goto create_fail; 2247 } 2248 2249 if (!resource_construct(num_virtual_links, dc, &pool->base, 2250 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2251 &res_create_funcs : &res_create_maximus_funcs))) 2252 goto create_fail; 2253 2254 dcn21_hw_sequencer_construct(dc); 2255 2256 dc->caps.max_planes = pool->base.pipe_count; 2257 2258 for (i = 0; i < dc->caps.max_planes; ++i) 2259 dc->caps.planes[i] = plane_cap; 2260 2261 dc->cap_funcs = cap_funcs; 2262 2263 return true; 2264 2265 create_fail: 2266 2267 dcn21_resource_destruct(pool); 2268 2269 return false; 2270 } 2271 2272 struct resource_pool *dcn21_create_resource_pool( 2273 const struct dc_init_data *init_data, 2274 struct dc *dc) 2275 { 2276 struct dcn21_resource_pool *pool = 2277 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL); 2278 2279 if (!pool) 2280 return NULL; 2281 2282 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool)) 2283 return &pool->base; 2284 2285 BREAK_TO_DEBUGGER(); 2286 kfree(pool); 2287 return NULL; 2288 } 2289