1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 #include "dc.h" 30 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dcn20/dcn20_resource.h" 34 35 #include "clk_mgr.h" 36 #include "dcn10/dcn10_hubp.h" 37 #include "dcn10/dcn10_ipp.h" 38 #include "dcn20/dcn20_hubbub.h" 39 #include "dcn20/dcn20_mpc.h" 40 #include "dcn20/dcn20_hubp.h" 41 #include "dcn21_hubp.h" 42 #include "irq/dcn21/irq_service_dcn21.h" 43 #include "dcn20/dcn20_dpp.h" 44 #include "dcn20/dcn20_optc.h" 45 #include "dcn21/dcn21_hwseq.h" 46 #include "dce110/dce110_hw_sequencer.h" 47 #include "dcn20/dcn20_opp.h" 48 #include "dcn20/dcn20_dsc.h" 49 #include "dcn21/dcn21_link_encoder.h" 50 #include "dcn20/dcn20_stream_encoder.h" 51 #include "dce/dce_clock_source.h" 52 #include "dce/dce_audio.h" 53 #include "dce/dce_hwseq.h" 54 #include "virtual/virtual_stream_encoder.h" 55 #include "dce110/dce110_resource.h" 56 #include "dml/display_mode_vba.h" 57 #include "dcn20/dcn20_dccg.h" 58 #include "dcn21_hubbub.h" 59 #include "dcn10/dcn10_resource.h" 60 61 #include "dcn20/dcn20_dwb.h" 62 #include "dcn20/dcn20_mmhubbub.h" 63 64 #include "renoir_ip_offset.h" 65 #include "dcn/dcn_2_1_0_offset.h" 66 #include "dcn/dcn_2_1_0_sh_mask.h" 67 68 #include "nbio/nbio_7_0_offset.h" 69 70 #include "mmhub/mmhub_2_0_0_offset.h" 71 #include "mmhub/mmhub_2_0_0_sh_mask.h" 72 73 #include "reg_helper.h" 74 #include "dce/dce_abm.h" 75 #include "dce/dce_dmcu.h" 76 #include "dce/dce_aux.h" 77 #include "dce/dce_i2c.h" 78 #include "dcn21_resource.h" 79 #include "vm_helper.h" 80 #include "dcn20/dcn20_vmid.h" 81 82 #define SOC_BOUNDING_BOX_VALID false 83 #define DC_LOGGER_INIT(logger) 84 85 86 struct _vcs_dpi_ip_params_st dcn2_1_ip = { 87 .odm_capable = 1, 88 .gpuvm_enable = 1, 89 .hostvm_enable = 1, 90 .gpuvm_max_page_table_levels = 1, 91 .hostvm_max_page_table_levels = 4, 92 .hostvm_cached_page_table_levels = 2, 93 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 94 .num_dsc = 3, 95 #else 96 .num_dsc = 0, 97 #endif 98 .rob_buffer_size_kbytes = 168, 99 .det_buffer_size_kbytes = 164, 100 .dpte_buffer_size_in_pte_reqs_luma = 44, 101 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo 102 .dpp_output_buffer_pixels = 2560, 103 .opp_output_buffer_lines = 1, 104 .pixel_chunk_size_kbytes = 8, 105 .pte_enable = 1, 106 .max_page_table_levels = 4, 107 .pte_chunk_size_kbytes = 2, 108 .meta_chunk_size_kbytes = 2, 109 .writeback_chunk_size_kbytes = 2, 110 .line_buffer_size_bits = 789504, 111 .is_line_buffer_bpp_fixed = 0, 112 .line_buffer_fixed_bpp = 0, 113 .dcc_supported = true, 114 .max_line_buffer_lines = 12, 115 .writeback_luma_buffer_size_kbytes = 12, 116 .writeback_chroma_buffer_size_kbytes = 8, 117 .writeback_chroma_line_buffer_width_pixels = 4, 118 .writeback_max_hscl_ratio = 1, 119 .writeback_max_vscl_ratio = 1, 120 .writeback_min_hscl_ratio = 1, 121 .writeback_min_vscl_ratio = 1, 122 .writeback_max_hscl_taps = 12, 123 .writeback_max_vscl_taps = 12, 124 .writeback_line_buffer_luma_buffer_size = 0, 125 .writeback_line_buffer_chroma_buffer_size = 14643, 126 .cursor_buffer_size = 8, 127 .cursor_chunk_size = 2, 128 .max_num_otg = 4, 129 .max_num_dpp = 4, 130 .max_num_wb = 1, 131 .max_dchub_pscl_bw_pix_per_clk = 4, 132 .max_pscl_lb_bw_pix_per_clk = 2, 133 .max_lb_vscl_bw_pix_per_clk = 4, 134 .max_vscl_hscl_bw_pix_per_clk = 4, 135 .max_hscl_ratio = 4, 136 .max_vscl_ratio = 4, 137 .hscl_mults = 4, 138 .vscl_mults = 4, 139 .max_hscl_taps = 8, 140 .max_vscl_taps = 8, 141 .dispclk_ramp_margin_percent = 1, 142 .underscan_factor = 1.10, 143 .min_vblank_lines = 32, // 144 .dppclk_delay_subtotal = 77, // 145 .dppclk_delay_scl_lb_only = 16, 146 .dppclk_delay_scl = 50, 147 .dppclk_delay_cnvc_formatter = 8, 148 .dppclk_delay_cnvc_cursor = 6, 149 .dispclk_delay_subtotal = 87, // 150 .dcfclk_cstate_latency = 10, // SRExitTime 151 .max_inter_dcn_tile_repeaters = 8, 152 153 .xfc_supported = false, 154 .xfc_fill_bw_overhead_percent = 10.0, 155 .xfc_fill_constant_bytes = 0, 156 .ptoi_supported = 0 157 }; 158 159 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { 160 .clock_limits = { 161 { 162 .state = 0, 163 .dcfclk_mhz = 304.0, 164 .fabricclk_mhz = 600.0, 165 .dispclk_mhz = 618.0, 166 .dppclk_mhz = 440.0, 167 .phyclk_mhz = 600.0, 168 .socclk_mhz = 278.0, 169 .dscclk_mhz = 205.67, 170 .dram_speed_mts = 1600.0, 171 }, 172 { 173 .state = 1, 174 .dcfclk_mhz = 304.0, 175 .fabricclk_mhz = 600.0, 176 .dispclk_mhz = 618.0, 177 .dppclk_mhz = 618.0, 178 .phyclk_mhz = 600.0, 179 .socclk_mhz = 278.0, 180 .dscclk_mhz = 205.67, 181 .dram_speed_mts = 1600.0, 182 }, 183 { 184 .state = 2, 185 .dcfclk_mhz = 608.0, 186 .fabricclk_mhz = 1066.0, 187 .dispclk_mhz = 888.0, 188 .dppclk_mhz = 888.0, 189 .phyclk_mhz = 810.0, 190 .socclk_mhz = 278.0, 191 .dscclk_mhz = 287.67, 192 .dram_speed_mts = 2133.0, 193 }, 194 { 195 .state = 3, 196 .dcfclk_mhz = 676.0, 197 .fabricclk_mhz = 1600.0, 198 .dispclk_mhz = 1015.0, 199 .dppclk_mhz = 1015.0, 200 .phyclk_mhz = 810.0, 201 .socclk_mhz = 715.0, 202 .dscclk_mhz = 318.334, 203 .dram_speed_mts = 4266.0, 204 }, 205 { 206 .state = 4, 207 .dcfclk_mhz = 810.0, 208 .fabricclk_mhz = 1600.0, 209 .dispclk_mhz = 1395.0, 210 .dppclk_mhz = 1285.0, 211 .phyclk_mhz = 1325.0, 212 .socclk_mhz = 953.0, 213 .dscclk_mhz = 489.0, 214 .dram_speed_mts = 4266.0, 215 }, 216 /*Extra state, no dispclk ramping*/ 217 { 218 .state = 5, 219 .dcfclk_mhz = 810.0, 220 .fabricclk_mhz = 1600.0, 221 .dispclk_mhz = 1395.0, 222 .dppclk_mhz = 1285.0, 223 .phyclk_mhz = 1325.0, 224 .socclk_mhz = 953.0, 225 .dscclk_mhz = 489.0, 226 .dram_speed_mts = 4266.0, 227 }, 228 229 }, 230 231 .sr_exit_time_us = 12.5, 232 .sr_enter_plus_exit_time_us = 17.0, 233 .urgent_latency_us = 4.0, 234 .urgent_latency_pixel_data_only_us = 4.0, 235 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 236 .urgent_latency_vm_data_only_us = 4.0, 237 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 238 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 239 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 240 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 241 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0, 242 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 243 .max_avg_sdp_bw_use_normal_percent = 60.0, 244 .max_avg_dram_bw_use_normal_percent = 100.0, 245 .writeback_latency_us = 12.0, 246 .max_request_size_bytes = 256, 247 .dram_channel_width_bytes = 4, 248 .fabric_datapath_to_dcn_data_return_bytes = 32, 249 .dcn_downspread_percent = 0.5, 250 .downspread_percent = 0.5, 251 .dram_page_open_time_ns = 50.0, 252 .dram_rw_turnaround_time_ns = 17.5, 253 .dram_return_buffer_per_channel_bytes = 8192, 254 .round_trip_ping_latency_dcfclk_cycles = 128, 255 .urgent_out_of_order_return_per_channel_bytes = 4096, 256 .channel_interleave_bytes = 256, 257 .num_banks = 8, 258 .num_chans = 4, 259 .vmm_page_size_bytes = 4096, 260 .dram_clock_change_latency_us = 23.84, 261 .return_bus_width_bytes = 64, 262 .dispclk_dppclk_vco_speed_mhz = 3600, 263 .xfc_bus_transport_time_us = 4, 264 .xfc_xbuf_latency_tolerance_us = 4, 265 .use_urgent_burst_bw = 1, 266 .num_states = 5 267 }; 268 269 #ifndef MAX 270 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y)) 271 #endif 272 #ifndef MIN 273 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 274 #endif 275 276 /* begin ********************* 277 * macros to expend register list macro defined in HW object header file */ 278 279 /* DCN */ 280 /* TODO awful hack. fixup dcn20_dwb.h */ 281 #undef BASE_INNER 282 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg 283 284 #define BASE(seg) BASE_INNER(seg) 285 286 #define SR(reg_name)\ 287 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 288 mm ## reg_name 289 290 #define SRI(reg_name, block, id)\ 291 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 292 mm ## block ## id ## _ ## reg_name 293 294 #define SRIR(var_name, reg_name, block, id)\ 295 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 296 mm ## block ## id ## _ ## reg_name 297 298 #define SRII(reg_name, block, id)\ 299 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 300 mm ## block ## id ## _ ## reg_name 301 302 #define DCCG_SRII(reg_name, block, id)\ 303 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 304 mm ## block ## id ## _ ## reg_name 305 306 /* NBIO */ 307 #define NBIO_BASE_INNER(seg) \ 308 NBIF0_BASE__INST0_SEG ## seg 309 310 #define NBIO_BASE(seg) \ 311 NBIO_BASE_INNER(seg) 312 313 #define NBIO_SR(reg_name)\ 314 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 315 mm ## reg_name 316 317 /* MMHUB */ 318 #define MMHUB_BASE_INNER(seg) \ 319 MMHUB_BASE__INST0_SEG ## seg 320 321 #define MMHUB_BASE(seg) \ 322 MMHUB_BASE_INNER(seg) 323 324 #define MMHUB_SR(reg_name)\ 325 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 326 mmMM ## reg_name 327 328 #define clk_src_regs(index, pllid)\ 329 [index] = {\ 330 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\ 331 } 332 333 static const struct dce110_clk_src_regs clk_src_regs[] = { 334 clk_src_regs(0, A), 335 clk_src_regs(1, B), 336 clk_src_regs(2, C), 337 clk_src_regs(3, D), 338 clk_src_regs(4, E), 339 }; 340 341 static const struct dce110_clk_src_shift cs_shift = { 342 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 343 }; 344 345 static const struct dce110_clk_src_mask cs_mask = { 346 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 347 }; 348 349 static const struct bios_registers bios_regs = { 350 NBIO_SR(BIOS_SCRATCH_3), 351 NBIO_SR(BIOS_SCRATCH_6) 352 }; 353 354 static const struct dce_dmcu_registers dmcu_regs = { 355 DMCU_DCN10_REG_LIST() 356 }; 357 358 static const struct dce_dmcu_shift dmcu_shift = { 359 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 360 }; 361 362 static const struct dce_dmcu_mask dmcu_mask = { 363 DMCU_MASK_SH_LIST_DCN10(_MASK) 364 }; 365 366 static const struct dce_abm_registers abm_regs = { 367 ABM_DCN20_REG_LIST() 368 }; 369 370 static const struct dce_abm_shift abm_shift = { 371 ABM_MASK_SH_LIST_DCN20(__SHIFT) 372 }; 373 374 static const struct dce_abm_mask abm_mask = { 375 ABM_MASK_SH_LIST_DCN20(_MASK) 376 }; 377 378 #ifdef CONFIG_DRM_AMD_DC_DMUB 379 static const struct dcn21_dmcub_registers dmcub_regs = { 380 DMCUB_REG_LIST_DCN() 381 }; 382 383 static const struct dcn21_dmcub_shift dmcub_shift = { 384 DMCUB_COMMON_MASK_SH_LIST_BASE(__SHIFT) 385 }; 386 387 static const struct dcn21_dmcub_mask dmcub_mask = { 388 DMCUB_COMMON_MASK_SH_LIST_BASE(_MASK) 389 }; 390 #endif 391 392 #define audio_regs(id)\ 393 [id] = {\ 394 AUD_COMMON_REG_LIST(id)\ 395 } 396 397 static const struct dce_audio_registers audio_regs[] = { 398 audio_regs(0), 399 audio_regs(1), 400 audio_regs(2), 401 audio_regs(3), 402 audio_regs(4), 403 audio_regs(5), 404 }; 405 406 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 407 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 408 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 409 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 410 411 static const struct dce_audio_shift audio_shift = { 412 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 413 }; 414 415 static const struct dce_audio_mask audio_mask = { 416 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 417 }; 418 419 static const struct dccg_registers dccg_regs = { 420 DCCG_COMMON_REG_LIST_DCN_BASE() 421 }; 422 423 static const struct dccg_shift dccg_shift = { 424 DCCG_MASK_SH_LIST_DCN2(__SHIFT) 425 }; 426 427 static const struct dccg_mask dccg_mask = { 428 DCCG_MASK_SH_LIST_DCN2(_MASK) 429 }; 430 431 #define opp_regs(id)\ 432 [id] = {\ 433 OPP_REG_LIST_DCN20(id),\ 434 } 435 436 static const struct dcn20_opp_registers opp_regs[] = { 437 opp_regs(0), 438 opp_regs(1), 439 opp_regs(2), 440 opp_regs(3), 441 opp_regs(4), 442 opp_regs(5), 443 }; 444 445 static const struct dcn20_opp_shift opp_shift = { 446 OPP_MASK_SH_LIST_DCN20(__SHIFT) 447 }; 448 449 static const struct dcn20_opp_mask opp_mask = { 450 OPP_MASK_SH_LIST_DCN20(_MASK) 451 }; 452 453 #define tg_regs(id)\ 454 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)} 455 456 static const struct dcn_optc_registers tg_regs[] = { 457 tg_regs(0), 458 tg_regs(1), 459 tg_regs(2), 460 tg_regs(3) 461 }; 462 463 static const struct dcn_optc_shift tg_shift = { 464 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 465 }; 466 467 static const struct dcn_optc_mask tg_mask = { 468 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 469 }; 470 471 static const struct dcn20_mpc_registers mpc_regs = { 472 MPC_REG_LIST_DCN2_0(0), 473 MPC_REG_LIST_DCN2_0(1), 474 MPC_REG_LIST_DCN2_0(2), 475 MPC_REG_LIST_DCN2_0(3), 476 MPC_REG_LIST_DCN2_0(4), 477 MPC_REG_LIST_DCN2_0(5), 478 MPC_OUT_MUX_REG_LIST_DCN2_0(0), 479 MPC_OUT_MUX_REG_LIST_DCN2_0(1), 480 MPC_OUT_MUX_REG_LIST_DCN2_0(2), 481 MPC_OUT_MUX_REG_LIST_DCN2_0(3) 482 }; 483 484 static const struct dcn20_mpc_shift mpc_shift = { 485 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 486 }; 487 488 static const struct dcn20_mpc_mask mpc_mask = { 489 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 490 }; 491 492 #define hubp_regs(id)\ 493 [id] = {\ 494 HUBP_REG_LIST_DCN21(id)\ 495 } 496 497 static const struct dcn_hubp2_registers hubp_regs[] = { 498 hubp_regs(0), 499 hubp_regs(1), 500 hubp_regs(2), 501 hubp_regs(3) 502 }; 503 504 static const struct dcn_hubp2_shift hubp_shift = { 505 HUBP_MASK_SH_LIST_DCN21(__SHIFT) 506 }; 507 508 static const struct dcn_hubp2_mask hubp_mask = { 509 HUBP_MASK_SH_LIST_DCN21(_MASK) 510 }; 511 512 static const struct dcn_hubbub_registers hubbub_reg = { 513 HUBBUB_REG_LIST_DCN21() 514 }; 515 516 static const struct dcn_hubbub_shift hubbub_shift = { 517 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT) 518 }; 519 520 static const struct dcn_hubbub_mask hubbub_mask = { 521 HUBBUB_MASK_SH_LIST_DCN21(_MASK) 522 }; 523 524 525 #define vmid_regs(id)\ 526 [id] = {\ 527 DCN20_VMID_REG_LIST(id)\ 528 } 529 530 static const struct dcn_vmid_registers vmid_regs[] = { 531 vmid_regs(0), 532 vmid_regs(1), 533 vmid_regs(2), 534 vmid_regs(3), 535 vmid_regs(4), 536 vmid_regs(5), 537 vmid_regs(6), 538 vmid_regs(7), 539 vmid_regs(8), 540 vmid_regs(9), 541 vmid_regs(10), 542 vmid_regs(11), 543 vmid_regs(12), 544 vmid_regs(13), 545 vmid_regs(14), 546 vmid_regs(15) 547 }; 548 549 static const struct dcn20_vmid_shift vmid_shifts = { 550 DCN20_VMID_MASK_SH_LIST(__SHIFT) 551 }; 552 553 static const struct dcn20_vmid_mask vmid_masks = { 554 DCN20_VMID_MASK_SH_LIST(_MASK) 555 }; 556 557 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 558 #define dsc_regsDCN20(id)\ 559 [id] = {\ 560 DSC_REG_LIST_DCN20(id)\ 561 } 562 563 static const struct dcn20_dsc_registers dsc_regs[] = { 564 dsc_regsDCN20(0), 565 dsc_regsDCN20(1), 566 dsc_regsDCN20(2), 567 dsc_regsDCN20(3), 568 dsc_regsDCN20(4), 569 dsc_regsDCN20(5) 570 }; 571 572 static const struct dcn20_dsc_shift dsc_shift = { 573 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 574 }; 575 576 static const struct dcn20_dsc_mask dsc_mask = { 577 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 578 }; 579 #endif 580 581 #define ipp_regs(id)\ 582 [id] = {\ 583 IPP_REG_LIST_DCN20(id),\ 584 } 585 586 static const struct dcn10_ipp_registers ipp_regs[] = { 587 ipp_regs(0), 588 ipp_regs(1), 589 ipp_regs(2), 590 ipp_regs(3), 591 }; 592 593 static const struct dcn10_ipp_shift ipp_shift = { 594 IPP_MASK_SH_LIST_DCN20(__SHIFT) 595 }; 596 597 static const struct dcn10_ipp_mask ipp_mask = { 598 IPP_MASK_SH_LIST_DCN20(_MASK), 599 }; 600 601 #define opp_regs(id)\ 602 [id] = {\ 603 OPP_REG_LIST_DCN20(id),\ 604 } 605 606 607 #define aux_engine_regs(id)\ 608 [id] = {\ 609 AUX_COMMON_REG_LIST0(id), \ 610 .AUXN_IMPCAL = 0, \ 611 .AUXP_IMPCAL = 0, \ 612 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 613 } 614 615 static const struct dce110_aux_registers aux_engine_regs[] = { 616 aux_engine_regs(0), 617 aux_engine_regs(1), 618 aux_engine_regs(2), 619 aux_engine_regs(3), 620 aux_engine_regs(4), 621 }; 622 623 #define tf_regs(id)\ 624 [id] = {\ 625 TF_REG_LIST_DCN20(id),\ 626 } 627 628 static const struct dcn2_dpp_registers tf_regs[] = { 629 tf_regs(0), 630 tf_regs(1), 631 tf_regs(2), 632 tf_regs(3), 633 }; 634 635 static const struct dcn2_dpp_shift tf_shift = { 636 TF_REG_LIST_SH_MASK_DCN20(__SHIFT) 637 }; 638 639 static const struct dcn2_dpp_mask tf_mask = { 640 TF_REG_LIST_SH_MASK_DCN20(_MASK) 641 }; 642 643 #define stream_enc_regs(id)\ 644 [id] = {\ 645 SE_DCN2_REG_LIST(id)\ 646 } 647 648 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 649 stream_enc_regs(0), 650 stream_enc_regs(1), 651 stream_enc_regs(2), 652 stream_enc_regs(3), 653 stream_enc_regs(4), 654 }; 655 656 static const struct dce110_aux_registers_shift aux_shift = { 657 DCN_AUX_MASK_SH_LIST(__SHIFT) 658 }; 659 660 static const struct dce110_aux_registers_mask aux_mask = { 661 DCN_AUX_MASK_SH_LIST(_MASK) 662 }; 663 664 static const struct dcn10_stream_encoder_shift se_shift = { 665 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) 666 }; 667 668 static const struct dcn10_stream_encoder_mask se_mask = { 669 SE_COMMON_MASK_SH_LIST_DCN20(_MASK) 670 }; 671 672 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu); 673 674 static int dcn21_populate_dml_pipes_from_context( 675 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes); 676 677 static struct input_pixel_processor *dcn21_ipp_create( 678 struct dc_context *ctx, uint32_t inst) 679 { 680 struct dcn10_ipp *ipp = 681 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 682 683 if (!ipp) { 684 BREAK_TO_DEBUGGER(); 685 return NULL; 686 } 687 688 dcn20_ipp_construct(ipp, ctx, inst, 689 &ipp_regs[inst], &ipp_shift, &ipp_mask); 690 return &ipp->base; 691 } 692 693 static struct dpp *dcn21_dpp_create( 694 struct dc_context *ctx, 695 uint32_t inst) 696 { 697 struct dcn20_dpp *dpp = 698 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL); 699 700 if (!dpp) 701 return NULL; 702 703 if (dpp2_construct(dpp, ctx, inst, 704 &tf_regs[inst], &tf_shift, &tf_mask)) 705 return &dpp->base; 706 707 BREAK_TO_DEBUGGER(); 708 kfree(dpp); 709 return NULL; 710 } 711 712 static struct dce_aux *dcn21_aux_engine_create( 713 struct dc_context *ctx, 714 uint32_t inst) 715 { 716 struct aux_engine_dce110 *aux_engine = 717 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 718 719 if (!aux_engine) 720 return NULL; 721 722 dce110_aux_engine_construct(aux_engine, ctx, inst, 723 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 724 &aux_engine_regs[inst], 725 &aux_mask, 726 &aux_shift, 727 ctx->dc->caps.extended_aux_timeout_support); 728 729 return &aux_engine->base; 730 } 731 732 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 733 734 static const struct dce_i2c_registers i2c_hw_regs[] = { 735 i2c_inst_regs(1), 736 i2c_inst_regs(2), 737 i2c_inst_regs(3), 738 i2c_inst_regs(4), 739 i2c_inst_regs(5), 740 }; 741 742 static const struct dce_i2c_shift i2c_shifts = { 743 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 744 }; 745 746 static const struct dce_i2c_mask i2c_masks = { 747 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 748 }; 749 750 struct dce_i2c_hw *dcn21_i2c_hw_create( 751 struct dc_context *ctx, 752 uint32_t inst) 753 { 754 struct dce_i2c_hw *dce_i2c_hw = 755 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 756 757 if (!dce_i2c_hw) 758 return NULL; 759 760 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 761 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 762 763 return dce_i2c_hw; 764 } 765 766 static const struct resource_caps res_cap_rn = { 767 .num_timing_generator = 4, 768 .num_opp = 4, 769 .num_video_plane = 4, 770 .num_audio = 4, // 4 audio endpoints. 4 audio streams 771 .num_stream_encoder = 5, 772 .num_pll = 5, // maybe 3 because the last two used for USB-c 773 .num_dwb = 1, 774 .num_ddc = 5, 775 .num_vmid = 1, 776 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 777 .num_dsc = 3, 778 #endif 779 }; 780 781 #ifdef DIAGS_BUILD 782 static const struct resource_caps res_cap_rn_FPGA_4pipe = { 783 .num_timing_generator = 4, 784 .num_opp = 4, 785 .num_video_plane = 4, 786 .num_audio = 7, 787 .num_stream_encoder = 4, 788 .num_pll = 4, 789 .num_dwb = 1, 790 .num_ddc = 4, 791 .num_dsc = 0, 792 }; 793 794 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = { 795 .num_timing_generator = 2, 796 .num_opp = 2, 797 .num_video_plane = 2, 798 .num_audio = 7, 799 .num_stream_encoder = 2, 800 .num_pll = 4, 801 .num_dwb = 1, 802 .num_ddc = 4, 803 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 804 .num_dsc = 2, 805 #endif 806 }; 807 #endif 808 809 static const struct dc_plane_cap plane_cap = { 810 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 811 .blends_with_above = true, 812 .blends_with_below = true, 813 .per_pixel_alpha = true, 814 815 .pixel_format_support = { 816 .argb8888 = true, 817 .nv12 = true, 818 .fp16 = true 819 }, 820 821 .max_upscale_factor = { 822 .argb8888 = 16000, 823 .nv12 = 16000, 824 .fp16 = 16000 825 }, 826 827 .max_downscale_factor = { 828 .argb8888 = 250, 829 .nv12 = 250, 830 .fp16 = 250 831 } 832 }; 833 834 static const struct dc_debug_options debug_defaults_drv = { 835 .disable_dmcu = true, 836 .force_abm_enable = false, 837 .timing_trace = false, 838 .clock_trace = true, 839 .disable_pplib_clock_request = true, 840 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 841 .force_single_disp_pipe_split = false, 842 .disable_dcc = DCC_ENABLE, 843 .vsr_support = true, 844 .performance_trace = false, 845 .max_downscale_src_width = 3840, 846 .disable_pplib_wm_range = false, 847 .scl_reset_length10 = true, 848 .sanity_checks = true, 849 .disable_48mhz_pwrdwn = false, 850 }; 851 852 static const struct dc_debug_options debug_defaults_diags = { 853 .disable_dmcu = true, 854 .force_abm_enable = false, 855 .timing_trace = true, 856 .clock_trace = true, 857 .disable_dpp_power_gate = true, 858 .disable_hubp_power_gate = true, 859 .disable_clock_gate = true, 860 .disable_pplib_clock_request = true, 861 .disable_pplib_wm_range = true, 862 .disable_stutter = true, 863 .disable_48mhz_pwrdwn = true, 864 }; 865 866 enum dcn20_clk_src_array_id { 867 DCN20_CLK_SRC_PLL0, 868 DCN20_CLK_SRC_PLL1, 869 DCN20_CLK_SRC_TOTAL_DCN21 870 }; 871 872 static void destruct(struct dcn21_resource_pool *pool) 873 { 874 unsigned int i; 875 876 for (i = 0; i < pool->base.stream_enc_count; i++) { 877 if (pool->base.stream_enc[i] != NULL) { 878 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 879 pool->base.stream_enc[i] = NULL; 880 } 881 } 882 883 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 884 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 885 if (pool->base.dscs[i] != NULL) 886 dcn20_dsc_destroy(&pool->base.dscs[i]); 887 } 888 #endif 889 890 if (pool->base.mpc != NULL) { 891 kfree(TO_DCN20_MPC(pool->base.mpc)); 892 pool->base.mpc = NULL; 893 } 894 if (pool->base.hubbub != NULL) { 895 kfree(pool->base.hubbub); 896 pool->base.hubbub = NULL; 897 } 898 for (i = 0; i < pool->base.pipe_count; i++) { 899 if (pool->base.dpps[i] != NULL) 900 dcn20_dpp_destroy(&pool->base.dpps[i]); 901 902 if (pool->base.ipps[i] != NULL) 903 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 904 905 if (pool->base.hubps[i] != NULL) { 906 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 907 pool->base.hubps[i] = NULL; 908 } 909 910 if (pool->base.irqs != NULL) { 911 dal_irq_service_destroy(&pool->base.irqs); 912 } 913 } 914 915 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 916 if (pool->base.engines[i] != NULL) 917 dce110_engine_destroy(&pool->base.engines[i]); 918 if (pool->base.hw_i2cs[i] != NULL) { 919 kfree(pool->base.hw_i2cs[i]); 920 pool->base.hw_i2cs[i] = NULL; 921 } 922 if (pool->base.sw_i2cs[i] != NULL) { 923 kfree(pool->base.sw_i2cs[i]); 924 pool->base.sw_i2cs[i] = NULL; 925 } 926 } 927 928 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 929 if (pool->base.opps[i] != NULL) 930 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 931 } 932 933 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 934 if (pool->base.timing_generators[i] != NULL) { 935 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 936 pool->base.timing_generators[i] = NULL; 937 } 938 } 939 940 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 941 if (pool->base.dwbc[i] != NULL) { 942 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); 943 pool->base.dwbc[i] = NULL; 944 } 945 if (pool->base.mcif_wb[i] != NULL) { 946 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); 947 pool->base.mcif_wb[i] = NULL; 948 } 949 } 950 951 for (i = 0; i < pool->base.audio_count; i++) { 952 if (pool->base.audios[i]) 953 dce_aud_destroy(&pool->base.audios[i]); 954 } 955 956 for (i = 0; i < pool->base.clk_src_count; i++) { 957 if (pool->base.clock_sources[i] != NULL) { 958 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 959 pool->base.clock_sources[i] = NULL; 960 } 961 } 962 963 if (pool->base.dp_clock_source != NULL) { 964 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 965 pool->base.dp_clock_source = NULL; 966 } 967 968 969 if (pool->base.abm != NULL) 970 dce_abm_destroy(&pool->base.abm); 971 972 if (pool->base.dmcu != NULL) 973 dce_dmcu_destroy(&pool->base.dmcu); 974 975 #ifdef CONFIG_DRM_AMD_DC_DMUB 976 if (pool->base.dmcub != NULL) 977 dcn21_dmcub_destroy(&pool->base.dmcub); 978 #endif 979 980 if (pool->base.dccg != NULL) 981 dcn_dccg_destroy(&pool->base.dccg); 982 983 if (pool->base.pp_smu != NULL) 984 dcn21_pp_smu_destroy(&pool->base.pp_smu); 985 } 986 987 988 static void calculate_wm_set_for_vlevel( 989 int vlevel, 990 struct wm_range_table_entry *table_entry, 991 struct dcn_watermarks *wm_set, 992 struct display_mode_lib *dml, 993 display_e2e_pipe_params_st *pipes, 994 int pipe_cnt) 995 { 996 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; 997 998 ASSERT(vlevel < dml->soc.num_states); 999 /* only pipe 0 is read for voltage and dcf/soc clocks */ 1000 pipes[0].clks_cfg.voltage = vlevel; 1001 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; 1002 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; 1003 1004 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; 1005 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; 1006 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; 1007 1008 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; 1009 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; 1010 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; 1011 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 1012 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; 1013 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 1014 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; 1015 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; 1016 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000; 1017 #endif 1018 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; 1019 1020 } 1021 1022 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) 1023 { 1024 int i; 1025 1026 kernel_fpu_begin(); 1027 if (dc->bb_overrides.sr_exit_time_ns) { 1028 for (i = 0; i < WM_SET_COUNT; i++) { 1029 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us = 1030 dc->bb_overrides.sr_exit_time_ns / 1000.0; 1031 } 1032 } 1033 1034 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) { 1035 for (i = 0; i < WM_SET_COUNT; i++) { 1036 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us = 1037 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 1038 } 1039 } 1040 1041 if (dc->bb_overrides.urgent_latency_ns) { 1042 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 1043 } 1044 1045 if (dc->bb_overrides.dram_clock_change_latency_ns) { 1046 for (i = 0; i < WM_SET_COUNT; i++) { 1047 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us = 1048 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 1049 } 1050 } 1051 1052 kernel_fpu_end(); 1053 } 1054 1055 void dcn21_calculate_wm( 1056 struct dc *dc, struct dc_state *context, 1057 display_e2e_pipe_params_st *pipes, 1058 int *out_pipe_cnt, 1059 int *pipe_split_from, 1060 int vlevel_req) 1061 { 1062 int pipe_cnt, i, pipe_idx; 1063 int vlevel, vlevel_max; 1064 struct wm_range_table_entry *table_entry; 1065 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; 1066 1067 ASSERT(bw_params); 1068 1069 patch_bounding_box(dc, &context->bw_ctx.dml.soc); 1070 1071 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1072 if (!context->res_ctx.pipe_ctx[i].stream) 1073 continue; 1074 1075 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 1076 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb]; 1077 1078 if (pipe_split_from[i] < 0) { 1079 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1080 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; 1081 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) 1082 pipes[pipe_cnt].pipe.dest.odm_combine = 1083 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx]; 1084 else 1085 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1086 pipe_idx++; 1087 } else { 1088 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1089 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; 1090 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) 1091 pipes[pipe_cnt].pipe.dest.odm_combine = 1092 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]]; 1093 else 1094 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1095 } 1096 pipe_cnt++; 1097 } 1098 1099 if (pipe_cnt != pipe_idx) { 1100 if (dc->res_pool->funcs->populate_dml_pipes) 1101 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, 1102 &context->res_ctx, pipes); 1103 else 1104 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc, 1105 &context->res_ctx, pipes); 1106 } 1107 1108 *out_pipe_cnt = pipe_cnt; 1109 1110 vlevel_max = bw_params->clk_table.num_entries - 1; 1111 1112 1113 /* WM Set D */ 1114 table_entry = &bw_params->wm_table.entries[WM_D]; 1115 if (table_entry->wm_type == WM_TYPE_RETRAINING) 1116 vlevel = 0; 1117 else 1118 vlevel = vlevel_max; 1119 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, 1120 &context->bw_ctx.dml, pipes, pipe_cnt); 1121 /* WM Set C */ 1122 table_entry = &bw_params->wm_table.entries[WM_C]; 1123 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max); 1124 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, 1125 &context->bw_ctx.dml, pipes, pipe_cnt); 1126 /* WM Set B */ 1127 table_entry = &bw_params->wm_table.entries[WM_B]; 1128 vlevel = MIN(MAX(vlevel_req, 1), vlevel_max); 1129 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, 1130 &context->bw_ctx.dml, pipes, pipe_cnt); 1131 1132 /* WM Set A */ 1133 table_entry = &bw_params->wm_table.entries[WM_A]; 1134 vlevel = MIN(vlevel_req, vlevel_max); 1135 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, 1136 &context->bw_ctx.dml, pipes, pipe_cnt); 1137 } 1138 1139 1140 bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context, 1141 bool fast_validate) 1142 { 1143 bool out = false; 1144 1145 BW_VAL_TRACE_SETUP(); 1146 1147 int vlevel = 0; 1148 int pipe_split_from[MAX_PIPES]; 1149 int pipe_cnt = 0; 1150 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1151 DC_LOGGER_INIT(dc->ctx->logger); 1152 1153 BW_VAL_TRACE_COUNT(); 1154 1155 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel); 1156 1157 if (pipe_cnt == 0) 1158 goto validate_out; 1159 1160 if (!out) 1161 goto validate_fail; 1162 1163 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1164 1165 if (fast_validate) { 1166 BW_VAL_TRACE_SKIP(fast); 1167 goto validate_out; 1168 } 1169 1170 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel); 1171 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 1172 1173 BW_VAL_TRACE_END_WATERMARKS(); 1174 1175 goto validate_out; 1176 1177 validate_fail: 1178 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1179 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1180 1181 BW_VAL_TRACE_SKIP(fail); 1182 out = false; 1183 1184 validate_out: 1185 kfree(pipes); 1186 1187 BW_VAL_TRACE_FINISH(); 1188 1189 return out; 1190 } 1191 static void dcn21_destroy_resource_pool(struct resource_pool **pool) 1192 { 1193 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool); 1194 1195 destruct(dcn21_pool); 1196 kfree(dcn21_pool); 1197 *pool = NULL; 1198 } 1199 1200 static struct clock_source *dcn21_clock_source_create( 1201 struct dc_context *ctx, 1202 struct dc_bios *bios, 1203 enum clock_source_id id, 1204 const struct dce110_clk_src_regs *regs, 1205 bool dp_clk_src) 1206 { 1207 struct dce110_clk_src *clk_src = 1208 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1209 1210 if (!clk_src) 1211 return NULL; 1212 1213 if (dcn20_clk_src_construct(clk_src, ctx, bios, id, 1214 regs, &cs_shift, &cs_mask)) { 1215 clk_src->base.dp_clk_src = dp_clk_src; 1216 return &clk_src->base; 1217 } 1218 1219 BREAK_TO_DEBUGGER(); 1220 return NULL; 1221 } 1222 1223 static struct hubp *dcn21_hubp_create( 1224 struct dc_context *ctx, 1225 uint32_t inst) 1226 { 1227 struct dcn21_hubp *hubp21 = 1228 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL); 1229 1230 if (!hubp21) 1231 return NULL; 1232 1233 if (hubp21_construct(hubp21, ctx, inst, 1234 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1235 return &hubp21->base; 1236 1237 BREAK_TO_DEBUGGER(); 1238 kfree(hubp21); 1239 return NULL; 1240 } 1241 1242 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx) 1243 { 1244 int i; 1245 1246 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), 1247 GFP_KERNEL); 1248 1249 if (!hubbub) 1250 return NULL; 1251 1252 hubbub21_construct(hubbub, ctx, 1253 &hubbub_reg, 1254 &hubbub_shift, 1255 &hubbub_mask); 1256 1257 for (i = 0; i < res_cap_rn.num_vmid; i++) { 1258 struct dcn20_vmid *vmid = &hubbub->vmid[i]; 1259 1260 vmid->ctx = ctx; 1261 1262 vmid->regs = &vmid_regs[i]; 1263 vmid->shifts = &vmid_shifts; 1264 vmid->masks = &vmid_masks; 1265 } 1266 1267 return &hubbub->base; 1268 } 1269 1270 struct output_pixel_processor *dcn21_opp_create( 1271 struct dc_context *ctx, uint32_t inst) 1272 { 1273 struct dcn20_opp *opp = 1274 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1275 1276 if (!opp) { 1277 BREAK_TO_DEBUGGER(); 1278 return NULL; 1279 } 1280 1281 dcn20_opp_construct(opp, ctx, inst, 1282 &opp_regs[inst], &opp_shift, &opp_mask); 1283 return &opp->base; 1284 } 1285 1286 struct timing_generator *dcn21_timing_generator_create( 1287 struct dc_context *ctx, 1288 uint32_t instance) 1289 { 1290 struct optc *tgn10 = 1291 kzalloc(sizeof(struct optc), GFP_KERNEL); 1292 1293 if (!tgn10) 1294 return NULL; 1295 1296 tgn10->base.inst = instance; 1297 tgn10->base.ctx = ctx; 1298 1299 tgn10->tg_regs = &tg_regs[instance]; 1300 tgn10->tg_shift = &tg_shift; 1301 tgn10->tg_mask = &tg_mask; 1302 1303 dcn20_timing_generator_init(tgn10); 1304 1305 return &tgn10->base; 1306 } 1307 1308 struct mpc *dcn21_mpc_create(struct dc_context *ctx) 1309 { 1310 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), 1311 GFP_KERNEL); 1312 1313 if (!mpc20) 1314 return NULL; 1315 1316 dcn20_mpc_construct(mpc20, ctx, 1317 &mpc_regs, 1318 &mpc_shift, 1319 &mpc_mask, 1320 6); 1321 1322 return &mpc20->base; 1323 } 1324 1325 static void read_dce_straps( 1326 struct dc_context *ctx, 1327 struct resource_straps *straps) 1328 { 1329 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1330 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1331 1332 } 1333 1334 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1335 1336 struct display_stream_compressor *dcn21_dsc_create( 1337 struct dc_context *ctx, uint32_t inst) 1338 { 1339 struct dcn20_dsc *dsc = 1340 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1341 1342 if (!dsc) { 1343 BREAK_TO_DEBUGGER(); 1344 return NULL; 1345 } 1346 1347 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1348 return &dsc->base; 1349 } 1350 #endif 1351 1352 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1353 { 1354 /* 1355 TODO: Fix this function to calcualte correct values. 1356 There are known issues with this function currently 1357 that will need to be investigated. Use hardcoded known good values for now. 1358 1359 1360 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool); 1361 struct clk_limit_table *clk_table = &bw_params->clk_table; 1362 int i; 1363 1364 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator; 1365 dcn2_1_ip.max_num_dpp = pool->base.pipe_count; 1366 dcn2_1_soc.num_chans = bw_params->num_channels; 1367 1368 for (i = 0; i < clk_table->num_entries; i++) { 1369 1370 dcn2_1_soc.clock_limits[i].state = i; 1371 dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 1372 dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 1373 dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; 1374 dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 16 / 1000; 1375 } 1376 dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i - i]; 1377 dcn2_1_soc.num_states = i; 1378 */ 1379 } 1380 1381 /* Temporary Place holder until we can get them from fuse */ 1382 static struct dpm_clocks dummy_clocks = { 1383 .DcfClocks = { 1384 {.Freq = 400, .Vol = 1}, 1385 {.Freq = 483, .Vol = 1}, 1386 {.Freq = 602, .Vol = 1}, 1387 {.Freq = 738, .Vol = 1} }, 1388 .SocClocks = { 1389 {.Freq = 300, .Vol = 1}, 1390 {.Freq = 400, .Vol = 1}, 1391 {.Freq = 400, .Vol = 1}, 1392 {.Freq = 400, .Vol = 1} }, 1393 .FClocks = { 1394 {.Freq = 400, .Vol = 1}, 1395 {.Freq = 800, .Vol = 1}, 1396 {.Freq = 1067, .Vol = 1}, 1397 {.Freq = 1600, .Vol = 1} }, 1398 .MemClocks = { 1399 {.Freq = 800, .Vol = 1}, 1400 {.Freq = 1600, .Vol = 1}, 1401 {.Freq = 1067, .Vol = 1}, 1402 {.Freq = 1600, .Vol = 1} }, 1403 1404 }; 1405 1406 static enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp, 1407 struct pp_smu_wm_range_sets *ranges) 1408 { 1409 return PP_SMU_RESULT_OK; 1410 } 1411 1412 static enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp, 1413 struct dpm_clocks *clock_table) 1414 { 1415 *clock_table = dummy_clocks; 1416 return PP_SMU_RESULT_OK; 1417 } 1418 1419 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx) 1420 { 1421 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 1422 1423 if (!pp_smu) 1424 return pp_smu; 1425 1426 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) { 1427 pp_smu->ctx.ver = PP_SMU_VER_RN; 1428 pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table; 1429 pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges; 1430 } else { 1431 1432 dm_pp_get_funcs(ctx, pp_smu); 1433 1434 if (pp_smu->ctx.ver != PP_SMU_VER_RN) 1435 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); 1436 } 1437 1438 return pp_smu; 1439 } 1440 1441 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu) 1442 { 1443 if (pp_smu && *pp_smu) { 1444 kfree(*pp_smu); 1445 *pp_smu = NULL; 1446 } 1447 } 1448 1449 static struct audio *dcn21_create_audio( 1450 struct dc_context *ctx, unsigned int inst) 1451 { 1452 return dce_audio_create(ctx, inst, 1453 &audio_regs[inst], &audio_shift, &audio_mask); 1454 } 1455 1456 static struct dc_cap_funcs cap_funcs = { 1457 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1458 }; 1459 1460 struct stream_encoder *dcn21_stream_encoder_create( 1461 enum engine_id eng_id, 1462 struct dc_context *ctx) 1463 { 1464 struct dcn10_stream_encoder *enc1 = 1465 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1466 1467 if (!enc1) 1468 return NULL; 1469 1470 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1471 &stream_enc_regs[eng_id], 1472 &se_shift, &se_mask); 1473 1474 return &enc1->base; 1475 } 1476 1477 static const struct dce_hwseq_registers hwseq_reg = { 1478 HWSEQ_DCN21_REG_LIST() 1479 }; 1480 1481 static const struct dce_hwseq_shift hwseq_shift = { 1482 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT) 1483 }; 1484 1485 static const struct dce_hwseq_mask hwseq_mask = { 1486 HWSEQ_DCN21_MASK_SH_LIST(_MASK) 1487 }; 1488 1489 static struct dce_hwseq *dcn21_hwseq_create( 1490 struct dc_context *ctx) 1491 { 1492 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1493 1494 if (hws) { 1495 hws->ctx = ctx; 1496 hws->regs = &hwseq_reg; 1497 hws->shifts = &hwseq_shift; 1498 hws->masks = &hwseq_mask; 1499 hws->wa.DEGVIDCN21 = true; 1500 } 1501 return hws; 1502 } 1503 1504 static const struct resource_create_funcs res_create_funcs = { 1505 .read_dce_straps = read_dce_straps, 1506 .create_audio = dcn21_create_audio, 1507 .create_stream_encoder = dcn21_stream_encoder_create, 1508 .create_hwseq = dcn21_hwseq_create, 1509 }; 1510 1511 static const struct resource_create_funcs res_create_maximus_funcs = { 1512 .read_dce_straps = NULL, 1513 .create_audio = NULL, 1514 .create_stream_encoder = NULL, 1515 .create_hwseq = dcn21_hwseq_create, 1516 }; 1517 1518 static const struct encoder_feature_support link_enc_feature = { 1519 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1520 .max_hdmi_pixel_clock = 600000, 1521 .hdmi_ycbcr420_supported = true, 1522 .dp_ycbcr420_supported = true, 1523 .flags.bits.IS_HBR2_CAPABLE = true, 1524 .flags.bits.IS_HBR3_CAPABLE = true, 1525 .flags.bits.IS_TPS3_CAPABLE = true, 1526 .flags.bits.IS_TPS4_CAPABLE = true 1527 }; 1528 1529 1530 #define link_regs(id, phyid)\ 1531 [id] = {\ 1532 LE_DCN10_REG_LIST(id), \ 1533 UNIPHY_DCN2_REG_LIST(phyid), \ 1534 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 1535 } 1536 1537 static const struct dcn10_link_enc_registers link_enc_regs[] = { 1538 link_regs(0, A), 1539 link_regs(1, B), 1540 link_regs(2, C), 1541 link_regs(3, D), 1542 link_regs(4, E), 1543 }; 1544 1545 #define aux_regs(id)\ 1546 [id] = {\ 1547 DCN2_AUX_REG_LIST(id)\ 1548 } 1549 1550 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 1551 aux_regs(0), 1552 aux_regs(1), 1553 aux_regs(2), 1554 aux_regs(3), 1555 aux_regs(4) 1556 }; 1557 1558 #define hpd_regs(id)\ 1559 [id] = {\ 1560 HPD_REG_LIST(id)\ 1561 } 1562 1563 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 1564 hpd_regs(0), 1565 hpd_regs(1), 1566 hpd_regs(2), 1567 hpd_regs(3), 1568 hpd_regs(4) 1569 }; 1570 1571 static const struct dcn10_link_enc_shift le_shift = { 1572 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT) 1573 }; 1574 1575 static const struct dcn10_link_enc_mask le_mask = { 1576 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK) 1577 }; 1578 1579 static int map_transmitter_id_to_phy_instance( 1580 enum transmitter transmitter) 1581 { 1582 switch (transmitter) { 1583 case TRANSMITTER_UNIPHY_A: 1584 return 0; 1585 break; 1586 case TRANSMITTER_UNIPHY_B: 1587 return 1; 1588 break; 1589 case TRANSMITTER_UNIPHY_C: 1590 return 2; 1591 break; 1592 case TRANSMITTER_UNIPHY_D: 1593 return 3; 1594 break; 1595 case TRANSMITTER_UNIPHY_E: 1596 return 4; 1597 break; 1598 default: 1599 ASSERT(0); 1600 return 0; 1601 } 1602 } 1603 1604 static struct link_encoder *dcn21_link_encoder_create( 1605 const struct encoder_init_data *enc_init_data) 1606 { 1607 struct dcn21_link_encoder *enc21 = 1608 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL); 1609 int link_regs_id; 1610 1611 if (!enc21) 1612 return NULL; 1613 1614 link_regs_id = 1615 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 1616 1617 dcn21_link_encoder_construct(enc21, 1618 enc_init_data, 1619 &link_enc_feature, 1620 &link_enc_regs[link_regs_id], 1621 &link_enc_aux_regs[enc_init_data->channel - 1], 1622 &link_enc_hpd_regs[enc_init_data->hpd_source], 1623 &le_shift, 1624 &le_mask); 1625 1626 return &enc21->enc10.base; 1627 } 1628 #define CTX ctx 1629 1630 #define REG(reg_name) \ 1631 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 1632 1633 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1634 { 1635 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 1636 /* RV1 support max 4 pipes */ 1637 value = value & 0xf; 1638 return value; 1639 } 1640 1641 static int dcn21_populate_dml_pipes_from_context( 1642 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) 1643 { 1644 uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, res_ctx, pipes); 1645 int i; 1646 1647 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1648 1649 if (!res_ctx->pipe_ctx[i].stream) 1650 continue; 1651 1652 pipes[i].pipe.src.hostvm = 1; 1653 pipes[i].pipe.src.gpuvm = 1; 1654 } 1655 1656 return pipe_cnt; 1657 } 1658 1659 static struct resource_funcs dcn21_res_pool_funcs = { 1660 .destroy = dcn21_destroy_resource_pool, 1661 .link_enc_create = dcn21_link_encoder_create, 1662 .validate_bandwidth = dcn21_validate_bandwidth, 1663 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context, 1664 .add_stream_to_ctx = dcn20_add_stream_to_ctx, 1665 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1666 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1667 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, 1668 .get_default_swizzle_mode = dcn20_get_default_swizzle_mode, 1669 .set_mcif_arb_params = dcn20_set_mcif_arb_params, 1670 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1671 .update_bw_bounding_box = update_bw_bounding_box 1672 }; 1673 1674 static bool construct( 1675 uint8_t num_virtual_links, 1676 struct dc *dc, 1677 struct dcn21_resource_pool *pool) 1678 { 1679 int i, j; 1680 struct dc_context *ctx = dc->ctx; 1681 struct irq_service_init_data init_data; 1682 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1683 uint32_t num_pipes; 1684 1685 ctx->dc_bios->regs = &bios_regs; 1686 1687 pool->base.res_cap = &res_cap_rn; 1688 #ifdef DIAGS_BUILD 1689 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1690 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc; 1691 pool->base.res_cap = &res_cap_rn_FPGA_4pipe; 1692 #endif 1693 1694 pool->base.funcs = &dcn21_res_pool_funcs; 1695 1696 /************************************************* 1697 * Resource + asic cap harcoding * 1698 *************************************************/ 1699 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1700 1701 /* max pipe num for ASIC before check pipe fuses */ 1702 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1703 1704 dc->caps.max_downscale_ratio = 200; 1705 dc->caps.i2c_speed_in_khz = 100; 1706 dc->caps.max_cursor_size = 256; 1707 dc->caps.dmdata_alloc_size = 2048; 1708 dc->caps.hw_3d_lut = true; 1709 1710 dc->caps.max_slave_planes = 1; 1711 dc->caps.post_blend_color_processing = true; 1712 dc->caps.force_dp_tps4_for_cp2520 = true; 1713 dc->caps.extended_aux_timeout_support = true; 1714 1715 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1716 dc->debug = debug_defaults_drv; 1717 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1718 pool->base.pipe_count = 4; 1719 dc->debug = debug_defaults_diags; 1720 } else 1721 dc->debug = debug_defaults_diags; 1722 1723 // Init the vm_helper 1724 if (dc->vm_helper) 1725 vm_helper_init(dc->vm_helper, 16); 1726 1727 /************************************************* 1728 * Create resources * 1729 *************************************************/ 1730 1731 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = 1732 dcn21_clock_source_create(ctx, ctx->dc_bios, 1733 CLOCK_SOURCE_COMBO_PHY_PLL0, 1734 &clk_src_regs[0], false); 1735 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = 1736 dcn21_clock_source_create(ctx, ctx->dc_bios, 1737 CLOCK_SOURCE_COMBO_PHY_PLL1, 1738 &clk_src_regs[1], false); 1739 1740 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21; 1741 1742 /* todo: not reuse phy_pll registers */ 1743 pool->base.dp_clock_source = 1744 dcn21_clock_source_create(ctx, ctx->dc_bios, 1745 CLOCK_SOURCE_ID_DP_DTO, 1746 &clk_src_regs[0], true); 1747 1748 for (i = 0; i < pool->base.clk_src_count; i++) { 1749 if (pool->base.clock_sources[i] == NULL) { 1750 dm_error("DC: failed to create clock sources!\n"); 1751 BREAK_TO_DEBUGGER(); 1752 goto create_fail; 1753 } 1754 } 1755 1756 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1757 if (pool->base.dccg == NULL) { 1758 dm_error("DC: failed to create dccg!\n"); 1759 BREAK_TO_DEBUGGER(); 1760 goto create_fail; 1761 } 1762 1763 pool->base.dmcu = dcn20_dmcu_create(ctx, 1764 &dmcu_regs, 1765 &dmcu_shift, 1766 &dmcu_mask); 1767 if (pool->base.dmcu == NULL) { 1768 dm_error("DC: failed to create dmcu!\n"); 1769 BREAK_TO_DEBUGGER(); 1770 goto create_fail; 1771 } 1772 1773 pool->base.abm = dce_abm_create(ctx, 1774 &abm_regs, 1775 &abm_shift, 1776 &abm_mask); 1777 if (pool->base.abm == NULL) { 1778 dm_error("DC: failed to create abm!\n"); 1779 BREAK_TO_DEBUGGER(); 1780 goto create_fail; 1781 } 1782 1783 #ifdef CONFIG_DRM_AMD_DC_DMUB 1784 pool->base.dmcub = dcn21_dmcub_create(ctx, 1785 &dmcub_regs, 1786 &dmcub_shift, 1787 &dmcub_mask); 1788 if (pool->base.dmcub == NULL) { 1789 dm_error("DC: failed to create dmcub!\n"); 1790 BREAK_TO_DEBUGGER(); 1791 goto create_fail; 1792 } 1793 #endif 1794 1795 pool->base.pp_smu = dcn21_pp_smu_create(ctx); 1796 1797 num_pipes = dcn2_1_ip.max_num_dpp; 1798 1799 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++) 1800 if (pipe_fuses & 1 << i) 1801 num_pipes--; 1802 dcn2_1_ip.max_num_dpp = num_pipes; 1803 dcn2_1_ip.max_num_otg = num_pipes; 1804 1805 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); 1806 1807 init_data.ctx = dc->ctx; 1808 pool->base.irqs = dal_irq_service_dcn21_create(&init_data); 1809 if (!pool->base.irqs) 1810 goto create_fail; 1811 1812 j = 0; 1813 /* mem input -> ipp -> dpp -> opp -> TG */ 1814 for (i = 0; i < pool->base.pipe_count; i++) { 1815 /* if pipe is disabled, skip instance of HW pipe, 1816 * i.e, skip ASIC register instance 1817 */ 1818 if ((pipe_fuses & (1 << i)) != 0) 1819 continue; 1820 1821 pool->base.hubps[i] = dcn21_hubp_create(ctx, i); 1822 if (pool->base.hubps[i] == NULL) { 1823 BREAK_TO_DEBUGGER(); 1824 dm_error( 1825 "DC: failed to create memory input!\n"); 1826 goto create_fail; 1827 } 1828 1829 pool->base.ipps[i] = dcn21_ipp_create(ctx, i); 1830 if (pool->base.ipps[i] == NULL) { 1831 BREAK_TO_DEBUGGER(); 1832 dm_error( 1833 "DC: failed to create input pixel processor!\n"); 1834 goto create_fail; 1835 } 1836 1837 pool->base.dpps[i] = dcn21_dpp_create(ctx, i); 1838 if (pool->base.dpps[i] == NULL) { 1839 BREAK_TO_DEBUGGER(); 1840 dm_error( 1841 "DC: failed to create dpps!\n"); 1842 goto create_fail; 1843 } 1844 1845 pool->base.opps[i] = dcn21_opp_create(ctx, i); 1846 if (pool->base.opps[i] == NULL) { 1847 BREAK_TO_DEBUGGER(); 1848 dm_error( 1849 "DC: failed to create output pixel processor!\n"); 1850 goto create_fail; 1851 } 1852 1853 pool->base.timing_generators[i] = dcn21_timing_generator_create( 1854 ctx, i); 1855 if (pool->base.timing_generators[i] == NULL) { 1856 BREAK_TO_DEBUGGER(); 1857 dm_error("DC: failed to create tg!\n"); 1858 goto create_fail; 1859 } 1860 j++; 1861 } 1862 1863 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1864 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i); 1865 if (pool->base.engines[i] == NULL) { 1866 BREAK_TO_DEBUGGER(); 1867 dm_error( 1868 "DC:failed to create aux engine!!\n"); 1869 goto create_fail; 1870 } 1871 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i); 1872 if (pool->base.hw_i2cs[i] == NULL) { 1873 BREAK_TO_DEBUGGER(); 1874 dm_error( 1875 "DC:failed to create hw i2c!!\n"); 1876 goto create_fail; 1877 } 1878 pool->base.sw_i2cs[i] = NULL; 1879 } 1880 1881 pool->base.timing_generator_count = j; 1882 pool->base.pipe_count = j; 1883 pool->base.mpcc_count = j; 1884 1885 pool->base.mpc = dcn21_mpc_create(ctx); 1886 if (pool->base.mpc == NULL) { 1887 BREAK_TO_DEBUGGER(); 1888 dm_error("DC: failed to create mpc!\n"); 1889 goto create_fail; 1890 } 1891 1892 pool->base.hubbub = dcn21_hubbub_create(ctx); 1893 if (pool->base.hubbub == NULL) { 1894 BREAK_TO_DEBUGGER(); 1895 dm_error("DC: failed to create hubbub!\n"); 1896 goto create_fail; 1897 } 1898 1899 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1900 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1901 pool->base.dscs[i] = dcn21_dsc_create(ctx, i); 1902 if (pool->base.dscs[i] == NULL) { 1903 BREAK_TO_DEBUGGER(); 1904 dm_error("DC: failed to create display stream compressor %d!\n", i); 1905 goto create_fail; 1906 } 1907 } 1908 #endif 1909 1910 if (!dcn20_dwbc_create(ctx, &pool->base)) { 1911 BREAK_TO_DEBUGGER(); 1912 dm_error("DC: failed to create dwbc!\n"); 1913 goto create_fail; 1914 } 1915 if (!dcn20_mmhubbub_create(ctx, &pool->base)) { 1916 BREAK_TO_DEBUGGER(); 1917 dm_error("DC: failed to create mcif_wb!\n"); 1918 goto create_fail; 1919 } 1920 1921 if (!resource_construct(num_virtual_links, dc, &pool->base, 1922 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1923 &res_create_funcs : &res_create_maximus_funcs))) 1924 goto create_fail; 1925 1926 dcn21_hw_sequencer_construct(dc); 1927 1928 dc->caps.max_planes = pool->base.pipe_count; 1929 1930 for (i = 0; i < dc->caps.max_planes; ++i) 1931 dc->caps.planes[i] = plane_cap; 1932 1933 dc->cap_funcs = cap_funcs; 1934 1935 return true; 1936 1937 create_fail: 1938 1939 destruct(pool); 1940 1941 return false; 1942 } 1943 1944 struct resource_pool *dcn21_create_resource_pool( 1945 const struct dc_init_data *init_data, 1946 struct dc *dc) 1947 { 1948 struct dcn21_resource_pool *pool = 1949 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL); 1950 1951 if (!pool) 1952 return NULL; 1953 1954 if (construct(init_data->num_virtual_links, dc, pool)) 1955 return &pool->base; 1956 1957 BREAK_TO_DEBUGGER(); 1958 kfree(pool); 1959 return NULL; 1960 } 1961