1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dc.h" 28 29 #include "resource.h" 30 #include "include/irq_service_interface.h" 31 #include "dcn20/dcn20_resource.h" 32 33 #include "clk_mgr.h" 34 #include "dcn10/dcn10_hubp.h" 35 #include "dcn10/dcn10_ipp.h" 36 #include "dcn20/dcn20_hubbub.h" 37 #include "dcn20/dcn20_mpc.h" 38 #include "dcn20/dcn20_hubp.h" 39 #include "dcn21_hubp.h" 40 #include "irq/dcn21/irq_service_dcn21.h" 41 #include "dcn20/dcn20_dpp.h" 42 #include "dcn20/dcn20_optc.h" 43 #include "dcn20/dcn20_hwseq.h" 44 #include "dce110/dce110_hw_sequencer.h" 45 #include "dcn20/dcn20_opp.h" 46 #include "dcn20/dcn20_dsc.h" 47 #include "dcn20/dcn20_link_encoder.h" 48 #include "dcn20/dcn20_stream_encoder.h" 49 #include "dce/dce_clock_source.h" 50 #include "dce/dce_audio.h" 51 #include "dce/dce_hwseq.h" 52 #include "virtual/virtual_stream_encoder.h" 53 #include "dce110/dce110_resource.h" 54 #include "dml/display_mode_vba.h" 55 #include "dcn20/dcn20_dccg.h" 56 #include "dcn21_hubbub.h" 57 #include "dcn10/dcn10_resource.h" 58 59 #include "dcn20/dcn20_dwb.h" 60 #include "dcn20/dcn20_mmhubbub.h" 61 62 #include "renoir_ip_offset.h" 63 #include "dcn/dcn_2_1_0_offset.h" 64 #include "dcn/dcn_2_1_0_sh_mask.h" 65 66 #include "nbio/nbio_7_0_offset.h" 67 68 #include "mmhub/mmhub_2_0_0_offset.h" 69 #include "mmhub/mmhub_2_0_0_sh_mask.h" 70 71 #include "reg_helper.h" 72 #include "dce/dce_abm.h" 73 #include "dce/dce_dmcu.h" 74 #include "dce/dce_aux.h" 75 #include "dce/dce_i2c.h" 76 #include "dcn21_resource.h" 77 #include "vm_helper.h" 78 #include "dcn20/dcn20_vmid.h" 79 80 #define SOC_BOUNDING_BOX_VALID false 81 #define DC_LOGGER_INIT(logger) 82 83 84 struct _vcs_dpi_ip_params_st dcn2_1_ip = { 85 .gpuvm_enable = 0, 86 .hostvm_enable = 0, 87 .gpuvm_max_page_table_levels = 1, 88 .hostvm_max_page_table_levels = 4, 89 .hostvm_cached_page_table_levels = 2, 90 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 91 .num_dsc = 3, 92 #else 93 .num_dsc = 0, 94 #endif 95 .rob_buffer_size_kbytes = 168, 96 .det_buffer_size_kbytes = 164, 97 .dpte_buffer_size_in_pte_reqs_luma = 44, 98 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo 99 .dpp_output_buffer_pixels = 2560, 100 .opp_output_buffer_lines = 1, 101 .pixel_chunk_size_kbytes = 8, 102 .pte_enable = 1, 103 .max_page_table_levels = 4, 104 .pte_chunk_size_kbytes = 2, 105 .meta_chunk_size_kbytes = 2, 106 .writeback_chunk_size_kbytes = 2, 107 .line_buffer_size_bits = 789504, 108 .is_line_buffer_bpp_fixed = 0, 109 .line_buffer_fixed_bpp = 0, 110 .dcc_supported = true, 111 .max_line_buffer_lines = 12, 112 .writeback_luma_buffer_size_kbytes = 12, 113 .writeback_chroma_buffer_size_kbytes = 8, 114 .writeback_chroma_line_buffer_width_pixels = 4, 115 .writeback_max_hscl_ratio = 1, 116 .writeback_max_vscl_ratio = 1, 117 .writeback_min_hscl_ratio = 1, 118 .writeback_min_vscl_ratio = 1, 119 .writeback_max_hscl_taps = 12, 120 .writeback_max_vscl_taps = 12, 121 .writeback_line_buffer_luma_buffer_size = 0, 122 .writeback_line_buffer_chroma_buffer_size = 14643, 123 .cursor_buffer_size = 8, 124 .cursor_chunk_size = 2, 125 .max_num_otg = 4, 126 .max_num_dpp = 4, 127 .max_num_wb = 1, 128 .max_dchub_pscl_bw_pix_per_clk = 4, 129 .max_pscl_lb_bw_pix_per_clk = 2, 130 .max_lb_vscl_bw_pix_per_clk = 4, 131 .max_vscl_hscl_bw_pix_per_clk = 4, 132 .max_hscl_ratio = 4, 133 .max_vscl_ratio = 4, 134 .hscl_mults = 4, 135 .vscl_mults = 4, 136 .max_hscl_taps = 8, 137 .max_vscl_taps = 8, 138 .dispclk_ramp_margin_percent = 1, 139 .underscan_factor = 1.10, 140 .min_vblank_lines = 32, // 141 .dppclk_delay_subtotal = 77, // 142 .dppclk_delay_scl_lb_only = 16, 143 .dppclk_delay_scl = 50, 144 .dppclk_delay_cnvc_formatter = 8, 145 .dppclk_delay_cnvc_cursor = 6, 146 .dispclk_delay_subtotal = 87, // 147 .dcfclk_cstate_latency = 10, // SRExitTime 148 .max_inter_dcn_tile_repeaters = 8, 149 150 .xfc_supported = false, 151 .xfc_fill_bw_overhead_percent = 10.0, 152 .xfc_fill_constant_bytes = 0, 153 .ptoi_supported = 0 154 }; 155 156 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { 157 .clock_limits = { 158 { 159 .state = 0, 160 .dcfclk_mhz = 304.0, 161 .fabricclk_mhz = 600.0, 162 .dispclk_mhz = 618.0, 163 .dppclk_mhz = 440.0, 164 .phyclk_mhz = 600.0, 165 .socclk_mhz = 278.0, 166 .dscclk_mhz = 205.67, 167 .dram_speed_mts = 1600.0, 168 }, 169 { 170 .state = 1, 171 .dcfclk_mhz = 304.0, 172 .fabricclk_mhz = 600.0, 173 .dispclk_mhz = 618.0, 174 .dppclk_mhz = 618.0, 175 .phyclk_mhz = 600.0, 176 .socclk_mhz = 278.0, 177 .dscclk_mhz = 205.67, 178 .dram_speed_mts = 1600.0, 179 }, 180 { 181 .state = 2, 182 .dcfclk_mhz = 608.0, 183 .fabricclk_mhz = 1066.0, 184 .dispclk_mhz = 888.0, 185 .dppclk_mhz = 888.0, 186 .phyclk_mhz = 810.0, 187 .socclk_mhz = 278.0, 188 .dscclk_mhz = 287.67, 189 .dram_speed_mts = 2133.0, 190 }, 191 { 192 .state = 3, 193 .dcfclk_mhz = 676.0, 194 .fabricclk_mhz = 1600.0, 195 .dispclk_mhz = 1015.0, 196 .dppclk_mhz = 1015.0, 197 .phyclk_mhz = 810.0, 198 .socclk_mhz = 715.0, 199 .dscclk_mhz = 318.334, 200 .dram_speed_mts = 4266.0, 201 }, 202 { 203 .state = 4, 204 .dcfclk_mhz = 810.0, 205 .fabricclk_mhz = 1600.0, 206 .dispclk_mhz = 1015.0, 207 .dppclk_mhz = 1015.0, 208 .phyclk_mhz = 810.0, 209 .socclk_mhz = 953.0, 210 .dscclk_mhz = 318.334, 211 .dram_speed_mts = 4266.0, 212 }, 213 /*Extra state, no dispclk ramping*/ 214 { 215 .state = 5, 216 .dcfclk_mhz = 810.0, 217 .fabricclk_mhz = 1600.0, 218 .dispclk_mhz = 1015.0, 219 .dppclk_mhz = 1015.0, 220 .phyclk_mhz = 810.0, 221 .socclk_mhz = 953.0, 222 .dscclk_mhz = 318.334, 223 .dram_speed_mts = 4266.0, 224 }, 225 226 }, 227 228 .sr_exit_time_us = 9.0, 229 .sr_enter_plus_exit_time_us = 11.0, 230 .urgent_latency_us = 4.0, 231 .urgent_latency_pixel_data_only_us = 4.0, 232 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 233 .urgent_latency_vm_data_only_us = 4.0, 234 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 235 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 236 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 237 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 238 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0, 239 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 240 .max_avg_sdp_bw_use_normal_percent = 60.0, 241 .max_avg_dram_bw_use_normal_percent = 100.0, 242 .writeback_latency_us = 12.0, 243 .max_request_size_bytes = 256, 244 .dram_channel_width_bytes = 4, 245 .fabric_datapath_to_dcn_data_return_bytes = 32, 246 .dcn_downspread_percent = 0.5, 247 .downspread_percent = 0.5, 248 .dram_page_open_time_ns = 50.0, 249 .dram_rw_turnaround_time_ns = 17.5, 250 .dram_return_buffer_per_channel_bytes = 8192, 251 .round_trip_ping_latency_dcfclk_cycles = 128, 252 .urgent_out_of_order_return_per_channel_bytes = 4096, 253 .channel_interleave_bytes = 256, 254 .num_banks = 8, 255 .num_chans = 4, 256 .vmm_page_size_bytes = 4096, 257 .dram_clock_change_latency_us = 23.84, 258 .return_bus_width_bytes = 64, 259 .dispclk_dppclk_vco_speed_mhz = 3550, 260 .xfc_bus_transport_time_us = 4, 261 .xfc_xbuf_latency_tolerance_us = 4, 262 .use_urgent_burst_bw = 1, 263 .num_states = 5 264 }; 265 266 #ifndef MAX 267 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y)) 268 #endif 269 #ifndef MIN 270 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 271 #endif 272 273 /* begin ********************* 274 * macros to expend register list macro defined in HW object header file */ 275 276 /* DCN */ 277 /* TODO awful hack. fixup dcn20_dwb.h */ 278 #undef BASE_INNER 279 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg 280 281 #define BASE(seg) BASE_INNER(seg) 282 283 #define SR(reg_name)\ 284 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 285 mm ## reg_name 286 287 #define SRI(reg_name, block, id)\ 288 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 289 mm ## block ## id ## _ ## reg_name 290 291 #define SRIR(var_name, reg_name, block, id)\ 292 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 293 mm ## block ## id ## _ ## reg_name 294 295 #define SRII(reg_name, block, id)\ 296 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 297 mm ## block ## id ## _ ## reg_name 298 299 #define DCCG_SRII(reg_name, block, id)\ 300 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 301 mm ## block ## id ## _ ## reg_name 302 303 /* NBIO */ 304 #define NBIO_BASE_INNER(seg) \ 305 NBIF0_BASE__INST0_SEG ## seg 306 307 #define NBIO_BASE(seg) \ 308 NBIO_BASE_INNER(seg) 309 310 #define NBIO_SR(reg_name)\ 311 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 312 mm ## reg_name 313 314 /* MMHUB */ 315 #define MMHUB_BASE_INNER(seg) \ 316 MMHUB_BASE__INST0_SEG ## seg 317 318 #define MMHUB_BASE(seg) \ 319 MMHUB_BASE_INNER(seg) 320 321 #define MMHUB_SR(reg_name)\ 322 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 323 mmMM ## reg_name 324 325 #define clk_src_regs(index, pllid)\ 326 [index] = {\ 327 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\ 328 } 329 330 static const struct dce110_clk_src_regs clk_src_regs[] = { 331 clk_src_regs(0, A), 332 clk_src_regs(1, B), 333 clk_src_regs(2, C), 334 clk_src_regs(3, D), 335 clk_src_regs(4, E), 336 }; 337 338 static const struct dce110_clk_src_shift cs_shift = { 339 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 340 }; 341 342 static const struct dce110_clk_src_mask cs_mask = { 343 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 344 }; 345 346 static const struct bios_registers bios_regs = { 347 NBIO_SR(BIOS_SCRATCH_3), 348 NBIO_SR(BIOS_SCRATCH_6) 349 }; 350 351 #ifdef CONFIG_DRM_AMD_DC_DMUB 352 static const struct dcn21_dmcub_registers dmcub_regs = { 353 DMCUB_REG_LIST_DCN() 354 }; 355 356 static const struct dcn21_dmcub_shift dmcub_shift = { 357 DMCUB_COMMON_MASK_SH_LIST_BASE(__SHIFT) 358 }; 359 360 static const struct dcn21_dmcub_mask dmcub_mask = { 361 DMCUB_COMMON_MASK_SH_LIST_BASE(_MASK) 362 }; 363 #endif 364 365 #define audio_regs(id)\ 366 [id] = {\ 367 AUD_COMMON_REG_LIST(id)\ 368 } 369 370 static const struct dce_audio_registers audio_regs[] = { 371 audio_regs(0), 372 audio_regs(1), 373 audio_regs(2), 374 audio_regs(3), 375 audio_regs(4), 376 audio_regs(5), 377 }; 378 379 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 380 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 381 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 382 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 383 384 static const struct dce_audio_shift audio_shift = { 385 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 386 }; 387 388 static const struct dce_audio_mask audio_mask = { 389 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 390 }; 391 392 static const struct dccg_registers dccg_regs = { 393 DCCG_COMMON_REG_LIST_DCN_BASE() 394 }; 395 396 static const struct dccg_shift dccg_shift = { 397 DCCG_MASK_SH_LIST_DCN2(__SHIFT) 398 }; 399 400 static const struct dccg_mask dccg_mask = { 401 DCCG_MASK_SH_LIST_DCN2(_MASK) 402 }; 403 404 #define opp_regs(id)\ 405 [id] = {\ 406 OPP_REG_LIST_DCN20(id),\ 407 } 408 409 static const struct dcn20_opp_registers opp_regs[] = { 410 opp_regs(0), 411 opp_regs(1), 412 opp_regs(2), 413 opp_regs(3), 414 opp_regs(4), 415 opp_regs(5), 416 }; 417 418 static const struct dcn20_opp_shift opp_shift = { 419 OPP_MASK_SH_LIST_DCN20(__SHIFT) 420 }; 421 422 static const struct dcn20_opp_mask opp_mask = { 423 OPP_MASK_SH_LIST_DCN20(_MASK) 424 }; 425 426 #define tg_regs(id)\ 427 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)} 428 429 static const struct dcn_optc_registers tg_regs[] = { 430 tg_regs(0), 431 tg_regs(1), 432 tg_regs(2), 433 tg_regs(3) 434 }; 435 436 static const struct dcn_optc_shift tg_shift = { 437 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 438 }; 439 440 static const struct dcn_optc_mask tg_mask = { 441 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 442 }; 443 444 static const struct dcn20_mpc_registers mpc_regs = { 445 MPC_REG_LIST_DCN2_0(0), 446 MPC_REG_LIST_DCN2_0(1), 447 MPC_REG_LIST_DCN2_0(2), 448 MPC_REG_LIST_DCN2_0(3), 449 MPC_REG_LIST_DCN2_0(4), 450 MPC_REG_LIST_DCN2_0(5), 451 MPC_OUT_MUX_REG_LIST_DCN2_0(0), 452 MPC_OUT_MUX_REG_LIST_DCN2_0(1), 453 MPC_OUT_MUX_REG_LIST_DCN2_0(2), 454 MPC_OUT_MUX_REG_LIST_DCN2_0(3) 455 }; 456 457 static const struct dcn20_mpc_shift mpc_shift = { 458 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 459 }; 460 461 static const struct dcn20_mpc_mask mpc_mask = { 462 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 463 }; 464 465 #define hubp_regs(id)\ 466 [id] = {\ 467 HUBP_REG_LIST_DCN21(id)\ 468 } 469 470 static const struct dcn_hubp2_registers hubp_regs[] = { 471 hubp_regs(0), 472 hubp_regs(1), 473 hubp_regs(2), 474 hubp_regs(3) 475 }; 476 477 static const struct dcn_hubp2_shift hubp_shift = { 478 HUBP_MASK_SH_LIST_DCN21(__SHIFT) 479 }; 480 481 static const struct dcn_hubp2_mask hubp_mask = { 482 HUBP_MASK_SH_LIST_DCN21(_MASK) 483 }; 484 485 static const struct dcn_hubbub_registers hubbub_reg = { 486 HUBBUB_REG_LIST_DCN21() 487 }; 488 489 static const struct dcn_hubbub_shift hubbub_shift = { 490 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT) 491 }; 492 493 static const struct dcn_hubbub_mask hubbub_mask = { 494 HUBBUB_MASK_SH_LIST_DCN21(_MASK) 495 }; 496 497 498 #define vmid_regs(id)\ 499 [id] = {\ 500 DCN20_VMID_REG_LIST(id)\ 501 } 502 503 static const struct dcn_vmid_registers vmid_regs[] = { 504 vmid_regs(0), 505 vmid_regs(1), 506 vmid_regs(2), 507 vmid_regs(3), 508 vmid_regs(4), 509 vmid_regs(5), 510 vmid_regs(6), 511 vmid_regs(7), 512 vmid_regs(8), 513 vmid_regs(9), 514 vmid_regs(10), 515 vmid_regs(11), 516 vmid_regs(12), 517 vmid_regs(13), 518 vmid_regs(14), 519 vmid_regs(15) 520 }; 521 522 static const struct dcn20_vmid_shift vmid_shifts = { 523 DCN20_VMID_MASK_SH_LIST(__SHIFT) 524 }; 525 526 static const struct dcn20_vmid_mask vmid_masks = { 527 DCN20_VMID_MASK_SH_LIST(_MASK) 528 }; 529 530 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 531 #define dsc_regsDCN20(id)\ 532 [id] = {\ 533 DSC_REG_LIST_DCN20(id)\ 534 } 535 536 static const struct dcn20_dsc_registers dsc_regs[] = { 537 dsc_regsDCN20(0), 538 dsc_regsDCN20(1), 539 dsc_regsDCN20(2), 540 dsc_regsDCN20(3), 541 dsc_regsDCN20(4), 542 dsc_regsDCN20(5) 543 }; 544 545 static const struct dcn20_dsc_shift dsc_shift = { 546 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 547 }; 548 549 static const struct dcn20_dsc_mask dsc_mask = { 550 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 551 }; 552 #endif 553 554 #define ipp_regs(id)\ 555 [id] = {\ 556 IPP_REG_LIST_DCN20(id),\ 557 } 558 559 static const struct dcn10_ipp_registers ipp_regs[] = { 560 ipp_regs(0), 561 ipp_regs(1), 562 ipp_regs(2), 563 ipp_regs(3), 564 }; 565 566 static const struct dcn10_ipp_shift ipp_shift = { 567 IPP_MASK_SH_LIST_DCN20(__SHIFT) 568 }; 569 570 static const struct dcn10_ipp_mask ipp_mask = { 571 IPP_MASK_SH_LIST_DCN20(_MASK), 572 }; 573 574 #define opp_regs(id)\ 575 [id] = {\ 576 OPP_REG_LIST_DCN20(id),\ 577 } 578 579 580 #define aux_engine_regs(id)\ 581 [id] = {\ 582 AUX_COMMON_REG_LIST0(id), \ 583 .AUXN_IMPCAL = 0, \ 584 .AUXP_IMPCAL = 0, \ 585 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 586 } 587 588 static const struct dce110_aux_registers aux_engine_regs[] = { 589 aux_engine_regs(0), 590 aux_engine_regs(1), 591 aux_engine_regs(2), 592 aux_engine_regs(3), 593 aux_engine_regs(4), 594 }; 595 596 #define tf_regs(id)\ 597 [id] = {\ 598 TF_REG_LIST_DCN20(id),\ 599 } 600 601 static const struct dcn2_dpp_registers tf_regs[] = { 602 tf_regs(0), 603 tf_regs(1), 604 tf_regs(2), 605 tf_regs(3), 606 }; 607 608 static const struct dcn2_dpp_shift tf_shift = { 609 TF_REG_LIST_SH_MASK_DCN20(__SHIFT) 610 }; 611 612 static const struct dcn2_dpp_mask tf_mask = { 613 TF_REG_LIST_SH_MASK_DCN20(_MASK) 614 }; 615 616 #define stream_enc_regs(id)\ 617 [id] = {\ 618 SE_DCN2_REG_LIST(id)\ 619 } 620 621 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 622 stream_enc_regs(0), 623 stream_enc_regs(1), 624 stream_enc_regs(2), 625 stream_enc_regs(3), 626 stream_enc_regs(4), 627 }; 628 629 static const struct dcn10_stream_encoder_shift se_shift = { 630 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) 631 }; 632 633 static const struct dcn10_stream_encoder_mask se_mask = { 634 SE_COMMON_MASK_SH_LIST_DCN20(_MASK) 635 }; 636 637 static struct input_pixel_processor *dcn21_ipp_create( 638 struct dc_context *ctx, uint32_t inst) 639 { 640 struct dcn10_ipp *ipp = 641 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 642 643 if (!ipp) { 644 BREAK_TO_DEBUGGER(); 645 return NULL; 646 } 647 648 dcn20_ipp_construct(ipp, ctx, inst, 649 &ipp_regs[inst], &ipp_shift, &ipp_mask); 650 return &ipp->base; 651 } 652 653 static struct dpp *dcn21_dpp_create( 654 struct dc_context *ctx, 655 uint32_t inst) 656 { 657 struct dcn20_dpp *dpp = 658 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL); 659 660 if (!dpp) 661 return NULL; 662 663 if (dpp2_construct(dpp, ctx, inst, 664 &tf_regs[inst], &tf_shift, &tf_mask)) 665 return &dpp->base; 666 667 BREAK_TO_DEBUGGER(); 668 kfree(dpp); 669 return NULL; 670 } 671 672 static struct dce_aux *dcn21_aux_engine_create( 673 struct dc_context *ctx, 674 uint32_t inst) 675 { 676 struct aux_engine_dce110 *aux_engine = 677 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 678 679 if (!aux_engine) 680 return NULL; 681 682 dce110_aux_engine_construct(aux_engine, ctx, inst, 683 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 684 &aux_engine_regs[inst]); 685 686 return &aux_engine->base; 687 } 688 689 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 690 691 static const struct dce_i2c_registers i2c_hw_regs[] = { 692 i2c_inst_regs(1), 693 i2c_inst_regs(2), 694 i2c_inst_regs(3), 695 i2c_inst_regs(4), 696 i2c_inst_regs(5), 697 }; 698 699 static const struct dce_i2c_shift i2c_shifts = { 700 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 701 }; 702 703 static const struct dce_i2c_mask i2c_masks = { 704 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 705 }; 706 707 struct dce_i2c_hw *dcn21_i2c_hw_create( 708 struct dc_context *ctx, 709 uint32_t inst) 710 { 711 struct dce_i2c_hw *dce_i2c_hw = 712 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 713 714 if (!dce_i2c_hw) 715 return NULL; 716 717 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 718 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 719 720 return dce_i2c_hw; 721 } 722 723 static const struct resource_caps res_cap_rn = { 724 .num_timing_generator = 4, 725 .num_opp = 4, 726 .num_video_plane = 4, 727 .num_audio = 6, // 6 audio endpoints. 4 audio streams 728 .num_stream_encoder = 5, 729 .num_pll = 5, // maybe 3 because the last two used for USB-c 730 .num_dwb = 1, 731 .num_ddc = 5, 732 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 733 .num_dsc = 3, 734 #endif 735 }; 736 737 #ifdef DIAGS_BUILD 738 static const struct resource_caps res_cap_rn_FPGA_4pipe = { 739 .num_timing_generator = 4, 740 .num_opp = 4, 741 .num_video_plane = 4, 742 .num_audio = 7, 743 .num_stream_encoder = 4, 744 .num_pll = 4, 745 .num_dwb = 1, 746 .num_ddc = 4, 747 .num_dsc = 0, 748 }; 749 750 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = { 751 .num_timing_generator = 2, 752 .num_opp = 2, 753 .num_video_plane = 2, 754 .num_audio = 7, 755 .num_stream_encoder = 2, 756 .num_pll = 4, 757 .num_dwb = 1, 758 .num_ddc = 4, 759 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 760 .num_dsc = 2, 761 #endif 762 }; 763 #endif 764 765 static const struct dc_plane_cap plane_cap = { 766 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 767 .blends_with_above = true, 768 .blends_with_below = true, 769 .per_pixel_alpha = true, 770 771 .pixel_format_support = { 772 .argb8888 = true, 773 .nv12 = true, 774 .fp16 = true 775 }, 776 777 .max_upscale_factor = { 778 .argb8888 = 16000, 779 .nv12 = 16000, 780 .fp16 = 16000 781 }, 782 783 .max_downscale_factor = { 784 .argb8888 = 250, 785 .nv12 = 250, 786 .fp16 = 250 787 } 788 }; 789 790 static const struct dc_debug_options debug_defaults_drv = { 791 .disable_dmcu = true, 792 .force_abm_enable = false, 793 .timing_trace = false, 794 .clock_trace = true, 795 .disable_pplib_clock_request = true, 796 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 797 .force_single_disp_pipe_split = true, 798 .disable_dcc = DCC_ENABLE, 799 .vsr_support = true, 800 .performance_trace = false, 801 .max_downscale_src_width = 5120,/*upto 5K*/ 802 .disable_pplib_wm_range = false, 803 .scl_reset_length10 = true, 804 .sanity_checks = true, 805 .disable_48mhz_pwrdwn = true, 806 }; 807 808 static const struct dc_debug_options debug_defaults_diags = { 809 .disable_dmcu = true, 810 .force_abm_enable = false, 811 .timing_trace = true, 812 .clock_trace = true, 813 .disable_dpp_power_gate = true, 814 .disable_hubp_power_gate = true, 815 .disable_clock_gate = true, 816 .disable_pplib_clock_request = true, 817 .disable_pplib_wm_range = true, 818 .disable_stutter = true, 819 .disable_48mhz_pwrdwn = true, 820 }; 821 822 enum dcn20_clk_src_array_id { 823 DCN20_CLK_SRC_PLL0, 824 DCN20_CLK_SRC_PLL1, 825 DCN20_CLK_SRC_TOTAL_DCN21 826 }; 827 828 static void destruct(struct dcn21_resource_pool *pool) 829 { 830 unsigned int i; 831 832 for (i = 0; i < pool->base.stream_enc_count; i++) { 833 if (pool->base.stream_enc[i] != NULL) { 834 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 835 pool->base.stream_enc[i] = NULL; 836 } 837 } 838 839 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 840 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 841 if (pool->base.dscs[i] != NULL) 842 dcn20_dsc_destroy(&pool->base.dscs[i]); 843 } 844 #endif 845 846 if (pool->base.mpc != NULL) { 847 kfree(TO_DCN20_MPC(pool->base.mpc)); 848 pool->base.mpc = NULL; 849 } 850 if (pool->base.hubbub != NULL) { 851 kfree(pool->base.hubbub); 852 pool->base.hubbub = NULL; 853 } 854 for (i = 0; i < pool->base.pipe_count; i++) { 855 if (pool->base.dpps[i] != NULL) 856 dcn20_dpp_destroy(&pool->base.dpps[i]); 857 858 if (pool->base.ipps[i] != NULL) 859 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 860 861 if (pool->base.hubps[i] != NULL) { 862 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 863 pool->base.hubps[i] = NULL; 864 } 865 866 if (pool->base.irqs != NULL) { 867 dal_irq_service_destroy(&pool->base.irqs); 868 } 869 } 870 871 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 872 if (pool->base.engines[i] != NULL) 873 dce110_engine_destroy(&pool->base.engines[i]); 874 if (pool->base.hw_i2cs[i] != NULL) { 875 kfree(pool->base.hw_i2cs[i]); 876 pool->base.hw_i2cs[i] = NULL; 877 } 878 if (pool->base.sw_i2cs[i] != NULL) { 879 kfree(pool->base.sw_i2cs[i]); 880 pool->base.sw_i2cs[i] = NULL; 881 } 882 } 883 884 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 885 if (pool->base.opps[i] != NULL) 886 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 887 } 888 889 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 890 if (pool->base.timing_generators[i] != NULL) { 891 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 892 pool->base.timing_generators[i] = NULL; 893 } 894 } 895 896 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 897 if (pool->base.dwbc[i] != NULL) { 898 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); 899 pool->base.dwbc[i] = NULL; 900 } 901 if (pool->base.mcif_wb[i] != NULL) { 902 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); 903 pool->base.mcif_wb[i] = NULL; 904 } 905 } 906 907 for (i = 0; i < pool->base.audio_count; i++) { 908 if (pool->base.audios[i]) 909 dce_aud_destroy(&pool->base.audios[i]); 910 } 911 912 for (i = 0; i < pool->base.clk_src_count; i++) { 913 if (pool->base.clock_sources[i] != NULL) { 914 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 915 pool->base.clock_sources[i] = NULL; 916 } 917 } 918 919 if (pool->base.dp_clock_source != NULL) { 920 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 921 pool->base.dp_clock_source = NULL; 922 } 923 924 925 if (pool->base.abm != NULL) 926 dce_abm_destroy(&pool->base.abm); 927 928 if (pool->base.dmcu != NULL) 929 dce_dmcu_destroy(&pool->base.dmcu); 930 931 #ifdef CONFIG_DRM_AMD_DC_DMUB 932 if (pool->base.dmcub != NULL) 933 dcn21_dmcub_destroy(&pool->base.dmcub); 934 #endif 935 936 if (pool->base.dccg != NULL) 937 dcn_dccg_destroy(&pool->base.dccg); 938 939 if (pool->base.pp_smu != NULL) 940 dcn20_pp_smu_destroy(&pool->base.pp_smu); 941 } 942 943 944 static void calculate_wm_set_for_vlevel( 945 int vlevel, 946 struct wm_range_table_entry *table_entry, 947 struct dcn_watermarks *wm_set, 948 struct display_mode_lib *dml, 949 display_e2e_pipe_params_st *pipes, 950 int pipe_cnt) 951 { 952 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; 953 954 ASSERT(vlevel < dml->soc.num_states); 955 /* only pipe 0 is read for voltage and dcf/soc clocks */ 956 pipes[0].clks_cfg.voltage = vlevel; 957 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; 958 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; 959 960 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; 961 962 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; 963 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; 964 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; 965 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 966 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; 967 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 968 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; 969 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; 970 #endif 971 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; 972 973 } 974 975 void dcn21_calculate_wm( 976 struct dc *dc, struct dc_state *context, 977 display_e2e_pipe_params_st *pipes, 978 int *out_pipe_cnt, 979 int *pipe_split_from, 980 int vlevel_req) 981 { 982 int pipe_cnt, i, pipe_idx; 983 int vlevel, vlevel_max; 984 struct wm_range_table_entry *table_entry; 985 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; 986 987 ASSERT(bw_params); 988 989 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 990 if (!context->res_ctx.pipe_ctx[i].stream) 991 continue; 992 993 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 994 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb]; 995 996 if (pipe_split_from[i] < 0) { 997 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 998 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; 999 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) 1000 pipes[pipe_cnt].pipe.dest.odm_combine = 1001 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx]; 1002 else 1003 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1004 pipe_idx++; 1005 } else { 1006 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1007 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; 1008 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) 1009 pipes[pipe_cnt].pipe.dest.odm_combine = 1010 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]]; 1011 else 1012 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1013 } 1014 pipe_cnt++; 1015 } 1016 1017 if (pipe_cnt != pipe_idx) { 1018 if (dc->res_pool->funcs->populate_dml_pipes) 1019 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, 1020 &context->res_ctx, pipes); 1021 else 1022 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, 1023 &context->res_ctx, pipes); 1024 } 1025 1026 *out_pipe_cnt = pipe_cnt; 1027 1028 vlevel_max = bw_params->clk_table.num_entries - 1; 1029 1030 1031 /* WM Set D */ 1032 table_entry = &bw_params->wm_table.entries[WM_D]; 1033 if (table_entry->wm_type == WM_TYPE_RETRAINING) 1034 vlevel = 0; 1035 else 1036 vlevel = vlevel_max; 1037 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, 1038 &context->bw_ctx.dml, pipes, pipe_cnt); 1039 /* WM Set C */ 1040 table_entry = &bw_params->wm_table.entries[WM_C]; 1041 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max); 1042 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, 1043 &context->bw_ctx.dml, pipes, pipe_cnt); 1044 /* WM Set B */ 1045 table_entry = &bw_params->wm_table.entries[WM_B]; 1046 vlevel = MIN(MAX(vlevel_req, 1), vlevel_max); 1047 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, 1048 &context->bw_ctx.dml, pipes, pipe_cnt); 1049 1050 /* WM Set A */ 1051 table_entry = &bw_params->wm_table.entries[WM_A]; 1052 vlevel = MIN(vlevel_req, vlevel_max); 1053 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, 1054 &context->bw_ctx.dml, pipes, pipe_cnt); 1055 } 1056 1057 1058 bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context, 1059 bool fast_validate) 1060 { 1061 bool out = false; 1062 1063 BW_VAL_TRACE_SETUP(); 1064 1065 int vlevel = 0; 1066 int pipe_split_from[MAX_PIPES]; 1067 int pipe_cnt = 0; 1068 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1069 DC_LOGGER_INIT(dc->ctx->logger); 1070 1071 BW_VAL_TRACE_COUNT(); 1072 1073 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel); 1074 1075 if (pipe_cnt == 0) 1076 goto validate_out; 1077 1078 if (!out) 1079 goto validate_fail; 1080 1081 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1082 1083 if (fast_validate) { 1084 BW_VAL_TRACE_SKIP(fast); 1085 goto validate_out; 1086 } 1087 1088 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel); 1089 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 1090 1091 BW_VAL_TRACE_END_WATERMARKS(); 1092 1093 goto validate_out; 1094 1095 validate_fail: 1096 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1097 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1098 1099 BW_VAL_TRACE_SKIP(fail); 1100 out = false; 1101 1102 validate_out: 1103 kfree(pipes); 1104 1105 BW_VAL_TRACE_FINISH(); 1106 1107 return out; 1108 } 1109 static void dcn21_destroy_resource_pool(struct resource_pool **pool) 1110 { 1111 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool); 1112 1113 destruct(dcn21_pool); 1114 kfree(dcn21_pool); 1115 *pool = NULL; 1116 } 1117 1118 static struct clock_source *dcn21_clock_source_create( 1119 struct dc_context *ctx, 1120 struct dc_bios *bios, 1121 enum clock_source_id id, 1122 const struct dce110_clk_src_regs *regs, 1123 bool dp_clk_src) 1124 { 1125 struct dce110_clk_src *clk_src = 1126 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1127 1128 if (!clk_src) 1129 return NULL; 1130 1131 if (dcn20_clk_src_construct(clk_src, ctx, bios, id, 1132 regs, &cs_shift, &cs_mask)) { 1133 clk_src->base.dp_clk_src = dp_clk_src; 1134 return &clk_src->base; 1135 } 1136 1137 BREAK_TO_DEBUGGER(); 1138 return NULL; 1139 } 1140 1141 static struct hubp *dcn21_hubp_create( 1142 struct dc_context *ctx, 1143 uint32_t inst) 1144 { 1145 struct dcn21_hubp *hubp21 = 1146 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL); 1147 1148 if (!hubp21) 1149 return NULL; 1150 1151 if (hubp21_construct(hubp21, ctx, inst, 1152 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1153 return &hubp21->base; 1154 1155 BREAK_TO_DEBUGGER(); 1156 kfree(hubp21); 1157 return NULL; 1158 } 1159 1160 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx) 1161 { 1162 int i; 1163 1164 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), 1165 GFP_KERNEL); 1166 1167 if (!hubbub) 1168 return NULL; 1169 1170 hubbub21_construct(hubbub, ctx, 1171 &hubbub_reg, 1172 &hubbub_shift, 1173 &hubbub_mask); 1174 1175 for (i = 0; i < res_cap_rn.num_vmid; i++) { 1176 struct dcn20_vmid *vmid = &hubbub->vmid[i]; 1177 1178 vmid->ctx = ctx; 1179 1180 vmid->regs = &vmid_regs[i]; 1181 vmid->shifts = &vmid_shifts; 1182 vmid->masks = &vmid_masks; 1183 } 1184 1185 return &hubbub->base; 1186 } 1187 1188 struct output_pixel_processor *dcn21_opp_create( 1189 struct dc_context *ctx, uint32_t inst) 1190 { 1191 struct dcn20_opp *opp = 1192 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1193 1194 if (!opp) { 1195 BREAK_TO_DEBUGGER(); 1196 return NULL; 1197 } 1198 1199 dcn20_opp_construct(opp, ctx, inst, 1200 &opp_regs[inst], &opp_shift, &opp_mask); 1201 return &opp->base; 1202 } 1203 1204 struct timing_generator *dcn21_timing_generator_create( 1205 struct dc_context *ctx, 1206 uint32_t instance) 1207 { 1208 struct optc *tgn10 = 1209 kzalloc(sizeof(struct optc), GFP_KERNEL); 1210 1211 if (!tgn10) 1212 return NULL; 1213 1214 tgn10->base.inst = instance; 1215 tgn10->base.ctx = ctx; 1216 1217 tgn10->tg_regs = &tg_regs[instance]; 1218 tgn10->tg_shift = &tg_shift; 1219 tgn10->tg_mask = &tg_mask; 1220 1221 dcn20_timing_generator_init(tgn10); 1222 1223 return &tgn10->base; 1224 } 1225 1226 struct mpc *dcn21_mpc_create(struct dc_context *ctx) 1227 { 1228 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), 1229 GFP_KERNEL); 1230 1231 if (!mpc20) 1232 return NULL; 1233 1234 dcn20_mpc_construct(mpc20, ctx, 1235 &mpc_regs, 1236 &mpc_shift, 1237 &mpc_mask, 1238 6); 1239 1240 return &mpc20->base; 1241 } 1242 1243 static void read_dce_straps( 1244 struct dc_context *ctx, 1245 struct resource_straps *straps) 1246 { 1247 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1248 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1249 1250 } 1251 1252 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1253 1254 struct display_stream_compressor *dcn21_dsc_create( 1255 struct dc_context *ctx, uint32_t inst) 1256 { 1257 struct dcn20_dsc *dsc = 1258 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1259 1260 if (!dsc) { 1261 BREAK_TO_DEBUGGER(); 1262 return NULL; 1263 } 1264 1265 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1266 return &dsc->base; 1267 } 1268 #endif 1269 1270 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1271 { 1272 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool); 1273 struct clk_limit_table *clk_table = &bw_params->clk_table; 1274 int i; 1275 1276 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator; 1277 dcn2_1_ip.max_num_dpp = pool->base.pipe_count; 1278 dcn2_1_soc.num_chans = bw_params->num_channels; 1279 dcn2_1_soc.num_states = 0; 1280 1281 for (i = 0; i < clk_table->num_entries; i++) { 1282 1283 dcn2_1_soc.clock_limits[i].state = i; 1284 dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 1285 dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 1286 dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; 1287 /* This is probably wrong, TODO: find correct calculation */ 1288 dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 16 / 1000; 1289 dcn2_1_soc.num_states++; 1290 } 1291 } 1292 1293 /* Temporary Place holder until we can get them from fuse */ 1294 static struct dpm_clocks dummy_clocks = { 1295 .DcfClocks = { 1296 {.Freq = 400, .Vol = 1}, 1297 {.Freq = 483, .Vol = 1}, 1298 {.Freq = 602, .Vol = 1}, 1299 {.Freq = 738, .Vol = 1} }, 1300 .SocClocks = { 1301 {.Freq = 300, .Vol = 1}, 1302 {.Freq = 400, .Vol = 1}, 1303 {.Freq = 400, .Vol = 1}, 1304 {.Freq = 400, .Vol = 1} }, 1305 .FClocks = { 1306 {.Freq = 400, .Vol = 1}, 1307 {.Freq = 800, .Vol = 1}, 1308 {.Freq = 1067, .Vol = 1}, 1309 {.Freq = 1600, .Vol = 1} }, 1310 .MemClocks = { 1311 {.Freq = 800, .Vol = 1}, 1312 {.Freq = 1600, .Vol = 1}, 1313 {.Freq = 1067, .Vol = 1}, 1314 {.Freq = 1600, .Vol = 1} }, 1315 1316 }; 1317 1318 enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp, 1319 struct pp_smu_wm_range_sets *ranges) 1320 { 1321 return PP_SMU_RESULT_OK; 1322 } 1323 1324 enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp, 1325 struct dpm_clocks *clock_table) 1326 { 1327 *clock_table = dummy_clocks; 1328 return PP_SMU_RESULT_OK; 1329 } 1330 1331 struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx) 1332 { 1333 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 1334 1335 pp_smu->ctx.ver = PP_SMU_VER_RN; 1336 1337 pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table; 1338 pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges; 1339 1340 return pp_smu; 1341 } 1342 1343 void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu) 1344 { 1345 if (pp_smu && *pp_smu) { 1346 kfree(*pp_smu); 1347 *pp_smu = NULL; 1348 } 1349 } 1350 1351 static struct audio *dcn21_create_audio( 1352 struct dc_context *ctx, unsigned int inst) 1353 { 1354 return dce_audio_create(ctx, inst, 1355 &audio_regs[inst], &audio_shift, &audio_mask); 1356 } 1357 1358 static struct dc_cap_funcs cap_funcs = { 1359 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1360 }; 1361 1362 struct stream_encoder *dcn21_stream_encoder_create( 1363 enum engine_id eng_id, 1364 struct dc_context *ctx) 1365 { 1366 struct dcn10_stream_encoder *enc1 = 1367 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1368 1369 if (!enc1) 1370 return NULL; 1371 1372 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1373 &stream_enc_regs[eng_id], 1374 &se_shift, &se_mask); 1375 1376 return &enc1->base; 1377 } 1378 1379 static const struct dce_hwseq_registers hwseq_reg = { 1380 HWSEQ_DCN21_REG_LIST() 1381 }; 1382 1383 static const struct dce_hwseq_shift hwseq_shift = { 1384 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT) 1385 }; 1386 1387 static const struct dce_hwseq_mask hwseq_mask = { 1388 HWSEQ_DCN21_MASK_SH_LIST(_MASK) 1389 }; 1390 1391 static struct dce_hwseq *dcn21_hwseq_create( 1392 struct dc_context *ctx) 1393 { 1394 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1395 1396 if (hws) { 1397 hws->ctx = ctx; 1398 hws->regs = &hwseq_reg; 1399 hws->shifts = &hwseq_shift; 1400 hws->masks = &hwseq_mask; 1401 } 1402 return hws; 1403 } 1404 1405 static const struct resource_create_funcs res_create_funcs = { 1406 .read_dce_straps = read_dce_straps, 1407 .create_audio = dcn21_create_audio, 1408 .create_stream_encoder = dcn21_stream_encoder_create, 1409 .create_hwseq = dcn21_hwseq_create, 1410 }; 1411 1412 static const struct resource_create_funcs res_create_maximus_funcs = { 1413 .read_dce_straps = NULL, 1414 .create_audio = NULL, 1415 .create_stream_encoder = NULL, 1416 .create_hwseq = dcn21_hwseq_create, 1417 }; 1418 1419 static struct resource_funcs dcn21_res_pool_funcs = { 1420 .destroy = dcn21_destroy_resource_pool, 1421 .link_enc_create = dcn20_link_encoder_create, 1422 .validate_bandwidth = dcn21_validate_bandwidth, 1423 .add_stream_to_ctx = dcn20_add_stream_to_ctx, 1424 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1425 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1426 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, 1427 .get_default_swizzle_mode = dcn20_get_default_swizzle_mode, 1428 .set_mcif_arb_params = dcn20_set_mcif_arb_params, 1429 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1430 .update_bw_bounding_box = update_bw_bounding_box 1431 }; 1432 1433 static bool construct( 1434 uint8_t num_virtual_links, 1435 struct dc *dc, 1436 struct dcn21_resource_pool *pool) 1437 { 1438 int i; 1439 struct dc_context *ctx = dc->ctx; 1440 struct irq_service_init_data init_data; 1441 1442 ctx->dc_bios->regs = &bios_regs; 1443 1444 pool->base.res_cap = &res_cap_rn; 1445 #ifdef DIAGS_BUILD 1446 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1447 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc; 1448 pool->base.res_cap = &res_cap_rn_FPGA_4pipe; 1449 #endif 1450 1451 pool->base.funcs = &dcn21_res_pool_funcs; 1452 1453 /************************************************* 1454 * Resource + asic cap harcoding * 1455 *************************************************/ 1456 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1457 1458 pool->base.pipe_count = 4; 1459 dc->caps.max_downscale_ratio = 200; 1460 dc->caps.i2c_speed_in_khz = 100; 1461 dc->caps.max_cursor_size = 256; 1462 dc->caps.dmdata_alloc_size = 2048; 1463 dc->caps.hw_3d_lut = true; 1464 1465 dc->caps.max_slave_planes = 1; 1466 dc->caps.post_blend_color_processing = true; 1467 dc->caps.force_dp_tps4_for_cp2520 = true; 1468 1469 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1470 dc->debug = debug_defaults_drv; 1471 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1472 pool->base.pipe_count = 4; 1473 dc->debug = debug_defaults_diags; 1474 } else 1475 dc->debug = debug_defaults_diags; 1476 1477 // Init the vm_helper 1478 if (dc->vm_helper) 1479 vm_helper_init(dc->vm_helper, 16); 1480 1481 /************************************************* 1482 * Create resources * 1483 *************************************************/ 1484 1485 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = 1486 dcn21_clock_source_create(ctx, ctx->dc_bios, 1487 CLOCK_SOURCE_COMBO_PHY_PLL0, 1488 &clk_src_regs[0], false); 1489 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = 1490 dcn21_clock_source_create(ctx, ctx->dc_bios, 1491 CLOCK_SOURCE_COMBO_PHY_PLL1, 1492 &clk_src_regs[1], false); 1493 1494 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21; 1495 1496 /* todo: not reuse phy_pll registers */ 1497 pool->base.dp_clock_source = 1498 dcn21_clock_source_create(ctx, ctx->dc_bios, 1499 CLOCK_SOURCE_ID_DP_DTO, 1500 &clk_src_regs[0], true); 1501 1502 for (i = 0; i < pool->base.clk_src_count; i++) { 1503 if (pool->base.clock_sources[i] == NULL) { 1504 dm_error("DC: failed to create clock sources!\n"); 1505 BREAK_TO_DEBUGGER(); 1506 goto create_fail; 1507 } 1508 } 1509 1510 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1511 if (pool->base.dccg == NULL) { 1512 dm_error("DC: failed to create dccg!\n"); 1513 BREAK_TO_DEBUGGER(); 1514 goto create_fail; 1515 } 1516 1517 #ifdef CONFIG_DRM_AMD_DC_DMUB 1518 pool->base.dmcub = dcn21_dmcub_create(ctx, 1519 &dmcub_regs, 1520 &dmcub_shift, 1521 &dmcub_mask); 1522 if (pool->base.dmcub == NULL) { 1523 dm_error("DC: failed to create dmcub!\n"); 1524 BREAK_TO_DEBUGGER(); 1525 goto create_fail; 1526 } 1527 #endif 1528 1529 pool->base.pp_smu = dcn21_pp_smu_create(ctx); 1530 1531 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); 1532 1533 init_data.ctx = dc->ctx; 1534 pool->base.irqs = dal_irq_service_dcn21_create(&init_data); 1535 if (!pool->base.irqs) 1536 goto create_fail; 1537 1538 /* mem input -> ipp -> dpp -> opp -> TG */ 1539 for (i = 0; i < pool->base.pipe_count; i++) { 1540 pool->base.hubps[i] = dcn21_hubp_create(ctx, i); 1541 if (pool->base.hubps[i] == NULL) { 1542 BREAK_TO_DEBUGGER(); 1543 dm_error( 1544 "DC: failed to create memory input!\n"); 1545 goto create_fail; 1546 } 1547 1548 pool->base.ipps[i] = dcn21_ipp_create(ctx, i); 1549 if (pool->base.ipps[i] == NULL) { 1550 BREAK_TO_DEBUGGER(); 1551 dm_error( 1552 "DC: failed to create input pixel processor!\n"); 1553 goto create_fail; 1554 } 1555 1556 pool->base.dpps[i] = dcn21_dpp_create(ctx, i); 1557 if (pool->base.dpps[i] == NULL) { 1558 BREAK_TO_DEBUGGER(); 1559 dm_error( 1560 "DC: failed to create dpps!\n"); 1561 goto create_fail; 1562 } 1563 } 1564 1565 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1566 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i); 1567 if (pool->base.engines[i] == NULL) { 1568 BREAK_TO_DEBUGGER(); 1569 dm_error( 1570 "DC:failed to create aux engine!!\n"); 1571 goto create_fail; 1572 } 1573 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i); 1574 if (pool->base.hw_i2cs[i] == NULL) { 1575 BREAK_TO_DEBUGGER(); 1576 dm_error( 1577 "DC:failed to create hw i2c!!\n"); 1578 goto create_fail; 1579 } 1580 pool->base.sw_i2cs[i] = NULL; 1581 } 1582 1583 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1584 pool->base.opps[i] = dcn21_opp_create(ctx, i); 1585 if (pool->base.opps[i] == NULL) { 1586 BREAK_TO_DEBUGGER(); 1587 dm_error( 1588 "DC: failed to create output pixel processor!\n"); 1589 goto create_fail; 1590 } 1591 } 1592 1593 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1594 pool->base.timing_generators[i] = dcn21_timing_generator_create( 1595 ctx, i); 1596 if (pool->base.timing_generators[i] == NULL) { 1597 BREAK_TO_DEBUGGER(); 1598 dm_error("DC: failed to create tg!\n"); 1599 goto create_fail; 1600 } 1601 } 1602 1603 pool->base.timing_generator_count = i; 1604 1605 pool->base.mpc = dcn21_mpc_create(ctx); 1606 if (pool->base.mpc == NULL) { 1607 BREAK_TO_DEBUGGER(); 1608 dm_error("DC: failed to create mpc!\n"); 1609 goto create_fail; 1610 } 1611 1612 pool->base.hubbub = dcn21_hubbub_create(ctx); 1613 if (pool->base.hubbub == NULL) { 1614 BREAK_TO_DEBUGGER(); 1615 dm_error("DC: failed to create hubbub!\n"); 1616 goto create_fail; 1617 } 1618 1619 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1620 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1621 pool->base.dscs[i] = dcn21_dsc_create(ctx, i); 1622 if (pool->base.dscs[i] == NULL) { 1623 BREAK_TO_DEBUGGER(); 1624 dm_error("DC: failed to create display stream compressor %d!\n", i); 1625 goto create_fail; 1626 } 1627 } 1628 #endif 1629 1630 if (!dcn20_dwbc_create(ctx, &pool->base)) { 1631 BREAK_TO_DEBUGGER(); 1632 dm_error("DC: failed to create dwbc!\n"); 1633 goto create_fail; 1634 } 1635 if (!dcn20_mmhubbub_create(ctx, &pool->base)) { 1636 BREAK_TO_DEBUGGER(); 1637 dm_error("DC: failed to create mcif_wb!\n"); 1638 goto create_fail; 1639 } 1640 1641 if (!resource_construct(num_virtual_links, dc, &pool->base, 1642 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1643 &res_create_funcs : &res_create_maximus_funcs))) 1644 goto create_fail; 1645 1646 dcn20_hw_sequencer_construct(dc); 1647 1648 dc->caps.max_planes = pool->base.pipe_count; 1649 1650 for (i = 0; i < dc->caps.max_planes; ++i) 1651 dc->caps.planes[i] = plane_cap; 1652 1653 dc->cap_funcs = cap_funcs; 1654 1655 return true; 1656 1657 create_fail: 1658 1659 destruct(pool); 1660 1661 return false; 1662 } 1663 1664 struct resource_pool *dcn21_create_resource_pool( 1665 const struct dc_init_data *init_data, 1666 struct dc *dc) 1667 { 1668 struct dcn21_resource_pool *pool = 1669 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL); 1670 1671 if (!pool) 1672 return NULL; 1673 1674 if (construct(init_data->num_virtual_links, dc, pool)) 1675 return &pool->base; 1676 1677 BREAK_TO_DEBUGGER(); 1678 kfree(pool); 1679 return NULL; 1680 } 1681