1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3  * Copyright 2019 Raptor Engineering, LLC
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 
27 #include <linux/slab.h>
28 
29 #include "dm_services.h"
30 #include "dc.h"
31 
32 #include "dcn21_init.h"
33 
34 #include "resource.h"
35 #include "include/irq_service_interface.h"
36 #include "dcn20/dcn20_resource.h"
37 #include "dcn21/dcn21_resource.h"
38 
39 #include "dml/dcn20/dcn20_fpu.h"
40 
41 #include "clk_mgr.h"
42 #include "dcn10/dcn10_hubp.h"
43 #include "dcn10/dcn10_ipp.h"
44 #include "dcn20/dcn20_hubbub.h"
45 #include "dcn20/dcn20_mpc.h"
46 #include "dcn20/dcn20_hubp.h"
47 #include "dcn21_hubp.h"
48 #include "irq/dcn21/irq_service_dcn21.h"
49 #include "dcn20/dcn20_dpp.h"
50 #include "dcn20/dcn20_optc.h"
51 #include "dcn21/dcn21_hwseq.h"
52 #include "dce110/dce110_hw_sequencer.h"
53 #include "dcn20/dcn20_opp.h"
54 #include "dcn20/dcn20_dsc.h"
55 #include "dcn21/dcn21_link_encoder.h"
56 #include "dcn20/dcn20_stream_encoder.h"
57 #include "dce/dce_clock_source.h"
58 #include "dce/dce_audio.h"
59 #include "dce/dce_hwseq.h"
60 #include "virtual/virtual_stream_encoder.h"
61 #include "dml/display_mode_vba.h"
62 #include "dcn20/dcn20_dccg.h"
63 #include "dcn21/dcn21_dccg.h"
64 #include "dcn21_hubbub.h"
65 #include "dcn10/dcn10_resource.h"
66 #include "dce/dce_panel_cntl.h"
67 
68 #include "dcn20/dcn20_dwb.h"
69 #include "dcn20/dcn20_mmhubbub.h"
70 #include "dpcs/dpcs_2_1_0_offset.h"
71 #include "dpcs/dpcs_2_1_0_sh_mask.h"
72 
73 #include "renoir_ip_offset.h"
74 #include "dcn/dcn_2_1_0_offset.h"
75 #include "dcn/dcn_2_1_0_sh_mask.h"
76 
77 #include "nbio/nbio_7_0_offset.h"
78 
79 #include "mmhub/mmhub_2_0_0_offset.h"
80 #include "mmhub/mmhub_2_0_0_sh_mask.h"
81 
82 #include "reg_helper.h"
83 #include "dce/dce_abm.h"
84 #include "dce/dce_dmcu.h"
85 #include "dce/dce_aux.h"
86 #include "dce/dce_i2c.h"
87 #include "dcn21_resource.h"
88 #include "vm_helper.h"
89 #include "dcn20/dcn20_vmid.h"
90 #include "dce/dmub_psr.h"
91 #include "dce/dmub_abm.h"
92 
93 /* begin *********************
94  * macros to expend register list macro defined in HW object header file */
95 
96 /* DCN */
97 /* TODO awful hack. fixup dcn20_dwb.h */
98 #undef BASE_INNER
99 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
100 
101 #define BASE(seg) BASE_INNER(seg)
102 
103 #define SR(reg_name)\
104 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
105 					mm ## reg_name
106 
107 #define SRI(reg_name, block, id)\
108 	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
109 					mm ## block ## id ## _ ## reg_name
110 
111 #define SRIR(var_name, reg_name, block, id)\
112 	.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
113 					mm ## block ## id ## _ ## reg_name
114 
115 #define SRII(reg_name, block, id)\
116 	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
117 					mm ## block ## id ## _ ## reg_name
118 
119 #define DCCG_SRII(reg_name, block, id)\
120 	.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
121 					mm ## block ## id ## _ ## reg_name
122 
123 #define VUPDATE_SRII(reg_name, block, id)\
124 	.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
125 					mm ## reg_name ## _ ## block ## id
126 
127 /* NBIO */
128 #define NBIO_BASE_INNER(seg) \
129 	NBIF0_BASE__INST0_SEG ## seg
130 
131 #define NBIO_BASE(seg) \
132 	NBIO_BASE_INNER(seg)
133 
134 #define NBIO_SR(reg_name)\
135 		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
136 					mm ## reg_name
137 
138 /* MMHUB */
139 #define MMHUB_BASE_INNER(seg) \
140 	MMHUB_BASE__INST0_SEG ## seg
141 
142 #define MMHUB_BASE(seg) \
143 	MMHUB_BASE_INNER(seg)
144 
145 #define MMHUB_SR(reg_name)\
146 		.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
147 					mmMM ## reg_name
148 
149 #define clk_src_regs(index, pllid)\
150 [index] = {\
151 	CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
152 }
153 
154 static const struct dce110_clk_src_regs clk_src_regs[] = {
155 	clk_src_regs(0, A),
156 	clk_src_regs(1, B),
157 	clk_src_regs(2, C),
158 	clk_src_regs(3, D),
159 	clk_src_regs(4, E),
160 };
161 
162 static const struct dce110_clk_src_shift cs_shift = {
163 		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
164 };
165 
166 static const struct dce110_clk_src_mask cs_mask = {
167 		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
168 };
169 
170 static const struct bios_registers bios_regs = {
171 		NBIO_SR(BIOS_SCRATCH_3),
172 		NBIO_SR(BIOS_SCRATCH_6)
173 };
174 
175 static const struct dce_dmcu_registers dmcu_regs = {
176 		DMCU_DCN20_REG_LIST()
177 };
178 
179 static const struct dce_dmcu_shift dmcu_shift = {
180 		DMCU_MASK_SH_LIST_DCN10(__SHIFT)
181 };
182 
183 static const struct dce_dmcu_mask dmcu_mask = {
184 		DMCU_MASK_SH_LIST_DCN10(_MASK)
185 };
186 
187 static const struct dce_abm_registers abm_regs = {
188 		ABM_DCN20_REG_LIST()
189 };
190 
191 static const struct dce_abm_shift abm_shift = {
192 		ABM_MASK_SH_LIST_DCN20(__SHIFT)
193 };
194 
195 static const struct dce_abm_mask abm_mask = {
196 		ABM_MASK_SH_LIST_DCN20(_MASK)
197 };
198 
199 #define audio_regs(id)\
200 [id] = {\
201 		AUD_COMMON_REG_LIST(id)\
202 }
203 
204 static const struct dce_audio_registers audio_regs[] = {
205 	audio_regs(0),
206 	audio_regs(1),
207 	audio_regs(2),
208 	audio_regs(3),
209 	audio_regs(4),
210 	audio_regs(5),
211 };
212 
213 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
214 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
215 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
216 		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
217 
218 static const struct dce_audio_shift audio_shift = {
219 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
220 };
221 
222 static const struct dce_audio_mask audio_mask = {
223 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
224 };
225 
226 static const struct dccg_registers dccg_regs = {
227 		DCCG_COMMON_REG_LIST_DCN_BASE()
228 };
229 
230 static const struct dccg_shift dccg_shift = {
231 		DCCG_MASK_SH_LIST_DCN2_1(__SHIFT)
232 };
233 
234 static const struct dccg_mask dccg_mask = {
235 		DCCG_MASK_SH_LIST_DCN2_1(_MASK)
236 };
237 
238 #define opp_regs(id)\
239 [id] = {\
240 	OPP_REG_LIST_DCN20(id),\
241 }
242 
243 static const struct dcn20_opp_registers opp_regs[] = {
244 	opp_regs(0),
245 	opp_regs(1),
246 	opp_regs(2),
247 	opp_regs(3),
248 	opp_regs(4),
249 	opp_regs(5),
250 };
251 
252 static const struct dcn20_opp_shift opp_shift = {
253 		OPP_MASK_SH_LIST_DCN20(__SHIFT)
254 };
255 
256 static const struct dcn20_opp_mask opp_mask = {
257 		OPP_MASK_SH_LIST_DCN20(_MASK)
258 };
259 
260 #define tg_regs(id)\
261 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
262 
263 static const struct dcn_optc_registers tg_regs[] = {
264 	tg_regs(0),
265 	tg_regs(1),
266 	tg_regs(2),
267 	tg_regs(3)
268 };
269 
270 static const struct dcn_optc_shift tg_shift = {
271 	TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
272 };
273 
274 static const struct dcn_optc_mask tg_mask = {
275 	TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
276 };
277 
278 static const struct dcn20_mpc_registers mpc_regs = {
279 		MPC_REG_LIST_DCN2_0(0),
280 		MPC_REG_LIST_DCN2_0(1),
281 		MPC_REG_LIST_DCN2_0(2),
282 		MPC_REG_LIST_DCN2_0(3),
283 		MPC_REG_LIST_DCN2_0(4),
284 		MPC_REG_LIST_DCN2_0(5),
285 		MPC_OUT_MUX_REG_LIST_DCN2_0(0),
286 		MPC_OUT_MUX_REG_LIST_DCN2_0(1),
287 		MPC_OUT_MUX_REG_LIST_DCN2_0(2),
288 		MPC_OUT_MUX_REG_LIST_DCN2_0(3),
289 		MPC_DBG_REG_LIST_DCN2_0()
290 };
291 
292 static const struct dcn20_mpc_shift mpc_shift = {
293 	MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
294 	MPC_DEBUG_REG_LIST_SH_DCN20
295 };
296 
297 static const struct dcn20_mpc_mask mpc_mask = {
298 	MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
299 	MPC_DEBUG_REG_LIST_MASK_DCN20
300 };
301 
302 #define hubp_regs(id)\
303 [id] = {\
304 	HUBP_REG_LIST_DCN21(id)\
305 }
306 
307 static const struct dcn_hubp2_registers hubp_regs[] = {
308 		hubp_regs(0),
309 		hubp_regs(1),
310 		hubp_regs(2),
311 		hubp_regs(3)
312 };
313 
314 static const struct dcn_hubp2_shift hubp_shift = {
315 		HUBP_MASK_SH_LIST_DCN21(__SHIFT)
316 };
317 
318 static const struct dcn_hubp2_mask hubp_mask = {
319 		HUBP_MASK_SH_LIST_DCN21(_MASK)
320 };
321 
322 static const struct dcn_hubbub_registers hubbub_reg = {
323 		HUBBUB_REG_LIST_DCN21()
324 };
325 
326 static const struct dcn_hubbub_shift hubbub_shift = {
327 		HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
328 };
329 
330 static const struct dcn_hubbub_mask hubbub_mask = {
331 		HUBBUB_MASK_SH_LIST_DCN21(_MASK)
332 };
333 
334 
335 #define vmid_regs(id)\
336 [id] = {\
337 		DCN20_VMID_REG_LIST(id)\
338 }
339 
340 static const struct dcn_vmid_registers vmid_regs[] = {
341 	vmid_regs(0),
342 	vmid_regs(1),
343 	vmid_regs(2),
344 	vmid_regs(3),
345 	vmid_regs(4),
346 	vmid_regs(5),
347 	vmid_regs(6),
348 	vmid_regs(7),
349 	vmid_regs(8),
350 	vmid_regs(9),
351 	vmid_regs(10),
352 	vmid_regs(11),
353 	vmid_regs(12),
354 	vmid_regs(13),
355 	vmid_regs(14),
356 	vmid_regs(15)
357 };
358 
359 static const struct dcn20_vmid_shift vmid_shifts = {
360 		DCN20_VMID_MASK_SH_LIST(__SHIFT)
361 };
362 
363 static const struct dcn20_vmid_mask vmid_masks = {
364 		DCN20_VMID_MASK_SH_LIST(_MASK)
365 };
366 
367 #define dsc_regsDCN20(id)\
368 [id] = {\
369 	DSC_REG_LIST_DCN20(id)\
370 }
371 
372 static const struct dcn20_dsc_registers dsc_regs[] = {
373 	dsc_regsDCN20(0),
374 	dsc_regsDCN20(1),
375 	dsc_regsDCN20(2),
376 	dsc_regsDCN20(3),
377 	dsc_regsDCN20(4),
378 	dsc_regsDCN20(5)
379 };
380 
381 static const struct dcn20_dsc_shift dsc_shift = {
382 	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
383 };
384 
385 static const struct dcn20_dsc_mask dsc_mask = {
386 	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
387 };
388 
389 #define ipp_regs(id)\
390 [id] = {\
391 	IPP_REG_LIST_DCN20(id),\
392 }
393 
394 static const struct dcn10_ipp_registers ipp_regs[] = {
395 	ipp_regs(0),
396 	ipp_regs(1),
397 	ipp_regs(2),
398 	ipp_regs(3),
399 };
400 
401 static const struct dcn10_ipp_shift ipp_shift = {
402 		IPP_MASK_SH_LIST_DCN20(__SHIFT)
403 };
404 
405 static const struct dcn10_ipp_mask ipp_mask = {
406 		IPP_MASK_SH_LIST_DCN20(_MASK),
407 };
408 
409 #define opp_regs(id)\
410 [id] = {\
411 	OPP_REG_LIST_DCN20(id),\
412 }
413 
414 
415 #define aux_engine_regs(id)\
416 [id] = {\
417 	AUX_COMMON_REG_LIST0(id), \
418 	.AUXN_IMPCAL = 0, \
419 	.AUXP_IMPCAL = 0, \
420 	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
421 }
422 
423 static const struct dce110_aux_registers aux_engine_regs[] = {
424 		aux_engine_regs(0),
425 		aux_engine_regs(1),
426 		aux_engine_regs(2),
427 		aux_engine_regs(3),
428 		aux_engine_regs(4),
429 };
430 
431 #define tf_regs(id)\
432 [id] = {\
433 	TF_REG_LIST_DCN20(id),\
434 	TF_REG_LIST_DCN20_COMMON_APPEND(id),\
435 }
436 
437 static const struct dcn2_dpp_registers tf_regs[] = {
438 	tf_regs(0),
439 	tf_regs(1),
440 	tf_regs(2),
441 	tf_regs(3),
442 };
443 
444 static const struct dcn2_dpp_shift tf_shift = {
445 		TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
446 		TF_DEBUG_REG_LIST_SH_DCN20
447 };
448 
449 static const struct dcn2_dpp_mask tf_mask = {
450 		TF_REG_LIST_SH_MASK_DCN20(_MASK),
451 		TF_DEBUG_REG_LIST_MASK_DCN20
452 };
453 
454 #define stream_enc_regs(id)\
455 [id] = {\
456 	SE_DCN2_REG_LIST(id)\
457 }
458 
459 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
460 	stream_enc_regs(0),
461 	stream_enc_regs(1),
462 	stream_enc_regs(2),
463 	stream_enc_regs(3),
464 	stream_enc_regs(4),
465 };
466 
467 static const struct dce110_aux_registers_shift aux_shift = {
468 	DCN_AUX_MASK_SH_LIST(__SHIFT)
469 };
470 
471 static const struct dce110_aux_registers_mask aux_mask = {
472 	DCN_AUX_MASK_SH_LIST(_MASK)
473 };
474 
475 static const struct dcn10_stream_encoder_shift se_shift = {
476 		SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
477 };
478 
479 static const struct dcn10_stream_encoder_mask se_mask = {
480 		SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
481 };
482 
483 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
484 
485 static struct input_pixel_processor *dcn21_ipp_create(
486 	struct dc_context *ctx, uint32_t inst)
487 {
488 	struct dcn10_ipp *ipp =
489 		kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
490 
491 	if (!ipp) {
492 		BREAK_TO_DEBUGGER();
493 		return NULL;
494 	}
495 
496 	dcn20_ipp_construct(ipp, ctx, inst,
497 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
498 	return &ipp->base;
499 }
500 
501 static struct dpp *dcn21_dpp_create(
502 	struct dc_context *ctx,
503 	uint32_t inst)
504 {
505 	struct dcn20_dpp *dpp =
506 		kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
507 
508 	if (!dpp)
509 		return NULL;
510 
511 	if (dpp2_construct(dpp, ctx, inst,
512 			&tf_regs[inst], &tf_shift, &tf_mask))
513 		return &dpp->base;
514 
515 	BREAK_TO_DEBUGGER();
516 	kfree(dpp);
517 	return NULL;
518 }
519 
520 static struct dce_aux *dcn21_aux_engine_create(
521 	struct dc_context *ctx,
522 	uint32_t inst)
523 {
524 	struct aux_engine_dce110 *aux_engine =
525 		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
526 
527 	if (!aux_engine)
528 		return NULL;
529 
530 	dce110_aux_engine_construct(aux_engine, ctx, inst,
531 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
532 				    &aux_engine_regs[inst],
533 					&aux_mask,
534 					&aux_shift,
535 					ctx->dc->caps.extended_aux_timeout_support);
536 
537 	return &aux_engine->base;
538 }
539 
540 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
541 
542 static const struct dce_i2c_registers i2c_hw_regs[] = {
543 		i2c_inst_regs(1),
544 		i2c_inst_regs(2),
545 		i2c_inst_regs(3),
546 		i2c_inst_regs(4),
547 		i2c_inst_regs(5),
548 };
549 
550 static const struct dce_i2c_shift i2c_shifts = {
551 		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
552 };
553 
554 static const struct dce_i2c_mask i2c_masks = {
555 		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
556 };
557 
558 static struct dce_i2c_hw *dcn21_i2c_hw_create(struct dc_context *ctx,
559 					      uint32_t inst)
560 {
561 	struct dce_i2c_hw *dce_i2c_hw =
562 		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
563 
564 	if (!dce_i2c_hw)
565 		return NULL;
566 
567 	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
568 				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
569 
570 	return dce_i2c_hw;
571 }
572 
573 static const struct resource_caps res_cap_rn = {
574 		.num_timing_generator = 4,
575 		.num_opp = 4,
576 		.num_video_plane = 4,
577 		.num_audio = 4, // 4 audio endpoints.  4 audio streams
578 		.num_stream_encoder = 5,
579 		.num_pll = 5,  // maybe 3 because the last two used for USB-c
580 		.num_dwb = 1,
581 		.num_ddc = 5,
582 		.num_vmid = 16,
583 		.num_dsc = 3,
584 };
585 
586 #ifdef DIAGS_BUILD
587 static const struct resource_caps res_cap_rn_FPGA_4pipe = {
588 		.num_timing_generator = 4,
589 		.num_opp = 4,
590 		.num_video_plane = 4,
591 		.num_audio = 7,
592 		.num_stream_encoder = 4,
593 		.num_pll = 4,
594 		.num_dwb = 1,
595 		.num_ddc = 4,
596 		.num_dsc = 0,
597 };
598 
599 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
600 		.num_timing_generator = 2,
601 		.num_opp = 2,
602 		.num_video_plane = 2,
603 		.num_audio = 7,
604 		.num_stream_encoder = 2,
605 		.num_pll = 4,
606 		.num_dwb = 1,
607 		.num_ddc = 4,
608 		.num_dsc = 2,
609 };
610 #endif
611 
612 static const struct dc_plane_cap plane_cap = {
613 	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
614 	.blends_with_above = true,
615 	.blends_with_below = true,
616 	.per_pixel_alpha = true,
617 
618 	.pixel_format_support = {
619 			.argb8888 = true,
620 			.nv12 = true,
621 			.fp16 = true,
622 			.p010 = true
623 	},
624 
625 	.max_upscale_factor = {
626 			.argb8888 = 16000,
627 			.nv12 = 16000,
628 			.fp16 = 16000
629 	},
630 
631 	.max_downscale_factor = {
632 			.argb8888 = 250,
633 			.nv12 = 250,
634 			.fp16 = 250
635 	},
636 	64,
637 	64
638 };
639 
640 static const struct dc_debug_options debug_defaults_drv = {
641 		.disable_dmcu = false,
642 		.force_abm_enable = false,
643 		.timing_trace = false,
644 		.clock_trace = true,
645 		.disable_pplib_clock_request = true,
646 		.min_disp_clk_khz = 100000,
647 		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
648 		.force_single_disp_pipe_split = false,
649 		.disable_dcc = DCC_ENABLE,
650 		.vsr_support = true,
651 		.performance_trace = false,
652 		.max_downscale_src_width = 4096,
653 		.disable_pplib_wm_range = false,
654 		.scl_reset_length10 = true,
655 		.sanity_checks = true,
656 		.disable_48mhz_pwrdwn = false,
657 		.usbc_combo_phy_reset_wa = true,
658 		.dmub_command_table = true,
659 		.use_max_lb = true,
660 		.optimize_edp_link_rate = true
661 };
662 
663 static const struct dc_debug_options debug_defaults_diags = {
664 		.disable_dmcu = false,
665 		.force_abm_enable = false,
666 		.timing_trace = true,
667 		.clock_trace = true,
668 		.disable_dpp_power_gate = true,
669 		.disable_hubp_power_gate = true,
670 		.disable_clock_gate = true,
671 		.disable_pplib_clock_request = true,
672 		.disable_pplib_wm_range = true,
673 		.disable_stutter = true,
674 		.disable_48mhz_pwrdwn = true,
675 		.disable_psr = true,
676 		.enable_tri_buf = true,
677 		.use_max_lb = true
678 };
679 
680 enum dcn20_clk_src_array_id {
681 	DCN20_CLK_SRC_PLL0,
682 	DCN20_CLK_SRC_PLL1,
683 	DCN20_CLK_SRC_PLL2,
684 	DCN20_CLK_SRC_PLL3,
685 	DCN20_CLK_SRC_PLL4,
686 	DCN20_CLK_SRC_TOTAL_DCN21
687 };
688 
689 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
690 {
691 	unsigned int i;
692 
693 	for (i = 0; i < pool->base.stream_enc_count; i++) {
694 		if (pool->base.stream_enc[i] != NULL) {
695 			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
696 			pool->base.stream_enc[i] = NULL;
697 		}
698 	}
699 
700 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
701 		if (pool->base.dscs[i] != NULL)
702 			dcn20_dsc_destroy(&pool->base.dscs[i]);
703 	}
704 
705 	if (pool->base.mpc != NULL) {
706 		kfree(TO_DCN20_MPC(pool->base.mpc));
707 		pool->base.mpc = NULL;
708 	}
709 	if (pool->base.hubbub != NULL) {
710 		kfree(pool->base.hubbub);
711 		pool->base.hubbub = NULL;
712 	}
713 	for (i = 0; i < pool->base.pipe_count; i++) {
714 		if (pool->base.dpps[i] != NULL)
715 			dcn20_dpp_destroy(&pool->base.dpps[i]);
716 
717 		if (pool->base.ipps[i] != NULL)
718 			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
719 
720 		if (pool->base.hubps[i] != NULL) {
721 			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
722 			pool->base.hubps[i] = NULL;
723 		}
724 
725 		if (pool->base.irqs != NULL) {
726 			dal_irq_service_destroy(&pool->base.irqs);
727 		}
728 	}
729 
730 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
731 		if (pool->base.engines[i] != NULL)
732 			dce110_engine_destroy(&pool->base.engines[i]);
733 		if (pool->base.hw_i2cs[i] != NULL) {
734 			kfree(pool->base.hw_i2cs[i]);
735 			pool->base.hw_i2cs[i] = NULL;
736 		}
737 		if (pool->base.sw_i2cs[i] != NULL) {
738 			kfree(pool->base.sw_i2cs[i]);
739 			pool->base.sw_i2cs[i] = NULL;
740 		}
741 	}
742 
743 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
744 		if (pool->base.opps[i] != NULL)
745 			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
746 	}
747 
748 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
749 		if (pool->base.timing_generators[i] != NULL)	{
750 			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
751 			pool->base.timing_generators[i] = NULL;
752 		}
753 	}
754 
755 	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
756 		if (pool->base.dwbc[i] != NULL) {
757 			kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
758 			pool->base.dwbc[i] = NULL;
759 		}
760 		if (pool->base.mcif_wb[i] != NULL) {
761 			kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
762 			pool->base.mcif_wb[i] = NULL;
763 		}
764 	}
765 
766 	for (i = 0; i < pool->base.audio_count; i++) {
767 		if (pool->base.audios[i])
768 			dce_aud_destroy(&pool->base.audios[i]);
769 	}
770 
771 	for (i = 0; i < pool->base.clk_src_count; i++) {
772 		if (pool->base.clock_sources[i] != NULL) {
773 			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
774 			pool->base.clock_sources[i] = NULL;
775 		}
776 	}
777 
778 	if (pool->base.dp_clock_source != NULL) {
779 		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
780 		pool->base.dp_clock_source = NULL;
781 	}
782 
783 	if (pool->base.abm != NULL) {
784 		if (pool->base.abm->ctx->dc->config.disable_dmcu)
785 			dmub_abm_destroy(&pool->base.abm);
786 		else
787 			dce_abm_destroy(&pool->base.abm);
788 	}
789 
790 	if (pool->base.dmcu != NULL)
791 		dce_dmcu_destroy(&pool->base.dmcu);
792 
793 	if (pool->base.psr != NULL)
794 		dmub_psr_destroy(&pool->base.psr);
795 
796 	if (pool->base.dccg != NULL)
797 		dcn_dccg_destroy(&pool->base.dccg);
798 
799 	if (pool->base.pp_smu != NULL)
800 		dcn21_pp_smu_destroy(&pool->base.pp_smu);
801 }
802 
803 bool dcn21_fast_validate_bw(struct dc *dc,
804 			    struct dc_state *context,
805 			    display_e2e_pipe_params_st *pipes,
806 			    int *pipe_cnt_out,
807 			    int *pipe_split_from,
808 			    int *vlevel_out,
809 			    bool fast_validate)
810 {
811 	bool out = false;
812 	int split[MAX_PIPES] = { 0 };
813 	int pipe_cnt, i, pipe_idx, vlevel;
814 
815 	ASSERT(pipes);
816 	if (!pipes)
817 		return false;
818 
819 	dcn20_merge_pipes_for_validate(dc, context);
820 
821 	DC_FP_START();
822 	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
823 	DC_FP_END();
824 
825 	*pipe_cnt_out = pipe_cnt;
826 
827 	if (!pipe_cnt) {
828 		out = true;
829 		goto validate_out;
830 	}
831 	/*
832 	 * DML favors voltage over p-state, but we're more interested in
833 	 * supporting p-state over voltage. We can't support p-state in
834 	 * prefetch mode > 0 so try capping the prefetch mode to start.
835 	 */
836 	context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
837 				dm_allow_self_refresh_and_mclk_switch;
838 	vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
839 
840 	if (vlevel > context->bw_ctx.dml.soc.num_states) {
841 		/*
842 		 * If mode is unsupported or there's still no p-state support then
843 		 * fall back to favoring voltage.
844 		 *
845 		 * We don't actually support prefetch mode 2, so require that we
846 		 * at least support prefetch mode 1.
847 		 */
848 		context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
849 					dm_allow_self_refresh;
850 		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
851 		if (vlevel > context->bw_ctx.dml.soc.num_states)
852 			goto validate_fail;
853 	}
854 
855 	vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
856 
857 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
858 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
859 		struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
860 		struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
861 
862 		if (!pipe->stream)
863 			continue;
864 
865 		/* We only support full screen mpo with ODM */
866 		if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
867 				&& pipe->plane_state && mpo_pipe
868 				&& memcmp(&mpo_pipe->plane_res.scl_data.recout,
869 						&pipe->plane_res.scl_data.recout,
870 						sizeof(struct rect)) != 0) {
871 			ASSERT(mpo_pipe->plane_state != pipe->plane_state);
872 			goto validate_fail;
873 		}
874 		pipe_idx++;
875 	}
876 
877 	/*initialize pipe_just_split_from to invalid idx*/
878 	for (i = 0; i < MAX_PIPES; i++)
879 		pipe_split_from[i] = -1;
880 
881 	for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
882 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
883 		struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
884 
885 		if (!pipe->stream || pipe_split_from[i] >= 0)
886 			continue;
887 
888 		pipe_idx++;
889 
890 		if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
891 			hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
892 			ASSERT(hsplit_pipe);
893 			if (!dcn20_split_stream_for_odm(
894 					dc, &context->res_ctx,
895 					pipe, hsplit_pipe))
896 				goto validate_fail;
897 			pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
898 			dcn20_build_mapped_resource(dc, context, pipe->stream);
899 		}
900 
901 		if (!pipe->plane_state)
902 			continue;
903 		/* Skip 2nd half of already split pipe */
904 		if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
905 			continue;
906 
907 		if (split[i] == 2) {
908 			if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
909 				/* pipe not split previously needs split */
910 				hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
911 				ASSERT(hsplit_pipe);
912 				if (!hsplit_pipe) {
913 					DC_FP_START();
914 					dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true);
915 					DC_FP_END();
916 					continue;
917 				}
918 				if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
919 					if (!dcn20_split_stream_for_odm(
920 							dc, &context->res_ctx,
921 							pipe, hsplit_pipe))
922 						goto validate_fail;
923 					dcn20_build_mapped_resource(dc, context, pipe->stream);
924 				} else {
925 					dcn20_split_stream_for_mpc(
926 							&context->res_ctx, dc->res_pool,
927 							pipe, hsplit_pipe);
928 					resource_build_scaling_params(pipe);
929 					resource_build_scaling_params(hsplit_pipe);
930 				}
931 				pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
932 			}
933 		} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
934 			/* merge should already have been done */
935 			ASSERT(0);
936 		}
937 	}
938 	/* Actual dsc count per stream dsc validation*/
939 	if (!dcn20_validate_dsc(dc, context)) {
940 		context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
941 				DML_FAIL_DSC_VALIDATION_FAILURE;
942 		goto validate_fail;
943 	}
944 
945 	*vlevel_out = vlevel;
946 
947 	out = true;
948 	goto validate_out;
949 
950 validate_fail:
951 	out = false;
952 
953 validate_out:
954 	return out;
955 }
956 
957 /*
958  * Some of the functions further below use the FPU, so we need to wrap this
959  * with DC_FP_START()/DC_FP_END(). Use the same approach as for
960  * dcn20_validate_bandwidth in dcn20_resource.c.
961  */
962 static bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
963 		bool fast_validate)
964 {
965 	bool voltage_supported;
966 	DC_FP_START();
967 	voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate);
968 	DC_FP_END();
969 	return voltage_supported;
970 }
971 
972 static void dcn21_destroy_resource_pool(struct resource_pool **pool)
973 {
974 	struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
975 
976 	dcn21_resource_destruct(dcn21_pool);
977 	kfree(dcn21_pool);
978 	*pool = NULL;
979 }
980 
981 static struct clock_source *dcn21_clock_source_create(
982 		struct dc_context *ctx,
983 		struct dc_bios *bios,
984 		enum clock_source_id id,
985 		const struct dce110_clk_src_regs *regs,
986 		bool dp_clk_src)
987 {
988 	struct dce110_clk_src *clk_src =
989 		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
990 
991 	if (!clk_src)
992 		return NULL;
993 
994 	if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
995 			regs, &cs_shift, &cs_mask)) {
996 		clk_src->base.dp_clk_src = dp_clk_src;
997 		return &clk_src->base;
998 	}
999 
1000 	kfree(clk_src);
1001 	BREAK_TO_DEBUGGER();
1002 	return NULL;
1003 }
1004 
1005 static struct hubp *dcn21_hubp_create(
1006 	struct dc_context *ctx,
1007 	uint32_t inst)
1008 {
1009 	struct dcn21_hubp *hubp21 =
1010 		kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
1011 
1012 	if (!hubp21)
1013 		return NULL;
1014 
1015 	if (hubp21_construct(hubp21, ctx, inst,
1016 			&hubp_regs[inst], &hubp_shift, &hubp_mask))
1017 		return &hubp21->base;
1018 
1019 	BREAK_TO_DEBUGGER();
1020 	kfree(hubp21);
1021 	return NULL;
1022 }
1023 
1024 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1025 {
1026 	int i;
1027 
1028 	struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1029 					  GFP_KERNEL);
1030 
1031 	if (!hubbub)
1032 		return NULL;
1033 
1034 	hubbub21_construct(hubbub, ctx,
1035 			&hubbub_reg,
1036 			&hubbub_shift,
1037 			&hubbub_mask);
1038 
1039 	for (i = 0; i < res_cap_rn.num_vmid; i++) {
1040 		struct dcn20_vmid *vmid = &hubbub->vmid[i];
1041 
1042 		vmid->ctx = ctx;
1043 
1044 		vmid->regs = &vmid_regs[i];
1045 		vmid->shifts = &vmid_shifts;
1046 		vmid->masks = &vmid_masks;
1047 	}
1048 	hubbub->num_vmid = res_cap_rn.num_vmid;
1049 
1050 	return &hubbub->base;
1051 }
1052 
1053 static struct output_pixel_processor *dcn21_opp_create(struct dc_context *ctx,
1054 						       uint32_t inst)
1055 {
1056 	struct dcn20_opp *opp =
1057 		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1058 
1059 	if (!opp) {
1060 		BREAK_TO_DEBUGGER();
1061 		return NULL;
1062 	}
1063 
1064 	dcn20_opp_construct(opp, ctx, inst,
1065 			&opp_regs[inst], &opp_shift, &opp_mask);
1066 	return &opp->base;
1067 }
1068 
1069 static struct timing_generator *dcn21_timing_generator_create(struct dc_context *ctx,
1070 							      uint32_t instance)
1071 {
1072 	struct optc *tgn10 =
1073 		kzalloc(sizeof(struct optc), GFP_KERNEL);
1074 
1075 	if (!tgn10)
1076 		return NULL;
1077 
1078 	tgn10->base.inst = instance;
1079 	tgn10->base.ctx = ctx;
1080 
1081 	tgn10->tg_regs = &tg_regs[instance];
1082 	tgn10->tg_shift = &tg_shift;
1083 	tgn10->tg_mask = &tg_mask;
1084 
1085 	dcn20_timing_generator_init(tgn10);
1086 
1087 	return &tgn10->base;
1088 }
1089 
1090 static struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1091 {
1092 	struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1093 					  GFP_KERNEL);
1094 
1095 	if (!mpc20)
1096 		return NULL;
1097 
1098 	dcn20_mpc_construct(mpc20, ctx,
1099 			&mpc_regs,
1100 			&mpc_shift,
1101 			&mpc_mask,
1102 			6);
1103 
1104 	return &mpc20->base;
1105 }
1106 
1107 static void read_dce_straps(
1108 	struct dc_context *ctx,
1109 	struct resource_straps *straps)
1110 {
1111 	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1112 		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1113 
1114 }
1115 
1116 
1117 static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx,
1118 							  uint32_t inst)
1119 {
1120 	struct dcn20_dsc *dsc =
1121 		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1122 
1123 	if (!dsc) {
1124 		BREAK_TO_DEBUGGER();
1125 		return NULL;
1126 	}
1127 
1128 	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1129 	return &dsc->base;
1130 }
1131 
1132 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
1133 {
1134 	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1135 
1136 	if (!pp_smu)
1137 		return pp_smu;
1138 
1139 	dm_pp_get_funcs(ctx, pp_smu);
1140 
1141 	if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1142 		pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1143 
1144 
1145 	return pp_smu;
1146 }
1147 
1148 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
1149 {
1150 	if (pp_smu && *pp_smu) {
1151 		kfree(*pp_smu);
1152 		*pp_smu = NULL;
1153 	}
1154 }
1155 
1156 static struct audio *dcn21_create_audio(
1157 		struct dc_context *ctx, unsigned int inst)
1158 {
1159 	return dce_audio_create(ctx, inst,
1160 			&audio_regs[inst], &audio_shift, &audio_mask);
1161 }
1162 
1163 static struct dc_cap_funcs cap_funcs = {
1164 	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1165 };
1166 
1167 static struct stream_encoder *dcn21_stream_encoder_create(enum engine_id eng_id,
1168 							  struct dc_context *ctx)
1169 {
1170 	struct dcn10_stream_encoder *enc1 =
1171 		kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1172 
1173 	if (!enc1)
1174 		return NULL;
1175 
1176 	dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1177 					&stream_enc_regs[eng_id],
1178 					&se_shift, &se_mask);
1179 
1180 	return &enc1->base;
1181 }
1182 
1183 static const struct dce_hwseq_registers hwseq_reg = {
1184 		HWSEQ_DCN21_REG_LIST()
1185 };
1186 
1187 static const struct dce_hwseq_shift hwseq_shift = {
1188 		HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1189 };
1190 
1191 static const struct dce_hwseq_mask hwseq_mask = {
1192 		HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1193 };
1194 
1195 static struct dce_hwseq *dcn21_hwseq_create(
1196 	struct dc_context *ctx)
1197 {
1198 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1199 
1200 	if (hws) {
1201 		hws->ctx = ctx;
1202 		hws->regs = &hwseq_reg;
1203 		hws->shifts = &hwseq_shift;
1204 		hws->masks = &hwseq_mask;
1205 		hws->wa.DEGVIDCN21 = true;
1206 		hws->wa.disallow_self_refresh_during_multi_plane_transition = true;
1207 	}
1208 	return hws;
1209 }
1210 
1211 static const struct resource_create_funcs res_create_funcs = {
1212 	.read_dce_straps = read_dce_straps,
1213 	.create_audio = dcn21_create_audio,
1214 	.create_stream_encoder = dcn21_stream_encoder_create,
1215 	.create_hwseq = dcn21_hwseq_create,
1216 };
1217 
1218 static const struct resource_create_funcs res_create_maximus_funcs = {
1219 	.read_dce_straps = NULL,
1220 	.create_audio = NULL,
1221 	.create_stream_encoder = NULL,
1222 	.create_hwseq = dcn21_hwseq_create,
1223 };
1224 
1225 static const struct encoder_feature_support link_enc_feature = {
1226 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
1227 		.max_hdmi_pixel_clock = 600000,
1228 		.hdmi_ycbcr420_supported = true,
1229 		.dp_ycbcr420_supported = true,
1230 		.fec_supported = true,
1231 		.flags.bits.IS_HBR2_CAPABLE = true,
1232 		.flags.bits.IS_HBR3_CAPABLE = true,
1233 		.flags.bits.IS_TPS3_CAPABLE = true,
1234 		.flags.bits.IS_TPS4_CAPABLE = true
1235 };
1236 
1237 
1238 #define link_regs(id, phyid)\
1239 [id] = {\
1240 	LE_DCN2_REG_LIST(id), \
1241 	UNIPHY_DCN2_REG_LIST(phyid), \
1242 	DPCS_DCN21_REG_LIST(id), \
1243 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1244 }
1245 
1246 static const struct dcn10_link_enc_registers link_enc_regs[] = {
1247 	link_regs(0, A),
1248 	link_regs(1, B),
1249 	link_regs(2, C),
1250 	link_regs(3, D),
1251 	link_regs(4, E),
1252 };
1253 
1254 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
1255 	{ DCN_PANEL_CNTL_REG_LIST() }
1256 };
1257 
1258 static const struct dce_panel_cntl_shift panel_cntl_shift = {
1259 	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
1260 };
1261 
1262 static const struct dce_panel_cntl_mask panel_cntl_mask = {
1263 	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
1264 };
1265 
1266 #define aux_regs(id)\
1267 [id] = {\
1268 	DCN2_AUX_REG_LIST(id)\
1269 }
1270 
1271 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1272 		aux_regs(0),
1273 		aux_regs(1),
1274 		aux_regs(2),
1275 		aux_regs(3),
1276 		aux_regs(4)
1277 };
1278 
1279 #define hpd_regs(id)\
1280 [id] = {\
1281 	HPD_REG_LIST(id)\
1282 }
1283 
1284 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1285 		hpd_regs(0),
1286 		hpd_regs(1),
1287 		hpd_regs(2),
1288 		hpd_regs(3),
1289 		hpd_regs(4)
1290 };
1291 
1292 static const struct dcn10_link_enc_shift le_shift = {
1293 	LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1294 	DPCS_DCN21_MASK_SH_LIST(__SHIFT)
1295 };
1296 
1297 static const struct dcn10_link_enc_mask le_mask = {
1298 	LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1299 	DPCS_DCN21_MASK_SH_LIST(_MASK)
1300 };
1301 
1302 static int map_transmitter_id_to_phy_instance(
1303 	enum transmitter transmitter)
1304 {
1305 	switch (transmitter) {
1306 	case TRANSMITTER_UNIPHY_A:
1307 		return 0;
1308 	break;
1309 	case TRANSMITTER_UNIPHY_B:
1310 		return 1;
1311 	break;
1312 	case TRANSMITTER_UNIPHY_C:
1313 		return 2;
1314 	break;
1315 	case TRANSMITTER_UNIPHY_D:
1316 		return 3;
1317 	break;
1318 	case TRANSMITTER_UNIPHY_E:
1319 		return 4;
1320 	break;
1321 	default:
1322 		ASSERT(0);
1323 		return 0;
1324 	}
1325 }
1326 
1327 static struct link_encoder *dcn21_link_encoder_create(
1328 	const struct encoder_init_data *enc_init_data)
1329 {
1330 	struct dcn21_link_encoder *enc21 =
1331 		kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
1332 	int link_regs_id;
1333 
1334 	if (!enc21)
1335 		return NULL;
1336 
1337 	link_regs_id =
1338 		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1339 
1340 	dcn21_link_encoder_construct(enc21,
1341 				      enc_init_data,
1342 				      &link_enc_feature,
1343 				      &link_enc_regs[link_regs_id],
1344 				      &link_enc_aux_regs[enc_init_data->channel - 1],
1345 				      &link_enc_hpd_regs[enc_init_data->hpd_source],
1346 				      &le_shift,
1347 				      &le_mask);
1348 
1349 	return &enc21->enc10.base;
1350 }
1351 
1352 static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1353 {
1354 	struct dce_panel_cntl *panel_cntl =
1355 		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1356 
1357 	if (!panel_cntl)
1358 		return NULL;
1359 
1360 	dce_panel_cntl_construct(panel_cntl,
1361 			init_data,
1362 			&panel_cntl_regs[init_data->inst],
1363 			&panel_cntl_shift,
1364 			&panel_cntl_mask);
1365 
1366 	return &panel_cntl->base;
1367 }
1368 
1369 #define CTX ctx
1370 
1371 #define REG(reg_name) \
1372 	(DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1373 
1374 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1375 {
1376 	uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1377 	/* RV1 support max 4 pipes */
1378 	value = value & 0xf;
1379 	return value;
1380 }
1381 
1382 static enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1383 {
1384 	enum dc_status result = DC_OK;
1385 
1386 	if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {
1387 		plane_state->dcc.enable = 1;
1388 		/* align to our worst case block width */
1389 		plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;
1390 	}
1391 	result = dcn20_patch_unknown_plane_state(plane_state);
1392 	return result;
1393 }
1394 
1395 static const struct resource_funcs dcn21_res_pool_funcs = {
1396 	.destroy = dcn21_destroy_resource_pool,
1397 	.link_enc_create = dcn21_link_encoder_create,
1398 	.panel_cntl_create = dcn21_panel_cntl_create,
1399 	.validate_bandwidth = dcn21_validate_bandwidth,
1400 	.populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
1401 	.add_stream_to_ctx = dcn20_add_stream_to_ctx,
1402 	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1403 	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1404 	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1405 	.populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
1406 	.patch_unknown_plane_state = dcn21_patch_unknown_plane_state,
1407 	.set_mcif_arb_params = dcn20_set_mcif_arb_params,
1408 	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1409 	.update_bw_bounding_box = dcn21_update_bw_bounding_box,
1410 };
1411 
1412 static bool dcn21_resource_construct(
1413 	uint8_t num_virtual_links,
1414 	struct dc *dc,
1415 	struct dcn21_resource_pool *pool)
1416 {
1417 	int i, j;
1418 	struct dc_context *ctx = dc->ctx;
1419 	struct irq_service_init_data init_data;
1420 	uint32_t pipe_fuses = read_pipe_fuses(ctx);
1421 	uint32_t num_pipes;
1422 
1423 	ctx->dc_bios->regs = &bios_regs;
1424 
1425 	pool->base.res_cap = &res_cap_rn;
1426 #ifdef DIAGS_BUILD
1427 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1428 		//pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
1429 		pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
1430 #endif
1431 
1432 	pool->base.funcs = &dcn21_res_pool_funcs;
1433 
1434 	/*************************************************
1435 	 *  Resource + asic cap harcoding                *
1436 	 *************************************************/
1437 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1438 
1439 	/* max pipe num for ASIC before check pipe fuses */
1440 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1441 
1442 	dc->caps.max_downscale_ratio = 200;
1443 	dc->caps.i2c_speed_in_khz = 100;
1444 	dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
1445 	dc->caps.max_cursor_size = 256;
1446 	dc->caps.min_horizontal_blanking_period = 80;
1447 	dc->caps.dmdata_alloc_size = 2048;
1448 
1449 	dc->caps.max_slave_planes = 1;
1450 	dc->caps.max_slave_yuv_planes = 1;
1451 	dc->caps.max_slave_rgb_planes = 1;
1452 	dc->caps.post_blend_color_processing = true;
1453 	dc->caps.force_dp_tps4_for_cp2520 = true;
1454 	dc->caps.extended_aux_timeout_support = true;
1455 	dc->caps.dmcub_support = true;
1456 	dc->caps.is_apu = true;
1457 
1458 	/* Color pipeline capabilities */
1459 	dc->caps.color.dpp.dcn_arch = 1;
1460 	dc->caps.color.dpp.input_lut_shared = 0;
1461 	dc->caps.color.dpp.icsc = 1;
1462 	dc->caps.color.dpp.dgam_ram = 1;
1463 	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1464 	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1465 	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1466 	dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1467 	dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1468 	dc->caps.color.dpp.post_csc = 0;
1469 	dc->caps.color.dpp.gamma_corr = 0;
1470 	dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1471 
1472 	dc->caps.color.dpp.hw_3d_lut = 1;
1473 	dc->caps.color.dpp.ogam_ram = 1;
1474 	// no OGAM ROM on DCN2
1475 	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1476 	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1477 	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1478 	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1479 	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1480 	dc->caps.color.dpp.ocsc = 0;
1481 
1482 	dc->caps.color.mpc.gamut_remap = 0;
1483 	dc->caps.color.mpc.num_3dluts = 0;
1484 	dc->caps.color.mpc.shared_3d_lut = 0;
1485 	dc->caps.color.mpc.ogam_ram = 1;
1486 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1487 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1488 	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1489 	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1490 	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1491 	dc->caps.color.mpc.ocsc = 1;
1492 
1493 	dc->caps.hdmi_frl_pcon_support = true;
1494 
1495 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1496 		dc->debug = debug_defaults_drv;
1497 	else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1498 		pool->base.pipe_count = 4;
1499 		dc->debug = debug_defaults_diags;
1500 	} else
1501 		dc->debug = debug_defaults_diags;
1502 
1503 	// Init the vm_helper
1504 	if (dc->vm_helper)
1505 		vm_helper_init(dc->vm_helper, 16);
1506 
1507 	/*************************************************
1508 	 *  Create resources                             *
1509 	 *************************************************/
1510 
1511 	pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1512 			dcn21_clock_source_create(ctx, ctx->dc_bios,
1513 				CLOCK_SOURCE_COMBO_PHY_PLL0,
1514 				&clk_src_regs[0], false);
1515 	pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1516 			dcn21_clock_source_create(ctx, ctx->dc_bios,
1517 				CLOCK_SOURCE_COMBO_PHY_PLL1,
1518 				&clk_src_regs[1], false);
1519 	pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
1520 			dcn21_clock_source_create(ctx, ctx->dc_bios,
1521 				CLOCK_SOURCE_COMBO_PHY_PLL2,
1522 				&clk_src_regs[2], false);
1523 	pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
1524 			dcn21_clock_source_create(ctx, ctx->dc_bios,
1525 				CLOCK_SOURCE_COMBO_PHY_PLL3,
1526 				&clk_src_regs[3], false);
1527 	pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
1528 			dcn21_clock_source_create(ctx, ctx->dc_bios,
1529 				CLOCK_SOURCE_COMBO_PHY_PLL4,
1530 				&clk_src_regs[4], false);
1531 
1532 	pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
1533 
1534 	/* todo: not reuse phy_pll registers */
1535 	pool->base.dp_clock_source =
1536 			dcn21_clock_source_create(ctx, ctx->dc_bios,
1537 				CLOCK_SOURCE_ID_DP_DTO,
1538 				&clk_src_regs[0], true);
1539 
1540 	for (i = 0; i < pool->base.clk_src_count; i++) {
1541 		if (pool->base.clock_sources[i] == NULL) {
1542 			dm_error("DC: failed to create clock sources!\n");
1543 			BREAK_TO_DEBUGGER();
1544 			goto create_fail;
1545 		}
1546 	}
1547 
1548 	pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1549 	if (pool->base.dccg == NULL) {
1550 		dm_error("DC: failed to create dccg!\n");
1551 		BREAK_TO_DEBUGGER();
1552 		goto create_fail;
1553 	}
1554 
1555 	if (!dc->config.disable_dmcu) {
1556 		pool->base.dmcu = dcn21_dmcu_create(ctx,
1557 				&dmcu_regs,
1558 				&dmcu_shift,
1559 				&dmcu_mask);
1560 		if (pool->base.dmcu == NULL) {
1561 			dm_error("DC: failed to create dmcu!\n");
1562 			BREAK_TO_DEBUGGER();
1563 			goto create_fail;
1564 		}
1565 
1566 		dc->debug.dmub_command_table = false;
1567 	}
1568 
1569 	if (dc->config.disable_dmcu) {
1570 		pool->base.psr = dmub_psr_create(ctx);
1571 
1572 		if (pool->base.psr == NULL) {
1573 			dm_error("DC: failed to create psr obj!\n");
1574 			BREAK_TO_DEBUGGER();
1575 			goto create_fail;
1576 		}
1577 	}
1578 
1579 	if (dc->config.disable_dmcu)
1580 		pool->base.abm = dmub_abm_create(ctx,
1581 			&abm_regs,
1582 			&abm_shift,
1583 			&abm_mask);
1584 	else
1585 		pool->base.abm = dce_abm_create(ctx,
1586 			&abm_regs,
1587 			&abm_shift,
1588 			&abm_mask);
1589 
1590 	pool->base.pp_smu = dcn21_pp_smu_create(ctx);
1591 
1592 	num_pipes = dcn2_1_ip.max_num_dpp;
1593 
1594 	for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
1595 		if (pipe_fuses & 1 << i)
1596 			num_pipes--;
1597 	dcn2_1_ip.max_num_dpp = num_pipes;
1598 	dcn2_1_ip.max_num_otg = num_pipes;
1599 
1600 	dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1601 
1602 	init_data.ctx = dc->ctx;
1603 	pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
1604 	if (!pool->base.irqs)
1605 		goto create_fail;
1606 
1607 	j = 0;
1608 	/* mem input -> ipp -> dpp -> opp -> TG */
1609 	for (i = 0; i < pool->base.pipe_count; i++) {
1610 		/* if pipe is disabled, skip instance of HW pipe,
1611 		 * i.e, skip ASIC register instance
1612 		 */
1613 		if ((pipe_fuses & (1 << i)) != 0)
1614 			continue;
1615 
1616 		pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
1617 		if (pool->base.hubps[j] == NULL) {
1618 			BREAK_TO_DEBUGGER();
1619 			dm_error(
1620 				"DC: failed to create memory input!\n");
1621 			goto create_fail;
1622 		}
1623 
1624 		pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
1625 		if (pool->base.ipps[j] == NULL) {
1626 			BREAK_TO_DEBUGGER();
1627 			dm_error(
1628 				"DC: failed to create input pixel processor!\n");
1629 			goto create_fail;
1630 		}
1631 
1632 		pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
1633 		if (pool->base.dpps[j] == NULL) {
1634 			BREAK_TO_DEBUGGER();
1635 			dm_error(
1636 				"DC: failed to create dpps!\n");
1637 			goto create_fail;
1638 		}
1639 
1640 		pool->base.opps[j] = dcn21_opp_create(ctx, i);
1641 		if (pool->base.opps[j] == NULL) {
1642 			BREAK_TO_DEBUGGER();
1643 			dm_error(
1644 				"DC: failed to create output pixel processor!\n");
1645 			goto create_fail;
1646 		}
1647 
1648 		pool->base.timing_generators[j] = dcn21_timing_generator_create(
1649 				ctx, i);
1650 		if (pool->base.timing_generators[j] == NULL) {
1651 			BREAK_TO_DEBUGGER();
1652 			dm_error("DC: failed to create tg!\n");
1653 			goto create_fail;
1654 		}
1655 		j++;
1656 	}
1657 
1658 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1659 		pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
1660 		if (pool->base.engines[i] == NULL) {
1661 			BREAK_TO_DEBUGGER();
1662 			dm_error(
1663 				"DC:failed to create aux engine!!\n");
1664 			goto create_fail;
1665 		}
1666 		pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
1667 		if (pool->base.hw_i2cs[i] == NULL) {
1668 			BREAK_TO_DEBUGGER();
1669 			dm_error(
1670 				"DC:failed to create hw i2c!!\n");
1671 			goto create_fail;
1672 		}
1673 		pool->base.sw_i2cs[i] = NULL;
1674 	}
1675 
1676 	pool->base.timing_generator_count = j;
1677 	pool->base.pipe_count = j;
1678 	pool->base.mpcc_count = j;
1679 
1680 	pool->base.mpc = dcn21_mpc_create(ctx);
1681 	if (pool->base.mpc == NULL) {
1682 		BREAK_TO_DEBUGGER();
1683 		dm_error("DC: failed to create mpc!\n");
1684 		goto create_fail;
1685 	}
1686 
1687 	pool->base.hubbub = dcn21_hubbub_create(ctx);
1688 	if (pool->base.hubbub == NULL) {
1689 		BREAK_TO_DEBUGGER();
1690 		dm_error("DC: failed to create hubbub!\n");
1691 		goto create_fail;
1692 	}
1693 
1694 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1695 		pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
1696 		if (pool->base.dscs[i] == NULL) {
1697 			BREAK_TO_DEBUGGER();
1698 			dm_error("DC: failed to create display stream compressor %d!\n", i);
1699 			goto create_fail;
1700 		}
1701 	}
1702 
1703 	if (!dcn20_dwbc_create(ctx, &pool->base)) {
1704 		BREAK_TO_DEBUGGER();
1705 		dm_error("DC: failed to create dwbc!\n");
1706 		goto create_fail;
1707 	}
1708 	if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
1709 		BREAK_TO_DEBUGGER();
1710 		dm_error("DC: failed to create mcif_wb!\n");
1711 		goto create_fail;
1712 	}
1713 
1714 	if (!resource_construct(num_virtual_links, dc, &pool->base,
1715 			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1716 			&res_create_funcs : &res_create_maximus_funcs)))
1717 			goto create_fail;
1718 
1719 	dcn21_hw_sequencer_construct(dc);
1720 
1721 	dc->caps.max_planes =  pool->base.pipe_count;
1722 
1723 	for (i = 0; i < dc->caps.max_planes; ++i)
1724 		dc->caps.planes[i] = plane_cap;
1725 
1726 	dc->cap_funcs = cap_funcs;
1727 
1728 	return true;
1729 
1730 create_fail:
1731 
1732 	dcn21_resource_destruct(pool);
1733 
1734 	return false;
1735 }
1736 
1737 struct resource_pool *dcn21_create_resource_pool(
1738 		const struct dc_init_data *init_data,
1739 		struct dc *dc)
1740 {
1741 	struct dcn21_resource_pool *pool =
1742 		kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
1743 
1744 	if (!pool)
1745 		return NULL;
1746 
1747 	if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
1748 		return &pool->base;
1749 
1750 	BREAK_TO_DEBUGGER();
1751 	kfree(pool);
1752 	return NULL;
1753 }
1754