1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * Copyright 2019 Raptor Engineering, LLC 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 #include "dc.h" 31 32 #include "dcn21_init.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dcn20/dcn20_resource.h" 37 38 #include "clk_mgr.h" 39 #include "dcn10/dcn10_hubp.h" 40 #include "dcn10/dcn10_ipp.h" 41 #include "dcn20/dcn20_hubbub.h" 42 #include "dcn20/dcn20_mpc.h" 43 #include "dcn20/dcn20_hubp.h" 44 #include "dcn21_hubp.h" 45 #include "irq/dcn21/irq_service_dcn21.h" 46 #include "dcn20/dcn20_dpp.h" 47 #include "dcn20/dcn20_optc.h" 48 #include "dcn21/dcn21_hwseq.h" 49 #include "dce110/dce110_hw_sequencer.h" 50 #include "dcn20/dcn20_opp.h" 51 #include "dcn20/dcn20_dsc.h" 52 #include "dcn21/dcn21_link_encoder.h" 53 #include "dcn20/dcn20_stream_encoder.h" 54 #include "dce/dce_clock_source.h" 55 #include "dce/dce_audio.h" 56 #include "dce/dce_hwseq.h" 57 #include "virtual/virtual_stream_encoder.h" 58 #include "dce110/dce110_resource.h" 59 #include "dml/display_mode_vba.h" 60 #include "dcn20/dcn20_dccg.h" 61 #include "dcn21_hubbub.h" 62 #include "dcn10/dcn10_resource.h" 63 #include "dce110/dce110_resource.h" 64 65 #include "dcn20/dcn20_dwb.h" 66 #include "dcn20/dcn20_mmhubbub.h" 67 #include "dpcs/dpcs_2_1_0_offset.h" 68 #include "dpcs/dpcs_2_1_0_sh_mask.h" 69 70 #include "renoir_ip_offset.h" 71 #include "dcn/dcn_2_1_0_offset.h" 72 #include "dcn/dcn_2_1_0_sh_mask.h" 73 74 #include "nbio/nbio_7_0_offset.h" 75 76 #include "mmhub/mmhub_2_0_0_offset.h" 77 #include "mmhub/mmhub_2_0_0_sh_mask.h" 78 79 #include "reg_helper.h" 80 #include "dce/dce_abm.h" 81 #include "dce/dce_dmcu.h" 82 #include "dce/dce_aux.h" 83 #include "dce/dce_i2c.h" 84 #include "dcn21_resource.h" 85 #include "vm_helper.h" 86 #include "dcn20/dcn20_vmid.h" 87 #include "dce/dmub_psr.h" 88 #include "dce/dmub_abm.h" 89 90 #define SOC_BOUNDING_BOX_VALID false 91 #define DC_LOGGER_INIT(logger) 92 93 94 struct _vcs_dpi_ip_params_st dcn2_1_ip = { 95 .odm_capable = 1, 96 .gpuvm_enable = 1, 97 .hostvm_enable = 1, 98 .gpuvm_max_page_table_levels = 1, 99 .hostvm_max_page_table_levels = 4, 100 .hostvm_cached_page_table_levels = 2, 101 .num_dsc = 3, 102 .rob_buffer_size_kbytes = 168, 103 .det_buffer_size_kbytes = 164, 104 .dpte_buffer_size_in_pte_reqs_luma = 44, 105 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo 106 .dpp_output_buffer_pixels = 2560, 107 .opp_output_buffer_lines = 1, 108 .pixel_chunk_size_kbytes = 8, 109 .pte_enable = 1, 110 .max_page_table_levels = 4, 111 .pte_chunk_size_kbytes = 2, 112 .meta_chunk_size_kbytes = 2, 113 .writeback_chunk_size_kbytes = 2, 114 .line_buffer_size_bits = 789504, 115 .is_line_buffer_bpp_fixed = 0, 116 .line_buffer_fixed_bpp = 0, 117 .dcc_supported = true, 118 .max_line_buffer_lines = 12, 119 .writeback_luma_buffer_size_kbytes = 12, 120 .writeback_chroma_buffer_size_kbytes = 8, 121 .writeback_chroma_line_buffer_width_pixels = 4, 122 .writeback_max_hscl_ratio = 1, 123 .writeback_max_vscl_ratio = 1, 124 .writeback_min_hscl_ratio = 1, 125 .writeback_min_vscl_ratio = 1, 126 .writeback_max_hscl_taps = 12, 127 .writeback_max_vscl_taps = 12, 128 .writeback_line_buffer_luma_buffer_size = 0, 129 .writeback_line_buffer_chroma_buffer_size = 14643, 130 .cursor_buffer_size = 8, 131 .cursor_chunk_size = 2, 132 .max_num_otg = 4, 133 .max_num_dpp = 4, 134 .max_num_wb = 1, 135 .max_dchub_pscl_bw_pix_per_clk = 4, 136 .max_pscl_lb_bw_pix_per_clk = 2, 137 .max_lb_vscl_bw_pix_per_clk = 4, 138 .max_vscl_hscl_bw_pix_per_clk = 4, 139 .max_hscl_ratio = 4, 140 .max_vscl_ratio = 4, 141 .hscl_mults = 4, 142 .vscl_mults = 4, 143 .max_hscl_taps = 8, 144 .max_vscl_taps = 8, 145 .dispclk_ramp_margin_percent = 1, 146 .underscan_factor = 1.10, 147 .min_vblank_lines = 32, // 148 .dppclk_delay_subtotal = 77, // 149 .dppclk_delay_scl_lb_only = 16, 150 .dppclk_delay_scl = 50, 151 .dppclk_delay_cnvc_formatter = 8, 152 .dppclk_delay_cnvc_cursor = 6, 153 .dispclk_delay_subtotal = 87, // 154 .dcfclk_cstate_latency = 10, // SRExitTime 155 .max_inter_dcn_tile_repeaters = 8, 156 157 .xfc_supported = false, 158 .xfc_fill_bw_overhead_percent = 10.0, 159 .xfc_fill_constant_bytes = 0, 160 .ptoi_supported = 0, 161 .number_of_cursors = 1, 162 }; 163 164 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { 165 .clock_limits = { 166 { 167 .state = 0, 168 .dcfclk_mhz = 400.0, 169 .fabricclk_mhz = 400.0, 170 .dispclk_mhz = 600.0, 171 .dppclk_mhz = 400.00, 172 .phyclk_mhz = 600.0, 173 .socclk_mhz = 278.0, 174 .dscclk_mhz = 205.67, 175 .dram_speed_mts = 1600.0, 176 }, 177 { 178 .state = 1, 179 .dcfclk_mhz = 464.52, 180 .fabricclk_mhz = 800.0, 181 .dispclk_mhz = 654.55, 182 .dppclk_mhz = 626.09, 183 .phyclk_mhz = 600.0, 184 .socclk_mhz = 278.0, 185 .dscclk_mhz = 205.67, 186 .dram_speed_mts = 1600.0, 187 }, 188 { 189 .state = 2, 190 .dcfclk_mhz = 514.29, 191 .fabricclk_mhz = 933.0, 192 .dispclk_mhz = 757.89, 193 .dppclk_mhz = 685.71, 194 .phyclk_mhz = 600.0, 195 .socclk_mhz = 278.0, 196 .dscclk_mhz = 287.67, 197 .dram_speed_mts = 1866.0, 198 }, 199 { 200 .state = 3, 201 .dcfclk_mhz = 576.00, 202 .fabricclk_mhz = 1067.0, 203 .dispclk_mhz = 847.06, 204 .dppclk_mhz = 757.89, 205 .phyclk_mhz = 600.0, 206 .socclk_mhz = 715.0, 207 .dscclk_mhz = 318.334, 208 .dram_speed_mts = 2134.0, 209 }, 210 { 211 .state = 4, 212 .dcfclk_mhz = 626.09, 213 .fabricclk_mhz = 1200.0, 214 .dispclk_mhz = 900.00, 215 .dppclk_mhz = 847.06, 216 .phyclk_mhz = 810.0, 217 .socclk_mhz = 953.0, 218 .dscclk_mhz = 489.0, 219 .dram_speed_mts = 2400.0, 220 }, 221 { 222 .state = 5, 223 .dcfclk_mhz = 685.71, 224 .fabricclk_mhz = 1333.0, 225 .dispclk_mhz = 1028.57, 226 .dppclk_mhz = 960.00, 227 .phyclk_mhz = 810.0, 228 .socclk_mhz = 278.0, 229 .dscclk_mhz = 287.67, 230 .dram_speed_mts = 2666.0, 231 }, 232 { 233 .state = 6, 234 .dcfclk_mhz = 757.89, 235 .fabricclk_mhz = 1467.0, 236 .dispclk_mhz = 1107.69, 237 .dppclk_mhz = 1028.57, 238 .phyclk_mhz = 810.0, 239 .socclk_mhz = 715.0, 240 .dscclk_mhz = 318.334, 241 .dram_speed_mts = 3200.0, 242 }, 243 { 244 .state = 7, 245 .dcfclk_mhz = 847.06, 246 .fabricclk_mhz = 1600.0, 247 .dispclk_mhz = 1395.0, 248 .dppclk_mhz = 1285.00, 249 .phyclk_mhz = 1325.0, 250 .socclk_mhz = 953.0, 251 .dscclk_mhz = 489.0, 252 .dram_speed_mts = 4266.0, 253 }, 254 /*Extra state, no dispclk ramping*/ 255 { 256 .state = 8, 257 .dcfclk_mhz = 847.06, 258 .fabricclk_mhz = 1600.0, 259 .dispclk_mhz = 1395.0, 260 .dppclk_mhz = 1285.0, 261 .phyclk_mhz = 1325.0, 262 .socclk_mhz = 953.0, 263 .dscclk_mhz = 489.0, 264 .dram_speed_mts = 4266.0, 265 }, 266 267 }, 268 269 .sr_exit_time_us = 12.5, 270 .sr_enter_plus_exit_time_us = 17.0, 271 .urgent_latency_us = 4.0, 272 .urgent_latency_pixel_data_only_us = 4.0, 273 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 274 .urgent_latency_vm_data_only_us = 4.0, 275 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 276 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 277 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 278 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 279 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0, 280 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 281 .max_avg_sdp_bw_use_normal_percent = 60.0, 282 .max_avg_dram_bw_use_normal_percent = 100.0, 283 .writeback_latency_us = 12.0, 284 .max_request_size_bytes = 256, 285 .dram_channel_width_bytes = 4, 286 .fabric_datapath_to_dcn_data_return_bytes = 32, 287 .dcn_downspread_percent = 0.5, 288 .downspread_percent = 0.5, 289 .dram_page_open_time_ns = 50.0, 290 .dram_rw_turnaround_time_ns = 17.5, 291 .dram_return_buffer_per_channel_bytes = 8192, 292 .round_trip_ping_latency_dcfclk_cycles = 128, 293 .urgent_out_of_order_return_per_channel_bytes = 4096, 294 .channel_interleave_bytes = 256, 295 .num_banks = 8, 296 .num_chans = 4, 297 .vmm_page_size_bytes = 4096, 298 .dram_clock_change_latency_us = 23.84, 299 .return_bus_width_bytes = 64, 300 .dispclk_dppclk_vco_speed_mhz = 3600, 301 .xfc_bus_transport_time_us = 4, 302 .xfc_xbuf_latency_tolerance_us = 4, 303 .use_urgent_burst_bw = 1, 304 .num_states = 8 305 }; 306 307 #ifndef MAX 308 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y)) 309 #endif 310 #ifndef MIN 311 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 312 #endif 313 314 /* begin ********************* 315 * macros to expend register list macro defined in HW object header file */ 316 317 /* DCN */ 318 /* TODO awful hack. fixup dcn20_dwb.h */ 319 #undef BASE_INNER 320 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg 321 322 #define BASE(seg) BASE_INNER(seg) 323 324 #define SR(reg_name)\ 325 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 326 mm ## reg_name 327 328 #define SRI(reg_name, block, id)\ 329 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 330 mm ## block ## id ## _ ## reg_name 331 332 #define SRIR(var_name, reg_name, block, id)\ 333 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 334 mm ## block ## id ## _ ## reg_name 335 336 #define SRII(reg_name, block, id)\ 337 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 338 mm ## block ## id ## _ ## reg_name 339 340 #define DCCG_SRII(reg_name, block, id)\ 341 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 342 mm ## block ## id ## _ ## reg_name 343 344 /* NBIO */ 345 #define NBIO_BASE_INNER(seg) \ 346 NBIF0_BASE__INST0_SEG ## seg 347 348 #define NBIO_BASE(seg) \ 349 NBIO_BASE_INNER(seg) 350 351 #define NBIO_SR(reg_name)\ 352 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 353 mm ## reg_name 354 355 /* MMHUB */ 356 #define MMHUB_BASE_INNER(seg) \ 357 MMHUB_BASE__INST0_SEG ## seg 358 359 #define MMHUB_BASE(seg) \ 360 MMHUB_BASE_INNER(seg) 361 362 #define MMHUB_SR(reg_name)\ 363 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 364 mmMM ## reg_name 365 366 #define clk_src_regs(index, pllid)\ 367 [index] = {\ 368 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\ 369 } 370 371 static const struct dce110_clk_src_regs clk_src_regs[] = { 372 clk_src_regs(0, A), 373 clk_src_regs(1, B), 374 clk_src_regs(2, C), 375 clk_src_regs(3, D), 376 clk_src_regs(4, E), 377 }; 378 379 static const struct dce110_clk_src_shift cs_shift = { 380 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 381 }; 382 383 static const struct dce110_clk_src_mask cs_mask = { 384 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 385 }; 386 387 static const struct bios_registers bios_regs = { 388 NBIO_SR(BIOS_SCRATCH_3), 389 NBIO_SR(BIOS_SCRATCH_6) 390 }; 391 392 static const struct dce_dmcu_registers dmcu_regs = { 393 DMCU_DCN20_REG_LIST() 394 }; 395 396 static const struct dce_dmcu_shift dmcu_shift = { 397 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 398 }; 399 400 static const struct dce_dmcu_mask dmcu_mask = { 401 DMCU_MASK_SH_LIST_DCN10(_MASK) 402 }; 403 404 static const struct dce_abm_registers abm_regs = { 405 ABM_DCN20_REG_LIST() 406 }; 407 408 static const struct dce_abm_shift abm_shift = { 409 ABM_MASK_SH_LIST_DCN20(__SHIFT) 410 }; 411 412 static const struct dce_abm_mask abm_mask = { 413 ABM_MASK_SH_LIST_DCN20(_MASK) 414 }; 415 416 #define audio_regs(id)\ 417 [id] = {\ 418 AUD_COMMON_REG_LIST(id)\ 419 } 420 421 static const struct dce_audio_registers audio_regs[] = { 422 audio_regs(0), 423 audio_regs(1), 424 audio_regs(2), 425 audio_regs(3), 426 audio_regs(4), 427 audio_regs(5), 428 }; 429 430 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 431 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 432 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 433 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 434 435 static const struct dce_audio_shift audio_shift = { 436 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 437 }; 438 439 static const struct dce_audio_mask audio_mask = { 440 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 441 }; 442 443 static const struct dccg_registers dccg_regs = { 444 DCCG_COMMON_REG_LIST_DCN_BASE() 445 }; 446 447 static const struct dccg_shift dccg_shift = { 448 DCCG_MASK_SH_LIST_DCN2(__SHIFT) 449 }; 450 451 static const struct dccg_mask dccg_mask = { 452 DCCG_MASK_SH_LIST_DCN2(_MASK) 453 }; 454 455 #define opp_regs(id)\ 456 [id] = {\ 457 OPP_REG_LIST_DCN20(id),\ 458 } 459 460 static const struct dcn20_opp_registers opp_regs[] = { 461 opp_regs(0), 462 opp_regs(1), 463 opp_regs(2), 464 opp_regs(3), 465 opp_regs(4), 466 opp_regs(5), 467 }; 468 469 static const struct dcn20_opp_shift opp_shift = { 470 OPP_MASK_SH_LIST_DCN20(__SHIFT) 471 }; 472 473 static const struct dcn20_opp_mask opp_mask = { 474 OPP_MASK_SH_LIST_DCN20(_MASK) 475 }; 476 477 #define tg_regs(id)\ 478 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)} 479 480 static const struct dcn_optc_registers tg_regs[] = { 481 tg_regs(0), 482 tg_regs(1), 483 tg_regs(2), 484 tg_regs(3) 485 }; 486 487 static const struct dcn_optc_shift tg_shift = { 488 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 489 }; 490 491 static const struct dcn_optc_mask tg_mask = { 492 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 493 }; 494 495 static const struct dcn20_mpc_registers mpc_regs = { 496 MPC_REG_LIST_DCN2_0(0), 497 MPC_REG_LIST_DCN2_0(1), 498 MPC_REG_LIST_DCN2_0(2), 499 MPC_REG_LIST_DCN2_0(3), 500 MPC_REG_LIST_DCN2_0(4), 501 MPC_REG_LIST_DCN2_0(5), 502 MPC_OUT_MUX_REG_LIST_DCN2_0(0), 503 MPC_OUT_MUX_REG_LIST_DCN2_0(1), 504 MPC_OUT_MUX_REG_LIST_DCN2_0(2), 505 MPC_OUT_MUX_REG_LIST_DCN2_0(3), 506 MPC_DBG_REG_LIST_DCN2_0() 507 }; 508 509 static const struct dcn20_mpc_shift mpc_shift = { 510 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT), 511 MPC_DEBUG_REG_LIST_SH_DCN20 512 }; 513 514 static const struct dcn20_mpc_mask mpc_mask = { 515 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK), 516 MPC_DEBUG_REG_LIST_MASK_DCN20 517 }; 518 519 #define hubp_regs(id)\ 520 [id] = {\ 521 HUBP_REG_LIST_DCN21(id)\ 522 } 523 524 static const struct dcn_hubp2_registers hubp_regs[] = { 525 hubp_regs(0), 526 hubp_regs(1), 527 hubp_regs(2), 528 hubp_regs(3) 529 }; 530 531 static const struct dcn_hubp2_shift hubp_shift = { 532 HUBP_MASK_SH_LIST_DCN21(__SHIFT) 533 }; 534 535 static const struct dcn_hubp2_mask hubp_mask = { 536 HUBP_MASK_SH_LIST_DCN21(_MASK) 537 }; 538 539 static const struct dcn_hubbub_registers hubbub_reg = { 540 HUBBUB_REG_LIST_DCN21() 541 }; 542 543 static const struct dcn_hubbub_shift hubbub_shift = { 544 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT) 545 }; 546 547 static const struct dcn_hubbub_mask hubbub_mask = { 548 HUBBUB_MASK_SH_LIST_DCN21(_MASK) 549 }; 550 551 552 #define vmid_regs(id)\ 553 [id] = {\ 554 DCN20_VMID_REG_LIST(id)\ 555 } 556 557 static const struct dcn_vmid_registers vmid_regs[] = { 558 vmid_regs(0), 559 vmid_regs(1), 560 vmid_regs(2), 561 vmid_regs(3), 562 vmid_regs(4), 563 vmid_regs(5), 564 vmid_regs(6), 565 vmid_regs(7), 566 vmid_regs(8), 567 vmid_regs(9), 568 vmid_regs(10), 569 vmid_regs(11), 570 vmid_regs(12), 571 vmid_regs(13), 572 vmid_regs(14), 573 vmid_regs(15) 574 }; 575 576 static const struct dcn20_vmid_shift vmid_shifts = { 577 DCN20_VMID_MASK_SH_LIST(__SHIFT) 578 }; 579 580 static const struct dcn20_vmid_mask vmid_masks = { 581 DCN20_VMID_MASK_SH_LIST(_MASK) 582 }; 583 584 #define dsc_regsDCN20(id)\ 585 [id] = {\ 586 DSC_REG_LIST_DCN20(id)\ 587 } 588 589 static const struct dcn20_dsc_registers dsc_regs[] = { 590 dsc_regsDCN20(0), 591 dsc_regsDCN20(1), 592 dsc_regsDCN20(2), 593 dsc_regsDCN20(3), 594 dsc_regsDCN20(4), 595 dsc_regsDCN20(5) 596 }; 597 598 static const struct dcn20_dsc_shift dsc_shift = { 599 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 600 }; 601 602 static const struct dcn20_dsc_mask dsc_mask = { 603 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 604 }; 605 606 #define ipp_regs(id)\ 607 [id] = {\ 608 IPP_REG_LIST_DCN20(id),\ 609 } 610 611 static const struct dcn10_ipp_registers ipp_regs[] = { 612 ipp_regs(0), 613 ipp_regs(1), 614 ipp_regs(2), 615 ipp_regs(3), 616 }; 617 618 static const struct dcn10_ipp_shift ipp_shift = { 619 IPP_MASK_SH_LIST_DCN20(__SHIFT) 620 }; 621 622 static const struct dcn10_ipp_mask ipp_mask = { 623 IPP_MASK_SH_LIST_DCN20(_MASK), 624 }; 625 626 #define opp_regs(id)\ 627 [id] = {\ 628 OPP_REG_LIST_DCN20(id),\ 629 } 630 631 632 #define aux_engine_regs(id)\ 633 [id] = {\ 634 AUX_COMMON_REG_LIST0(id), \ 635 .AUXN_IMPCAL = 0, \ 636 .AUXP_IMPCAL = 0, \ 637 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 638 } 639 640 static const struct dce110_aux_registers aux_engine_regs[] = { 641 aux_engine_regs(0), 642 aux_engine_regs(1), 643 aux_engine_regs(2), 644 aux_engine_regs(3), 645 aux_engine_regs(4), 646 }; 647 648 #define tf_regs(id)\ 649 [id] = {\ 650 TF_REG_LIST_DCN20(id),\ 651 TF_REG_LIST_DCN20_COMMON_APPEND(id),\ 652 } 653 654 static const struct dcn2_dpp_registers tf_regs[] = { 655 tf_regs(0), 656 tf_regs(1), 657 tf_regs(2), 658 tf_regs(3), 659 }; 660 661 static const struct dcn2_dpp_shift tf_shift = { 662 TF_REG_LIST_SH_MASK_DCN20(__SHIFT), 663 TF_DEBUG_REG_LIST_SH_DCN20 664 }; 665 666 static const struct dcn2_dpp_mask tf_mask = { 667 TF_REG_LIST_SH_MASK_DCN20(_MASK), 668 TF_DEBUG_REG_LIST_MASK_DCN20 669 }; 670 671 #define stream_enc_regs(id)\ 672 [id] = {\ 673 SE_DCN2_REG_LIST(id)\ 674 } 675 676 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 677 stream_enc_regs(0), 678 stream_enc_regs(1), 679 stream_enc_regs(2), 680 stream_enc_regs(3), 681 stream_enc_regs(4), 682 }; 683 684 static const struct dce110_aux_registers_shift aux_shift = { 685 DCN_AUX_MASK_SH_LIST(__SHIFT) 686 }; 687 688 static const struct dce110_aux_registers_mask aux_mask = { 689 DCN_AUX_MASK_SH_LIST(_MASK) 690 }; 691 692 static const struct dcn10_stream_encoder_shift se_shift = { 693 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) 694 }; 695 696 static const struct dcn10_stream_encoder_mask se_mask = { 697 SE_COMMON_MASK_SH_LIST_DCN20(_MASK) 698 }; 699 700 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu); 701 702 static int dcn21_populate_dml_pipes_from_context( 703 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes); 704 705 static struct input_pixel_processor *dcn21_ipp_create( 706 struct dc_context *ctx, uint32_t inst) 707 { 708 struct dcn10_ipp *ipp = 709 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 710 711 if (!ipp) { 712 BREAK_TO_DEBUGGER(); 713 return NULL; 714 } 715 716 dcn20_ipp_construct(ipp, ctx, inst, 717 &ipp_regs[inst], &ipp_shift, &ipp_mask); 718 return &ipp->base; 719 } 720 721 static struct dpp *dcn21_dpp_create( 722 struct dc_context *ctx, 723 uint32_t inst) 724 { 725 struct dcn20_dpp *dpp = 726 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL); 727 728 if (!dpp) 729 return NULL; 730 731 if (dpp2_construct(dpp, ctx, inst, 732 &tf_regs[inst], &tf_shift, &tf_mask)) 733 return &dpp->base; 734 735 BREAK_TO_DEBUGGER(); 736 kfree(dpp); 737 return NULL; 738 } 739 740 static struct dce_aux *dcn21_aux_engine_create( 741 struct dc_context *ctx, 742 uint32_t inst) 743 { 744 struct aux_engine_dce110 *aux_engine = 745 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 746 747 if (!aux_engine) 748 return NULL; 749 750 dce110_aux_engine_construct(aux_engine, ctx, inst, 751 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 752 &aux_engine_regs[inst], 753 &aux_mask, 754 &aux_shift, 755 ctx->dc->caps.extended_aux_timeout_support); 756 757 return &aux_engine->base; 758 } 759 760 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 761 762 static const struct dce_i2c_registers i2c_hw_regs[] = { 763 i2c_inst_regs(1), 764 i2c_inst_regs(2), 765 i2c_inst_regs(3), 766 i2c_inst_regs(4), 767 i2c_inst_regs(5), 768 }; 769 770 static const struct dce_i2c_shift i2c_shifts = { 771 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 772 }; 773 774 static const struct dce_i2c_mask i2c_masks = { 775 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 776 }; 777 778 struct dce_i2c_hw *dcn21_i2c_hw_create( 779 struct dc_context *ctx, 780 uint32_t inst) 781 { 782 struct dce_i2c_hw *dce_i2c_hw = 783 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 784 785 if (!dce_i2c_hw) 786 return NULL; 787 788 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 789 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 790 791 return dce_i2c_hw; 792 } 793 794 static const struct resource_caps res_cap_rn = { 795 .num_timing_generator = 4, 796 .num_opp = 4, 797 .num_video_plane = 4, 798 .num_audio = 4, // 4 audio endpoints. 4 audio streams 799 .num_stream_encoder = 5, 800 .num_pll = 5, // maybe 3 because the last two used for USB-c 801 .num_dwb = 1, 802 .num_ddc = 5, 803 .num_vmid = 1, 804 .num_dsc = 3, 805 }; 806 807 #ifdef DIAGS_BUILD 808 static const struct resource_caps res_cap_rn_FPGA_4pipe = { 809 .num_timing_generator = 4, 810 .num_opp = 4, 811 .num_video_plane = 4, 812 .num_audio = 7, 813 .num_stream_encoder = 4, 814 .num_pll = 4, 815 .num_dwb = 1, 816 .num_ddc = 4, 817 .num_dsc = 0, 818 }; 819 820 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = { 821 .num_timing_generator = 2, 822 .num_opp = 2, 823 .num_video_plane = 2, 824 .num_audio = 7, 825 .num_stream_encoder = 2, 826 .num_pll = 4, 827 .num_dwb = 1, 828 .num_ddc = 4, 829 .num_dsc = 2, 830 }; 831 #endif 832 833 static const struct dc_plane_cap plane_cap = { 834 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 835 .blends_with_above = true, 836 .blends_with_below = true, 837 .per_pixel_alpha = true, 838 839 .pixel_format_support = { 840 .argb8888 = true, 841 .nv12 = true, 842 .fp16 = true, 843 .p010 = true 844 }, 845 846 .max_upscale_factor = { 847 .argb8888 = 16000, 848 .nv12 = 16000, 849 .fp16 = 16000 850 }, 851 852 .max_downscale_factor = { 853 .argb8888 = 250, 854 .nv12 = 250, 855 .fp16 = 250 856 } 857 }; 858 859 static const struct dc_debug_options debug_defaults_drv = { 860 .disable_dmcu = false, 861 .force_abm_enable = false, 862 .timing_trace = false, 863 .clock_trace = true, 864 .disable_pplib_clock_request = true, 865 .min_disp_clk_khz = 100000, 866 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 867 .force_single_disp_pipe_split = false, 868 .disable_dcc = DCC_ENABLE, 869 .vsr_support = true, 870 .performance_trace = false, 871 .max_downscale_src_width = 4096, 872 .disable_pplib_wm_range = false, 873 .scl_reset_length10 = true, 874 .sanity_checks = true, 875 .disable_48mhz_pwrdwn = false, 876 .nv12_iflip_vm_wa = true, 877 .usbc_combo_phy_reset_wa = true 878 }; 879 880 static const struct dc_debug_options debug_defaults_diags = { 881 .disable_dmcu = false, 882 .force_abm_enable = false, 883 .timing_trace = true, 884 .clock_trace = true, 885 .disable_dpp_power_gate = true, 886 .disable_hubp_power_gate = true, 887 .disable_clock_gate = true, 888 .disable_pplib_clock_request = true, 889 .disable_pplib_wm_range = true, 890 .disable_stutter = true, 891 .disable_48mhz_pwrdwn = true, 892 }; 893 894 enum dcn20_clk_src_array_id { 895 DCN20_CLK_SRC_PLL0, 896 DCN20_CLK_SRC_PLL1, 897 DCN20_CLK_SRC_PLL2, 898 DCN20_CLK_SRC_TOTAL_DCN21 899 }; 900 901 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) 902 { 903 unsigned int i; 904 905 for (i = 0; i < pool->base.stream_enc_count; i++) { 906 if (pool->base.stream_enc[i] != NULL) { 907 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 908 pool->base.stream_enc[i] = NULL; 909 } 910 } 911 912 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 913 if (pool->base.dscs[i] != NULL) 914 dcn20_dsc_destroy(&pool->base.dscs[i]); 915 } 916 917 if (pool->base.mpc != NULL) { 918 kfree(TO_DCN20_MPC(pool->base.mpc)); 919 pool->base.mpc = NULL; 920 } 921 if (pool->base.hubbub != NULL) { 922 kfree(pool->base.hubbub); 923 pool->base.hubbub = NULL; 924 } 925 for (i = 0; i < pool->base.pipe_count; i++) { 926 if (pool->base.dpps[i] != NULL) 927 dcn20_dpp_destroy(&pool->base.dpps[i]); 928 929 if (pool->base.ipps[i] != NULL) 930 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 931 932 if (pool->base.hubps[i] != NULL) { 933 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 934 pool->base.hubps[i] = NULL; 935 } 936 937 if (pool->base.irqs != NULL) { 938 dal_irq_service_destroy(&pool->base.irqs); 939 } 940 } 941 942 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 943 if (pool->base.engines[i] != NULL) 944 dce110_engine_destroy(&pool->base.engines[i]); 945 if (pool->base.hw_i2cs[i] != NULL) { 946 kfree(pool->base.hw_i2cs[i]); 947 pool->base.hw_i2cs[i] = NULL; 948 } 949 if (pool->base.sw_i2cs[i] != NULL) { 950 kfree(pool->base.sw_i2cs[i]); 951 pool->base.sw_i2cs[i] = NULL; 952 } 953 } 954 955 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 956 if (pool->base.opps[i] != NULL) 957 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 958 } 959 960 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 961 if (pool->base.timing_generators[i] != NULL) { 962 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 963 pool->base.timing_generators[i] = NULL; 964 } 965 } 966 967 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 968 if (pool->base.dwbc[i] != NULL) { 969 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); 970 pool->base.dwbc[i] = NULL; 971 } 972 if (pool->base.mcif_wb[i] != NULL) { 973 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); 974 pool->base.mcif_wb[i] = NULL; 975 } 976 } 977 978 for (i = 0; i < pool->base.audio_count; i++) { 979 if (pool->base.audios[i]) 980 dce_aud_destroy(&pool->base.audios[i]); 981 } 982 983 for (i = 0; i < pool->base.clk_src_count; i++) { 984 if (pool->base.clock_sources[i] != NULL) { 985 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 986 pool->base.clock_sources[i] = NULL; 987 } 988 } 989 990 if (pool->base.dp_clock_source != NULL) { 991 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 992 pool->base.dp_clock_source = NULL; 993 } 994 995 if (pool->base.abm != NULL) { 996 if (pool->base.abm->ctx->dc->config.disable_dmcu) 997 dmub_abm_destroy(&pool->base.abm); 998 else 999 dce_abm_destroy(&pool->base.abm); 1000 } 1001 1002 if (pool->base.dmcu != NULL) 1003 dce_dmcu_destroy(&pool->base.dmcu); 1004 1005 if (pool->base.psr != NULL) 1006 dmub_psr_destroy(&pool->base.psr); 1007 1008 if (pool->base.dccg != NULL) 1009 dcn_dccg_destroy(&pool->base.dccg); 1010 1011 if (pool->base.pp_smu != NULL) 1012 dcn21_pp_smu_destroy(&pool->base.pp_smu); 1013 } 1014 1015 1016 static void calculate_wm_set_for_vlevel( 1017 int vlevel, 1018 struct wm_range_table_entry *table_entry, 1019 struct dcn_watermarks *wm_set, 1020 struct display_mode_lib *dml, 1021 display_e2e_pipe_params_st *pipes, 1022 int pipe_cnt) 1023 { 1024 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; 1025 1026 ASSERT(vlevel < dml->soc.num_states); 1027 /* only pipe 0 is read for voltage and dcf/soc clocks */ 1028 pipes[0].clks_cfg.voltage = vlevel; 1029 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; 1030 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; 1031 1032 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; 1033 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; 1034 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; 1035 1036 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; 1037 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; 1038 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; 1039 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 1040 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; 1041 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; 1042 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; 1043 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000; 1044 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; 1045 1046 } 1047 1048 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) 1049 { 1050 int i; 1051 1052 DC_FP_START(); 1053 1054 if (dc->bb_overrides.sr_exit_time_ns) { 1055 for (i = 0; i < WM_SET_COUNT; i++) { 1056 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us = 1057 dc->bb_overrides.sr_exit_time_ns / 1000.0; 1058 } 1059 } 1060 1061 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) { 1062 for (i = 0; i < WM_SET_COUNT; i++) { 1063 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us = 1064 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 1065 } 1066 } 1067 1068 if (dc->bb_overrides.urgent_latency_ns) { 1069 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 1070 } 1071 1072 if (dc->bb_overrides.dram_clock_change_latency_ns) { 1073 for (i = 0; i < WM_SET_COUNT; i++) { 1074 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us = 1075 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 1076 } 1077 } 1078 1079 DC_FP_END(); 1080 } 1081 1082 void dcn21_calculate_wm( 1083 struct dc *dc, struct dc_state *context, 1084 display_e2e_pipe_params_st *pipes, 1085 int *out_pipe_cnt, 1086 int *pipe_split_from, 1087 int vlevel_req) 1088 { 1089 int pipe_cnt, i, pipe_idx; 1090 int vlevel, vlevel_max; 1091 struct wm_range_table_entry *table_entry; 1092 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; 1093 1094 ASSERT(bw_params); 1095 1096 patch_bounding_box(dc, &context->bw_ctx.dml.soc); 1097 1098 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1099 if (!context->res_ctx.pipe_ctx[i].stream) 1100 continue; 1101 1102 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 1103 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb]; 1104 1105 if (pipe_split_from[i] < 0) { 1106 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1107 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; 1108 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) 1109 pipes[pipe_cnt].pipe.dest.odm_combine = 1110 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx]; 1111 else 1112 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1113 pipe_idx++; 1114 } else { 1115 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1116 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; 1117 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) 1118 pipes[pipe_cnt].pipe.dest.odm_combine = 1119 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]]; 1120 else 1121 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1122 } 1123 pipe_cnt++; 1124 } 1125 1126 if (pipe_cnt != pipe_idx) { 1127 if (dc->res_pool->funcs->populate_dml_pipes) 1128 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, 1129 context, pipes); 1130 else 1131 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc, 1132 context, pipes); 1133 } 1134 1135 *out_pipe_cnt = pipe_cnt; 1136 1137 vlevel_max = bw_params->clk_table.num_entries - 1; 1138 1139 1140 /* WM Set D */ 1141 table_entry = &bw_params->wm_table.entries[WM_D]; 1142 if (table_entry->wm_type == WM_TYPE_RETRAINING) 1143 vlevel = 0; 1144 else 1145 vlevel = vlevel_max; 1146 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, 1147 &context->bw_ctx.dml, pipes, pipe_cnt); 1148 /* WM Set C */ 1149 table_entry = &bw_params->wm_table.entries[WM_C]; 1150 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max); 1151 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, 1152 &context->bw_ctx.dml, pipes, pipe_cnt); 1153 /* WM Set B */ 1154 table_entry = &bw_params->wm_table.entries[WM_B]; 1155 vlevel = MIN(MAX(vlevel_req, 1), vlevel_max); 1156 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, 1157 &context->bw_ctx.dml, pipes, pipe_cnt); 1158 1159 /* WM Set A */ 1160 table_entry = &bw_params->wm_table.entries[WM_A]; 1161 vlevel = MIN(vlevel_req, vlevel_max); 1162 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, 1163 &context->bw_ctx.dml, pipes, pipe_cnt); 1164 } 1165 1166 1167 bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context, 1168 bool fast_validate) 1169 { 1170 bool out = false; 1171 1172 BW_VAL_TRACE_SETUP(); 1173 1174 int vlevel = 0; 1175 int pipe_split_from[MAX_PIPES]; 1176 int pipe_cnt = 0; 1177 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1178 DC_LOGGER_INIT(dc->ctx->logger); 1179 1180 BW_VAL_TRACE_COUNT(); 1181 1182 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel); 1183 1184 if (pipe_cnt == 0) 1185 goto validate_out; 1186 1187 if (!out) 1188 goto validate_fail; 1189 1190 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1191 1192 if (fast_validate) { 1193 BW_VAL_TRACE_SKIP(fast); 1194 goto validate_out; 1195 } 1196 1197 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel); 1198 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 1199 1200 BW_VAL_TRACE_END_WATERMARKS(); 1201 1202 goto validate_out; 1203 1204 validate_fail: 1205 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1206 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1207 1208 BW_VAL_TRACE_SKIP(fail); 1209 out = false; 1210 1211 validate_out: 1212 kfree(pipes); 1213 1214 BW_VAL_TRACE_FINISH(); 1215 1216 return out; 1217 } 1218 static void dcn21_destroy_resource_pool(struct resource_pool **pool) 1219 { 1220 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool); 1221 1222 dcn21_resource_destruct(dcn21_pool); 1223 kfree(dcn21_pool); 1224 *pool = NULL; 1225 } 1226 1227 static struct clock_source *dcn21_clock_source_create( 1228 struct dc_context *ctx, 1229 struct dc_bios *bios, 1230 enum clock_source_id id, 1231 const struct dce110_clk_src_regs *regs, 1232 bool dp_clk_src) 1233 { 1234 struct dce110_clk_src *clk_src = 1235 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1236 1237 if (!clk_src) 1238 return NULL; 1239 1240 if (dcn20_clk_src_construct(clk_src, ctx, bios, id, 1241 regs, &cs_shift, &cs_mask)) { 1242 clk_src->base.dp_clk_src = dp_clk_src; 1243 return &clk_src->base; 1244 } 1245 1246 BREAK_TO_DEBUGGER(); 1247 return NULL; 1248 } 1249 1250 static struct hubp *dcn21_hubp_create( 1251 struct dc_context *ctx, 1252 uint32_t inst) 1253 { 1254 struct dcn21_hubp *hubp21 = 1255 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL); 1256 1257 if (!hubp21) 1258 return NULL; 1259 1260 if (hubp21_construct(hubp21, ctx, inst, 1261 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1262 return &hubp21->base; 1263 1264 BREAK_TO_DEBUGGER(); 1265 kfree(hubp21); 1266 return NULL; 1267 } 1268 1269 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx) 1270 { 1271 int i; 1272 1273 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), 1274 GFP_KERNEL); 1275 1276 if (!hubbub) 1277 return NULL; 1278 1279 hubbub21_construct(hubbub, ctx, 1280 &hubbub_reg, 1281 &hubbub_shift, 1282 &hubbub_mask); 1283 1284 for (i = 0; i < res_cap_rn.num_vmid; i++) { 1285 struct dcn20_vmid *vmid = &hubbub->vmid[i]; 1286 1287 vmid->ctx = ctx; 1288 1289 vmid->regs = &vmid_regs[i]; 1290 vmid->shifts = &vmid_shifts; 1291 vmid->masks = &vmid_masks; 1292 } 1293 1294 return &hubbub->base; 1295 } 1296 1297 struct output_pixel_processor *dcn21_opp_create( 1298 struct dc_context *ctx, uint32_t inst) 1299 { 1300 struct dcn20_opp *opp = 1301 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1302 1303 if (!opp) { 1304 BREAK_TO_DEBUGGER(); 1305 return NULL; 1306 } 1307 1308 dcn20_opp_construct(opp, ctx, inst, 1309 &opp_regs[inst], &opp_shift, &opp_mask); 1310 return &opp->base; 1311 } 1312 1313 struct timing_generator *dcn21_timing_generator_create( 1314 struct dc_context *ctx, 1315 uint32_t instance) 1316 { 1317 struct optc *tgn10 = 1318 kzalloc(sizeof(struct optc), GFP_KERNEL); 1319 1320 if (!tgn10) 1321 return NULL; 1322 1323 tgn10->base.inst = instance; 1324 tgn10->base.ctx = ctx; 1325 1326 tgn10->tg_regs = &tg_regs[instance]; 1327 tgn10->tg_shift = &tg_shift; 1328 tgn10->tg_mask = &tg_mask; 1329 1330 dcn20_timing_generator_init(tgn10); 1331 1332 return &tgn10->base; 1333 } 1334 1335 struct mpc *dcn21_mpc_create(struct dc_context *ctx) 1336 { 1337 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), 1338 GFP_KERNEL); 1339 1340 if (!mpc20) 1341 return NULL; 1342 1343 dcn20_mpc_construct(mpc20, ctx, 1344 &mpc_regs, 1345 &mpc_shift, 1346 &mpc_mask, 1347 6); 1348 1349 return &mpc20->base; 1350 } 1351 1352 static void read_dce_straps( 1353 struct dc_context *ctx, 1354 struct resource_straps *straps) 1355 { 1356 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1357 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1358 1359 } 1360 1361 1362 struct display_stream_compressor *dcn21_dsc_create( 1363 struct dc_context *ctx, uint32_t inst) 1364 { 1365 struct dcn20_dsc *dsc = 1366 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1367 1368 if (!dsc) { 1369 BREAK_TO_DEBUGGER(); 1370 return NULL; 1371 } 1372 1373 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1374 return &dsc->base; 1375 } 1376 1377 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1378 { 1379 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool); 1380 struct clk_limit_table *clk_table = &bw_params->clk_table; 1381 unsigned int i, j, k; 1382 int closest_clk_lvl; 1383 1384 // Default clock levels are used for diags, which may lead to overclocking. 1385 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) && !IS_DIAG_DC(dc->ctx->dce_environment)) { 1386 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator; 1387 dcn2_1_ip.max_num_dpp = pool->base.pipe_count; 1388 dcn2_1_soc.num_chans = bw_params->num_channels; 1389 1390 /* Vmin: leave lowest DCN clocks, override with dcfclk, fclk, memclk from fuse */ 1391 dcn2_1_soc.clock_limits[0].state = 0; 1392 dcn2_1_soc.clock_limits[0].dcfclk_mhz = clk_table->entries[0].dcfclk_mhz; 1393 dcn2_1_soc.clock_limits[0].fabricclk_mhz = clk_table->entries[0].fclk_mhz; 1394 dcn2_1_soc.clock_limits[0].socclk_mhz = clk_table->entries[0].socclk_mhz; 1395 dcn2_1_soc.clock_limits[0].dram_speed_mts = clk_table->entries[0].memclk_mhz * 2; 1396 1397 /* 1398 * Other levels: find closest DCN clocks that fit the given clock limit using dcfclk 1399 * as indicator 1400 */ 1401 1402 closest_clk_lvl = -1; 1403 /* index currently being filled */ 1404 k = 1; 1405 for (i = 1; i < clk_table->num_entries; i++) { 1406 /* loop backwards, skip duplicate state*/ 1407 for (j = dcn2_1_soc.num_states - 1; j >= k; j--) { 1408 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { 1409 closest_clk_lvl = j; 1410 break; 1411 } 1412 } 1413 1414 /* if found a lvl that fits, use the DCN clks from it, if not, go to next clk limit*/ 1415 if (closest_clk_lvl != -1) { 1416 dcn2_1_soc.clock_limits[k].state = i; 1417 dcn2_1_soc.clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 1418 dcn2_1_soc.clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 1419 dcn2_1_soc.clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz; 1420 dcn2_1_soc.clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; 1421 1422 dcn2_1_soc.clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; 1423 dcn2_1_soc.clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; 1424 dcn2_1_soc.clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; 1425 dcn2_1_soc.clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; 1426 dcn2_1_soc.clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; 1427 dcn2_1_soc.clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; 1428 dcn2_1_soc.clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; 1429 k++; 1430 } 1431 } 1432 dcn2_1_soc.num_states = k; 1433 } 1434 1435 /* duplicate last level */ 1436 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1]; 1437 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states; 1438 1439 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); 1440 } 1441 1442 /* Temporary Place holder until we can get them from fuse */ 1443 static struct dpm_clocks dummy_clocks = { 1444 .DcfClocks = { 1445 {.Freq = 400, .Vol = 1}, 1446 {.Freq = 483, .Vol = 1}, 1447 {.Freq = 602, .Vol = 1}, 1448 {.Freq = 738, .Vol = 1} }, 1449 .SocClocks = { 1450 {.Freq = 300, .Vol = 1}, 1451 {.Freq = 400, .Vol = 1}, 1452 {.Freq = 400, .Vol = 1}, 1453 {.Freq = 400, .Vol = 1} }, 1454 .FClocks = { 1455 {.Freq = 400, .Vol = 1}, 1456 {.Freq = 800, .Vol = 1}, 1457 {.Freq = 1067, .Vol = 1}, 1458 {.Freq = 1600, .Vol = 1} }, 1459 .MemClocks = { 1460 {.Freq = 800, .Vol = 1}, 1461 {.Freq = 1600, .Vol = 1}, 1462 {.Freq = 1067, .Vol = 1}, 1463 {.Freq = 1600, .Vol = 1} }, 1464 1465 }; 1466 1467 static enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp, 1468 struct pp_smu_wm_range_sets *ranges) 1469 { 1470 return PP_SMU_RESULT_OK; 1471 } 1472 1473 static enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp, 1474 struct dpm_clocks *clock_table) 1475 { 1476 *clock_table = dummy_clocks; 1477 return PP_SMU_RESULT_OK; 1478 } 1479 1480 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx) 1481 { 1482 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 1483 1484 if (!pp_smu) 1485 return pp_smu; 1486 1487 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) { 1488 pp_smu->ctx.ver = PP_SMU_VER_RN; 1489 pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table; 1490 pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges; 1491 } else { 1492 1493 dm_pp_get_funcs(ctx, pp_smu); 1494 1495 if (pp_smu->ctx.ver != PP_SMU_VER_RN) 1496 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); 1497 } 1498 1499 return pp_smu; 1500 } 1501 1502 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu) 1503 { 1504 if (pp_smu && *pp_smu) { 1505 kfree(*pp_smu); 1506 *pp_smu = NULL; 1507 } 1508 } 1509 1510 static struct audio *dcn21_create_audio( 1511 struct dc_context *ctx, unsigned int inst) 1512 { 1513 return dce_audio_create(ctx, inst, 1514 &audio_regs[inst], &audio_shift, &audio_mask); 1515 } 1516 1517 static struct dc_cap_funcs cap_funcs = { 1518 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1519 }; 1520 1521 struct stream_encoder *dcn21_stream_encoder_create( 1522 enum engine_id eng_id, 1523 struct dc_context *ctx) 1524 { 1525 struct dcn10_stream_encoder *enc1 = 1526 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1527 1528 if (!enc1) 1529 return NULL; 1530 1531 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1532 &stream_enc_regs[eng_id], 1533 &se_shift, &se_mask); 1534 1535 return &enc1->base; 1536 } 1537 1538 static const struct dce_hwseq_registers hwseq_reg = { 1539 HWSEQ_DCN21_REG_LIST() 1540 }; 1541 1542 static const struct dce_hwseq_shift hwseq_shift = { 1543 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT) 1544 }; 1545 1546 static const struct dce_hwseq_mask hwseq_mask = { 1547 HWSEQ_DCN21_MASK_SH_LIST(_MASK) 1548 }; 1549 1550 static struct dce_hwseq *dcn21_hwseq_create( 1551 struct dc_context *ctx) 1552 { 1553 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1554 1555 if (hws) { 1556 hws->ctx = ctx; 1557 hws->regs = &hwseq_reg; 1558 hws->shifts = &hwseq_shift; 1559 hws->masks = &hwseq_mask; 1560 hws->wa.DEGVIDCN21 = true; 1561 hws->wa.disallow_self_refresh_during_multi_plane_transition = true; 1562 } 1563 return hws; 1564 } 1565 1566 static const struct resource_create_funcs res_create_funcs = { 1567 .read_dce_straps = read_dce_straps, 1568 .create_audio = dcn21_create_audio, 1569 .create_stream_encoder = dcn21_stream_encoder_create, 1570 .create_hwseq = dcn21_hwseq_create, 1571 }; 1572 1573 static const struct resource_create_funcs res_create_maximus_funcs = { 1574 .read_dce_straps = NULL, 1575 .create_audio = NULL, 1576 .create_stream_encoder = NULL, 1577 .create_hwseq = dcn21_hwseq_create, 1578 }; 1579 1580 static const struct encoder_feature_support link_enc_feature = { 1581 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1582 .max_hdmi_pixel_clock = 600000, 1583 .hdmi_ycbcr420_supported = true, 1584 .dp_ycbcr420_supported = true, 1585 .fec_supported = true, 1586 .flags.bits.IS_HBR2_CAPABLE = true, 1587 .flags.bits.IS_HBR3_CAPABLE = true, 1588 .flags.bits.IS_TPS3_CAPABLE = true, 1589 .flags.bits.IS_TPS4_CAPABLE = true 1590 }; 1591 1592 1593 #define link_regs(id, phyid)\ 1594 [id] = {\ 1595 LE_DCN2_REG_LIST(id), \ 1596 UNIPHY_DCN2_REG_LIST(phyid), \ 1597 DPCS_DCN21_REG_LIST(id), \ 1598 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 1599 } 1600 1601 static const struct dcn10_link_enc_registers link_enc_regs[] = { 1602 link_regs(0, A), 1603 link_regs(1, B), 1604 link_regs(2, C), 1605 link_regs(3, D), 1606 link_regs(4, E), 1607 }; 1608 1609 #define aux_regs(id)\ 1610 [id] = {\ 1611 DCN2_AUX_REG_LIST(id)\ 1612 } 1613 1614 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 1615 aux_regs(0), 1616 aux_regs(1), 1617 aux_regs(2), 1618 aux_regs(3), 1619 aux_regs(4) 1620 }; 1621 1622 #define hpd_regs(id)\ 1623 [id] = {\ 1624 HPD_REG_LIST(id)\ 1625 } 1626 1627 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 1628 hpd_regs(0), 1629 hpd_regs(1), 1630 hpd_regs(2), 1631 hpd_regs(3), 1632 hpd_regs(4) 1633 }; 1634 1635 static const struct dcn10_link_enc_shift le_shift = { 1636 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\ 1637 DPCS_DCN21_MASK_SH_LIST(__SHIFT) 1638 }; 1639 1640 static const struct dcn10_link_enc_mask le_mask = { 1641 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\ 1642 DPCS_DCN21_MASK_SH_LIST(_MASK) 1643 }; 1644 1645 static int map_transmitter_id_to_phy_instance( 1646 enum transmitter transmitter) 1647 { 1648 switch (transmitter) { 1649 case TRANSMITTER_UNIPHY_A: 1650 return 0; 1651 break; 1652 case TRANSMITTER_UNIPHY_B: 1653 return 1; 1654 break; 1655 case TRANSMITTER_UNIPHY_C: 1656 return 2; 1657 break; 1658 case TRANSMITTER_UNIPHY_D: 1659 return 3; 1660 break; 1661 case TRANSMITTER_UNIPHY_E: 1662 return 4; 1663 break; 1664 default: 1665 ASSERT(0); 1666 return 0; 1667 } 1668 } 1669 1670 static struct link_encoder *dcn21_link_encoder_create( 1671 const struct encoder_init_data *enc_init_data) 1672 { 1673 struct dcn21_link_encoder *enc21 = 1674 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL); 1675 int link_regs_id; 1676 1677 if (!enc21) 1678 return NULL; 1679 1680 link_regs_id = 1681 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 1682 1683 dcn21_link_encoder_construct(enc21, 1684 enc_init_data, 1685 &link_enc_feature, 1686 &link_enc_regs[link_regs_id], 1687 &link_enc_aux_regs[enc_init_data->channel - 1], 1688 &link_enc_hpd_regs[enc_init_data->hpd_source], 1689 &le_shift, 1690 &le_mask); 1691 1692 return &enc21->enc10.base; 1693 } 1694 #define CTX ctx 1695 1696 #define REG(reg_name) \ 1697 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 1698 1699 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1700 { 1701 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 1702 /* RV1 support max 4 pipes */ 1703 value = value & 0xf; 1704 return value; 1705 } 1706 1707 static int dcn21_populate_dml_pipes_from_context( 1708 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes) 1709 { 1710 uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes); 1711 int i; 1712 struct resource_context *res_ctx = &context->res_ctx; 1713 1714 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1715 1716 if (!res_ctx->pipe_ctx[i].stream) 1717 continue; 1718 1719 pipes[i].pipe.src.hostvm = 1; 1720 pipes[i].pipe.src.gpuvm = 1; 1721 } 1722 1723 return pipe_cnt; 1724 } 1725 1726 enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state) 1727 { 1728 enum dc_status result = DC_OK; 1729 1730 if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) { 1731 plane_state->dcc.enable = 1; 1732 /* align to our worst case block width */ 1733 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024; 1734 } 1735 result = dcn20_patch_unknown_plane_state(plane_state); 1736 return result; 1737 } 1738 1739 static struct resource_funcs dcn21_res_pool_funcs = { 1740 .destroy = dcn21_destroy_resource_pool, 1741 .link_enc_create = dcn21_link_encoder_create, 1742 .validate_bandwidth = dcn21_validate_bandwidth, 1743 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context, 1744 .add_stream_to_ctx = dcn20_add_stream_to_ctx, 1745 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1746 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1747 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, 1748 .patch_unknown_plane_state = dcn21_patch_unknown_plane_state, 1749 .set_mcif_arb_params = dcn20_set_mcif_arb_params, 1750 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1751 .update_bw_bounding_box = update_bw_bounding_box 1752 }; 1753 1754 static bool dcn21_resource_construct( 1755 uint8_t num_virtual_links, 1756 struct dc *dc, 1757 struct dcn21_resource_pool *pool) 1758 { 1759 int i, j; 1760 struct dc_context *ctx = dc->ctx; 1761 struct irq_service_init_data init_data; 1762 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1763 uint32_t num_pipes; 1764 1765 ctx->dc_bios->regs = &bios_regs; 1766 1767 pool->base.res_cap = &res_cap_rn; 1768 #ifdef DIAGS_BUILD 1769 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1770 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc; 1771 pool->base.res_cap = &res_cap_rn_FPGA_4pipe; 1772 #endif 1773 1774 pool->base.funcs = &dcn21_res_pool_funcs; 1775 1776 /************************************************* 1777 * Resource + asic cap harcoding * 1778 *************************************************/ 1779 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1780 1781 /* max pipe num for ASIC before check pipe fuses */ 1782 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1783 1784 dc->caps.max_downscale_ratio = 200; 1785 dc->caps.i2c_speed_in_khz = 100; 1786 dc->caps.max_cursor_size = 256; 1787 dc->caps.dmdata_alloc_size = 2048; 1788 dc->caps.hw_3d_lut = true; 1789 1790 dc->caps.max_slave_planes = 1; 1791 dc->caps.post_blend_color_processing = true; 1792 dc->caps.force_dp_tps4_for_cp2520 = true; 1793 dc->caps.extended_aux_timeout_support = true; 1794 dc->caps.dmcub_support = true; 1795 dc->caps.is_apu = true; 1796 1797 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1798 dc->debug = debug_defaults_drv; 1799 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1800 pool->base.pipe_count = 4; 1801 dc->debug = debug_defaults_diags; 1802 } else 1803 dc->debug = debug_defaults_diags; 1804 1805 // Init the vm_helper 1806 if (dc->vm_helper) 1807 vm_helper_init(dc->vm_helper, 16); 1808 1809 /************************************************* 1810 * Create resources * 1811 *************************************************/ 1812 1813 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = 1814 dcn21_clock_source_create(ctx, ctx->dc_bios, 1815 CLOCK_SOURCE_COMBO_PHY_PLL0, 1816 &clk_src_regs[0], false); 1817 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = 1818 dcn21_clock_source_create(ctx, ctx->dc_bios, 1819 CLOCK_SOURCE_COMBO_PHY_PLL1, 1820 &clk_src_regs[1], false); 1821 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = 1822 dcn21_clock_source_create(ctx, ctx->dc_bios, 1823 CLOCK_SOURCE_COMBO_PHY_PLL2, 1824 &clk_src_regs[2], false); 1825 1826 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21; 1827 1828 /* todo: not reuse phy_pll registers */ 1829 pool->base.dp_clock_source = 1830 dcn21_clock_source_create(ctx, ctx->dc_bios, 1831 CLOCK_SOURCE_ID_DP_DTO, 1832 &clk_src_regs[0], true); 1833 1834 for (i = 0; i < pool->base.clk_src_count; i++) { 1835 if (pool->base.clock_sources[i] == NULL) { 1836 dm_error("DC: failed to create clock sources!\n"); 1837 BREAK_TO_DEBUGGER(); 1838 goto create_fail; 1839 } 1840 } 1841 1842 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1843 if (pool->base.dccg == NULL) { 1844 dm_error("DC: failed to create dccg!\n"); 1845 BREAK_TO_DEBUGGER(); 1846 goto create_fail; 1847 } 1848 1849 if (!dc->config.disable_dmcu) { 1850 pool->base.dmcu = dcn21_dmcu_create(ctx, 1851 &dmcu_regs, 1852 &dmcu_shift, 1853 &dmcu_mask); 1854 if (pool->base.dmcu == NULL) { 1855 dm_error("DC: failed to create dmcu!\n"); 1856 BREAK_TO_DEBUGGER(); 1857 goto create_fail; 1858 } 1859 } 1860 1861 if (dc->config.disable_dmcu) { 1862 pool->base.psr = dmub_psr_create(ctx); 1863 1864 if (pool->base.psr == NULL) { 1865 dm_error("DC: failed to create psr obj!\n"); 1866 BREAK_TO_DEBUGGER(); 1867 goto create_fail; 1868 } 1869 } 1870 1871 if (dc->config.disable_dmcu) 1872 pool->base.abm = dmub_abm_create(ctx, 1873 &abm_regs, 1874 &abm_shift, 1875 &abm_mask); 1876 else 1877 pool->base.abm = dce_abm_create(ctx, 1878 &abm_regs, 1879 &abm_shift, 1880 &abm_mask); 1881 1882 pool->base.pp_smu = dcn21_pp_smu_create(ctx); 1883 1884 num_pipes = dcn2_1_ip.max_num_dpp; 1885 1886 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++) 1887 if (pipe_fuses & 1 << i) 1888 num_pipes--; 1889 dcn2_1_ip.max_num_dpp = num_pipes; 1890 dcn2_1_ip.max_num_otg = num_pipes; 1891 1892 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); 1893 1894 init_data.ctx = dc->ctx; 1895 pool->base.irqs = dal_irq_service_dcn21_create(&init_data); 1896 if (!pool->base.irqs) 1897 goto create_fail; 1898 1899 j = 0; 1900 /* mem input -> ipp -> dpp -> opp -> TG */ 1901 for (i = 0; i < pool->base.pipe_count; i++) { 1902 /* if pipe is disabled, skip instance of HW pipe, 1903 * i.e, skip ASIC register instance 1904 */ 1905 if ((pipe_fuses & (1 << i)) != 0) 1906 continue; 1907 1908 pool->base.hubps[j] = dcn21_hubp_create(ctx, i); 1909 if (pool->base.hubps[j] == NULL) { 1910 BREAK_TO_DEBUGGER(); 1911 dm_error( 1912 "DC: failed to create memory input!\n"); 1913 goto create_fail; 1914 } 1915 1916 pool->base.ipps[j] = dcn21_ipp_create(ctx, i); 1917 if (pool->base.ipps[j] == NULL) { 1918 BREAK_TO_DEBUGGER(); 1919 dm_error( 1920 "DC: failed to create input pixel processor!\n"); 1921 goto create_fail; 1922 } 1923 1924 pool->base.dpps[j] = dcn21_dpp_create(ctx, i); 1925 if (pool->base.dpps[j] == NULL) { 1926 BREAK_TO_DEBUGGER(); 1927 dm_error( 1928 "DC: failed to create dpps!\n"); 1929 goto create_fail; 1930 } 1931 1932 pool->base.opps[j] = dcn21_opp_create(ctx, i); 1933 if (pool->base.opps[j] == NULL) { 1934 BREAK_TO_DEBUGGER(); 1935 dm_error( 1936 "DC: failed to create output pixel processor!\n"); 1937 goto create_fail; 1938 } 1939 1940 pool->base.timing_generators[j] = dcn21_timing_generator_create( 1941 ctx, i); 1942 if (pool->base.timing_generators[j] == NULL) { 1943 BREAK_TO_DEBUGGER(); 1944 dm_error("DC: failed to create tg!\n"); 1945 goto create_fail; 1946 } 1947 j++; 1948 } 1949 1950 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1951 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i); 1952 if (pool->base.engines[i] == NULL) { 1953 BREAK_TO_DEBUGGER(); 1954 dm_error( 1955 "DC:failed to create aux engine!!\n"); 1956 goto create_fail; 1957 } 1958 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i); 1959 if (pool->base.hw_i2cs[i] == NULL) { 1960 BREAK_TO_DEBUGGER(); 1961 dm_error( 1962 "DC:failed to create hw i2c!!\n"); 1963 goto create_fail; 1964 } 1965 pool->base.sw_i2cs[i] = NULL; 1966 } 1967 1968 pool->base.timing_generator_count = j; 1969 pool->base.pipe_count = j; 1970 pool->base.mpcc_count = j; 1971 1972 pool->base.mpc = dcn21_mpc_create(ctx); 1973 if (pool->base.mpc == NULL) { 1974 BREAK_TO_DEBUGGER(); 1975 dm_error("DC: failed to create mpc!\n"); 1976 goto create_fail; 1977 } 1978 1979 pool->base.hubbub = dcn21_hubbub_create(ctx); 1980 if (pool->base.hubbub == NULL) { 1981 BREAK_TO_DEBUGGER(); 1982 dm_error("DC: failed to create hubbub!\n"); 1983 goto create_fail; 1984 } 1985 1986 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1987 pool->base.dscs[i] = dcn21_dsc_create(ctx, i); 1988 if (pool->base.dscs[i] == NULL) { 1989 BREAK_TO_DEBUGGER(); 1990 dm_error("DC: failed to create display stream compressor %d!\n", i); 1991 goto create_fail; 1992 } 1993 } 1994 1995 if (!dcn20_dwbc_create(ctx, &pool->base)) { 1996 BREAK_TO_DEBUGGER(); 1997 dm_error("DC: failed to create dwbc!\n"); 1998 goto create_fail; 1999 } 2000 if (!dcn20_mmhubbub_create(ctx, &pool->base)) { 2001 BREAK_TO_DEBUGGER(); 2002 dm_error("DC: failed to create mcif_wb!\n"); 2003 goto create_fail; 2004 } 2005 2006 if (!resource_construct(num_virtual_links, dc, &pool->base, 2007 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2008 &res_create_funcs : &res_create_maximus_funcs))) 2009 goto create_fail; 2010 2011 dcn21_hw_sequencer_construct(dc); 2012 2013 dc->caps.max_planes = pool->base.pipe_count; 2014 2015 for (i = 0; i < dc->caps.max_planes; ++i) 2016 dc->caps.planes[i] = plane_cap; 2017 2018 dc->cap_funcs = cap_funcs; 2019 2020 return true; 2021 2022 create_fail: 2023 2024 dcn21_resource_destruct(pool); 2025 2026 return false; 2027 } 2028 2029 struct resource_pool *dcn21_create_resource_pool( 2030 const struct dc_init_data *init_data, 2031 struct dc *dc) 2032 { 2033 struct dcn21_resource_pool *pool = 2034 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL); 2035 2036 if (!pool) 2037 return NULL; 2038 2039 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool)) 2040 return &pool->base; 2041 2042 BREAK_TO_DEBUGGER(); 2043 kfree(pool); 2044 return NULL; 2045 } 2046