1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dc.h" 28 29 #include "resource.h" 30 #include "include/irq_service_interface.h" 31 #include "dcn20/dcn20_resource.h" 32 33 #include "clk_mgr.h" 34 #include "dcn10/dcn10_hubp.h" 35 #include "dcn10/dcn10_ipp.h" 36 #include "dcn20/dcn20_hubbub.h" 37 #include "dcn20/dcn20_mpc.h" 38 #include "dcn20/dcn20_hubp.h" 39 #include "dcn21_hubp.h" 40 #include "irq/dcn21/irq_service_dcn21.h" 41 #include "dcn20/dcn20_dpp.h" 42 #include "dcn20/dcn20_optc.h" 43 #include "dcn21/dcn21_hwseq.h" 44 #include "dce110/dce110_hw_sequencer.h" 45 #include "dcn20/dcn20_opp.h" 46 #include "dcn20/dcn20_dsc.h" 47 #include "dcn21/dcn21_link_encoder.h" 48 #include "dcn20/dcn20_stream_encoder.h" 49 #include "dce/dce_clock_source.h" 50 #include "dce/dce_audio.h" 51 #include "dce/dce_hwseq.h" 52 #include "virtual/virtual_stream_encoder.h" 53 #include "dce110/dce110_resource.h" 54 #include "dml/display_mode_vba.h" 55 #include "dcn20/dcn20_dccg.h" 56 #include "dcn21_hubbub.h" 57 #include "dcn10/dcn10_resource.h" 58 59 #include "dcn20/dcn20_dwb.h" 60 #include "dcn20/dcn20_mmhubbub.h" 61 62 #include "renoir_ip_offset.h" 63 #include "dcn/dcn_2_1_0_offset.h" 64 #include "dcn/dcn_2_1_0_sh_mask.h" 65 66 #include "nbio/nbio_7_0_offset.h" 67 68 #include "mmhub/mmhub_2_0_0_offset.h" 69 #include "mmhub/mmhub_2_0_0_sh_mask.h" 70 71 #include "reg_helper.h" 72 #include "dce/dce_abm.h" 73 #include "dce/dce_dmcu.h" 74 #include "dce/dce_aux.h" 75 #include "dce/dce_i2c.h" 76 #include "dcn21_resource.h" 77 #include "vm_helper.h" 78 #include "dcn20/dcn20_vmid.h" 79 80 #define SOC_BOUNDING_BOX_VALID false 81 #define DC_LOGGER_INIT(logger) 82 83 84 struct _vcs_dpi_ip_params_st dcn2_1_ip = { 85 .odm_capable = 1, 86 .gpuvm_enable = 0, 87 .hostvm_enable = 0, 88 .gpuvm_max_page_table_levels = 1, 89 .hostvm_max_page_table_levels = 4, 90 .hostvm_cached_page_table_levels = 2, 91 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 92 .num_dsc = 3, 93 #else 94 .num_dsc = 0, 95 #endif 96 .rob_buffer_size_kbytes = 168, 97 .det_buffer_size_kbytes = 164, 98 .dpte_buffer_size_in_pte_reqs_luma = 44, 99 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo 100 .dpp_output_buffer_pixels = 2560, 101 .opp_output_buffer_lines = 1, 102 .pixel_chunk_size_kbytes = 8, 103 .pte_enable = 1, 104 .max_page_table_levels = 4, 105 .pte_chunk_size_kbytes = 2, 106 .meta_chunk_size_kbytes = 2, 107 .writeback_chunk_size_kbytes = 2, 108 .line_buffer_size_bits = 789504, 109 .is_line_buffer_bpp_fixed = 0, 110 .line_buffer_fixed_bpp = 0, 111 .dcc_supported = true, 112 .max_line_buffer_lines = 12, 113 .writeback_luma_buffer_size_kbytes = 12, 114 .writeback_chroma_buffer_size_kbytes = 8, 115 .writeback_chroma_line_buffer_width_pixels = 4, 116 .writeback_max_hscl_ratio = 1, 117 .writeback_max_vscl_ratio = 1, 118 .writeback_min_hscl_ratio = 1, 119 .writeback_min_vscl_ratio = 1, 120 .writeback_max_hscl_taps = 12, 121 .writeback_max_vscl_taps = 12, 122 .writeback_line_buffer_luma_buffer_size = 0, 123 .writeback_line_buffer_chroma_buffer_size = 14643, 124 .cursor_buffer_size = 8, 125 .cursor_chunk_size = 2, 126 .max_num_otg = 4, 127 .max_num_dpp = 4, 128 .max_num_wb = 1, 129 .max_dchub_pscl_bw_pix_per_clk = 4, 130 .max_pscl_lb_bw_pix_per_clk = 2, 131 .max_lb_vscl_bw_pix_per_clk = 4, 132 .max_vscl_hscl_bw_pix_per_clk = 4, 133 .max_hscl_ratio = 4, 134 .max_vscl_ratio = 4, 135 .hscl_mults = 4, 136 .vscl_mults = 4, 137 .max_hscl_taps = 8, 138 .max_vscl_taps = 8, 139 .dispclk_ramp_margin_percent = 1, 140 .underscan_factor = 1.10, 141 .min_vblank_lines = 32, // 142 .dppclk_delay_subtotal = 77, // 143 .dppclk_delay_scl_lb_only = 16, 144 .dppclk_delay_scl = 50, 145 .dppclk_delay_cnvc_formatter = 8, 146 .dppclk_delay_cnvc_cursor = 6, 147 .dispclk_delay_subtotal = 87, // 148 .dcfclk_cstate_latency = 10, // SRExitTime 149 .max_inter_dcn_tile_repeaters = 8, 150 151 .xfc_supported = false, 152 .xfc_fill_bw_overhead_percent = 10.0, 153 .xfc_fill_constant_bytes = 0, 154 .ptoi_supported = 0 155 }; 156 157 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { 158 .clock_limits = { 159 { 160 .state = 0, 161 .dcfclk_mhz = 304.0, 162 .fabricclk_mhz = 600.0, 163 .dispclk_mhz = 618.0, 164 .dppclk_mhz = 440.0, 165 .phyclk_mhz = 600.0, 166 .socclk_mhz = 278.0, 167 .dscclk_mhz = 205.67, 168 .dram_speed_mts = 1600.0, 169 }, 170 { 171 .state = 1, 172 .dcfclk_mhz = 304.0, 173 .fabricclk_mhz = 600.0, 174 .dispclk_mhz = 618.0, 175 .dppclk_mhz = 618.0, 176 .phyclk_mhz = 600.0, 177 .socclk_mhz = 278.0, 178 .dscclk_mhz = 205.67, 179 .dram_speed_mts = 1600.0, 180 }, 181 { 182 .state = 2, 183 .dcfclk_mhz = 608.0, 184 .fabricclk_mhz = 1066.0, 185 .dispclk_mhz = 888.0, 186 .dppclk_mhz = 888.0, 187 .phyclk_mhz = 810.0, 188 .socclk_mhz = 278.0, 189 .dscclk_mhz = 287.67, 190 .dram_speed_mts = 2133.0, 191 }, 192 { 193 .state = 3, 194 .dcfclk_mhz = 676.0, 195 .fabricclk_mhz = 1600.0, 196 .dispclk_mhz = 1015.0, 197 .dppclk_mhz = 1015.0, 198 .phyclk_mhz = 810.0, 199 .socclk_mhz = 715.0, 200 .dscclk_mhz = 318.334, 201 .dram_speed_mts = 4266.0, 202 }, 203 { 204 .state = 4, 205 .dcfclk_mhz = 810.0, 206 .fabricclk_mhz = 1600.0, 207 .dispclk_mhz = 1395.0, 208 .dppclk_mhz = 1285.0, 209 .phyclk_mhz = 1325.0, 210 .socclk_mhz = 953.0, 211 .dscclk_mhz = 489.0, 212 .dram_speed_mts = 4266.0, 213 }, 214 /*Extra state, no dispclk ramping*/ 215 { 216 .state = 5, 217 .dcfclk_mhz = 810.0, 218 .fabricclk_mhz = 1600.0, 219 .dispclk_mhz = 1395.0, 220 .dppclk_mhz = 1285.0, 221 .phyclk_mhz = 1325.0, 222 .socclk_mhz = 953.0, 223 .dscclk_mhz = 489.0, 224 .dram_speed_mts = 4266.0, 225 }, 226 227 }, 228 229 .sr_exit_time_us = 12.5, 230 .sr_enter_plus_exit_time_us = 17.0, 231 .urgent_latency_us = 4.0, 232 .urgent_latency_pixel_data_only_us = 4.0, 233 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 234 .urgent_latency_vm_data_only_us = 4.0, 235 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 236 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 237 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 238 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 239 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0, 240 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 241 .max_avg_sdp_bw_use_normal_percent = 60.0, 242 .max_avg_dram_bw_use_normal_percent = 100.0, 243 .writeback_latency_us = 12.0, 244 .max_request_size_bytes = 256, 245 .dram_channel_width_bytes = 4, 246 .fabric_datapath_to_dcn_data_return_bytes = 32, 247 .dcn_downspread_percent = 0.5, 248 .downspread_percent = 0.5, 249 .dram_page_open_time_ns = 50.0, 250 .dram_rw_turnaround_time_ns = 17.5, 251 .dram_return_buffer_per_channel_bytes = 8192, 252 .round_trip_ping_latency_dcfclk_cycles = 128, 253 .urgent_out_of_order_return_per_channel_bytes = 4096, 254 .channel_interleave_bytes = 256, 255 .num_banks = 8, 256 .num_chans = 4, 257 .vmm_page_size_bytes = 4096, 258 .dram_clock_change_latency_us = 23.84, 259 .return_bus_width_bytes = 64, 260 .dispclk_dppclk_vco_speed_mhz = 3550, 261 .xfc_bus_transport_time_us = 4, 262 .xfc_xbuf_latency_tolerance_us = 4, 263 .use_urgent_burst_bw = 1, 264 .num_states = 5 265 }; 266 267 #ifndef MAX 268 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y)) 269 #endif 270 #ifndef MIN 271 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 272 #endif 273 274 /* begin ********************* 275 * macros to expend register list macro defined in HW object header file */ 276 277 /* DCN */ 278 /* TODO awful hack. fixup dcn20_dwb.h */ 279 #undef BASE_INNER 280 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg 281 282 #define BASE(seg) BASE_INNER(seg) 283 284 #define SR(reg_name)\ 285 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 286 mm ## reg_name 287 288 #define SRI(reg_name, block, id)\ 289 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 290 mm ## block ## id ## _ ## reg_name 291 292 #define SRIR(var_name, reg_name, block, id)\ 293 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 294 mm ## block ## id ## _ ## reg_name 295 296 #define SRII(reg_name, block, id)\ 297 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 298 mm ## block ## id ## _ ## reg_name 299 300 #define DCCG_SRII(reg_name, block, id)\ 301 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 302 mm ## block ## id ## _ ## reg_name 303 304 /* NBIO */ 305 #define NBIO_BASE_INNER(seg) \ 306 NBIF0_BASE__INST0_SEG ## seg 307 308 #define NBIO_BASE(seg) \ 309 NBIO_BASE_INNER(seg) 310 311 #define NBIO_SR(reg_name)\ 312 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 313 mm ## reg_name 314 315 /* MMHUB */ 316 #define MMHUB_BASE_INNER(seg) \ 317 MMHUB_BASE__INST0_SEG ## seg 318 319 #define MMHUB_BASE(seg) \ 320 MMHUB_BASE_INNER(seg) 321 322 #define MMHUB_SR(reg_name)\ 323 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 324 mmMM ## reg_name 325 326 #define clk_src_regs(index, pllid)\ 327 [index] = {\ 328 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\ 329 } 330 331 static const struct dce110_clk_src_regs clk_src_regs[] = { 332 clk_src_regs(0, A), 333 clk_src_regs(1, B), 334 clk_src_regs(2, C), 335 clk_src_regs(3, D), 336 clk_src_regs(4, E), 337 }; 338 339 static const struct dce110_clk_src_shift cs_shift = { 340 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 341 }; 342 343 static const struct dce110_clk_src_mask cs_mask = { 344 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 345 }; 346 347 static const struct bios_registers bios_regs = { 348 NBIO_SR(BIOS_SCRATCH_3), 349 NBIO_SR(BIOS_SCRATCH_6) 350 }; 351 352 static const struct dce_dmcu_registers dmcu_regs = { 353 DMCU_DCN10_REG_LIST() 354 }; 355 356 static const struct dce_dmcu_shift dmcu_shift = { 357 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 358 }; 359 360 static const struct dce_dmcu_mask dmcu_mask = { 361 DMCU_MASK_SH_LIST_DCN10(_MASK) 362 }; 363 364 static const struct dce_abm_registers abm_regs = { 365 ABM_DCN20_REG_LIST() 366 }; 367 368 static const struct dce_abm_shift abm_shift = { 369 ABM_MASK_SH_LIST_DCN20(__SHIFT) 370 }; 371 372 static const struct dce_abm_mask abm_mask = { 373 ABM_MASK_SH_LIST_DCN20(_MASK) 374 }; 375 376 #ifdef CONFIG_DRM_AMD_DC_DMUB 377 static const struct dcn21_dmcub_registers dmcub_regs = { 378 DMCUB_REG_LIST_DCN() 379 }; 380 381 static const struct dcn21_dmcub_shift dmcub_shift = { 382 DMCUB_COMMON_MASK_SH_LIST_BASE(__SHIFT) 383 }; 384 385 static const struct dcn21_dmcub_mask dmcub_mask = { 386 DMCUB_COMMON_MASK_SH_LIST_BASE(_MASK) 387 }; 388 #endif 389 390 #define audio_regs(id)\ 391 [id] = {\ 392 AUD_COMMON_REG_LIST(id)\ 393 } 394 395 static const struct dce_audio_registers audio_regs[] = { 396 audio_regs(0), 397 audio_regs(1), 398 audio_regs(2), 399 audio_regs(3), 400 audio_regs(4), 401 audio_regs(5), 402 }; 403 404 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 405 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 406 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 407 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 408 409 static const struct dce_audio_shift audio_shift = { 410 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 411 }; 412 413 static const struct dce_audio_mask audio_mask = { 414 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 415 }; 416 417 static const struct dccg_registers dccg_regs = { 418 DCCG_COMMON_REG_LIST_DCN_BASE() 419 }; 420 421 static const struct dccg_shift dccg_shift = { 422 DCCG_MASK_SH_LIST_DCN2(__SHIFT) 423 }; 424 425 static const struct dccg_mask dccg_mask = { 426 DCCG_MASK_SH_LIST_DCN2(_MASK) 427 }; 428 429 #define opp_regs(id)\ 430 [id] = {\ 431 OPP_REG_LIST_DCN20(id),\ 432 } 433 434 static const struct dcn20_opp_registers opp_regs[] = { 435 opp_regs(0), 436 opp_regs(1), 437 opp_regs(2), 438 opp_regs(3), 439 opp_regs(4), 440 opp_regs(5), 441 }; 442 443 static const struct dcn20_opp_shift opp_shift = { 444 OPP_MASK_SH_LIST_DCN20(__SHIFT) 445 }; 446 447 static const struct dcn20_opp_mask opp_mask = { 448 OPP_MASK_SH_LIST_DCN20(_MASK) 449 }; 450 451 #define tg_regs(id)\ 452 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)} 453 454 static const struct dcn_optc_registers tg_regs[] = { 455 tg_regs(0), 456 tg_regs(1), 457 tg_regs(2), 458 tg_regs(3) 459 }; 460 461 static const struct dcn_optc_shift tg_shift = { 462 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 463 }; 464 465 static const struct dcn_optc_mask tg_mask = { 466 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 467 }; 468 469 static const struct dcn20_mpc_registers mpc_regs = { 470 MPC_REG_LIST_DCN2_0(0), 471 MPC_REG_LIST_DCN2_0(1), 472 MPC_REG_LIST_DCN2_0(2), 473 MPC_REG_LIST_DCN2_0(3), 474 MPC_REG_LIST_DCN2_0(4), 475 MPC_REG_LIST_DCN2_0(5), 476 MPC_OUT_MUX_REG_LIST_DCN2_0(0), 477 MPC_OUT_MUX_REG_LIST_DCN2_0(1), 478 MPC_OUT_MUX_REG_LIST_DCN2_0(2), 479 MPC_OUT_MUX_REG_LIST_DCN2_0(3) 480 }; 481 482 static const struct dcn20_mpc_shift mpc_shift = { 483 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 484 }; 485 486 static const struct dcn20_mpc_mask mpc_mask = { 487 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 488 }; 489 490 #define hubp_regs(id)\ 491 [id] = {\ 492 HUBP_REG_LIST_DCN21(id)\ 493 } 494 495 static const struct dcn_hubp2_registers hubp_regs[] = { 496 hubp_regs(0), 497 hubp_regs(1), 498 hubp_regs(2), 499 hubp_regs(3) 500 }; 501 502 static const struct dcn_hubp2_shift hubp_shift = { 503 HUBP_MASK_SH_LIST_DCN21(__SHIFT) 504 }; 505 506 static const struct dcn_hubp2_mask hubp_mask = { 507 HUBP_MASK_SH_LIST_DCN21(_MASK) 508 }; 509 510 static const struct dcn_hubbub_registers hubbub_reg = { 511 HUBBUB_REG_LIST_DCN21() 512 }; 513 514 static const struct dcn_hubbub_shift hubbub_shift = { 515 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT) 516 }; 517 518 static const struct dcn_hubbub_mask hubbub_mask = { 519 HUBBUB_MASK_SH_LIST_DCN21(_MASK) 520 }; 521 522 523 #define vmid_regs(id)\ 524 [id] = {\ 525 DCN20_VMID_REG_LIST(id)\ 526 } 527 528 static const struct dcn_vmid_registers vmid_regs[] = { 529 vmid_regs(0), 530 vmid_regs(1), 531 vmid_regs(2), 532 vmid_regs(3), 533 vmid_regs(4), 534 vmid_regs(5), 535 vmid_regs(6), 536 vmid_regs(7), 537 vmid_regs(8), 538 vmid_regs(9), 539 vmid_regs(10), 540 vmid_regs(11), 541 vmid_regs(12), 542 vmid_regs(13), 543 vmid_regs(14), 544 vmid_regs(15) 545 }; 546 547 static const struct dcn20_vmid_shift vmid_shifts = { 548 DCN20_VMID_MASK_SH_LIST(__SHIFT) 549 }; 550 551 static const struct dcn20_vmid_mask vmid_masks = { 552 DCN20_VMID_MASK_SH_LIST(_MASK) 553 }; 554 555 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 556 #define dsc_regsDCN20(id)\ 557 [id] = {\ 558 DSC_REG_LIST_DCN20(id)\ 559 } 560 561 static const struct dcn20_dsc_registers dsc_regs[] = { 562 dsc_regsDCN20(0), 563 dsc_regsDCN20(1), 564 dsc_regsDCN20(2), 565 dsc_regsDCN20(3), 566 dsc_regsDCN20(4), 567 dsc_regsDCN20(5) 568 }; 569 570 static const struct dcn20_dsc_shift dsc_shift = { 571 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 572 }; 573 574 static const struct dcn20_dsc_mask dsc_mask = { 575 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 576 }; 577 #endif 578 579 #define ipp_regs(id)\ 580 [id] = {\ 581 IPP_REG_LIST_DCN20(id),\ 582 } 583 584 static const struct dcn10_ipp_registers ipp_regs[] = { 585 ipp_regs(0), 586 ipp_regs(1), 587 ipp_regs(2), 588 ipp_regs(3), 589 }; 590 591 static const struct dcn10_ipp_shift ipp_shift = { 592 IPP_MASK_SH_LIST_DCN20(__SHIFT) 593 }; 594 595 static const struct dcn10_ipp_mask ipp_mask = { 596 IPP_MASK_SH_LIST_DCN20(_MASK), 597 }; 598 599 #define opp_regs(id)\ 600 [id] = {\ 601 OPP_REG_LIST_DCN20(id),\ 602 } 603 604 605 #define aux_engine_regs(id)\ 606 [id] = {\ 607 AUX_COMMON_REG_LIST0(id), \ 608 .AUXN_IMPCAL = 0, \ 609 .AUXP_IMPCAL = 0, \ 610 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 611 } 612 613 static const struct dce110_aux_registers aux_engine_regs[] = { 614 aux_engine_regs(0), 615 aux_engine_regs(1), 616 aux_engine_regs(2), 617 aux_engine_regs(3), 618 aux_engine_regs(4), 619 }; 620 621 #define tf_regs(id)\ 622 [id] = {\ 623 TF_REG_LIST_DCN20(id),\ 624 } 625 626 static const struct dcn2_dpp_registers tf_regs[] = { 627 tf_regs(0), 628 tf_regs(1), 629 tf_regs(2), 630 tf_regs(3), 631 }; 632 633 static const struct dcn2_dpp_shift tf_shift = { 634 TF_REG_LIST_SH_MASK_DCN20(__SHIFT) 635 }; 636 637 static const struct dcn2_dpp_mask tf_mask = { 638 TF_REG_LIST_SH_MASK_DCN20(_MASK) 639 }; 640 641 #define stream_enc_regs(id)\ 642 [id] = {\ 643 SE_DCN2_REG_LIST(id)\ 644 } 645 646 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 647 stream_enc_regs(0), 648 stream_enc_regs(1), 649 stream_enc_regs(2), 650 stream_enc_regs(3), 651 stream_enc_regs(4), 652 }; 653 654 static const struct dce110_aux_registers_shift aux_shift = { 655 DCN_AUX_MASK_SH_LIST(__SHIFT) 656 }; 657 658 static const struct dce110_aux_registers_mask aux_mask = { 659 DCN_AUX_MASK_SH_LIST(_MASK) 660 }; 661 662 static const struct dcn10_stream_encoder_shift se_shift = { 663 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) 664 }; 665 666 static const struct dcn10_stream_encoder_mask se_mask = { 667 SE_COMMON_MASK_SH_LIST_DCN20(_MASK) 668 }; 669 670 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu); 671 672 static struct input_pixel_processor *dcn21_ipp_create( 673 struct dc_context *ctx, uint32_t inst) 674 { 675 struct dcn10_ipp *ipp = 676 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 677 678 if (!ipp) { 679 BREAK_TO_DEBUGGER(); 680 return NULL; 681 } 682 683 dcn20_ipp_construct(ipp, ctx, inst, 684 &ipp_regs[inst], &ipp_shift, &ipp_mask); 685 return &ipp->base; 686 } 687 688 static struct dpp *dcn21_dpp_create( 689 struct dc_context *ctx, 690 uint32_t inst) 691 { 692 struct dcn20_dpp *dpp = 693 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL); 694 695 if (!dpp) 696 return NULL; 697 698 if (dpp2_construct(dpp, ctx, inst, 699 &tf_regs[inst], &tf_shift, &tf_mask)) 700 return &dpp->base; 701 702 BREAK_TO_DEBUGGER(); 703 kfree(dpp); 704 return NULL; 705 } 706 707 static struct dce_aux *dcn21_aux_engine_create( 708 struct dc_context *ctx, 709 uint32_t inst) 710 { 711 struct aux_engine_dce110 *aux_engine = 712 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 713 714 if (!aux_engine) 715 return NULL; 716 717 dce110_aux_engine_construct(aux_engine, ctx, inst, 718 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 719 &aux_engine_regs[inst], 720 &aux_mask, 721 &aux_shift, 722 ctx->dc->caps.extended_aux_timeout_support); 723 724 return &aux_engine->base; 725 } 726 727 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 728 729 static const struct dce_i2c_registers i2c_hw_regs[] = { 730 i2c_inst_regs(1), 731 i2c_inst_regs(2), 732 i2c_inst_regs(3), 733 i2c_inst_regs(4), 734 i2c_inst_regs(5), 735 }; 736 737 static const struct dce_i2c_shift i2c_shifts = { 738 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 739 }; 740 741 static const struct dce_i2c_mask i2c_masks = { 742 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 743 }; 744 745 struct dce_i2c_hw *dcn21_i2c_hw_create( 746 struct dc_context *ctx, 747 uint32_t inst) 748 { 749 struct dce_i2c_hw *dce_i2c_hw = 750 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 751 752 if (!dce_i2c_hw) 753 return NULL; 754 755 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 756 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 757 758 return dce_i2c_hw; 759 } 760 761 static const struct resource_caps res_cap_rn = { 762 .num_timing_generator = 4, 763 .num_opp = 4, 764 .num_video_plane = 4, 765 .num_audio = 4, // 4 audio endpoints. 4 audio streams 766 .num_stream_encoder = 5, 767 .num_pll = 5, // maybe 3 because the last two used for USB-c 768 .num_dwb = 1, 769 .num_ddc = 5, 770 .num_vmid = 1, 771 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 772 .num_dsc = 3, 773 #endif 774 }; 775 776 #ifdef DIAGS_BUILD 777 static const struct resource_caps res_cap_rn_FPGA_4pipe = { 778 .num_timing_generator = 4, 779 .num_opp = 4, 780 .num_video_plane = 4, 781 .num_audio = 7, 782 .num_stream_encoder = 4, 783 .num_pll = 4, 784 .num_dwb = 1, 785 .num_ddc = 4, 786 .num_dsc = 0, 787 }; 788 789 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = { 790 .num_timing_generator = 2, 791 .num_opp = 2, 792 .num_video_plane = 2, 793 .num_audio = 7, 794 .num_stream_encoder = 2, 795 .num_pll = 4, 796 .num_dwb = 1, 797 .num_ddc = 4, 798 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 799 .num_dsc = 2, 800 #endif 801 }; 802 #endif 803 804 static const struct dc_plane_cap plane_cap = { 805 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 806 .blends_with_above = true, 807 .blends_with_below = true, 808 .per_pixel_alpha = true, 809 810 .pixel_format_support = { 811 .argb8888 = true, 812 .nv12 = true, 813 .fp16 = true 814 }, 815 816 .max_upscale_factor = { 817 .argb8888 = 16000, 818 .nv12 = 16000, 819 .fp16 = 16000 820 }, 821 822 .max_downscale_factor = { 823 .argb8888 = 250, 824 .nv12 = 250, 825 .fp16 = 250 826 } 827 }; 828 829 static const struct dc_debug_options debug_defaults_drv = { 830 .disable_dmcu = true, 831 .force_abm_enable = false, 832 .timing_trace = false, 833 .clock_trace = true, 834 .disable_pplib_clock_request = true, 835 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 836 .force_single_disp_pipe_split = true, 837 .disable_dcc = DCC_ENABLE, 838 .vsr_support = true, 839 .performance_trace = false, 840 .max_downscale_src_width = 3840, 841 .disable_pplib_wm_range = false, 842 .scl_reset_length10 = true, 843 .sanity_checks = true, 844 .disable_48mhz_pwrdwn = false, 845 }; 846 847 static const struct dc_debug_options debug_defaults_diags = { 848 .disable_dmcu = true, 849 .force_abm_enable = false, 850 .timing_trace = true, 851 .clock_trace = true, 852 .disable_dpp_power_gate = true, 853 .disable_hubp_power_gate = true, 854 .disable_clock_gate = true, 855 .disable_pplib_clock_request = true, 856 .disable_pplib_wm_range = true, 857 .disable_stutter = true, 858 .disable_48mhz_pwrdwn = true, 859 }; 860 861 enum dcn20_clk_src_array_id { 862 DCN20_CLK_SRC_PLL0, 863 DCN20_CLK_SRC_PLL1, 864 DCN20_CLK_SRC_TOTAL_DCN21 865 }; 866 867 static void destruct(struct dcn21_resource_pool *pool) 868 { 869 unsigned int i; 870 871 for (i = 0; i < pool->base.stream_enc_count; i++) { 872 if (pool->base.stream_enc[i] != NULL) { 873 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 874 pool->base.stream_enc[i] = NULL; 875 } 876 } 877 878 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 879 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 880 if (pool->base.dscs[i] != NULL) 881 dcn20_dsc_destroy(&pool->base.dscs[i]); 882 } 883 #endif 884 885 if (pool->base.mpc != NULL) { 886 kfree(TO_DCN20_MPC(pool->base.mpc)); 887 pool->base.mpc = NULL; 888 } 889 if (pool->base.hubbub != NULL) { 890 kfree(pool->base.hubbub); 891 pool->base.hubbub = NULL; 892 } 893 for (i = 0; i < pool->base.pipe_count; i++) { 894 if (pool->base.dpps[i] != NULL) 895 dcn20_dpp_destroy(&pool->base.dpps[i]); 896 897 if (pool->base.ipps[i] != NULL) 898 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 899 900 if (pool->base.hubps[i] != NULL) { 901 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 902 pool->base.hubps[i] = NULL; 903 } 904 905 if (pool->base.irqs != NULL) { 906 dal_irq_service_destroy(&pool->base.irqs); 907 } 908 } 909 910 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 911 if (pool->base.engines[i] != NULL) 912 dce110_engine_destroy(&pool->base.engines[i]); 913 if (pool->base.hw_i2cs[i] != NULL) { 914 kfree(pool->base.hw_i2cs[i]); 915 pool->base.hw_i2cs[i] = NULL; 916 } 917 if (pool->base.sw_i2cs[i] != NULL) { 918 kfree(pool->base.sw_i2cs[i]); 919 pool->base.sw_i2cs[i] = NULL; 920 } 921 } 922 923 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 924 if (pool->base.opps[i] != NULL) 925 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 926 } 927 928 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 929 if (pool->base.timing_generators[i] != NULL) { 930 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 931 pool->base.timing_generators[i] = NULL; 932 } 933 } 934 935 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 936 if (pool->base.dwbc[i] != NULL) { 937 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); 938 pool->base.dwbc[i] = NULL; 939 } 940 if (pool->base.mcif_wb[i] != NULL) { 941 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); 942 pool->base.mcif_wb[i] = NULL; 943 } 944 } 945 946 for (i = 0; i < pool->base.audio_count; i++) { 947 if (pool->base.audios[i]) 948 dce_aud_destroy(&pool->base.audios[i]); 949 } 950 951 for (i = 0; i < pool->base.clk_src_count; i++) { 952 if (pool->base.clock_sources[i] != NULL) { 953 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 954 pool->base.clock_sources[i] = NULL; 955 } 956 } 957 958 if (pool->base.dp_clock_source != NULL) { 959 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 960 pool->base.dp_clock_source = NULL; 961 } 962 963 964 if (pool->base.abm != NULL) 965 dce_abm_destroy(&pool->base.abm); 966 967 if (pool->base.dmcu != NULL) 968 dce_dmcu_destroy(&pool->base.dmcu); 969 970 #ifdef CONFIG_DRM_AMD_DC_DMUB 971 if (pool->base.dmcub != NULL) 972 dcn21_dmcub_destroy(&pool->base.dmcub); 973 #endif 974 975 if (pool->base.dccg != NULL) 976 dcn_dccg_destroy(&pool->base.dccg); 977 978 if (pool->base.pp_smu != NULL) 979 dcn21_pp_smu_destroy(&pool->base.pp_smu); 980 } 981 982 983 static void calculate_wm_set_for_vlevel( 984 int vlevel, 985 struct wm_range_table_entry *table_entry, 986 struct dcn_watermarks *wm_set, 987 struct display_mode_lib *dml, 988 display_e2e_pipe_params_st *pipes, 989 int pipe_cnt) 990 { 991 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; 992 993 ASSERT(vlevel < dml->soc.num_states); 994 /* only pipe 0 is read for voltage and dcf/soc clocks */ 995 pipes[0].clks_cfg.voltage = vlevel; 996 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; 997 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; 998 999 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; 1000 1001 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; 1002 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; 1003 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; 1004 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 1005 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; 1006 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 1007 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; 1008 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; 1009 #endif 1010 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; 1011 1012 } 1013 1014 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) 1015 { 1016 kernel_fpu_begin(); 1017 if (dc->bb_overrides.sr_exit_time_ns) { 1018 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; 1019 } 1020 1021 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) { 1022 bb->sr_enter_plus_exit_time_us = 1023 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 1024 } 1025 1026 if (dc->bb_overrides.urgent_latency_ns) { 1027 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 1028 } 1029 1030 if (dc->bb_overrides.dram_clock_change_latency_ns) { 1031 bb->dram_clock_change_latency_us = 1032 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 1033 } 1034 kernel_fpu_end(); 1035 } 1036 1037 void dcn21_calculate_wm( 1038 struct dc *dc, struct dc_state *context, 1039 display_e2e_pipe_params_st *pipes, 1040 int *out_pipe_cnt, 1041 int *pipe_split_from, 1042 int vlevel_req) 1043 { 1044 int pipe_cnt, i, pipe_idx; 1045 int vlevel, vlevel_max; 1046 struct wm_range_table_entry *table_entry; 1047 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; 1048 1049 ASSERT(bw_params); 1050 1051 patch_bounding_box(dc, &context->bw_ctx.dml.soc); 1052 1053 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1054 if (!context->res_ctx.pipe_ctx[i].stream) 1055 continue; 1056 1057 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 1058 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb]; 1059 1060 if (pipe_split_from[i] < 0) { 1061 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1062 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; 1063 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) 1064 pipes[pipe_cnt].pipe.dest.odm_combine = 1065 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx]; 1066 else 1067 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1068 pipe_idx++; 1069 } else { 1070 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1071 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; 1072 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) 1073 pipes[pipe_cnt].pipe.dest.odm_combine = 1074 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]]; 1075 else 1076 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1077 } 1078 pipe_cnt++; 1079 } 1080 1081 if (pipe_cnt != pipe_idx) { 1082 if (dc->res_pool->funcs->populate_dml_pipes) 1083 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, 1084 &context->res_ctx, pipes); 1085 else 1086 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, 1087 &context->res_ctx, pipes); 1088 } 1089 1090 *out_pipe_cnt = pipe_cnt; 1091 1092 vlevel_max = bw_params->clk_table.num_entries - 1; 1093 1094 1095 /* WM Set D */ 1096 table_entry = &bw_params->wm_table.entries[WM_D]; 1097 if (table_entry->wm_type == WM_TYPE_RETRAINING) 1098 vlevel = 0; 1099 else 1100 vlevel = vlevel_max; 1101 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, 1102 &context->bw_ctx.dml, pipes, pipe_cnt); 1103 /* WM Set C */ 1104 table_entry = &bw_params->wm_table.entries[WM_C]; 1105 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max); 1106 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, 1107 &context->bw_ctx.dml, pipes, pipe_cnt); 1108 /* WM Set B */ 1109 table_entry = &bw_params->wm_table.entries[WM_B]; 1110 vlevel = MIN(MAX(vlevel_req, 1), vlevel_max); 1111 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, 1112 &context->bw_ctx.dml, pipes, pipe_cnt); 1113 1114 /* WM Set A */ 1115 table_entry = &bw_params->wm_table.entries[WM_A]; 1116 vlevel = MIN(vlevel_req, vlevel_max); 1117 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, 1118 &context->bw_ctx.dml, pipes, pipe_cnt); 1119 } 1120 1121 1122 bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context, 1123 bool fast_validate) 1124 { 1125 bool out = false; 1126 1127 BW_VAL_TRACE_SETUP(); 1128 1129 int vlevel = 0; 1130 int pipe_split_from[MAX_PIPES]; 1131 int pipe_cnt = 0; 1132 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1133 DC_LOGGER_INIT(dc->ctx->logger); 1134 1135 BW_VAL_TRACE_COUNT(); 1136 1137 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel); 1138 1139 if (pipe_cnt == 0) 1140 goto validate_out; 1141 1142 if (!out) 1143 goto validate_fail; 1144 1145 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1146 1147 if (fast_validate) { 1148 BW_VAL_TRACE_SKIP(fast); 1149 goto validate_out; 1150 } 1151 1152 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel); 1153 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 1154 1155 BW_VAL_TRACE_END_WATERMARKS(); 1156 1157 goto validate_out; 1158 1159 validate_fail: 1160 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1161 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1162 1163 BW_VAL_TRACE_SKIP(fail); 1164 out = false; 1165 1166 validate_out: 1167 kfree(pipes); 1168 1169 BW_VAL_TRACE_FINISH(); 1170 1171 return out; 1172 } 1173 static void dcn21_destroy_resource_pool(struct resource_pool **pool) 1174 { 1175 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool); 1176 1177 destruct(dcn21_pool); 1178 kfree(dcn21_pool); 1179 *pool = NULL; 1180 } 1181 1182 static struct clock_source *dcn21_clock_source_create( 1183 struct dc_context *ctx, 1184 struct dc_bios *bios, 1185 enum clock_source_id id, 1186 const struct dce110_clk_src_regs *regs, 1187 bool dp_clk_src) 1188 { 1189 struct dce110_clk_src *clk_src = 1190 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1191 1192 if (!clk_src) 1193 return NULL; 1194 1195 if (dcn20_clk_src_construct(clk_src, ctx, bios, id, 1196 regs, &cs_shift, &cs_mask)) { 1197 clk_src->base.dp_clk_src = dp_clk_src; 1198 return &clk_src->base; 1199 } 1200 1201 BREAK_TO_DEBUGGER(); 1202 return NULL; 1203 } 1204 1205 static struct hubp *dcn21_hubp_create( 1206 struct dc_context *ctx, 1207 uint32_t inst) 1208 { 1209 struct dcn21_hubp *hubp21 = 1210 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL); 1211 1212 if (!hubp21) 1213 return NULL; 1214 1215 if (hubp21_construct(hubp21, ctx, inst, 1216 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1217 return &hubp21->base; 1218 1219 BREAK_TO_DEBUGGER(); 1220 kfree(hubp21); 1221 return NULL; 1222 } 1223 1224 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx) 1225 { 1226 int i; 1227 1228 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), 1229 GFP_KERNEL); 1230 1231 if (!hubbub) 1232 return NULL; 1233 1234 hubbub21_construct(hubbub, ctx, 1235 &hubbub_reg, 1236 &hubbub_shift, 1237 &hubbub_mask); 1238 1239 for (i = 0; i < res_cap_rn.num_vmid; i++) { 1240 struct dcn20_vmid *vmid = &hubbub->vmid[i]; 1241 1242 vmid->ctx = ctx; 1243 1244 vmid->regs = &vmid_regs[i]; 1245 vmid->shifts = &vmid_shifts; 1246 vmid->masks = &vmid_masks; 1247 } 1248 1249 return &hubbub->base; 1250 } 1251 1252 struct output_pixel_processor *dcn21_opp_create( 1253 struct dc_context *ctx, uint32_t inst) 1254 { 1255 struct dcn20_opp *opp = 1256 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1257 1258 if (!opp) { 1259 BREAK_TO_DEBUGGER(); 1260 return NULL; 1261 } 1262 1263 dcn20_opp_construct(opp, ctx, inst, 1264 &opp_regs[inst], &opp_shift, &opp_mask); 1265 return &opp->base; 1266 } 1267 1268 struct timing_generator *dcn21_timing_generator_create( 1269 struct dc_context *ctx, 1270 uint32_t instance) 1271 { 1272 struct optc *tgn10 = 1273 kzalloc(sizeof(struct optc), GFP_KERNEL); 1274 1275 if (!tgn10) 1276 return NULL; 1277 1278 tgn10->base.inst = instance; 1279 tgn10->base.ctx = ctx; 1280 1281 tgn10->tg_regs = &tg_regs[instance]; 1282 tgn10->tg_shift = &tg_shift; 1283 tgn10->tg_mask = &tg_mask; 1284 1285 dcn20_timing_generator_init(tgn10); 1286 1287 return &tgn10->base; 1288 } 1289 1290 struct mpc *dcn21_mpc_create(struct dc_context *ctx) 1291 { 1292 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), 1293 GFP_KERNEL); 1294 1295 if (!mpc20) 1296 return NULL; 1297 1298 dcn20_mpc_construct(mpc20, ctx, 1299 &mpc_regs, 1300 &mpc_shift, 1301 &mpc_mask, 1302 6); 1303 1304 return &mpc20->base; 1305 } 1306 1307 static void read_dce_straps( 1308 struct dc_context *ctx, 1309 struct resource_straps *straps) 1310 { 1311 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1312 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1313 1314 } 1315 1316 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1317 1318 struct display_stream_compressor *dcn21_dsc_create( 1319 struct dc_context *ctx, uint32_t inst) 1320 { 1321 struct dcn20_dsc *dsc = 1322 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1323 1324 if (!dsc) { 1325 BREAK_TO_DEBUGGER(); 1326 return NULL; 1327 } 1328 1329 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1330 return &dsc->base; 1331 } 1332 #endif 1333 1334 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1335 { 1336 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool); 1337 struct clk_limit_table *clk_table = &bw_params->clk_table; 1338 int i; 1339 1340 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator; 1341 dcn2_1_ip.max_num_dpp = pool->base.pipe_count; 1342 dcn2_1_soc.num_chans = bw_params->num_channels; 1343 1344 for (i = 0; i < clk_table->num_entries; i++) { 1345 1346 dcn2_1_soc.clock_limits[i].state = i; 1347 dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 1348 dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 1349 dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; 1350 /* This is probably wrong, TODO: find correct calculation */ 1351 dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 16 / 1000; 1352 } 1353 dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i - i]; 1354 dcn2_1_soc.num_states = i; 1355 } 1356 1357 /* Temporary Place holder until we can get them from fuse */ 1358 static struct dpm_clocks dummy_clocks = { 1359 .DcfClocks = { 1360 {.Freq = 400, .Vol = 1}, 1361 {.Freq = 483, .Vol = 1}, 1362 {.Freq = 602, .Vol = 1}, 1363 {.Freq = 738, .Vol = 1} }, 1364 .SocClocks = { 1365 {.Freq = 300, .Vol = 1}, 1366 {.Freq = 400, .Vol = 1}, 1367 {.Freq = 400, .Vol = 1}, 1368 {.Freq = 400, .Vol = 1} }, 1369 .FClocks = { 1370 {.Freq = 400, .Vol = 1}, 1371 {.Freq = 800, .Vol = 1}, 1372 {.Freq = 1067, .Vol = 1}, 1373 {.Freq = 1600, .Vol = 1} }, 1374 .MemClocks = { 1375 {.Freq = 800, .Vol = 1}, 1376 {.Freq = 1600, .Vol = 1}, 1377 {.Freq = 1067, .Vol = 1}, 1378 {.Freq = 1600, .Vol = 1} }, 1379 1380 }; 1381 1382 static enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp, 1383 struct pp_smu_wm_range_sets *ranges) 1384 { 1385 return PP_SMU_RESULT_OK; 1386 } 1387 1388 static enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp, 1389 struct dpm_clocks *clock_table) 1390 { 1391 *clock_table = dummy_clocks; 1392 return PP_SMU_RESULT_OK; 1393 } 1394 1395 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx) 1396 { 1397 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 1398 1399 if (!pp_smu) 1400 return pp_smu; 1401 1402 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) { 1403 pp_smu->ctx.ver = PP_SMU_VER_RN; 1404 pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table; 1405 pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges; 1406 } else { 1407 1408 dm_pp_get_funcs(ctx, pp_smu); 1409 1410 if (pp_smu->ctx.ver != PP_SMU_VER_RN) 1411 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); 1412 } 1413 1414 return pp_smu; 1415 } 1416 1417 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu) 1418 { 1419 if (pp_smu && *pp_smu) { 1420 kfree(*pp_smu); 1421 *pp_smu = NULL; 1422 } 1423 } 1424 1425 static struct audio *dcn21_create_audio( 1426 struct dc_context *ctx, unsigned int inst) 1427 { 1428 return dce_audio_create(ctx, inst, 1429 &audio_regs[inst], &audio_shift, &audio_mask); 1430 } 1431 1432 static struct dc_cap_funcs cap_funcs = { 1433 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1434 }; 1435 1436 struct stream_encoder *dcn21_stream_encoder_create( 1437 enum engine_id eng_id, 1438 struct dc_context *ctx) 1439 { 1440 struct dcn10_stream_encoder *enc1 = 1441 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1442 1443 if (!enc1) 1444 return NULL; 1445 1446 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1447 &stream_enc_regs[eng_id], 1448 &se_shift, &se_mask); 1449 1450 return &enc1->base; 1451 } 1452 1453 static const struct dce_hwseq_registers hwseq_reg = { 1454 HWSEQ_DCN21_REG_LIST() 1455 }; 1456 1457 static const struct dce_hwseq_shift hwseq_shift = { 1458 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT) 1459 }; 1460 1461 static const struct dce_hwseq_mask hwseq_mask = { 1462 HWSEQ_DCN21_MASK_SH_LIST(_MASK) 1463 }; 1464 1465 static struct dce_hwseq *dcn21_hwseq_create( 1466 struct dc_context *ctx) 1467 { 1468 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1469 1470 if (hws) { 1471 hws->ctx = ctx; 1472 hws->regs = &hwseq_reg; 1473 hws->shifts = &hwseq_shift; 1474 hws->masks = &hwseq_mask; 1475 hws->wa.DEGVIDCN21 = true; 1476 } 1477 return hws; 1478 } 1479 1480 static const struct resource_create_funcs res_create_funcs = { 1481 .read_dce_straps = read_dce_straps, 1482 .create_audio = dcn21_create_audio, 1483 .create_stream_encoder = dcn21_stream_encoder_create, 1484 .create_hwseq = dcn21_hwseq_create, 1485 }; 1486 1487 static const struct resource_create_funcs res_create_maximus_funcs = { 1488 .read_dce_straps = NULL, 1489 .create_audio = NULL, 1490 .create_stream_encoder = NULL, 1491 .create_hwseq = dcn21_hwseq_create, 1492 }; 1493 1494 static const struct encoder_feature_support link_enc_feature = { 1495 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1496 .max_hdmi_pixel_clock = 600000, 1497 .hdmi_ycbcr420_supported = true, 1498 .dp_ycbcr420_supported = true, 1499 .flags.bits.IS_HBR2_CAPABLE = true, 1500 .flags.bits.IS_HBR3_CAPABLE = true, 1501 .flags.bits.IS_TPS3_CAPABLE = true, 1502 .flags.bits.IS_TPS4_CAPABLE = true 1503 }; 1504 1505 1506 #define link_regs(id, phyid)\ 1507 [id] = {\ 1508 LE_DCN10_REG_LIST(id), \ 1509 UNIPHY_DCN2_REG_LIST(phyid), \ 1510 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 1511 } 1512 1513 static const struct dcn10_link_enc_registers link_enc_regs[] = { 1514 link_regs(0, A), 1515 link_regs(1, B), 1516 link_regs(2, C), 1517 link_regs(3, D), 1518 link_regs(4, E), 1519 }; 1520 1521 #define aux_regs(id)\ 1522 [id] = {\ 1523 DCN2_AUX_REG_LIST(id)\ 1524 } 1525 1526 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 1527 aux_regs(0), 1528 aux_regs(1), 1529 aux_regs(2), 1530 aux_regs(3), 1531 aux_regs(4) 1532 }; 1533 1534 #define hpd_regs(id)\ 1535 [id] = {\ 1536 HPD_REG_LIST(id)\ 1537 } 1538 1539 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 1540 hpd_regs(0), 1541 hpd_regs(1), 1542 hpd_regs(2), 1543 hpd_regs(3), 1544 hpd_regs(4) 1545 }; 1546 1547 static const struct dcn10_link_enc_shift le_shift = { 1548 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT) 1549 }; 1550 1551 static const struct dcn10_link_enc_mask le_mask = { 1552 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK) 1553 }; 1554 1555 static struct link_encoder *dcn21_link_encoder_create( 1556 const struct encoder_init_data *enc_init_data) 1557 { 1558 struct dcn21_link_encoder *enc21 = 1559 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL); 1560 1561 if (!enc21) 1562 return NULL; 1563 1564 dcn21_link_encoder_construct(enc21, 1565 enc_init_data, 1566 &link_enc_feature, 1567 &link_enc_regs[enc_init_data->transmitter], 1568 &link_enc_aux_regs[enc_init_data->channel - 1], 1569 &link_enc_hpd_regs[enc_init_data->hpd_source], 1570 &le_shift, 1571 &le_mask); 1572 1573 return &enc21->enc10.base; 1574 } 1575 #define CTX ctx 1576 1577 #define REG(reg_name) \ 1578 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 1579 1580 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1581 { 1582 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 1583 /* RV1 support max 4 pipes */ 1584 value = value & 0xf; 1585 return value; 1586 } 1587 1588 static struct resource_funcs dcn21_res_pool_funcs = { 1589 .destroy = dcn21_destroy_resource_pool, 1590 .link_enc_create = dcn21_link_encoder_create, 1591 .validate_bandwidth = dcn21_validate_bandwidth, 1592 .populate_dml_pipes = dcn20_populate_dml_pipes_from_context, 1593 .add_stream_to_ctx = dcn20_add_stream_to_ctx, 1594 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1595 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1596 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, 1597 .get_default_swizzle_mode = dcn20_get_default_swizzle_mode, 1598 .set_mcif_arb_params = dcn20_set_mcif_arb_params, 1599 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1600 .update_bw_bounding_box = update_bw_bounding_box 1601 }; 1602 1603 static bool construct( 1604 uint8_t num_virtual_links, 1605 struct dc *dc, 1606 struct dcn21_resource_pool *pool) 1607 { 1608 int i, j; 1609 struct dc_context *ctx = dc->ctx; 1610 struct irq_service_init_data init_data; 1611 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1612 1613 ctx->dc_bios->regs = &bios_regs; 1614 1615 pool->base.res_cap = &res_cap_rn; 1616 #ifdef DIAGS_BUILD 1617 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1618 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc; 1619 pool->base.res_cap = &res_cap_rn_FPGA_4pipe; 1620 #endif 1621 1622 pool->base.funcs = &dcn21_res_pool_funcs; 1623 1624 /************************************************* 1625 * Resource + asic cap harcoding * 1626 *************************************************/ 1627 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1628 1629 /* max pipe num for ASIC before check pipe fuses */ 1630 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1631 1632 dc->caps.max_downscale_ratio = 200; 1633 dc->caps.i2c_speed_in_khz = 100; 1634 dc->caps.max_cursor_size = 256; 1635 dc->caps.dmdata_alloc_size = 2048; 1636 dc->caps.hw_3d_lut = true; 1637 1638 dc->caps.max_slave_planes = 1; 1639 dc->caps.post_blend_color_processing = true; 1640 dc->caps.force_dp_tps4_for_cp2520 = true; 1641 dc->caps.extended_aux_timeout_support = true; 1642 1643 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1644 dc->debug = debug_defaults_drv; 1645 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1646 pool->base.pipe_count = 4; 1647 dc->debug = debug_defaults_diags; 1648 } else 1649 dc->debug = debug_defaults_diags; 1650 1651 // Init the vm_helper 1652 if (dc->vm_helper) 1653 vm_helper_init(dc->vm_helper, 16); 1654 1655 /************************************************* 1656 * Create resources * 1657 *************************************************/ 1658 1659 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = 1660 dcn21_clock_source_create(ctx, ctx->dc_bios, 1661 CLOCK_SOURCE_COMBO_PHY_PLL0, 1662 &clk_src_regs[0], false); 1663 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = 1664 dcn21_clock_source_create(ctx, ctx->dc_bios, 1665 CLOCK_SOURCE_COMBO_PHY_PLL1, 1666 &clk_src_regs[1], false); 1667 1668 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21; 1669 1670 /* todo: not reuse phy_pll registers */ 1671 pool->base.dp_clock_source = 1672 dcn21_clock_source_create(ctx, ctx->dc_bios, 1673 CLOCK_SOURCE_ID_DP_DTO, 1674 &clk_src_regs[0], true); 1675 1676 for (i = 0; i < pool->base.clk_src_count; i++) { 1677 if (pool->base.clock_sources[i] == NULL) { 1678 dm_error("DC: failed to create clock sources!\n"); 1679 BREAK_TO_DEBUGGER(); 1680 goto create_fail; 1681 } 1682 } 1683 1684 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1685 if (pool->base.dccg == NULL) { 1686 dm_error("DC: failed to create dccg!\n"); 1687 BREAK_TO_DEBUGGER(); 1688 goto create_fail; 1689 } 1690 1691 pool->base.dmcu = dcn20_dmcu_create(ctx, 1692 &dmcu_regs, 1693 &dmcu_shift, 1694 &dmcu_mask); 1695 if (pool->base.dmcu == NULL) { 1696 dm_error("DC: failed to create dmcu!\n"); 1697 BREAK_TO_DEBUGGER(); 1698 goto create_fail; 1699 } 1700 1701 pool->base.abm = dce_abm_create(ctx, 1702 &abm_regs, 1703 &abm_shift, 1704 &abm_mask); 1705 if (pool->base.abm == NULL) { 1706 dm_error("DC: failed to create abm!\n"); 1707 BREAK_TO_DEBUGGER(); 1708 goto create_fail; 1709 } 1710 1711 #ifdef CONFIG_DRM_AMD_DC_DMUB 1712 pool->base.dmcub = dcn21_dmcub_create(ctx, 1713 &dmcub_regs, 1714 &dmcub_shift, 1715 &dmcub_mask); 1716 if (pool->base.dmcub == NULL) { 1717 dm_error("DC: failed to create dmcub!\n"); 1718 BREAK_TO_DEBUGGER(); 1719 goto create_fail; 1720 } 1721 #endif 1722 1723 pool->base.pp_smu = dcn21_pp_smu_create(ctx); 1724 1725 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); 1726 1727 init_data.ctx = dc->ctx; 1728 pool->base.irqs = dal_irq_service_dcn21_create(&init_data); 1729 if (!pool->base.irqs) 1730 goto create_fail; 1731 1732 j = 0; 1733 /* mem input -> ipp -> dpp -> opp -> TG */ 1734 for (i = 0; i < pool->base.pipe_count; i++) { 1735 /* if pipe is disabled, skip instance of HW pipe, 1736 * i.e, skip ASIC register instance 1737 */ 1738 if ((pipe_fuses & (1 << i)) != 0) 1739 continue; 1740 1741 pool->base.hubps[i] = dcn21_hubp_create(ctx, i); 1742 if (pool->base.hubps[i] == NULL) { 1743 BREAK_TO_DEBUGGER(); 1744 dm_error( 1745 "DC: failed to create memory input!\n"); 1746 goto create_fail; 1747 } 1748 1749 pool->base.ipps[i] = dcn21_ipp_create(ctx, i); 1750 if (pool->base.ipps[i] == NULL) { 1751 BREAK_TO_DEBUGGER(); 1752 dm_error( 1753 "DC: failed to create input pixel processor!\n"); 1754 goto create_fail; 1755 } 1756 1757 pool->base.dpps[i] = dcn21_dpp_create(ctx, i); 1758 if (pool->base.dpps[i] == NULL) { 1759 BREAK_TO_DEBUGGER(); 1760 dm_error( 1761 "DC: failed to create dpps!\n"); 1762 goto create_fail; 1763 } 1764 1765 pool->base.opps[i] = dcn21_opp_create(ctx, i); 1766 if (pool->base.opps[i] == NULL) { 1767 BREAK_TO_DEBUGGER(); 1768 dm_error( 1769 "DC: failed to create output pixel processor!\n"); 1770 goto create_fail; 1771 } 1772 1773 pool->base.timing_generators[i] = dcn21_timing_generator_create( 1774 ctx, i); 1775 if (pool->base.timing_generators[i] == NULL) { 1776 BREAK_TO_DEBUGGER(); 1777 dm_error("DC: failed to create tg!\n"); 1778 goto create_fail; 1779 } 1780 j++; 1781 } 1782 1783 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1784 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i); 1785 if (pool->base.engines[i] == NULL) { 1786 BREAK_TO_DEBUGGER(); 1787 dm_error( 1788 "DC:failed to create aux engine!!\n"); 1789 goto create_fail; 1790 } 1791 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i); 1792 if (pool->base.hw_i2cs[i] == NULL) { 1793 BREAK_TO_DEBUGGER(); 1794 dm_error( 1795 "DC:failed to create hw i2c!!\n"); 1796 goto create_fail; 1797 } 1798 pool->base.sw_i2cs[i] = NULL; 1799 } 1800 1801 pool->base.timing_generator_count = j; 1802 pool->base.pipe_count = j; 1803 pool->base.mpcc_count = j; 1804 1805 pool->base.mpc = dcn21_mpc_create(ctx); 1806 if (pool->base.mpc == NULL) { 1807 BREAK_TO_DEBUGGER(); 1808 dm_error("DC: failed to create mpc!\n"); 1809 goto create_fail; 1810 } 1811 1812 pool->base.hubbub = dcn21_hubbub_create(ctx); 1813 if (pool->base.hubbub == NULL) { 1814 BREAK_TO_DEBUGGER(); 1815 dm_error("DC: failed to create hubbub!\n"); 1816 goto create_fail; 1817 } 1818 1819 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1820 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1821 pool->base.dscs[i] = dcn21_dsc_create(ctx, i); 1822 if (pool->base.dscs[i] == NULL) { 1823 BREAK_TO_DEBUGGER(); 1824 dm_error("DC: failed to create display stream compressor %d!\n", i); 1825 goto create_fail; 1826 } 1827 } 1828 #endif 1829 1830 if (!dcn20_dwbc_create(ctx, &pool->base)) { 1831 BREAK_TO_DEBUGGER(); 1832 dm_error("DC: failed to create dwbc!\n"); 1833 goto create_fail; 1834 } 1835 if (!dcn20_mmhubbub_create(ctx, &pool->base)) { 1836 BREAK_TO_DEBUGGER(); 1837 dm_error("DC: failed to create mcif_wb!\n"); 1838 goto create_fail; 1839 } 1840 1841 if (!resource_construct(num_virtual_links, dc, &pool->base, 1842 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1843 &res_create_funcs : &res_create_maximus_funcs))) 1844 goto create_fail; 1845 1846 dcn21_hw_sequencer_construct(dc); 1847 1848 dc->caps.max_planes = pool->base.pipe_count; 1849 1850 for (i = 0; i < dc->caps.max_planes; ++i) 1851 dc->caps.planes[i] = plane_cap; 1852 1853 dc->cap_funcs = cap_funcs; 1854 1855 return true; 1856 1857 create_fail: 1858 1859 destruct(pool); 1860 1861 return false; 1862 } 1863 1864 struct resource_pool *dcn21_create_resource_pool( 1865 const struct dc_init_data *init_data, 1866 struct dc *dc) 1867 { 1868 struct dcn21_resource_pool *pool = 1869 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL); 1870 1871 if (!pool) 1872 return NULL; 1873 1874 if (construct(init_data->num_virtual_links, dc, pool)) 1875 return &pool->base; 1876 1877 BREAK_TO_DEBUGGER(); 1878 kfree(pool); 1879 return NULL; 1880 } 1881