1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3  * Copyright 2019 Raptor Engineering, LLC
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 
27 #include <linux/slab.h>
28 
29 #include "dm_services.h"
30 #include "dc.h"
31 
32 #include "dcn21_init.h"
33 
34 #include "resource.h"
35 #include "include/irq_service_interface.h"
36 #include "dcn20/dcn20_resource.h"
37 #include "dcn21/dcn21_resource.h"
38 
39 #include "dml/dcn20/dcn20_fpu.h"
40 
41 #include "clk_mgr.h"
42 #include "dcn10/dcn10_hubp.h"
43 #include "dcn10/dcn10_ipp.h"
44 #include "dcn20/dcn20_hubbub.h"
45 #include "dcn20/dcn20_mpc.h"
46 #include "dcn20/dcn20_hubp.h"
47 #include "dcn21_hubp.h"
48 #include "irq/dcn21/irq_service_dcn21.h"
49 #include "dcn20/dcn20_dpp.h"
50 #include "dcn20/dcn20_optc.h"
51 #include "dcn21/dcn21_hwseq.h"
52 #include "dce110/dce110_hw_sequencer.h"
53 #include "dcn20/dcn20_opp.h"
54 #include "dcn20/dcn20_dsc.h"
55 #include "dcn21/dcn21_link_encoder.h"
56 #include "dcn20/dcn20_stream_encoder.h"
57 #include "dce/dce_clock_source.h"
58 #include "dce/dce_audio.h"
59 #include "dce/dce_hwseq.h"
60 #include "virtual/virtual_stream_encoder.h"
61 #include "dml/display_mode_vba.h"
62 #include "dcn20/dcn20_dccg.h"
63 #include "dcn21/dcn21_dccg.h"
64 #include "dcn21_hubbub.h"
65 #include "dcn10/dcn10_resource.h"
66 #include "dce/dce_panel_cntl.h"
67 
68 #include "dcn20/dcn20_dwb.h"
69 #include "dcn20/dcn20_mmhubbub.h"
70 #include "dpcs/dpcs_2_1_0_offset.h"
71 #include "dpcs/dpcs_2_1_0_sh_mask.h"
72 
73 #include "renoir_ip_offset.h"
74 #include "dcn/dcn_2_1_0_offset.h"
75 #include "dcn/dcn_2_1_0_sh_mask.h"
76 
77 #include "nbio/nbio_7_0_offset.h"
78 
79 #include "mmhub/mmhub_2_0_0_offset.h"
80 #include "mmhub/mmhub_2_0_0_sh_mask.h"
81 
82 #include "reg_helper.h"
83 #include "dce/dce_abm.h"
84 #include "dce/dce_dmcu.h"
85 #include "dce/dce_aux.h"
86 #include "dce/dce_i2c.h"
87 #include "dcn21_resource.h"
88 #include "vm_helper.h"
89 #include "dcn20/dcn20_vmid.h"
90 #include "dce/dmub_psr.h"
91 #include "dce/dmub_abm.h"
92 
93 /* begin *********************
94  * macros to expend register list macro defined in HW object header file */
95 
96 /* DCN */
97 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
98 
99 #define BASE(seg) BASE_INNER(seg)
100 
101 #define SR(reg_name)\
102 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
103 					mm ## reg_name
104 
105 #define SRI(reg_name, block, id)\
106 	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
107 					mm ## block ## id ## _ ## reg_name
108 
109 #define SRIR(var_name, reg_name, block, id)\
110 	.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
111 					mm ## block ## id ## _ ## reg_name
112 
113 #define SRII(reg_name, block, id)\
114 	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
115 					mm ## block ## id ## _ ## reg_name
116 
117 #define DCCG_SRII(reg_name, block, id)\
118 	.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
119 					mm ## block ## id ## _ ## reg_name
120 
121 #define VUPDATE_SRII(reg_name, block, id)\
122 	.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
123 					mm ## reg_name ## _ ## block ## id
124 
125 /* NBIO */
126 #define NBIO_BASE_INNER(seg) \
127 	NBIF0_BASE__INST0_SEG ## seg
128 
129 #define NBIO_BASE(seg) \
130 	NBIO_BASE_INNER(seg)
131 
132 #define NBIO_SR(reg_name)\
133 		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
134 					mm ## reg_name
135 
136 /* MMHUB */
137 #define MMHUB_BASE_INNER(seg) \
138 	MMHUB_BASE__INST0_SEG ## seg
139 
140 #define MMHUB_BASE(seg) \
141 	MMHUB_BASE_INNER(seg)
142 
143 #define MMHUB_SR(reg_name)\
144 		.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
145 					mmMM ## reg_name
146 
147 #define clk_src_regs(index, pllid)\
148 [index] = {\
149 	CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
150 }
151 
152 static const struct dce110_clk_src_regs clk_src_regs[] = {
153 	clk_src_regs(0, A),
154 	clk_src_regs(1, B),
155 	clk_src_regs(2, C),
156 	clk_src_regs(3, D),
157 	clk_src_regs(4, E),
158 };
159 
160 static const struct dce110_clk_src_shift cs_shift = {
161 		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
162 };
163 
164 static const struct dce110_clk_src_mask cs_mask = {
165 		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
166 };
167 
168 static const struct bios_registers bios_regs = {
169 		NBIO_SR(BIOS_SCRATCH_3),
170 		NBIO_SR(BIOS_SCRATCH_6)
171 };
172 
173 static const struct dce_dmcu_registers dmcu_regs = {
174 		DMCU_DCN20_REG_LIST()
175 };
176 
177 static const struct dce_dmcu_shift dmcu_shift = {
178 		DMCU_MASK_SH_LIST_DCN10(__SHIFT)
179 };
180 
181 static const struct dce_dmcu_mask dmcu_mask = {
182 		DMCU_MASK_SH_LIST_DCN10(_MASK)
183 };
184 
185 static const struct dce_abm_registers abm_regs = {
186 		ABM_DCN20_REG_LIST()
187 };
188 
189 static const struct dce_abm_shift abm_shift = {
190 		ABM_MASK_SH_LIST_DCN20(__SHIFT)
191 };
192 
193 static const struct dce_abm_mask abm_mask = {
194 		ABM_MASK_SH_LIST_DCN20(_MASK)
195 };
196 
197 #define audio_regs(id)\
198 [id] = {\
199 		AUD_COMMON_REG_LIST(id)\
200 }
201 
202 static const struct dce_audio_registers audio_regs[] = {
203 	audio_regs(0),
204 	audio_regs(1),
205 	audio_regs(2),
206 	audio_regs(3),
207 	audio_regs(4),
208 	audio_regs(5),
209 };
210 
211 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
212 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
213 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
214 		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
215 
216 static const struct dce_audio_shift audio_shift = {
217 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
218 };
219 
220 static const struct dce_audio_mask audio_mask = {
221 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
222 };
223 
224 static const struct dccg_registers dccg_regs = {
225 		DCCG_COMMON_REG_LIST_DCN_BASE()
226 };
227 
228 static const struct dccg_shift dccg_shift = {
229 		DCCG_MASK_SH_LIST_DCN2_1(__SHIFT)
230 };
231 
232 static const struct dccg_mask dccg_mask = {
233 		DCCG_MASK_SH_LIST_DCN2_1(_MASK)
234 };
235 
236 #define opp_regs(id)\
237 [id] = {\
238 	OPP_REG_LIST_DCN20(id),\
239 }
240 
241 static const struct dcn20_opp_registers opp_regs[] = {
242 	opp_regs(0),
243 	opp_regs(1),
244 	opp_regs(2),
245 	opp_regs(3),
246 	opp_regs(4),
247 	opp_regs(5),
248 };
249 
250 static const struct dcn20_opp_shift opp_shift = {
251 		OPP_MASK_SH_LIST_DCN20(__SHIFT)
252 };
253 
254 static const struct dcn20_opp_mask opp_mask = {
255 		OPP_MASK_SH_LIST_DCN20(_MASK)
256 };
257 
258 #define tg_regs(id)\
259 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
260 
261 static const struct dcn_optc_registers tg_regs[] = {
262 	tg_regs(0),
263 	tg_regs(1),
264 	tg_regs(2),
265 	tg_regs(3)
266 };
267 
268 static const struct dcn_optc_shift tg_shift = {
269 	TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
270 };
271 
272 static const struct dcn_optc_mask tg_mask = {
273 	TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
274 };
275 
276 static const struct dcn20_mpc_registers mpc_regs = {
277 		MPC_REG_LIST_DCN2_0(0),
278 		MPC_REG_LIST_DCN2_0(1),
279 		MPC_REG_LIST_DCN2_0(2),
280 		MPC_REG_LIST_DCN2_0(3),
281 		MPC_REG_LIST_DCN2_0(4),
282 		MPC_REG_LIST_DCN2_0(5),
283 		MPC_OUT_MUX_REG_LIST_DCN2_0(0),
284 		MPC_OUT_MUX_REG_LIST_DCN2_0(1),
285 		MPC_OUT_MUX_REG_LIST_DCN2_0(2),
286 		MPC_OUT_MUX_REG_LIST_DCN2_0(3),
287 		MPC_DBG_REG_LIST_DCN2_0()
288 };
289 
290 static const struct dcn20_mpc_shift mpc_shift = {
291 	MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
292 	MPC_DEBUG_REG_LIST_SH_DCN20
293 };
294 
295 static const struct dcn20_mpc_mask mpc_mask = {
296 	MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
297 	MPC_DEBUG_REG_LIST_MASK_DCN20
298 };
299 
300 #define hubp_regs(id)\
301 [id] = {\
302 	HUBP_REG_LIST_DCN21(id)\
303 }
304 
305 static const struct dcn_hubp2_registers hubp_regs[] = {
306 		hubp_regs(0),
307 		hubp_regs(1),
308 		hubp_regs(2),
309 		hubp_regs(3)
310 };
311 
312 static const struct dcn_hubp2_shift hubp_shift = {
313 		HUBP_MASK_SH_LIST_DCN21(__SHIFT)
314 };
315 
316 static const struct dcn_hubp2_mask hubp_mask = {
317 		HUBP_MASK_SH_LIST_DCN21(_MASK)
318 };
319 
320 static const struct dcn_hubbub_registers hubbub_reg = {
321 		HUBBUB_REG_LIST_DCN21()
322 };
323 
324 static const struct dcn_hubbub_shift hubbub_shift = {
325 		HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
326 };
327 
328 static const struct dcn_hubbub_mask hubbub_mask = {
329 		HUBBUB_MASK_SH_LIST_DCN21(_MASK)
330 };
331 
332 
333 #define vmid_regs(id)\
334 [id] = {\
335 		DCN20_VMID_REG_LIST(id)\
336 }
337 
338 static const struct dcn_vmid_registers vmid_regs[] = {
339 	vmid_regs(0),
340 	vmid_regs(1),
341 	vmid_regs(2),
342 	vmid_regs(3),
343 	vmid_regs(4),
344 	vmid_regs(5),
345 	vmid_regs(6),
346 	vmid_regs(7),
347 	vmid_regs(8),
348 	vmid_regs(9),
349 	vmid_regs(10),
350 	vmid_regs(11),
351 	vmid_regs(12),
352 	vmid_regs(13),
353 	vmid_regs(14),
354 	vmid_regs(15)
355 };
356 
357 static const struct dcn20_vmid_shift vmid_shifts = {
358 		DCN20_VMID_MASK_SH_LIST(__SHIFT)
359 };
360 
361 static const struct dcn20_vmid_mask vmid_masks = {
362 		DCN20_VMID_MASK_SH_LIST(_MASK)
363 };
364 
365 #define dsc_regsDCN20(id)\
366 [id] = {\
367 	DSC_REG_LIST_DCN20(id)\
368 }
369 
370 static const struct dcn20_dsc_registers dsc_regs[] = {
371 	dsc_regsDCN20(0),
372 	dsc_regsDCN20(1),
373 	dsc_regsDCN20(2),
374 	dsc_regsDCN20(3),
375 	dsc_regsDCN20(4),
376 	dsc_regsDCN20(5)
377 };
378 
379 static const struct dcn20_dsc_shift dsc_shift = {
380 	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
381 };
382 
383 static const struct dcn20_dsc_mask dsc_mask = {
384 	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
385 };
386 
387 #define ipp_regs(id)\
388 [id] = {\
389 	IPP_REG_LIST_DCN20(id),\
390 }
391 
392 static const struct dcn10_ipp_registers ipp_regs[] = {
393 	ipp_regs(0),
394 	ipp_regs(1),
395 	ipp_regs(2),
396 	ipp_regs(3),
397 };
398 
399 static const struct dcn10_ipp_shift ipp_shift = {
400 		IPP_MASK_SH_LIST_DCN20(__SHIFT)
401 };
402 
403 static const struct dcn10_ipp_mask ipp_mask = {
404 		IPP_MASK_SH_LIST_DCN20(_MASK),
405 };
406 
407 #define opp_regs(id)\
408 [id] = {\
409 	OPP_REG_LIST_DCN20(id),\
410 }
411 
412 
413 #define aux_engine_regs(id)\
414 [id] = {\
415 	AUX_COMMON_REG_LIST0(id), \
416 	.AUXN_IMPCAL = 0, \
417 	.AUXP_IMPCAL = 0, \
418 	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
419 }
420 
421 static const struct dce110_aux_registers aux_engine_regs[] = {
422 		aux_engine_regs(0),
423 		aux_engine_regs(1),
424 		aux_engine_regs(2),
425 		aux_engine_regs(3),
426 		aux_engine_regs(4),
427 };
428 
429 #define tf_regs(id)\
430 [id] = {\
431 	TF_REG_LIST_DCN20(id),\
432 	TF_REG_LIST_DCN20_COMMON_APPEND(id),\
433 }
434 
435 static const struct dcn2_dpp_registers tf_regs[] = {
436 	tf_regs(0),
437 	tf_regs(1),
438 	tf_regs(2),
439 	tf_regs(3),
440 };
441 
442 static const struct dcn2_dpp_shift tf_shift = {
443 		TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
444 		TF_DEBUG_REG_LIST_SH_DCN20
445 };
446 
447 static const struct dcn2_dpp_mask tf_mask = {
448 		TF_REG_LIST_SH_MASK_DCN20(_MASK),
449 		TF_DEBUG_REG_LIST_MASK_DCN20
450 };
451 
452 #define stream_enc_regs(id)\
453 [id] = {\
454 	SE_DCN2_REG_LIST(id)\
455 }
456 
457 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
458 	stream_enc_regs(0),
459 	stream_enc_regs(1),
460 	stream_enc_regs(2),
461 	stream_enc_regs(3),
462 	stream_enc_regs(4),
463 };
464 
465 static const struct dce110_aux_registers_shift aux_shift = {
466 	DCN_AUX_MASK_SH_LIST(__SHIFT)
467 };
468 
469 static const struct dce110_aux_registers_mask aux_mask = {
470 	DCN_AUX_MASK_SH_LIST(_MASK)
471 };
472 
473 static const struct dcn10_stream_encoder_shift se_shift = {
474 		SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
475 };
476 
477 static const struct dcn10_stream_encoder_mask se_mask = {
478 		SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
479 };
480 
481 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
482 
483 static struct input_pixel_processor *dcn21_ipp_create(
484 	struct dc_context *ctx, uint32_t inst)
485 {
486 	struct dcn10_ipp *ipp =
487 		kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
488 
489 	if (!ipp) {
490 		BREAK_TO_DEBUGGER();
491 		return NULL;
492 	}
493 
494 	dcn20_ipp_construct(ipp, ctx, inst,
495 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
496 	return &ipp->base;
497 }
498 
499 static struct dpp *dcn21_dpp_create(
500 	struct dc_context *ctx,
501 	uint32_t inst)
502 {
503 	struct dcn20_dpp *dpp =
504 		kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
505 
506 	if (!dpp)
507 		return NULL;
508 
509 	if (dpp2_construct(dpp, ctx, inst,
510 			&tf_regs[inst], &tf_shift, &tf_mask))
511 		return &dpp->base;
512 
513 	BREAK_TO_DEBUGGER();
514 	kfree(dpp);
515 	return NULL;
516 }
517 
518 static struct dce_aux *dcn21_aux_engine_create(
519 	struct dc_context *ctx,
520 	uint32_t inst)
521 {
522 	struct aux_engine_dce110 *aux_engine =
523 		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
524 
525 	if (!aux_engine)
526 		return NULL;
527 
528 	dce110_aux_engine_construct(aux_engine, ctx, inst,
529 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
530 				    &aux_engine_regs[inst],
531 					&aux_mask,
532 					&aux_shift,
533 					ctx->dc->caps.extended_aux_timeout_support);
534 
535 	return &aux_engine->base;
536 }
537 
538 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
539 
540 static const struct dce_i2c_registers i2c_hw_regs[] = {
541 		i2c_inst_regs(1),
542 		i2c_inst_regs(2),
543 		i2c_inst_regs(3),
544 		i2c_inst_regs(4),
545 		i2c_inst_regs(5),
546 };
547 
548 static const struct dce_i2c_shift i2c_shifts = {
549 		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
550 };
551 
552 static const struct dce_i2c_mask i2c_masks = {
553 		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
554 };
555 
556 static struct dce_i2c_hw *dcn21_i2c_hw_create(struct dc_context *ctx,
557 					      uint32_t inst)
558 {
559 	struct dce_i2c_hw *dce_i2c_hw =
560 		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
561 
562 	if (!dce_i2c_hw)
563 		return NULL;
564 
565 	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
566 				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
567 
568 	return dce_i2c_hw;
569 }
570 
571 static const struct resource_caps res_cap_rn = {
572 		.num_timing_generator = 4,
573 		.num_opp = 4,
574 		.num_video_plane = 4,
575 		.num_audio = 4, // 4 audio endpoints.  4 audio streams
576 		.num_stream_encoder = 5,
577 		.num_pll = 5,  // maybe 3 because the last two used for USB-c
578 		.num_dwb = 1,
579 		.num_ddc = 5,
580 		.num_vmid = 16,
581 		.num_dsc = 3,
582 };
583 
584 #ifdef DIAGS_BUILD
585 static const struct resource_caps res_cap_rn_FPGA_4pipe = {
586 		.num_timing_generator = 4,
587 		.num_opp = 4,
588 		.num_video_plane = 4,
589 		.num_audio = 7,
590 		.num_stream_encoder = 4,
591 		.num_pll = 4,
592 		.num_dwb = 1,
593 		.num_ddc = 4,
594 		.num_dsc = 0,
595 };
596 
597 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
598 		.num_timing_generator = 2,
599 		.num_opp = 2,
600 		.num_video_plane = 2,
601 		.num_audio = 7,
602 		.num_stream_encoder = 2,
603 		.num_pll = 4,
604 		.num_dwb = 1,
605 		.num_ddc = 4,
606 		.num_dsc = 2,
607 };
608 #endif
609 
610 static const struct dc_plane_cap plane_cap = {
611 	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
612 	.blends_with_above = true,
613 	.blends_with_below = true,
614 	.per_pixel_alpha = true,
615 
616 	.pixel_format_support = {
617 			.argb8888 = true,
618 			.nv12 = true,
619 			.fp16 = true,
620 			.p010 = true
621 	},
622 
623 	.max_upscale_factor = {
624 			.argb8888 = 16000,
625 			.nv12 = 16000,
626 			.fp16 = 16000
627 	},
628 
629 	.max_downscale_factor = {
630 			.argb8888 = 250,
631 			.nv12 = 250,
632 			.fp16 = 250
633 	},
634 	64,
635 	64
636 };
637 
638 static const struct dc_debug_options debug_defaults_drv = {
639 		.disable_dmcu = false,
640 		.force_abm_enable = false,
641 		.timing_trace = false,
642 		.clock_trace = true,
643 		.disable_pplib_clock_request = true,
644 		.min_disp_clk_khz = 100000,
645 		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
646 		.force_single_disp_pipe_split = false,
647 		.disable_dcc = DCC_ENABLE,
648 		.vsr_support = true,
649 		.performance_trace = false,
650 		.max_downscale_src_width = 4096,
651 		.disable_pplib_wm_range = false,
652 		.scl_reset_length10 = true,
653 		.sanity_checks = true,
654 		.disable_48mhz_pwrdwn = false,
655 		.usbc_combo_phy_reset_wa = true,
656 		.dmub_command_table = true,
657 		.use_max_lb = true,
658 };
659 
660 static const struct dc_debug_options debug_defaults_diags = {
661 		.disable_dmcu = false,
662 		.force_abm_enable = false,
663 		.timing_trace = true,
664 		.clock_trace = true,
665 		.disable_dpp_power_gate = true,
666 		.disable_hubp_power_gate = true,
667 		.disable_clock_gate = true,
668 		.disable_pplib_clock_request = true,
669 		.disable_pplib_wm_range = true,
670 		.disable_stutter = true,
671 		.disable_48mhz_pwrdwn = true,
672 		.enable_tri_buf = true,
673 		.use_max_lb = true
674 };
675 
676 static const struct dc_panel_config panel_config_defaults = {
677 		.psr = {
678 			.disable_psr = false,
679 			.disallow_psrsu = false,
680 		},
681 		.ilr = {
682 			.optimize_edp_link_rate = true,
683 		},
684 };
685 
686 enum dcn20_clk_src_array_id {
687 	DCN20_CLK_SRC_PLL0,
688 	DCN20_CLK_SRC_PLL1,
689 	DCN20_CLK_SRC_PLL2,
690 	DCN20_CLK_SRC_PLL3,
691 	DCN20_CLK_SRC_PLL4,
692 	DCN20_CLK_SRC_TOTAL_DCN21
693 };
694 
695 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
696 {
697 	unsigned int i;
698 
699 	for (i = 0; i < pool->base.stream_enc_count; i++) {
700 		if (pool->base.stream_enc[i] != NULL) {
701 			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
702 			pool->base.stream_enc[i] = NULL;
703 		}
704 	}
705 
706 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
707 		if (pool->base.dscs[i] != NULL)
708 			dcn20_dsc_destroy(&pool->base.dscs[i]);
709 	}
710 
711 	if (pool->base.mpc != NULL) {
712 		kfree(TO_DCN20_MPC(pool->base.mpc));
713 		pool->base.mpc = NULL;
714 	}
715 	if (pool->base.hubbub != NULL) {
716 		kfree(pool->base.hubbub);
717 		pool->base.hubbub = NULL;
718 	}
719 	for (i = 0; i < pool->base.pipe_count; i++) {
720 		if (pool->base.dpps[i] != NULL)
721 			dcn20_dpp_destroy(&pool->base.dpps[i]);
722 
723 		if (pool->base.ipps[i] != NULL)
724 			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
725 
726 		if (pool->base.hubps[i] != NULL) {
727 			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
728 			pool->base.hubps[i] = NULL;
729 		}
730 
731 		if (pool->base.irqs != NULL) {
732 			dal_irq_service_destroy(&pool->base.irqs);
733 		}
734 	}
735 
736 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
737 		if (pool->base.engines[i] != NULL)
738 			dce110_engine_destroy(&pool->base.engines[i]);
739 		if (pool->base.hw_i2cs[i] != NULL) {
740 			kfree(pool->base.hw_i2cs[i]);
741 			pool->base.hw_i2cs[i] = NULL;
742 		}
743 		if (pool->base.sw_i2cs[i] != NULL) {
744 			kfree(pool->base.sw_i2cs[i]);
745 			pool->base.sw_i2cs[i] = NULL;
746 		}
747 	}
748 
749 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
750 		if (pool->base.opps[i] != NULL)
751 			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
752 	}
753 
754 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
755 		if (pool->base.timing_generators[i] != NULL)	{
756 			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
757 			pool->base.timing_generators[i] = NULL;
758 		}
759 	}
760 
761 	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
762 		if (pool->base.dwbc[i] != NULL) {
763 			kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
764 			pool->base.dwbc[i] = NULL;
765 		}
766 		if (pool->base.mcif_wb[i] != NULL) {
767 			kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
768 			pool->base.mcif_wb[i] = NULL;
769 		}
770 	}
771 
772 	for (i = 0; i < pool->base.audio_count; i++) {
773 		if (pool->base.audios[i])
774 			dce_aud_destroy(&pool->base.audios[i]);
775 	}
776 
777 	for (i = 0; i < pool->base.clk_src_count; i++) {
778 		if (pool->base.clock_sources[i] != NULL) {
779 			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
780 			pool->base.clock_sources[i] = NULL;
781 		}
782 	}
783 
784 	if (pool->base.dp_clock_source != NULL) {
785 		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
786 		pool->base.dp_clock_source = NULL;
787 	}
788 
789 	if (pool->base.abm != NULL) {
790 		if (pool->base.abm->ctx->dc->config.disable_dmcu)
791 			dmub_abm_destroy(&pool->base.abm);
792 		else
793 			dce_abm_destroy(&pool->base.abm);
794 	}
795 
796 	if (pool->base.dmcu != NULL)
797 		dce_dmcu_destroy(&pool->base.dmcu);
798 
799 	if (pool->base.psr != NULL)
800 		dmub_psr_destroy(&pool->base.psr);
801 
802 	if (pool->base.dccg != NULL)
803 		dcn_dccg_destroy(&pool->base.dccg);
804 
805 	if (pool->base.pp_smu != NULL)
806 		dcn21_pp_smu_destroy(&pool->base.pp_smu);
807 }
808 
809 bool dcn21_fast_validate_bw(struct dc *dc,
810 			    struct dc_state *context,
811 			    display_e2e_pipe_params_st *pipes,
812 			    int *pipe_cnt_out,
813 			    int *pipe_split_from,
814 			    int *vlevel_out,
815 			    bool fast_validate)
816 {
817 	bool out = false;
818 	int split[MAX_PIPES] = { 0 };
819 	int pipe_cnt, i, pipe_idx, vlevel;
820 
821 	ASSERT(pipes);
822 	if (!pipes)
823 		return false;
824 
825 	dcn20_merge_pipes_for_validate(dc, context);
826 
827 	DC_FP_START();
828 	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
829 	DC_FP_END();
830 
831 	*pipe_cnt_out = pipe_cnt;
832 
833 	if (!pipe_cnt) {
834 		out = true;
835 		goto validate_out;
836 	}
837 	/*
838 	 * DML favors voltage over p-state, but we're more interested in
839 	 * supporting p-state over voltage. We can't support p-state in
840 	 * prefetch mode > 0 so try capping the prefetch mode to start.
841 	 */
842 	context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
843 				dm_allow_self_refresh_and_mclk_switch;
844 	vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
845 
846 	if (vlevel > context->bw_ctx.dml.soc.num_states) {
847 		/*
848 		 * If mode is unsupported or there's still no p-state support then
849 		 * fall back to favoring voltage.
850 		 *
851 		 * We don't actually support prefetch mode 2, so require that we
852 		 * at least support prefetch mode 1.
853 		 */
854 		context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
855 					dm_allow_self_refresh;
856 		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
857 		if (vlevel > context->bw_ctx.dml.soc.num_states)
858 			goto validate_fail;
859 	}
860 
861 	vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
862 
863 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
864 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
865 		struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
866 		struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
867 
868 		if (!pipe->stream)
869 			continue;
870 
871 		/* We only support full screen mpo with ODM */
872 		if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
873 				&& pipe->plane_state && mpo_pipe
874 				&& memcmp(&mpo_pipe->plane_res.scl_data.recout,
875 						&pipe->plane_res.scl_data.recout,
876 						sizeof(struct rect)) != 0) {
877 			ASSERT(mpo_pipe->plane_state != pipe->plane_state);
878 			goto validate_fail;
879 		}
880 		pipe_idx++;
881 	}
882 
883 	/*initialize pipe_just_split_from to invalid idx*/
884 	for (i = 0; i < MAX_PIPES; i++)
885 		pipe_split_from[i] = -1;
886 
887 	for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
888 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
889 		struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
890 
891 		if (!pipe->stream || pipe_split_from[i] >= 0)
892 			continue;
893 
894 		pipe_idx++;
895 
896 		if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
897 			hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
898 			ASSERT(hsplit_pipe);
899 			if (!dcn20_split_stream_for_odm(
900 					dc, &context->res_ctx,
901 					pipe, hsplit_pipe))
902 				goto validate_fail;
903 			pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
904 			dcn20_build_mapped_resource(dc, context, pipe->stream);
905 		}
906 
907 		if (!pipe->plane_state)
908 			continue;
909 		/* Skip 2nd half of already split pipe */
910 		if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
911 			continue;
912 
913 		if (split[i] == 2) {
914 			if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
915 				/* pipe not split previously needs split */
916 				hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
917 				ASSERT(hsplit_pipe);
918 				if (!hsplit_pipe) {
919 					DC_FP_START();
920 					dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true);
921 					DC_FP_END();
922 					continue;
923 				}
924 				if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
925 					if (!dcn20_split_stream_for_odm(
926 							dc, &context->res_ctx,
927 							pipe, hsplit_pipe))
928 						goto validate_fail;
929 					dcn20_build_mapped_resource(dc, context, pipe->stream);
930 				} else {
931 					dcn20_split_stream_for_mpc(
932 							&context->res_ctx, dc->res_pool,
933 							pipe, hsplit_pipe);
934 					resource_build_scaling_params(pipe);
935 					resource_build_scaling_params(hsplit_pipe);
936 				}
937 				pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
938 			}
939 		} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
940 			/* merge should already have been done */
941 			ASSERT(0);
942 		}
943 	}
944 	/* Actual dsc count per stream dsc validation*/
945 	if (!dcn20_validate_dsc(dc, context)) {
946 		context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
947 				DML_FAIL_DSC_VALIDATION_FAILURE;
948 		goto validate_fail;
949 	}
950 
951 	*vlevel_out = vlevel;
952 
953 	out = true;
954 	goto validate_out;
955 
956 validate_fail:
957 	out = false;
958 
959 validate_out:
960 	return out;
961 }
962 
963 /*
964  * Some of the functions further below use the FPU, so we need to wrap this
965  * with DC_FP_START()/DC_FP_END(). Use the same approach as for
966  * dcn20_validate_bandwidth in dcn20_resource.c.
967  */
968 static bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
969 		bool fast_validate)
970 {
971 	bool voltage_supported;
972 	DC_FP_START();
973 	voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate);
974 	DC_FP_END();
975 	return voltage_supported;
976 }
977 
978 static void dcn21_destroy_resource_pool(struct resource_pool **pool)
979 {
980 	struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
981 
982 	dcn21_resource_destruct(dcn21_pool);
983 	kfree(dcn21_pool);
984 	*pool = NULL;
985 }
986 
987 static struct clock_source *dcn21_clock_source_create(
988 		struct dc_context *ctx,
989 		struct dc_bios *bios,
990 		enum clock_source_id id,
991 		const struct dce110_clk_src_regs *regs,
992 		bool dp_clk_src)
993 {
994 	struct dce110_clk_src *clk_src =
995 		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
996 
997 	if (!clk_src)
998 		return NULL;
999 
1000 	if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1001 			regs, &cs_shift, &cs_mask)) {
1002 		clk_src->base.dp_clk_src = dp_clk_src;
1003 		return &clk_src->base;
1004 	}
1005 
1006 	kfree(clk_src);
1007 	BREAK_TO_DEBUGGER();
1008 	return NULL;
1009 }
1010 
1011 static struct hubp *dcn21_hubp_create(
1012 	struct dc_context *ctx,
1013 	uint32_t inst)
1014 {
1015 	struct dcn21_hubp *hubp21 =
1016 		kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
1017 
1018 	if (!hubp21)
1019 		return NULL;
1020 
1021 	if (hubp21_construct(hubp21, ctx, inst,
1022 			&hubp_regs[inst], &hubp_shift, &hubp_mask))
1023 		return &hubp21->base;
1024 
1025 	BREAK_TO_DEBUGGER();
1026 	kfree(hubp21);
1027 	return NULL;
1028 }
1029 
1030 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1031 {
1032 	int i;
1033 
1034 	struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1035 					  GFP_KERNEL);
1036 
1037 	if (!hubbub)
1038 		return NULL;
1039 
1040 	hubbub21_construct(hubbub, ctx,
1041 			&hubbub_reg,
1042 			&hubbub_shift,
1043 			&hubbub_mask);
1044 
1045 	for (i = 0; i < res_cap_rn.num_vmid; i++) {
1046 		struct dcn20_vmid *vmid = &hubbub->vmid[i];
1047 
1048 		vmid->ctx = ctx;
1049 
1050 		vmid->regs = &vmid_regs[i];
1051 		vmid->shifts = &vmid_shifts;
1052 		vmid->masks = &vmid_masks;
1053 	}
1054 	hubbub->num_vmid = res_cap_rn.num_vmid;
1055 
1056 	return &hubbub->base;
1057 }
1058 
1059 static struct output_pixel_processor *dcn21_opp_create(struct dc_context *ctx,
1060 						       uint32_t inst)
1061 {
1062 	struct dcn20_opp *opp =
1063 		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1064 
1065 	if (!opp) {
1066 		BREAK_TO_DEBUGGER();
1067 		return NULL;
1068 	}
1069 
1070 	dcn20_opp_construct(opp, ctx, inst,
1071 			&opp_regs[inst], &opp_shift, &opp_mask);
1072 	return &opp->base;
1073 }
1074 
1075 static struct timing_generator *dcn21_timing_generator_create(struct dc_context *ctx,
1076 							      uint32_t instance)
1077 {
1078 	struct optc *tgn10 =
1079 		kzalloc(sizeof(struct optc), GFP_KERNEL);
1080 
1081 	if (!tgn10)
1082 		return NULL;
1083 
1084 	tgn10->base.inst = instance;
1085 	tgn10->base.ctx = ctx;
1086 
1087 	tgn10->tg_regs = &tg_regs[instance];
1088 	tgn10->tg_shift = &tg_shift;
1089 	tgn10->tg_mask = &tg_mask;
1090 
1091 	dcn20_timing_generator_init(tgn10);
1092 
1093 	return &tgn10->base;
1094 }
1095 
1096 static struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1097 {
1098 	struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1099 					  GFP_KERNEL);
1100 
1101 	if (!mpc20)
1102 		return NULL;
1103 
1104 	dcn20_mpc_construct(mpc20, ctx,
1105 			&mpc_regs,
1106 			&mpc_shift,
1107 			&mpc_mask,
1108 			6);
1109 
1110 	return &mpc20->base;
1111 }
1112 
1113 static void read_dce_straps(
1114 	struct dc_context *ctx,
1115 	struct resource_straps *straps)
1116 {
1117 	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1118 		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1119 
1120 }
1121 
1122 
1123 static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx,
1124 							  uint32_t inst)
1125 {
1126 	struct dcn20_dsc *dsc =
1127 		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1128 
1129 	if (!dsc) {
1130 		BREAK_TO_DEBUGGER();
1131 		return NULL;
1132 	}
1133 
1134 	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1135 	return &dsc->base;
1136 }
1137 
1138 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
1139 {
1140 	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1141 
1142 	if (!pp_smu)
1143 		return pp_smu;
1144 
1145 	dm_pp_get_funcs(ctx, pp_smu);
1146 
1147 	if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1148 		pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1149 
1150 
1151 	return pp_smu;
1152 }
1153 
1154 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
1155 {
1156 	if (pp_smu && *pp_smu) {
1157 		kfree(*pp_smu);
1158 		*pp_smu = NULL;
1159 	}
1160 }
1161 
1162 static struct audio *dcn21_create_audio(
1163 		struct dc_context *ctx, unsigned int inst)
1164 {
1165 	return dce_audio_create(ctx, inst,
1166 			&audio_regs[inst], &audio_shift, &audio_mask);
1167 }
1168 
1169 static struct dc_cap_funcs cap_funcs = {
1170 	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1171 };
1172 
1173 static struct stream_encoder *dcn21_stream_encoder_create(enum engine_id eng_id,
1174 							  struct dc_context *ctx)
1175 {
1176 	struct dcn10_stream_encoder *enc1 =
1177 		kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1178 
1179 	if (!enc1)
1180 		return NULL;
1181 
1182 	dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1183 					&stream_enc_regs[eng_id],
1184 					&se_shift, &se_mask);
1185 
1186 	return &enc1->base;
1187 }
1188 
1189 static const struct dce_hwseq_registers hwseq_reg = {
1190 		HWSEQ_DCN21_REG_LIST()
1191 };
1192 
1193 static const struct dce_hwseq_shift hwseq_shift = {
1194 		HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1195 };
1196 
1197 static const struct dce_hwseq_mask hwseq_mask = {
1198 		HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1199 };
1200 
1201 static struct dce_hwseq *dcn21_hwseq_create(
1202 	struct dc_context *ctx)
1203 {
1204 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1205 
1206 	if (hws) {
1207 		hws->ctx = ctx;
1208 		hws->regs = &hwseq_reg;
1209 		hws->shifts = &hwseq_shift;
1210 		hws->masks = &hwseq_mask;
1211 		hws->wa.DEGVIDCN21 = true;
1212 		hws->wa.disallow_self_refresh_during_multi_plane_transition = true;
1213 	}
1214 	return hws;
1215 }
1216 
1217 static const struct resource_create_funcs res_create_funcs = {
1218 	.read_dce_straps = read_dce_straps,
1219 	.create_audio = dcn21_create_audio,
1220 	.create_stream_encoder = dcn21_stream_encoder_create,
1221 	.create_hwseq = dcn21_hwseq_create,
1222 };
1223 
1224 static const struct resource_create_funcs res_create_maximus_funcs = {
1225 	.read_dce_straps = NULL,
1226 	.create_audio = NULL,
1227 	.create_stream_encoder = NULL,
1228 	.create_hwseq = dcn21_hwseq_create,
1229 };
1230 
1231 static const struct encoder_feature_support link_enc_feature = {
1232 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
1233 		.max_hdmi_pixel_clock = 600000,
1234 		.hdmi_ycbcr420_supported = true,
1235 		.dp_ycbcr420_supported = true,
1236 		.fec_supported = true,
1237 		.flags.bits.IS_HBR2_CAPABLE = true,
1238 		.flags.bits.IS_HBR3_CAPABLE = true,
1239 		.flags.bits.IS_TPS3_CAPABLE = true,
1240 		.flags.bits.IS_TPS4_CAPABLE = true
1241 };
1242 
1243 
1244 #define link_regs(id, phyid)\
1245 [id] = {\
1246 	LE_DCN2_REG_LIST(id), \
1247 	UNIPHY_DCN2_REG_LIST(phyid), \
1248 	DPCS_DCN21_REG_LIST(id), \
1249 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1250 }
1251 
1252 static const struct dcn10_link_enc_registers link_enc_regs[] = {
1253 	link_regs(0, A),
1254 	link_regs(1, B),
1255 	link_regs(2, C),
1256 	link_regs(3, D),
1257 	link_regs(4, E),
1258 };
1259 
1260 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
1261 	{ DCN_PANEL_CNTL_REG_LIST() }
1262 };
1263 
1264 static const struct dce_panel_cntl_shift panel_cntl_shift = {
1265 	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
1266 };
1267 
1268 static const struct dce_panel_cntl_mask panel_cntl_mask = {
1269 	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
1270 };
1271 
1272 #define aux_regs(id)\
1273 [id] = {\
1274 	DCN2_AUX_REG_LIST(id)\
1275 }
1276 
1277 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1278 		aux_regs(0),
1279 		aux_regs(1),
1280 		aux_regs(2),
1281 		aux_regs(3),
1282 		aux_regs(4)
1283 };
1284 
1285 #define hpd_regs(id)\
1286 [id] = {\
1287 	HPD_REG_LIST(id)\
1288 }
1289 
1290 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1291 		hpd_regs(0),
1292 		hpd_regs(1),
1293 		hpd_regs(2),
1294 		hpd_regs(3),
1295 		hpd_regs(4)
1296 };
1297 
1298 static const struct dcn10_link_enc_shift le_shift = {
1299 	LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1300 	DPCS_DCN21_MASK_SH_LIST(__SHIFT)
1301 };
1302 
1303 static const struct dcn10_link_enc_mask le_mask = {
1304 	LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1305 	DPCS_DCN21_MASK_SH_LIST(_MASK)
1306 };
1307 
1308 static int map_transmitter_id_to_phy_instance(
1309 	enum transmitter transmitter)
1310 {
1311 	switch (transmitter) {
1312 	case TRANSMITTER_UNIPHY_A:
1313 		return 0;
1314 	break;
1315 	case TRANSMITTER_UNIPHY_B:
1316 		return 1;
1317 	break;
1318 	case TRANSMITTER_UNIPHY_C:
1319 		return 2;
1320 	break;
1321 	case TRANSMITTER_UNIPHY_D:
1322 		return 3;
1323 	break;
1324 	case TRANSMITTER_UNIPHY_E:
1325 		return 4;
1326 	break;
1327 	default:
1328 		ASSERT(0);
1329 		return 0;
1330 	}
1331 }
1332 
1333 static struct link_encoder *dcn21_link_encoder_create(
1334 	struct dc_context *ctx,
1335 	const struct encoder_init_data *enc_init_data)
1336 {
1337 	struct dcn21_link_encoder *enc21 =
1338 		kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
1339 	int link_regs_id;
1340 
1341 	if (!enc21)
1342 		return NULL;
1343 
1344 	link_regs_id =
1345 		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1346 
1347 	dcn21_link_encoder_construct(enc21,
1348 				      enc_init_data,
1349 				      &link_enc_feature,
1350 				      &link_enc_regs[link_regs_id],
1351 				      &link_enc_aux_regs[enc_init_data->channel - 1],
1352 				      &link_enc_hpd_regs[enc_init_data->hpd_source],
1353 				      &le_shift,
1354 				      &le_mask);
1355 
1356 	return &enc21->enc10.base;
1357 }
1358 
1359 static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1360 {
1361 	struct dce_panel_cntl *panel_cntl =
1362 		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1363 
1364 	if (!panel_cntl)
1365 		return NULL;
1366 
1367 	dce_panel_cntl_construct(panel_cntl,
1368 			init_data,
1369 			&panel_cntl_regs[init_data->inst],
1370 			&panel_cntl_shift,
1371 			&panel_cntl_mask);
1372 
1373 	return &panel_cntl->base;
1374 }
1375 
1376 static void dcn21_get_panel_config_defaults(struct dc_panel_config *panel_config)
1377 {
1378 	*panel_config = panel_config_defaults;
1379 }
1380 
1381 #define CTX ctx
1382 
1383 #define REG(reg_name) \
1384 	(DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1385 
1386 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1387 {
1388 	uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1389 	/* RV1 support max 4 pipes */
1390 	value = value & 0xf;
1391 	return value;
1392 }
1393 
1394 static enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1395 {
1396 	enum dc_status result = DC_OK;
1397 
1398 	if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {
1399 		plane_state->dcc.enable = 1;
1400 		/* align to our worst case block width */
1401 		plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;
1402 	}
1403 	result = dcn20_patch_unknown_plane_state(plane_state);
1404 	return result;
1405 }
1406 
1407 static const struct resource_funcs dcn21_res_pool_funcs = {
1408 	.destroy = dcn21_destroy_resource_pool,
1409 	.link_enc_create = dcn21_link_encoder_create,
1410 	.panel_cntl_create = dcn21_panel_cntl_create,
1411 	.validate_bandwidth = dcn21_validate_bandwidth,
1412 	.populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
1413 	.add_stream_to_ctx = dcn20_add_stream_to_ctx,
1414 	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1415 	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1416 	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1417 	.populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
1418 	.patch_unknown_plane_state = dcn21_patch_unknown_plane_state,
1419 	.set_mcif_arb_params = dcn20_set_mcif_arb_params,
1420 	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1421 	.update_bw_bounding_box = dcn21_update_bw_bounding_box,
1422 	.get_panel_config_defaults = dcn21_get_panel_config_defaults,
1423 };
1424 
1425 static bool dcn21_resource_construct(
1426 	uint8_t num_virtual_links,
1427 	struct dc *dc,
1428 	struct dcn21_resource_pool *pool)
1429 {
1430 	int i, j;
1431 	struct dc_context *ctx = dc->ctx;
1432 	struct irq_service_init_data init_data;
1433 	uint32_t pipe_fuses = read_pipe_fuses(ctx);
1434 	uint32_t num_pipes;
1435 
1436 	ctx->dc_bios->regs = &bios_regs;
1437 
1438 	pool->base.res_cap = &res_cap_rn;
1439 #ifdef DIAGS_BUILD
1440 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1441 		//pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
1442 		pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
1443 #endif
1444 
1445 	pool->base.funcs = &dcn21_res_pool_funcs;
1446 
1447 	/*************************************************
1448 	 *  Resource + asic cap harcoding                *
1449 	 *************************************************/
1450 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1451 
1452 	/* max pipe num for ASIC before check pipe fuses */
1453 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1454 
1455 	dc->caps.max_downscale_ratio = 200;
1456 	dc->caps.i2c_speed_in_khz = 100;
1457 	dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
1458 	dc->caps.max_cursor_size = 256;
1459 	dc->caps.min_horizontal_blanking_period = 80;
1460 	dc->caps.dmdata_alloc_size = 2048;
1461 
1462 	dc->caps.max_slave_planes = 1;
1463 	dc->caps.max_slave_yuv_planes = 1;
1464 	dc->caps.max_slave_rgb_planes = 1;
1465 	dc->caps.post_blend_color_processing = true;
1466 	dc->caps.force_dp_tps4_for_cp2520 = true;
1467 	dc->caps.extended_aux_timeout_support = true;
1468 	dc->caps.dmcub_support = true;
1469 	dc->caps.is_apu = true;
1470 
1471 	/* Color pipeline capabilities */
1472 	dc->caps.color.dpp.dcn_arch = 1;
1473 	dc->caps.color.dpp.input_lut_shared = 0;
1474 	dc->caps.color.dpp.icsc = 1;
1475 	dc->caps.color.dpp.dgam_ram = 1;
1476 	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1477 	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1478 	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1479 	dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1480 	dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1481 	dc->caps.color.dpp.post_csc = 0;
1482 	dc->caps.color.dpp.gamma_corr = 0;
1483 	dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1484 
1485 	dc->caps.color.dpp.hw_3d_lut = 1;
1486 	dc->caps.color.dpp.ogam_ram = 1;
1487 	// no OGAM ROM on DCN2
1488 	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1489 	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1490 	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1491 	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1492 	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1493 	dc->caps.color.dpp.ocsc = 0;
1494 
1495 	dc->caps.color.mpc.gamut_remap = 0;
1496 	dc->caps.color.mpc.num_3dluts = 0;
1497 	dc->caps.color.mpc.shared_3d_lut = 0;
1498 	dc->caps.color.mpc.ogam_ram = 1;
1499 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1500 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1501 	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1502 	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1503 	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1504 	dc->caps.color.mpc.ocsc = 1;
1505 
1506 	dc->caps.dp_hdmi21_pcon_support = true;
1507 
1508 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1509 		dc->debug = debug_defaults_drv;
1510 	else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1511 		pool->base.pipe_count = 4;
1512 		dc->debug = debug_defaults_diags;
1513 	} else
1514 		dc->debug = debug_defaults_diags;
1515 
1516 	// Init the vm_helper
1517 	if (dc->vm_helper)
1518 		vm_helper_init(dc->vm_helper, 16);
1519 
1520 	/*************************************************
1521 	 *  Create resources                             *
1522 	 *************************************************/
1523 
1524 	pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1525 			dcn21_clock_source_create(ctx, ctx->dc_bios,
1526 				CLOCK_SOURCE_COMBO_PHY_PLL0,
1527 				&clk_src_regs[0], false);
1528 	pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1529 			dcn21_clock_source_create(ctx, ctx->dc_bios,
1530 				CLOCK_SOURCE_COMBO_PHY_PLL1,
1531 				&clk_src_regs[1], false);
1532 	pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
1533 			dcn21_clock_source_create(ctx, ctx->dc_bios,
1534 				CLOCK_SOURCE_COMBO_PHY_PLL2,
1535 				&clk_src_regs[2], false);
1536 	pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
1537 			dcn21_clock_source_create(ctx, ctx->dc_bios,
1538 				CLOCK_SOURCE_COMBO_PHY_PLL3,
1539 				&clk_src_regs[3], false);
1540 	pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
1541 			dcn21_clock_source_create(ctx, ctx->dc_bios,
1542 				CLOCK_SOURCE_COMBO_PHY_PLL4,
1543 				&clk_src_regs[4], false);
1544 
1545 	pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
1546 
1547 	/* todo: not reuse phy_pll registers */
1548 	pool->base.dp_clock_source =
1549 			dcn21_clock_source_create(ctx, ctx->dc_bios,
1550 				CLOCK_SOURCE_ID_DP_DTO,
1551 				&clk_src_regs[0], true);
1552 
1553 	for (i = 0; i < pool->base.clk_src_count; i++) {
1554 		if (pool->base.clock_sources[i] == NULL) {
1555 			dm_error("DC: failed to create clock sources!\n");
1556 			BREAK_TO_DEBUGGER();
1557 			goto create_fail;
1558 		}
1559 	}
1560 
1561 	pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1562 	if (pool->base.dccg == NULL) {
1563 		dm_error("DC: failed to create dccg!\n");
1564 		BREAK_TO_DEBUGGER();
1565 		goto create_fail;
1566 	}
1567 
1568 	if (!dc->config.disable_dmcu) {
1569 		pool->base.dmcu = dcn21_dmcu_create(ctx,
1570 				&dmcu_regs,
1571 				&dmcu_shift,
1572 				&dmcu_mask);
1573 		if (pool->base.dmcu == NULL) {
1574 			dm_error("DC: failed to create dmcu!\n");
1575 			BREAK_TO_DEBUGGER();
1576 			goto create_fail;
1577 		}
1578 
1579 		dc->debug.dmub_command_table = false;
1580 	}
1581 
1582 	if (dc->config.disable_dmcu) {
1583 		pool->base.psr = dmub_psr_create(ctx);
1584 
1585 		if (pool->base.psr == NULL) {
1586 			dm_error("DC: failed to create psr obj!\n");
1587 			BREAK_TO_DEBUGGER();
1588 			goto create_fail;
1589 		}
1590 	}
1591 
1592 	if (dc->config.disable_dmcu)
1593 		pool->base.abm = dmub_abm_create(ctx,
1594 			&abm_regs,
1595 			&abm_shift,
1596 			&abm_mask);
1597 	else
1598 		pool->base.abm = dce_abm_create(ctx,
1599 			&abm_regs,
1600 			&abm_shift,
1601 			&abm_mask);
1602 
1603 	pool->base.pp_smu = dcn21_pp_smu_create(ctx);
1604 
1605 	num_pipes = dcn2_1_ip.max_num_dpp;
1606 
1607 	for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
1608 		if (pipe_fuses & 1 << i)
1609 			num_pipes--;
1610 	dcn2_1_ip.max_num_dpp = num_pipes;
1611 	dcn2_1_ip.max_num_otg = num_pipes;
1612 
1613 	dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1614 
1615 	init_data.ctx = dc->ctx;
1616 	pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
1617 	if (!pool->base.irqs)
1618 		goto create_fail;
1619 
1620 	j = 0;
1621 	/* mem input -> ipp -> dpp -> opp -> TG */
1622 	for (i = 0; i < pool->base.pipe_count; i++) {
1623 		/* if pipe is disabled, skip instance of HW pipe,
1624 		 * i.e, skip ASIC register instance
1625 		 */
1626 		if ((pipe_fuses & (1 << i)) != 0)
1627 			continue;
1628 
1629 		pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
1630 		if (pool->base.hubps[j] == NULL) {
1631 			BREAK_TO_DEBUGGER();
1632 			dm_error(
1633 				"DC: failed to create memory input!\n");
1634 			goto create_fail;
1635 		}
1636 
1637 		pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
1638 		if (pool->base.ipps[j] == NULL) {
1639 			BREAK_TO_DEBUGGER();
1640 			dm_error(
1641 				"DC: failed to create input pixel processor!\n");
1642 			goto create_fail;
1643 		}
1644 
1645 		pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
1646 		if (pool->base.dpps[j] == NULL) {
1647 			BREAK_TO_DEBUGGER();
1648 			dm_error(
1649 				"DC: failed to create dpps!\n");
1650 			goto create_fail;
1651 		}
1652 
1653 		pool->base.opps[j] = dcn21_opp_create(ctx, i);
1654 		if (pool->base.opps[j] == NULL) {
1655 			BREAK_TO_DEBUGGER();
1656 			dm_error(
1657 				"DC: failed to create output pixel processor!\n");
1658 			goto create_fail;
1659 		}
1660 
1661 		pool->base.timing_generators[j] = dcn21_timing_generator_create(
1662 				ctx, i);
1663 		if (pool->base.timing_generators[j] == NULL) {
1664 			BREAK_TO_DEBUGGER();
1665 			dm_error("DC: failed to create tg!\n");
1666 			goto create_fail;
1667 		}
1668 		j++;
1669 	}
1670 
1671 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1672 		pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
1673 		if (pool->base.engines[i] == NULL) {
1674 			BREAK_TO_DEBUGGER();
1675 			dm_error(
1676 				"DC:failed to create aux engine!!\n");
1677 			goto create_fail;
1678 		}
1679 		pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
1680 		if (pool->base.hw_i2cs[i] == NULL) {
1681 			BREAK_TO_DEBUGGER();
1682 			dm_error(
1683 				"DC:failed to create hw i2c!!\n");
1684 			goto create_fail;
1685 		}
1686 		pool->base.sw_i2cs[i] = NULL;
1687 	}
1688 
1689 	pool->base.timing_generator_count = j;
1690 	pool->base.pipe_count = j;
1691 	pool->base.mpcc_count = j;
1692 
1693 	pool->base.mpc = dcn21_mpc_create(ctx);
1694 	if (pool->base.mpc == NULL) {
1695 		BREAK_TO_DEBUGGER();
1696 		dm_error("DC: failed to create mpc!\n");
1697 		goto create_fail;
1698 	}
1699 
1700 	pool->base.hubbub = dcn21_hubbub_create(ctx);
1701 	if (pool->base.hubbub == NULL) {
1702 		BREAK_TO_DEBUGGER();
1703 		dm_error("DC: failed to create hubbub!\n");
1704 		goto create_fail;
1705 	}
1706 
1707 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1708 		pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
1709 		if (pool->base.dscs[i] == NULL) {
1710 			BREAK_TO_DEBUGGER();
1711 			dm_error("DC: failed to create display stream compressor %d!\n", i);
1712 			goto create_fail;
1713 		}
1714 	}
1715 
1716 	if (!dcn20_dwbc_create(ctx, &pool->base)) {
1717 		BREAK_TO_DEBUGGER();
1718 		dm_error("DC: failed to create dwbc!\n");
1719 		goto create_fail;
1720 	}
1721 	if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
1722 		BREAK_TO_DEBUGGER();
1723 		dm_error("DC: failed to create mcif_wb!\n");
1724 		goto create_fail;
1725 	}
1726 
1727 	if (!resource_construct(num_virtual_links, dc, &pool->base,
1728 			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1729 			&res_create_funcs : &res_create_maximus_funcs)))
1730 			goto create_fail;
1731 
1732 	dcn21_hw_sequencer_construct(dc);
1733 
1734 	dc->caps.max_planes =  pool->base.pipe_count;
1735 
1736 	for (i = 0; i < dc->caps.max_planes; ++i)
1737 		dc->caps.planes[i] = plane_cap;
1738 
1739 	dc->cap_funcs = cap_funcs;
1740 
1741 	return true;
1742 
1743 create_fail:
1744 
1745 	dcn21_resource_destruct(pool);
1746 
1747 	return false;
1748 }
1749 
1750 struct resource_pool *dcn21_create_resource_pool(
1751 		const struct dc_init_data *init_data,
1752 		struct dc *dc)
1753 {
1754 	struct dcn21_resource_pool *pool =
1755 		kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
1756 
1757 	if (!pool)
1758 		return NULL;
1759 
1760 	if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
1761 		return &pool->base;
1762 
1763 	BREAK_TO_DEBUGGER();
1764 	kfree(pool);
1765 	return NULL;
1766 }
1767