1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * Copyright 2019 Raptor Engineering, LLC 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 #include "dc.h" 31 32 #include "dcn21_init.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dcn20/dcn20_resource.h" 37 38 #include "clk_mgr.h" 39 #include "dcn10/dcn10_hubp.h" 40 #include "dcn10/dcn10_ipp.h" 41 #include "dcn20/dcn20_hubbub.h" 42 #include "dcn20/dcn20_mpc.h" 43 #include "dcn20/dcn20_hubp.h" 44 #include "dcn21_hubp.h" 45 #include "irq/dcn21/irq_service_dcn21.h" 46 #include "dcn20/dcn20_dpp.h" 47 #include "dcn20/dcn20_optc.h" 48 #include "dcn21/dcn21_hwseq.h" 49 #include "dce110/dce110_hw_sequencer.h" 50 #include "dcn20/dcn20_opp.h" 51 #include "dcn20/dcn20_dsc.h" 52 #include "dcn21/dcn21_link_encoder.h" 53 #include "dcn20/dcn20_stream_encoder.h" 54 #include "dce/dce_clock_source.h" 55 #include "dce/dce_audio.h" 56 #include "dce/dce_hwseq.h" 57 #include "virtual/virtual_stream_encoder.h" 58 #include "dce110/dce110_resource.h" 59 #include "dml/display_mode_vba.h" 60 #include "dcn20/dcn20_dccg.h" 61 #include "dcn21/dcn21_dccg.h" 62 #include "dcn21_hubbub.h" 63 #include "dcn10/dcn10_resource.h" 64 #include "dce110/dce110_resource.h" 65 #include "dce/dce_panel_cntl.h" 66 67 #include "dcn20/dcn20_dwb.h" 68 #include "dcn20/dcn20_mmhubbub.h" 69 #include "dpcs/dpcs_2_1_0_offset.h" 70 #include "dpcs/dpcs_2_1_0_sh_mask.h" 71 72 #include "renoir_ip_offset.h" 73 #include "dcn/dcn_2_1_0_offset.h" 74 #include "dcn/dcn_2_1_0_sh_mask.h" 75 76 #include "nbio/nbio_7_0_offset.h" 77 78 #include "mmhub/mmhub_2_0_0_offset.h" 79 #include "mmhub/mmhub_2_0_0_sh_mask.h" 80 81 #include "reg_helper.h" 82 #include "dce/dce_abm.h" 83 #include "dce/dce_dmcu.h" 84 #include "dce/dce_aux.h" 85 #include "dce/dce_i2c.h" 86 #include "dcn21_resource.h" 87 #include "vm_helper.h" 88 #include "dcn20/dcn20_vmid.h" 89 #include "dce/dmub_psr.h" 90 #include "dce/dmub_abm.h" 91 92 #define DC_LOGGER_INIT(logger) 93 94 95 struct _vcs_dpi_ip_params_st dcn2_1_ip = { 96 .odm_capable = 1, 97 .gpuvm_enable = 1, 98 .hostvm_enable = 1, 99 .gpuvm_max_page_table_levels = 1, 100 .hostvm_max_page_table_levels = 4, 101 .hostvm_cached_page_table_levels = 2, 102 .num_dsc = 3, 103 .rob_buffer_size_kbytes = 168, 104 .det_buffer_size_kbytes = 164, 105 .dpte_buffer_size_in_pte_reqs_luma = 44, 106 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo 107 .dpp_output_buffer_pixels = 2560, 108 .opp_output_buffer_lines = 1, 109 .pixel_chunk_size_kbytes = 8, 110 .pte_enable = 1, 111 .max_page_table_levels = 4, 112 .pte_chunk_size_kbytes = 2, 113 .meta_chunk_size_kbytes = 2, 114 .writeback_chunk_size_kbytes = 2, 115 .line_buffer_size_bits = 789504, 116 .is_line_buffer_bpp_fixed = 0, 117 .line_buffer_fixed_bpp = 0, 118 .dcc_supported = true, 119 .max_line_buffer_lines = 12, 120 .writeback_luma_buffer_size_kbytes = 12, 121 .writeback_chroma_buffer_size_kbytes = 8, 122 .writeback_chroma_line_buffer_width_pixels = 4, 123 .writeback_max_hscl_ratio = 1, 124 .writeback_max_vscl_ratio = 1, 125 .writeback_min_hscl_ratio = 1, 126 .writeback_min_vscl_ratio = 1, 127 .writeback_max_hscl_taps = 12, 128 .writeback_max_vscl_taps = 12, 129 .writeback_line_buffer_luma_buffer_size = 0, 130 .writeback_line_buffer_chroma_buffer_size = 14643, 131 .cursor_buffer_size = 8, 132 .cursor_chunk_size = 2, 133 .max_num_otg = 4, 134 .max_num_dpp = 4, 135 .max_num_wb = 1, 136 .max_dchub_pscl_bw_pix_per_clk = 4, 137 .max_pscl_lb_bw_pix_per_clk = 2, 138 .max_lb_vscl_bw_pix_per_clk = 4, 139 .max_vscl_hscl_bw_pix_per_clk = 4, 140 .max_hscl_ratio = 4, 141 .max_vscl_ratio = 4, 142 .hscl_mults = 4, 143 .vscl_mults = 4, 144 .max_hscl_taps = 8, 145 .max_vscl_taps = 8, 146 .dispclk_ramp_margin_percent = 1, 147 .underscan_factor = 1.10, 148 .min_vblank_lines = 32, // 149 .dppclk_delay_subtotal = 77, // 150 .dppclk_delay_scl_lb_only = 16, 151 .dppclk_delay_scl = 50, 152 .dppclk_delay_cnvc_formatter = 8, 153 .dppclk_delay_cnvc_cursor = 6, 154 .dispclk_delay_subtotal = 87, // 155 .dcfclk_cstate_latency = 10, // SRExitTime 156 .max_inter_dcn_tile_repeaters = 8, 157 158 .xfc_supported = false, 159 .xfc_fill_bw_overhead_percent = 10.0, 160 .xfc_fill_constant_bytes = 0, 161 .ptoi_supported = 0, 162 .number_of_cursors = 1, 163 }; 164 165 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { 166 .clock_limits = { 167 { 168 .state = 0, 169 .dcfclk_mhz = 400.0, 170 .fabricclk_mhz = 400.0, 171 .dispclk_mhz = 600.0, 172 .dppclk_mhz = 400.00, 173 .phyclk_mhz = 600.0, 174 .socclk_mhz = 278.0, 175 .dscclk_mhz = 205.67, 176 .dram_speed_mts = 1600.0, 177 }, 178 { 179 .state = 1, 180 .dcfclk_mhz = 464.52, 181 .fabricclk_mhz = 800.0, 182 .dispclk_mhz = 654.55, 183 .dppclk_mhz = 626.09, 184 .phyclk_mhz = 600.0, 185 .socclk_mhz = 278.0, 186 .dscclk_mhz = 205.67, 187 .dram_speed_mts = 1600.0, 188 }, 189 { 190 .state = 2, 191 .dcfclk_mhz = 514.29, 192 .fabricclk_mhz = 933.0, 193 .dispclk_mhz = 757.89, 194 .dppclk_mhz = 685.71, 195 .phyclk_mhz = 600.0, 196 .socclk_mhz = 278.0, 197 .dscclk_mhz = 287.67, 198 .dram_speed_mts = 1866.0, 199 }, 200 { 201 .state = 3, 202 .dcfclk_mhz = 576.00, 203 .fabricclk_mhz = 1067.0, 204 .dispclk_mhz = 847.06, 205 .dppclk_mhz = 757.89, 206 .phyclk_mhz = 600.0, 207 .socclk_mhz = 715.0, 208 .dscclk_mhz = 318.334, 209 .dram_speed_mts = 2134.0, 210 }, 211 { 212 .state = 4, 213 .dcfclk_mhz = 626.09, 214 .fabricclk_mhz = 1200.0, 215 .dispclk_mhz = 900.00, 216 .dppclk_mhz = 847.06, 217 .phyclk_mhz = 810.0, 218 .socclk_mhz = 953.0, 219 .dscclk_mhz = 489.0, 220 .dram_speed_mts = 2400.0, 221 }, 222 { 223 .state = 5, 224 .dcfclk_mhz = 685.71, 225 .fabricclk_mhz = 1333.0, 226 .dispclk_mhz = 1028.57, 227 .dppclk_mhz = 960.00, 228 .phyclk_mhz = 810.0, 229 .socclk_mhz = 278.0, 230 .dscclk_mhz = 287.67, 231 .dram_speed_mts = 2666.0, 232 }, 233 { 234 .state = 6, 235 .dcfclk_mhz = 757.89, 236 .fabricclk_mhz = 1467.0, 237 .dispclk_mhz = 1107.69, 238 .dppclk_mhz = 1028.57, 239 .phyclk_mhz = 810.0, 240 .socclk_mhz = 715.0, 241 .dscclk_mhz = 318.334, 242 .dram_speed_mts = 3200.0, 243 }, 244 { 245 .state = 7, 246 .dcfclk_mhz = 847.06, 247 .fabricclk_mhz = 1600.0, 248 .dispclk_mhz = 1395.0, 249 .dppclk_mhz = 1285.00, 250 .phyclk_mhz = 1325.0, 251 .socclk_mhz = 953.0, 252 .dscclk_mhz = 489.0, 253 .dram_speed_mts = 4266.0, 254 }, 255 /*Extra state, no dispclk ramping*/ 256 { 257 .state = 8, 258 .dcfclk_mhz = 847.06, 259 .fabricclk_mhz = 1600.0, 260 .dispclk_mhz = 1395.0, 261 .dppclk_mhz = 1285.0, 262 .phyclk_mhz = 1325.0, 263 .socclk_mhz = 953.0, 264 .dscclk_mhz = 489.0, 265 .dram_speed_mts = 4266.0, 266 }, 267 268 }, 269 270 .sr_exit_time_us = 12.5, 271 .sr_enter_plus_exit_time_us = 17.0, 272 .urgent_latency_us = 4.0, 273 .urgent_latency_pixel_data_only_us = 4.0, 274 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 275 .urgent_latency_vm_data_only_us = 4.0, 276 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 277 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 278 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 279 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 280 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0, 281 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 282 .max_avg_sdp_bw_use_normal_percent = 60.0, 283 .max_avg_dram_bw_use_normal_percent = 100.0, 284 .writeback_latency_us = 12.0, 285 .max_request_size_bytes = 256, 286 .dram_channel_width_bytes = 4, 287 .fabric_datapath_to_dcn_data_return_bytes = 32, 288 .dcn_downspread_percent = 0.5, 289 .downspread_percent = 0.38, 290 .dram_page_open_time_ns = 50.0, 291 .dram_rw_turnaround_time_ns = 17.5, 292 .dram_return_buffer_per_channel_bytes = 8192, 293 .round_trip_ping_latency_dcfclk_cycles = 128, 294 .urgent_out_of_order_return_per_channel_bytes = 4096, 295 .channel_interleave_bytes = 256, 296 .num_banks = 8, 297 .num_chans = 4, 298 .vmm_page_size_bytes = 4096, 299 .dram_clock_change_latency_us = 11.72, 300 .return_bus_width_bytes = 64, 301 .dispclk_dppclk_vco_speed_mhz = 3600, 302 .xfc_bus_transport_time_us = 4, 303 .xfc_xbuf_latency_tolerance_us = 4, 304 .use_urgent_burst_bw = 1, 305 .num_states = 8 306 }; 307 308 #ifndef MAX 309 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y)) 310 #endif 311 #ifndef MIN 312 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 313 #endif 314 315 /* begin ********************* 316 * macros to expend register list macro defined in HW object header file */ 317 318 /* DCN */ 319 /* TODO awful hack. fixup dcn20_dwb.h */ 320 #undef BASE_INNER 321 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg 322 323 #define BASE(seg) BASE_INNER(seg) 324 325 #define SR(reg_name)\ 326 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 327 mm ## reg_name 328 329 #define SRI(reg_name, block, id)\ 330 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 331 mm ## block ## id ## _ ## reg_name 332 333 #define SRIR(var_name, reg_name, block, id)\ 334 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 335 mm ## block ## id ## _ ## reg_name 336 337 #define SRII(reg_name, block, id)\ 338 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 339 mm ## block ## id ## _ ## reg_name 340 341 #define DCCG_SRII(reg_name, block, id)\ 342 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 343 mm ## block ## id ## _ ## reg_name 344 345 #define VUPDATE_SRII(reg_name, block, id)\ 346 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 347 mm ## reg_name ## _ ## block ## id 348 349 /* NBIO */ 350 #define NBIO_BASE_INNER(seg) \ 351 NBIF0_BASE__INST0_SEG ## seg 352 353 #define NBIO_BASE(seg) \ 354 NBIO_BASE_INNER(seg) 355 356 #define NBIO_SR(reg_name)\ 357 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 358 mm ## reg_name 359 360 /* MMHUB */ 361 #define MMHUB_BASE_INNER(seg) \ 362 MMHUB_BASE__INST0_SEG ## seg 363 364 #define MMHUB_BASE(seg) \ 365 MMHUB_BASE_INNER(seg) 366 367 #define MMHUB_SR(reg_name)\ 368 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 369 mmMM ## reg_name 370 371 #define clk_src_regs(index, pllid)\ 372 [index] = {\ 373 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\ 374 } 375 376 static const struct dce110_clk_src_regs clk_src_regs[] = { 377 clk_src_regs(0, A), 378 clk_src_regs(1, B), 379 clk_src_regs(2, C), 380 clk_src_regs(3, D), 381 clk_src_regs(4, E), 382 }; 383 384 static const struct dce110_clk_src_shift cs_shift = { 385 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 386 }; 387 388 static const struct dce110_clk_src_mask cs_mask = { 389 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 390 }; 391 392 static const struct bios_registers bios_regs = { 393 NBIO_SR(BIOS_SCRATCH_3), 394 NBIO_SR(BIOS_SCRATCH_6) 395 }; 396 397 static const struct dce_dmcu_registers dmcu_regs = { 398 DMCU_DCN20_REG_LIST() 399 }; 400 401 static const struct dce_dmcu_shift dmcu_shift = { 402 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 403 }; 404 405 static const struct dce_dmcu_mask dmcu_mask = { 406 DMCU_MASK_SH_LIST_DCN10(_MASK) 407 }; 408 409 static const struct dce_abm_registers abm_regs = { 410 ABM_DCN20_REG_LIST() 411 }; 412 413 static const struct dce_abm_shift abm_shift = { 414 ABM_MASK_SH_LIST_DCN20(__SHIFT) 415 }; 416 417 static const struct dce_abm_mask abm_mask = { 418 ABM_MASK_SH_LIST_DCN20(_MASK) 419 }; 420 421 #define audio_regs(id)\ 422 [id] = {\ 423 AUD_COMMON_REG_LIST(id)\ 424 } 425 426 static const struct dce_audio_registers audio_regs[] = { 427 audio_regs(0), 428 audio_regs(1), 429 audio_regs(2), 430 audio_regs(3), 431 audio_regs(4), 432 audio_regs(5), 433 }; 434 435 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 436 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 437 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 438 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 439 440 static const struct dce_audio_shift audio_shift = { 441 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 442 }; 443 444 static const struct dce_audio_mask audio_mask = { 445 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 446 }; 447 448 static const struct dccg_registers dccg_regs = { 449 DCCG_COMMON_REG_LIST_DCN_BASE() 450 }; 451 452 static const struct dccg_shift dccg_shift = { 453 DCCG_MASK_SH_LIST_DCN2(__SHIFT) 454 }; 455 456 static const struct dccg_mask dccg_mask = { 457 DCCG_MASK_SH_LIST_DCN2(_MASK) 458 }; 459 460 #define opp_regs(id)\ 461 [id] = {\ 462 OPP_REG_LIST_DCN20(id),\ 463 } 464 465 static const struct dcn20_opp_registers opp_regs[] = { 466 opp_regs(0), 467 opp_regs(1), 468 opp_regs(2), 469 opp_regs(3), 470 opp_regs(4), 471 opp_regs(5), 472 }; 473 474 static const struct dcn20_opp_shift opp_shift = { 475 OPP_MASK_SH_LIST_DCN20(__SHIFT) 476 }; 477 478 static const struct dcn20_opp_mask opp_mask = { 479 OPP_MASK_SH_LIST_DCN20(_MASK) 480 }; 481 482 #define tg_regs(id)\ 483 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)} 484 485 static const struct dcn_optc_registers tg_regs[] = { 486 tg_regs(0), 487 tg_regs(1), 488 tg_regs(2), 489 tg_regs(3) 490 }; 491 492 static const struct dcn_optc_shift tg_shift = { 493 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 494 }; 495 496 static const struct dcn_optc_mask tg_mask = { 497 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 498 }; 499 500 static const struct dcn20_mpc_registers mpc_regs = { 501 MPC_REG_LIST_DCN2_0(0), 502 MPC_REG_LIST_DCN2_0(1), 503 MPC_REG_LIST_DCN2_0(2), 504 MPC_REG_LIST_DCN2_0(3), 505 MPC_REG_LIST_DCN2_0(4), 506 MPC_REG_LIST_DCN2_0(5), 507 MPC_OUT_MUX_REG_LIST_DCN2_0(0), 508 MPC_OUT_MUX_REG_LIST_DCN2_0(1), 509 MPC_OUT_MUX_REG_LIST_DCN2_0(2), 510 MPC_OUT_MUX_REG_LIST_DCN2_0(3), 511 MPC_DBG_REG_LIST_DCN2_0() 512 }; 513 514 static const struct dcn20_mpc_shift mpc_shift = { 515 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT), 516 MPC_DEBUG_REG_LIST_SH_DCN20 517 }; 518 519 static const struct dcn20_mpc_mask mpc_mask = { 520 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK), 521 MPC_DEBUG_REG_LIST_MASK_DCN20 522 }; 523 524 #define hubp_regs(id)\ 525 [id] = {\ 526 HUBP_REG_LIST_DCN21(id)\ 527 } 528 529 static const struct dcn_hubp2_registers hubp_regs[] = { 530 hubp_regs(0), 531 hubp_regs(1), 532 hubp_regs(2), 533 hubp_regs(3) 534 }; 535 536 static const struct dcn_hubp2_shift hubp_shift = { 537 HUBP_MASK_SH_LIST_DCN21(__SHIFT) 538 }; 539 540 static const struct dcn_hubp2_mask hubp_mask = { 541 HUBP_MASK_SH_LIST_DCN21(_MASK) 542 }; 543 544 static const struct dcn_hubbub_registers hubbub_reg = { 545 HUBBUB_REG_LIST_DCN21() 546 }; 547 548 static const struct dcn_hubbub_shift hubbub_shift = { 549 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT) 550 }; 551 552 static const struct dcn_hubbub_mask hubbub_mask = { 553 HUBBUB_MASK_SH_LIST_DCN21(_MASK) 554 }; 555 556 557 #define vmid_regs(id)\ 558 [id] = {\ 559 DCN20_VMID_REG_LIST(id)\ 560 } 561 562 static const struct dcn_vmid_registers vmid_regs[] = { 563 vmid_regs(0), 564 vmid_regs(1), 565 vmid_regs(2), 566 vmid_regs(3), 567 vmid_regs(4), 568 vmid_regs(5), 569 vmid_regs(6), 570 vmid_regs(7), 571 vmid_regs(8), 572 vmid_regs(9), 573 vmid_regs(10), 574 vmid_regs(11), 575 vmid_regs(12), 576 vmid_regs(13), 577 vmid_regs(14), 578 vmid_regs(15) 579 }; 580 581 static const struct dcn20_vmid_shift vmid_shifts = { 582 DCN20_VMID_MASK_SH_LIST(__SHIFT) 583 }; 584 585 static const struct dcn20_vmid_mask vmid_masks = { 586 DCN20_VMID_MASK_SH_LIST(_MASK) 587 }; 588 589 #define dsc_regsDCN20(id)\ 590 [id] = {\ 591 DSC_REG_LIST_DCN20(id)\ 592 } 593 594 static const struct dcn20_dsc_registers dsc_regs[] = { 595 dsc_regsDCN20(0), 596 dsc_regsDCN20(1), 597 dsc_regsDCN20(2), 598 dsc_regsDCN20(3), 599 dsc_regsDCN20(4), 600 dsc_regsDCN20(5) 601 }; 602 603 static const struct dcn20_dsc_shift dsc_shift = { 604 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 605 }; 606 607 static const struct dcn20_dsc_mask dsc_mask = { 608 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 609 }; 610 611 #define ipp_regs(id)\ 612 [id] = {\ 613 IPP_REG_LIST_DCN20(id),\ 614 } 615 616 static const struct dcn10_ipp_registers ipp_regs[] = { 617 ipp_regs(0), 618 ipp_regs(1), 619 ipp_regs(2), 620 ipp_regs(3), 621 }; 622 623 static const struct dcn10_ipp_shift ipp_shift = { 624 IPP_MASK_SH_LIST_DCN20(__SHIFT) 625 }; 626 627 static const struct dcn10_ipp_mask ipp_mask = { 628 IPP_MASK_SH_LIST_DCN20(_MASK), 629 }; 630 631 #define opp_regs(id)\ 632 [id] = {\ 633 OPP_REG_LIST_DCN20(id),\ 634 } 635 636 637 #define aux_engine_regs(id)\ 638 [id] = {\ 639 AUX_COMMON_REG_LIST0(id), \ 640 .AUXN_IMPCAL = 0, \ 641 .AUXP_IMPCAL = 0, \ 642 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 643 } 644 645 static const struct dce110_aux_registers aux_engine_regs[] = { 646 aux_engine_regs(0), 647 aux_engine_regs(1), 648 aux_engine_regs(2), 649 aux_engine_regs(3), 650 aux_engine_regs(4), 651 }; 652 653 #define tf_regs(id)\ 654 [id] = {\ 655 TF_REG_LIST_DCN20(id),\ 656 TF_REG_LIST_DCN20_COMMON_APPEND(id),\ 657 } 658 659 static const struct dcn2_dpp_registers tf_regs[] = { 660 tf_regs(0), 661 tf_regs(1), 662 tf_regs(2), 663 tf_regs(3), 664 }; 665 666 static const struct dcn2_dpp_shift tf_shift = { 667 TF_REG_LIST_SH_MASK_DCN20(__SHIFT), 668 TF_DEBUG_REG_LIST_SH_DCN20 669 }; 670 671 static const struct dcn2_dpp_mask tf_mask = { 672 TF_REG_LIST_SH_MASK_DCN20(_MASK), 673 TF_DEBUG_REG_LIST_MASK_DCN20 674 }; 675 676 #define stream_enc_regs(id)\ 677 [id] = {\ 678 SE_DCN2_REG_LIST(id)\ 679 } 680 681 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 682 stream_enc_regs(0), 683 stream_enc_regs(1), 684 stream_enc_regs(2), 685 stream_enc_regs(3), 686 stream_enc_regs(4), 687 }; 688 689 static const struct dce110_aux_registers_shift aux_shift = { 690 DCN_AUX_MASK_SH_LIST(__SHIFT) 691 }; 692 693 static const struct dce110_aux_registers_mask aux_mask = { 694 DCN_AUX_MASK_SH_LIST(_MASK) 695 }; 696 697 static const struct dcn10_stream_encoder_shift se_shift = { 698 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) 699 }; 700 701 static const struct dcn10_stream_encoder_mask se_mask = { 702 SE_COMMON_MASK_SH_LIST_DCN20(_MASK) 703 }; 704 705 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu); 706 707 static int dcn21_populate_dml_pipes_from_context( 708 struct dc *dc, 709 struct dc_state *context, 710 display_e2e_pipe_params_st *pipes, 711 bool fast_validate); 712 713 static struct input_pixel_processor *dcn21_ipp_create( 714 struct dc_context *ctx, uint32_t inst) 715 { 716 struct dcn10_ipp *ipp = 717 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 718 719 if (!ipp) { 720 BREAK_TO_DEBUGGER(); 721 return NULL; 722 } 723 724 dcn20_ipp_construct(ipp, ctx, inst, 725 &ipp_regs[inst], &ipp_shift, &ipp_mask); 726 return &ipp->base; 727 } 728 729 static struct dpp *dcn21_dpp_create( 730 struct dc_context *ctx, 731 uint32_t inst) 732 { 733 struct dcn20_dpp *dpp = 734 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL); 735 736 if (!dpp) 737 return NULL; 738 739 if (dpp2_construct(dpp, ctx, inst, 740 &tf_regs[inst], &tf_shift, &tf_mask)) 741 return &dpp->base; 742 743 BREAK_TO_DEBUGGER(); 744 kfree(dpp); 745 return NULL; 746 } 747 748 static struct dce_aux *dcn21_aux_engine_create( 749 struct dc_context *ctx, 750 uint32_t inst) 751 { 752 struct aux_engine_dce110 *aux_engine = 753 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 754 755 if (!aux_engine) 756 return NULL; 757 758 dce110_aux_engine_construct(aux_engine, ctx, inst, 759 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 760 &aux_engine_regs[inst], 761 &aux_mask, 762 &aux_shift, 763 ctx->dc->caps.extended_aux_timeout_support); 764 765 return &aux_engine->base; 766 } 767 768 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 769 770 static const struct dce_i2c_registers i2c_hw_regs[] = { 771 i2c_inst_regs(1), 772 i2c_inst_regs(2), 773 i2c_inst_regs(3), 774 i2c_inst_regs(4), 775 i2c_inst_regs(5), 776 }; 777 778 static const struct dce_i2c_shift i2c_shifts = { 779 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 780 }; 781 782 static const struct dce_i2c_mask i2c_masks = { 783 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 784 }; 785 786 struct dce_i2c_hw *dcn21_i2c_hw_create( 787 struct dc_context *ctx, 788 uint32_t inst) 789 { 790 struct dce_i2c_hw *dce_i2c_hw = 791 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 792 793 if (!dce_i2c_hw) 794 return NULL; 795 796 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 797 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 798 799 return dce_i2c_hw; 800 } 801 802 static const struct resource_caps res_cap_rn = { 803 .num_timing_generator = 4, 804 .num_opp = 4, 805 .num_video_plane = 4, 806 .num_audio = 4, // 4 audio endpoints. 4 audio streams 807 .num_stream_encoder = 5, 808 .num_pll = 5, // maybe 3 because the last two used for USB-c 809 .num_dwb = 1, 810 .num_ddc = 5, 811 .num_vmid = 16, 812 .num_dsc = 3, 813 }; 814 815 #ifdef DIAGS_BUILD 816 static const struct resource_caps res_cap_rn_FPGA_4pipe = { 817 .num_timing_generator = 4, 818 .num_opp = 4, 819 .num_video_plane = 4, 820 .num_audio = 7, 821 .num_stream_encoder = 4, 822 .num_pll = 4, 823 .num_dwb = 1, 824 .num_ddc = 4, 825 .num_dsc = 0, 826 }; 827 828 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = { 829 .num_timing_generator = 2, 830 .num_opp = 2, 831 .num_video_plane = 2, 832 .num_audio = 7, 833 .num_stream_encoder = 2, 834 .num_pll = 4, 835 .num_dwb = 1, 836 .num_ddc = 4, 837 .num_dsc = 2, 838 }; 839 #endif 840 841 static const struct dc_plane_cap plane_cap = { 842 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 843 .blends_with_above = true, 844 .blends_with_below = true, 845 .per_pixel_alpha = true, 846 847 .pixel_format_support = { 848 .argb8888 = true, 849 .nv12 = true, 850 .fp16 = true, 851 .p010 = true 852 }, 853 854 .max_upscale_factor = { 855 .argb8888 = 16000, 856 .nv12 = 16000, 857 .fp16 = 16000 858 }, 859 860 .max_downscale_factor = { 861 .argb8888 = 250, 862 .nv12 = 250, 863 .fp16 = 250 864 }, 865 64, 866 64 867 }; 868 869 static const struct dc_debug_options debug_defaults_drv = { 870 .disable_dmcu = false, 871 .force_abm_enable = false, 872 .timing_trace = false, 873 .clock_trace = true, 874 .disable_pplib_clock_request = true, 875 .min_disp_clk_khz = 100000, 876 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 877 .force_single_disp_pipe_split = false, 878 .disable_dcc = DCC_ENABLE, 879 .vsr_support = true, 880 .performance_trace = false, 881 .max_downscale_src_width = 4096, 882 .disable_pplib_wm_range = false, 883 .scl_reset_length10 = true, 884 .sanity_checks = true, 885 .disable_48mhz_pwrdwn = false, 886 .usbc_combo_phy_reset_wa = true 887 }; 888 889 static const struct dc_debug_options debug_defaults_diags = { 890 .disable_dmcu = false, 891 .force_abm_enable = false, 892 .timing_trace = true, 893 .clock_trace = true, 894 .disable_dpp_power_gate = true, 895 .disable_hubp_power_gate = true, 896 .disable_clock_gate = true, 897 .disable_pplib_clock_request = true, 898 .disable_pplib_wm_range = true, 899 .disable_stutter = true, 900 .disable_48mhz_pwrdwn = true, 901 .disable_psr = true, 902 .enable_tri_buf = true 903 }; 904 905 enum dcn20_clk_src_array_id { 906 DCN20_CLK_SRC_PLL0, 907 DCN20_CLK_SRC_PLL1, 908 DCN20_CLK_SRC_PLL2, 909 DCN20_CLK_SRC_PLL3, 910 DCN20_CLK_SRC_PLL4, 911 DCN20_CLK_SRC_TOTAL_DCN21 912 }; 913 914 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) 915 { 916 unsigned int i; 917 918 for (i = 0; i < pool->base.stream_enc_count; i++) { 919 if (pool->base.stream_enc[i] != NULL) { 920 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 921 pool->base.stream_enc[i] = NULL; 922 } 923 } 924 925 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 926 if (pool->base.dscs[i] != NULL) 927 dcn20_dsc_destroy(&pool->base.dscs[i]); 928 } 929 930 if (pool->base.mpc != NULL) { 931 kfree(TO_DCN20_MPC(pool->base.mpc)); 932 pool->base.mpc = NULL; 933 } 934 if (pool->base.hubbub != NULL) { 935 kfree(pool->base.hubbub); 936 pool->base.hubbub = NULL; 937 } 938 for (i = 0; i < pool->base.pipe_count; i++) { 939 if (pool->base.dpps[i] != NULL) 940 dcn20_dpp_destroy(&pool->base.dpps[i]); 941 942 if (pool->base.ipps[i] != NULL) 943 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 944 945 if (pool->base.hubps[i] != NULL) { 946 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 947 pool->base.hubps[i] = NULL; 948 } 949 950 if (pool->base.irqs != NULL) { 951 dal_irq_service_destroy(&pool->base.irqs); 952 } 953 } 954 955 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 956 if (pool->base.engines[i] != NULL) 957 dce110_engine_destroy(&pool->base.engines[i]); 958 if (pool->base.hw_i2cs[i] != NULL) { 959 kfree(pool->base.hw_i2cs[i]); 960 pool->base.hw_i2cs[i] = NULL; 961 } 962 if (pool->base.sw_i2cs[i] != NULL) { 963 kfree(pool->base.sw_i2cs[i]); 964 pool->base.sw_i2cs[i] = NULL; 965 } 966 } 967 968 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 969 if (pool->base.opps[i] != NULL) 970 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 971 } 972 973 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 974 if (pool->base.timing_generators[i] != NULL) { 975 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 976 pool->base.timing_generators[i] = NULL; 977 } 978 } 979 980 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 981 if (pool->base.dwbc[i] != NULL) { 982 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); 983 pool->base.dwbc[i] = NULL; 984 } 985 if (pool->base.mcif_wb[i] != NULL) { 986 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); 987 pool->base.mcif_wb[i] = NULL; 988 } 989 } 990 991 for (i = 0; i < pool->base.audio_count; i++) { 992 if (pool->base.audios[i]) 993 dce_aud_destroy(&pool->base.audios[i]); 994 } 995 996 for (i = 0; i < pool->base.clk_src_count; i++) { 997 if (pool->base.clock_sources[i] != NULL) { 998 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 999 pool->base.clock_sources[i] = NULL; 1000 } 1001 } 1002 1003 if (pool->base.dp_clock_source != NULL) { 1004 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1005 pool->base.dp_clock_source = NULL; 1006 } 1007 1008 if (pool->base.abm != NULL) { 1009 if (pool->base.abm->ctx->dc->config.disable_dmcu) 1010 dmub_abm_destroy(&pool->base.abm); 1011 else 1012 dce_abm_destroy(&pool->base.abm); 1013 } 1014 1015 if (pool->base.dmcu != NULL) 1016 dce_dmcu_destroy(&pool->base.dmcu); 1017 1018 if (pool->base.psr != NULL) 1019 dmub_psr_destroy(&pool->base.psr); 1020 1021 if (pool->base.dccg != NULL) 1022 dcn_dccg_destroy(&pool->base.dccg); 1023 1024 if (pool->base.pp_smu != NULL) 1025 dcn21_pp_smu_destroy(&pool->base.pp_smu); 1026 } 1027 1028 1029 static void calculate_wm_set_for_vlevel( 1030 int vlevel, 1031 struct wm_range_table_entry *table_entry, 1032 struct dcn_watermarks *wm_set, 1033 struct display_mode_lib *dml, 1034 display_e2e_pipe_params_st *pipes, 1035 int pipe_cnt) 1036 { 1037 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; 1038 1039 ASSERT(vlevel < dml->soc.num_states); 1040 /* only pipe 0 is read for voltage and dcf/soc clocks */ 1041 pipes[0].clks_cfg.voltage = vlevel; 1042 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; 1043 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; 1044 1045 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; 1046 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; 1047 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; 1048 1049 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; 1050 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; 1051 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; 1052 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 1053 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; 1054 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; 1055 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; 1056 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000; 1057 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; 1058 1059 } 1060 1061 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) 1062 { 1063 int i; 1064 1065 DC_FP_START(); 1066 1067 if (dc->bb_overrides.sr_exit_time_ns) { 1068 for (i = 0; i < WM_SET_COUNT; i++) { 1069 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us = 1070 dc->bb_overrides.sr_exit_time_ns / 1000.0; 1071 } 1072 } 1073 1074 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) { 1075 for (i = 0; i < WM_SET_COUNT; i++) { 1076 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us = 1077 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 1078 } 1079 } 1080 1081 if (dc->bb_overrides.urgent_latency_ns) { 1082 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 1083 } 1084 1085 if (dc->bb_overrides.dram_clock_change_latency_ns) { 1086 for (i = 0; i < WM_SET_COUNT; i++) { 1087 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us = 1088 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 1089 } 1090 } 1091 1092 DC_FP_END(); 1093 } 1094 1095 void dcn21_calculate_wm( 1096 struct dc *dc, struct dc_state *context, 1097 display_e2e_pipe_params_st *pipes, 1098 int *out_pipe_cnt, 1099 int *pipe_split_from, 1100 int vlevel_req, 1101 bool fast_validate) 1102 { 1103 int pipe_cnt, i, pipe_idx; 1104 int vlevel, vlevel_max; 1105 struct wm_range_table_entry *table_entry; 1106 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; 1107 1108 ASSERT(bw_params); 1109 1110 patch_bounding_box(dc, &context->bw_ctx.dml.soc); 1111 1112 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1113 if (!context->res_ctx.pipe_ctx[i].stream) 1114 continue; 1115 1116 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 1117 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb]; 1118 1119 if (pipe_split_from[i] < 0) { 1120 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1121 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; 1122 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) 1123 pipes[pipe_cnt].pipe.dest.odm_combine = 1124 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx]; 1125 else 1126 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1127 pipe_idx++; 1128 } else { 1129 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 1130 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; 1131 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) 1132 pipes[pipe_cnt].pipe.dest.odm_combine = 1133 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]]; 1134 else 1135 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 1136 } 1137 pipe_cnt++; 1138 } 1139 1140 if (pipe_cnt != pipe_idx) { 1141 if (dc->res_pool->funcs->populate_dml_pipes) 1142 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, 1143 context, pipes, fast_validate); 1144 else 1145 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc, 1146 context, pipes, fast_validate); 1147 } 1148 1149 *out_pipe_cnt = pipe_cnt; 1150 1151 vlevel_max = bw_params->clk_table.num_entries - 1; 1152 1153 1154 /* WM Set D */ 1155 table_entry = &bw_params->wm_table.entries[WM_D]; 1156 if (table_entry->wm_type == WM_TYPE_RETRAINING) 1157 vlevel = 0; 1158 else 1159 vlevel = vlevel_max; 1160 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, 1161 &context->bw_ctx.dml, pipes, pipe_cnt); 1162 /* WM Set C */ 1163 table_entry = &bw_params->wm_table.entries[WM_C]; 1164 vlevel = MIN(MAX(vlevel_req, 3), vlevel_max); 1165 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, 1166 &context->bw_ctx.dml, pipes, pipe_cnt); 1167 /* WM Set B */ 1168 table_entry = &bw_params->wm_table.entries[WM_B]; 1169 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max); 1170 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, 1171 &context->bw_ctx.dml, pipes, pipe_cnt); 1172 1173 /* WM Set A */ 1174 table_entry = &bw_params->wm_table.entries[WM_A]; 1175 vlevel = MIN(vlevel_req, vlevel_max); 1176 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, 1177 &context->bw_ctx.dml, pipes, pipe_cnt); 1178 } 1179 1180 1181 static bool dcn21_fast_validate_bw( 1182 struct dc *dc, 1183 struct dc_state *context, 1184 display_e2e_pipe_params_st *pipes, 1185 int *pipe_cnt_out, 1186 int *pipe_split_from, 1187 int *vlevel_out, 1188 bool fast_validate) 1189 { 1190 bool out = false; 1191 int split[MAX_PIPES] = { 0 }; 1192 int pipe_cnt, i, pipe_idx, vlevel; 1193 1194 ASSERT(pipes); 1195 if (!pipes) 1196 return false; 1197 1198 dcn20_merge_pipes_for_validate(dc, context); 1199 1200 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 1201 1202 *pipe_cnt_out = pipe_cnt; 1203 1204 if (!pipe_cnt) { 1205 out = true; 1206 goto validate_out; 1207 } 1208 /* 1209 * DML favors voltage over p-state, but we're more interested in 1210 * supporting p-state over voltage. We can't support p-state in 1211 * prefetch mode > 0 so try capping the prefetch mode to start. 1212 */ 1213 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = 1214 dm_allow_self_refresh_and_mclk_switch; 1215 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1216 1217 if (vlevel > context->bw_ctx.dml.soc.num_states) { 1218 /* 1219 * If mode is unsupported or there's still no p-state support then 1220 * fall back to favoring voltage. 1221 * 1222 * We don't actually support prefetch mode 2, so require that we 1223 * at least support prefetch mode 1. 1224 */ 1225 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = 1226 dm_allow_self_refresh; 1227 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1228 if (vlevel > context->bw_ctx.dml.soc.num_states) 1229 goto validate_fail; 1230 } 1231 1232 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL); 1233 1234 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1235 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1236 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe; 1237 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 1238 1239 if (!pipe->stream) 1240 continue; 1241 1242 /* We only support full screen mpo with ODM */ 1243 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled 1244 && pipe->plane_state && mpo_pipe 1245 && memcmp(&mpo_pipe->plane_res.scl_data.recout, 1246 &pipe->plane_res.scl_data.recout, 1247 sizeof(struct rect)) != 0) { 1248 ASSERT(mpo_pipe->plane_state != pipe->plane_state); 1249 goto validate_fail; 1250 } 1251 pipe_idx++; 1252 } 1253 1254 /*initialize pipe_just_split_from to invalid idx*/ 1255 for (i = 0; i < MAX_PIPES; i++) 1256 pipe_split_from[i] = -1; 1257 1258 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { 1259 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1260 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 1261 1262 if (!pipe->stream || pipe_split_from[i] >= 0) 1263 continue; 1264 1265 pipe_idx++; 1266 1267 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 1268 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 1269 ASSERT(hsplit_pipe); 1270 if (!dcn20_split_stream_for_odm( 1271 dc, &context->res_ctx, 1272 pipe, hsplit_pipe)) 1273 goto validate_fail; 1274 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 1275 dcn20_build_mapped_resource(dc, context, pipe->stream); 1276 } 1277 1278 if (!pipe->plane_state) 1279 continue; 1280 /* Skip 2nd half of already split pipe */ 1281 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state) 1282 continue; 1283 1284 if (split[i] == 2) { 1285 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) { 1286 /* pipe not split previously needs split */ 1287 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 1288 ASSERT(hsplit_pipe); 1289 if (!hsplit_pipe) { 1290 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2; 1291 continue; 1292 } 1293 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 1294 if (!dcn20_split_stream_for_odm( 1295 dc, &context->res_ctx, 1296 pipe, hsplit_pipe)) 1297 goto validate_fail; 1298 dcn20_build_mapped_resource(dc, context, pipe->stream); 1299 } else { 1300 dcn20_split_stream_for_mpc( 1301 &context->res_ctx, dc->res_pool, 1302 pipe, hsplit_pipe); 1303 resource_build_scaling_params(pipe); 1304 resource_build_scaling_params(hsplit_pipe); 1305 } 1306 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 1307 } 1308 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { 1309 /* merge should already have been done */ 1310 ASSERT(0); 1311 } 1312 } 1313 /* Actual dsc count per stream dsc validation*/ 1314 if (!dcn20_validate_dsc(dc, context)) { 1315 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = 1316 DML_FAIL_DSC_VALIDATION_FAILURE; 1317 goto validate_fail; 1318 } 1319 1320 *vlevel_out = vlevel; 1321 1322 out = true; 1323 goto validate_out; 1324 1325 validate_fail: 1326 out = false; 1327 1328 validate_out: 1329 return out; 1330 } 1331 1332 static noinline bool dcn21_validate_bandwidth_fp(struct dc *dc, 1333 struct dc_state *context, bool fast_validate) 1334 { 1335 bool out = false; 1336 1337 BW_VAL_TRACE_SETUP(); 1338 1339 int vlevel = 0; 1340 int pipe_split_from[MAX_PIPES]; 1341 int pipe_cnt = 0; 1342 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1343 DC_LOGGER_INIT(dc->ctx->logger); 1344 1345 BW_VAL_TRACE_COUNT(); 1346 1347 /*Unsafe due to current pipe merge and split logic*/ 1348 ASSERT(context != dc->current_state); 1349 1350 out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate); 1351 1352 if (pipe_cnt == 0) 1353 goto validate_out; 1354 1355 if (!out) 1356 goto validate_fail; 1357 1358 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1359 1360 if (fast_validate) { 1361 BW_VAL_TRACE_SKIP(fast); 1362 goto validate_out; 1363 } 1364 1365 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate); 1366 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 1367 1368 BW_VAL_TRACE_END_WATERMARKS(); 1369 1370 goto validate_out; 1371 1372 validate_fail: 1373 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1374 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1375 1376 BW_VAL_TRACE_SKIP(fail); 1377 out = false; 1378 1379 validate_out: 1380 kfree(pipes); 1381 1382 BW_VAL_TRACE_FINISH(); 1383 1384 return out; 1385 } 1386 1387 /* 1388 * Some of the functions further below use the FPU, so we need to wrap this 1389 * with DC_FP_START()/DC_FP_END(). Use the same approach as for 1390 * dcn20_validate_bandwidth in dcn20_resource.c. 1391 */ 1392 bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context, 1393 bool fast_validate) 1394 { 1395 bool voltage_supported; 1396 DC_FP_START(); 1397 voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate); 1398 DC_FP_END(); 1399 return voltage_supported; 1400 } 1401 1402 static void dcn21_destroy_resource_pool(struct resource_pool **pool) 1403 { 1404 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool); 1405 1406 dcn21_resource_destruct(dcn21_pool); 1407 kfree(dcn21_pool); 1408 *pool = NULL; 1409 } 1410 1411 static struct clock_source *dcn21_clock_source_create( 1412 struct dc_context *ctx, 1413 struct dc_bios *bios, 1414 enum clock_source_id id, 1415 const struct dce110_clk_src_regs *regs, 1416 bool dp_clk_src) 1417 { 1418 struct dce110_clk_src *clk_src = 1419 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1420 1421 if (!clk_src) 1422 return NULL; 1423 1424 if (dcn20_clk_src_construct(clk_src, ctx, bios, id, 1425 regs, &cs_shift, &cs_mask)) { 1426 clk_src->base.dp_clk_src = dp_clk_src; 1427 return &clk_src->base; 1428 } 1429 1430 BREAK_TO_DEBUGGER(); 1431 return NULL; 1432 } 1433 1434 static struct hubp *dcn21_hubp_create( 1435 struct dc_context *ctx, 1436 uint32_t inst) 1437 { 1438 struct dcn21_hubp *hubp21 = 1439 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL); 1440 1441 if (!hubp21) 1442 return NULL; 1443 1444 if (hubp21_construct(hubp21, ctx, inst, 1445 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1446 return &hubp21->base; 1447 1448 BREAK_TO_DEBUGGER(); 1449 kfree(hubp21); 1450 return NULL; 1451 } 1452 1453 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx) 1454 { 1455 int i; 1456 1457 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), 1458 GFP_KERNEL); 1459 1460 if (!hubbub) 1461 return NULL; 1462 1463 hubbub21_construct(hubbub, ctx, 1464 &hubbub_reg, 1465 &hubbub_shift, 1466 &hubbub_mask); 1467 1468 for (i = 0; i < res_cap_rn.num_vmid; i++) { 1469 struct dcn20_vmid *vmid = &hubbub->vmid[i]; 1470 1471 vmid->ctx = ctx; 1472 1473 vmid->regs = &vmid_regs[i]; 1474 vmid->shifts = &vmid_shifts; 1475 vmid->masks = &vmid_masks; 1476 } 1477 hubbub->num_vmid = res_cap_rn.num_vmid; 1478 1479 return &hubbub->base; 1480 } 1481 1482 struct output_pixel_processor *dcn21_opp_create( 1483 struct dc_context *ctx, uint32_t inst) 1484 { 1485 struct dcn20_opp *opp = 1486 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1487 1488 if (!opp) { 1489 BREAK_TO_DEBUGGER(); 1490 return NULL; 1491 } 1492 1493 dcn20_opp_construct(opp, ctx, inst, 1494 &opp_regs[inst], &opp_shift, &opp_mask); 1495 return &opp->base; 1496 } 1497 1498 struct timing_generator *dcn21_timing_generator_create( 1499 struct dc_context *ctx, 1500 uint32_t instance) 1501 { 1502 struct optc *tgn10 = 1503 kzalloc(sizeof(struct optc), GFP_KERNEL); 1504 1505 if (!tgn10) 1506 return NULL; 1507 1508 tgn10->base.inst = instance; 1509 tgn10->base.ctx = ctx; 1510 1511 tgn10->tg_regs = &tg_regs[instance]; 1512 tgn10->tg_shift = &tg_shift; 1513 tgn10->tg_mask = &tg_mask; 1514 1515 dcn20_timing_generator_init(tgn10); 1516 1517 return &tgn10->base; 1518 } 1519 1520 struct mpc *dcn21_mpc_create(struct dc_context *ctx) 1521 { 1522 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), 1523 GFP_KERNEL); 1524 1525 if (!mpc20) 1526 return NULL; 1527 1528 dcn20_mpc_construct(mpc20, ctx, 1529 &mpc_regs, 1530 &mpc_shift, 1531 &mpc_mask, 1532 6); 1533 1534 return &mpc20->base; 1535 } 1536 1537 static void read_dce_straps( 1538 struct dc_context *ctx, 1539 struct resource_straps *straps) 1540 { 1541 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1542 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1543 1544 } 1545 1546 1547 struct display_stream_compressor *dcn21_dsc_create( 1548 struct dc_context *ctx, uint32_t inst) 1549 { 1550 struct dcn20_dsc *dsc = 1551 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1552 1553 if (!dsc) { 1554 BREAK_TO_DEBUGGER(); 1555 return NULL; 1556 } 1557 1558 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1559 return &dsc->base; 1560 } 1561 1562 static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_limit_table *clk_table, unsigned int high_voltage_lvl) 1563 { 1564 struct _vcs_dpi_voltage_scaling_st low_pstate_lvl; 1565 int i; 1566 1567 low_pstate_lvl.state = 1; 1568 low_pstate_lvl.dcfclk_mhz = clk_table->entries[0].dcfclk_mhz; 1569 low_pstate_lvl.fabricclk_mhz = clk_table->entries[0].fclk_mhz; 1570 low_pstate_lvl.socclk_mhz = clk_table->entries[0].socclk_mhz; 1571 low_pstate_lvl.dram_speed_mts = clk_table->entries[0].memclk_mhz * 2; 1572 1573 low_pstate_lvl.dispclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dispclk_mhz; 1574 low_pstate_lvl.dppclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dppclk_mhz; 1575 low_pstate_lvl.dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[high_voltage_lvl].dram_bw_per_chan_gbps; 1576 low_pstate_lvl.dscclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dscclk_mhz; 1577 low_pstate_lvl.dtbclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dtbclk_mhz; 1578 low_pstate_lvl.phyclk_d18_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_d18_mhz; 1579 low_pstate_lvl.phyclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_mhz; 1580 1581 for (i = clk_table->num_entries; i > 1; i--) 1582 clk_table->entries[i] = clk_table->entries[i-1]; 1583 clk_table->entries[1] = clk_table->entries[0]; 1584 clk_table->num_entries++; 1585 1586 return low_pstate_lvl; 1587 } 1588 1589 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1590 { 1591 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool); 1592 struct clk_limit_table *clk_table = &bw_params->clk_table; 1593 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1594 unsigned int i, closest_clk_lvl = 0, k = 0; 1595 int j; 1596 1597 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator; 1598 dcn2_1_ip.max_num_dpp = pool->base.pipe_count; 1599 dcn2_1_soc.num_chans = bw_params->num_channels; 1600 1601 ASSERT(clk_table->num_entries); 1602 for (i = 0; i < clk_table->num_entries; i++) { 1603 /* loop backwards*/ 1604 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) { 1605 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { 1606 closest_clk_lvl = j; 1607 break; 1608 } 1609 } 1610 1611 /* clk_table[1] is reserved for min DF PState. skip here to fill in later. */ 1612 if (i == 1) 1613 k++; 1614 1615 clock_limits[k].state = k; 1616 clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 1617 clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 1618 clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz; 1619 clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; 1620 1621 clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; 1622 clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; 1623 clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; 1624 clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; 1625 clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; 1626 clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; 1627 clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; 1628 1629 k++; 1630 } 1631 for (i = 0; i < clk_table->num_entries + 1; i++) 1632 dcn2_1_soc.clock_limits[i] = clock_limits[i]; 1633 if (clk_table->num_entries) { 1634 dcn2_1_soc.num_states = clk_table->num_entries + 1; 1635 /* duplicate last level */ 1636 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1]; 1637 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states; 1638 /* fill in min DF PState */ 1639 dcn2_1_soc.clock_limits[1] = construct_low_pstate_lvl(clk_table, closest_clk_lvl); 1640 } 1641 1642 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); 1643 } 1644 1645 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx) 1646 { 1647 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 1648 1649 if (!pp_smu) 1650 return pp_smu; 1651 1652 dm_pp_get_funcs(ctx, pp_smu); 1653 1654 if (pp_smu->ctx.ver != PP_SMU_VER_RN) 1655 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); 1656 1657 1658 return pp_smu; 1659 } 1660 1661 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu) 1662 { 1663 if (pp_smu && *pp_smu) { 1664 kfree(*pp_smu); 1665 *pp_smu = NULL; 1666 } 1667 } 1668 1669 static struct audio *dcn21_create_audio( 1670 struct dc_context *ctx, unsigned int inst) 1671 { 1672 return dce_audio_create(ctx, inst, 1673 &audio_regs[inst], &audio_shift, &audio_mask); 1674 } 1675 1676 static struct dc_cap_funcs cap_funcs = { 1677 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1678 }; 1679 1680 struct stream_encoder *dcn21_stream_encoder_create( 1681 enum engine_id eng_id, 1682 struct dc_context *ctx) 1683 { 1684 struct dcn10_stream_encoder *enc1 = 1685 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1686 1687 if (!enc1) 1688 return NULL; 1689 1690 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1691 &stream_enc_regs[eng_id], 1692 &se_shift, &se_mask); 1693 1694 return &enc1->base; 1695 } 1696 1697 static const struct dce_hwseq_registers hwseq_reg = { 1698 HWSEQ_DCN21_REG_LIST() 1699 }; 1700 1701 static const struct dce_hwseq_shift hwseq_shift = { 1702 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT) 1703 }; 1704 1705 static const struct dce_hwseq_mask hwseq_mask = { 1706 HWSEQ_DCN21_MASK_SH_LIST(_MASK) 1707 }; 1708 1709 static struct dce_hwseq *dcn21_hwseq_create( 1710 struct dc_context *ctx) 1711 { 1712 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1713 1714 if (hws) { 1715 hws->ctx = ctx; 1716 hws->regs = &hwseq_reg; 1717 hws->shifts = &hwseq_shift; 1718 hws->masks = &hwseq_mask; 1719 hws->wa.DEGVIDCN21 = true; 1720 hws->wa.disallow_self_refresh_during_multi_plane_transition = true; 1721 } 1722 return hws; 1723 } 1724 1725 static const struct resource_create_funcs res_create_funcs = { 1726 .read_dce_straps = read_dce_straps, 1727 .create_audio = dcn21_create_audio, 1728 .create_stream_encoder = dcn21_stream_encoder_create, 1729 .create_hwseq = dcn21_hwseq_create, 1730 }; 1731 1732 static const struct resource_create_funcs res_create_maximus_funcs = { 1733 .read_dce_straps = NULL, 1734 .create_audio = NULL, 1735 .create_stream_encoder = NULL, 1736 .create_hwseq = dcn21_hwseq_create, 1737 }; 1738 1739 static const struct encoder_feature_support link_enc_feature = { 1740 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1741 .max_hdmi_pixel_clock = 600000, 1742 .hdmi_ycbcr420_supported = true, 1743 .dp_ycbcr420_supported = true, 1744 .fec_supported = true, 1745 .flags.bits.IS_HBR2_CAPABLE = true, 1746 .flags.bits.IS_HBR3_CAPABLE = true, 1747 .flags.bits.IS_TPS3_CAPABLE = true, 1748 .flags.bits.IS_TPS4_CAPABLE = true 1749 }; 1750 1751 1752 #define link_regs(id, phyid)\ 1753 [id] = {\ 1754 LE_DCN2_REG_LIST(id), \ 1755 UNIPHY_DCN2_REG_LIST(phyid), \ 1756 DPCS_DCN21_REG_LIST(id), \ 1757 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 1758 } 1759 1760 static const struct dcn10_link_enc_registers link_enc_regs[] = { 1761 link_regs(0, A), 1762 link_regs(1, B), 1763 link_regs(2, C), 1764 link_regs(3, D), 1765 link_regs(4, E), 1766 }; 1767 1768 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 1769 { DCN_PANEL_CNTL_REG_LIST() } 1770 }; 1771 1772 static const struct dce_panel_cntl_shift panel_cntl_shift = { 1773 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 1774 }; 1775 1776 static const struct dce_panel_cntl_mask panel_cntl_mask = { 1777 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 1778 }; 1779 1780 #define aux_regs(id)\ 1781 [id] = {\ 1782 DCN2_AUX_REG_LIST(id)\ 1783 } 1784 1785 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 1786 aux_regs(0), 1787 aux_regs(1), 1788 aux_regs(2), 1789 aux_regs(3), 1790 aux_regs(4) 1791 }; 1792 1793 #define hpd_regs(id)\ 1794 [id] = {\ 1795 HPD_REG_LIST(id)\ 1796 } 1797 1798 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 1799 hpd_regs(0), 1800 hpd_regs(1), 1801 hpd_regs(2), 1802 hpd_regs(3), 1803 hpd_regs(4) 1804 }; 1805 1806 static const struct dcn10_link_enc_shift le_shift = { 1807 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\ 1808 DPCS_DCN21_MASK_SH_LIST(__SHIFT) 1809 }; 1810 1811 static const struct dcn10_link_enc_mask le_mask = { 1812 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\ 1813 DPCS_DCN21_MASK_SH_LIST(_MASK) 1814 }; 1815 1816 static int map_transmitter_id_to_phy_instance( 1817 enum transmitter transmitter) 1818 { 1819 switch (transmitter) { 1820 case TRANSMITTER_UNIPHY_A: 1821 return 0; 1822 break; 1823 case TRANSMITTER_UNIPHY_B: 1824 return 1; 1825 break; 1826 case TRANSMITTER_UNIPHY_C: 1827 return 2; 1828 break; 1829 case TRANSMITTER_UNIPHY_D: 1830 return 3; 1831 break; 1832 case TRANSMITTER_UNIPHY_E: 1833 return 4; 1834 break; 1835 default: 1836 ASSERT(0); 1837 return 0; 1838 } 1839 } 1840 1841 static struct link_encoder *dcn21_link_encoder_create( 1842 const struct encoder_init_data *enc_init_data) 1843 { 1844 struct dcn21_link_encoder *enc21 = 1845 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL); 1846 int link_regs_id; 1847 1848 if (!enc21) 1849 return NULL; 1850 1851 link_regs_id = 1852 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 1853 1854 dcn21_link_encoder_construct(enc21, 1855 enc_init_data, 1856 &link_enc_feature, 1857 &link_enc_regs[link_regs_id], 1858 &link_enc_aux_regs[enc_init_data->channel - 1], 1859 &link_enc_hpd_regs[enc_init_data->hpd_source], 1860 &le_shift, 1861 &le_mask); 1862 1863 return &enc21->enc10.base; 1864 } 1865 1866 static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1867 { 1868 struct dce_panel_cntl *panel_cntl = 1869 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 1870 1871 if (!panel_cntl) 1872 return NULL; 1873 1874 dce_panel_cntl_construct(panel_cntl, 1875 init_data, 1876 &panel_cntl_regs[init_data->inst], 1877 &panel_cntl_shift, 1878 &panel_cntl_mask); 1879 1880 return &panel_cntl->base; 1881 } 1882 1883 #define CTX ctx 1884 1885 #define REG(reg_name) \ 1886 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 1887 1888 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1889 { 1890 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 1891 /* RV1 support max 4 pipes */ 1892 value = value & 0xf; 1893 return value; 1894 } 1895 1896 static int dcn21_populate_dml_pipes_from_context( 1897 struct dc *dc, 1898 struct dc_state *context, 1899 display_e2e_pipe_params_st *pipes, 1900 bool fast_validate) 1901 { 1902 uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1903 int i; 1904 1905 for (i = 0; i < pipe_cnt; i++) { 1906 1907 pipes[i].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active; 1908 pipes[i].pipe.src.gpuvm = 1; 1909 } 1910 1911 return pipe_cnt; 1912 } 1913 1914 enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state) 1915 { 1916 enum dc_status result = DC_OK; 1917 1918 if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) { 1919 plane_state->dcc.enable = 1; 1920 /* align to our worst case block width */ 1921 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024; 1922 } 1923 result = dcn20_patch_unknown_plane_state(plane_state); 1924 return result; 1925 } 1926 1927 static const struct resource_funcs dcn21_res_pool_funcs = { 1928 .destroy = dcn21_destroy_resource_pool, 1929 .link_enc_create = dcn21_link_encoder_create, 1930 .panel_cntl_create = dcn21_panel_cntl_create, 1931 .validate_bandwidth = dcn21_validate_bandwidth, 1932 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context, 1933 .add_stream_to_ctx = dcn20_add_stream_to_ctx, 1934 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1935 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1936 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1937 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, 1938 .patch_unknown_plane_state = dcn21_patch_unknown_plane_state, 1939 .set_mcif_arb_params = dcn20_set_mcif_arb_params, 1940 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1941 .update_bw_bounding_box = update_bw_bounding_box 1942 }; 1943 1944 static bool dcn21_resource_construct( 1945 uint8_t num_virtual_links, 1946 struct dc *dc, 1947 struct dcn21_resource_pool *pool) 1948 { 1949 int i, j; 1950 struct dc_context *ctx = dc->ctx; 1951 struct irq_service_init_data init_data; 1952 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1953 uint32_t num_pipes; 1954 1955 ctx->dc_bios->regs = &bios_regs; 1956 1957 pool->base.res_cap = &res_cap_rn; 1958 #ifdef DIAGS_BUILD 1959 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1960 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc; 1961 pool->base.res_cap = &res_cap_rn_FPGA_4pipe; 1962 #endif 1963 1964 pool->base.funcs = &dcn21_res_pool_funcs; 1965 1966 /************************************************* 1967 * Resource + asic cap harcoding * 1968 *************************************************/ 1969 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1970 1971 /* max pipe num for ASIC before check pipe fuses */ 1972 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1973 1974 dc->caps.max_downscale_ratio = 200; 1975 dc->caps.i2c_speed_in_khz = 100; 1976 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/ 1977 dc->caps.max_cursor_size = 256; 1978 dc->caps.min_horizontal_blanking_period = 80; 1979 dc->caps.dmdata_alloc_size = 2048; 1980 1981 dc->caps.max_slave_planes = 1; 1982 dc->caps.post_blend_color_processing = true; 1983 dc->caps.force_dp_tps4_for_cp2520 = true; 1984 dc->caps.extended_aux_timeout_support = true; 1985 dc->caps.dmcub_support = true; 1986 dc->caps.is_apu = true; 1987 1988 /* Color pipeline capabilities */ 1989 dc->caps.color.dpp.dcn_arch = 1; 1990 dc->caps.color.dpp.input_lut_shared = 0; 1991 dc->caps.color.dpp.icsc = 1; 1992 dc->caps.color.dpp.dgam_ram = 1; 1993 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1994 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1995 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0; 1996 dc->caps.color.dpp.dgam_rom_caps.pq = 0; 1997 dc->caps.color.dpp.dgam_rom_caps.hlg = 0; 1998 dc->caps.color.dpp.post_csc = 0; 1999 dc->caps.color.dpp.gamma_corr = 0; 2000 dc->caps.color.dpp.dgam_rom_for_yuv = 1; 2001 2002 dc->caps.color.dpp.hw_3d_lut = 1; 2003 dc->caps.color.dpp.ogam_ram = 1; 2004 // no OGAM ROM on DCN2 2005 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2006 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2007 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2008 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2009 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2010 dc->caps.color.dpp.ocsc = 0; 2011 2012 dc->caps.color.mpc.gamut_remap = 0; 2013 dc->caps.color.mpc.num_3dluts = 0; 2014 dc->caps.color.mpc.shared_3d_lut = 0; 2015 dc->caps.color.mpc.ogam_ram = 1; 2016 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2017 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2018 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2019 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2020 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2021 dc->caps.color.mpc.ocsc = 1; 2022 2023 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2024 dc->debug = debug_defaults_drv; 2025 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 2026 pool->base.pipe_count = 4; 2027 dc->debug = debug_defaults_diags; 2028 } else 2029 dc->debug = debug_defaults_diags; 2030 2031 // Init the vm_helper 2032 if (dc->vm_helper) 2033 vm_helper_init(dc->vm_helper, 16); 2034 2035 /************************************************* 2036 * Create resources * 2037 *************************************************/ 2038 2039 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = 2040 dcn21_clock_source_create(ctx, ctx->dc_bios, 2041 CLOCK_SOURCE_COMBO_PHY_PLL0, 2042 &clk_src_regs[0], false); 2043 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = 2044 dcn21_clock_source_create(ctx, ctx->dc_bios, 2045 CLOCK_SOURCE_COMBO_PHY_PLL1, 2046 &clk_src_regs[1], false); 2047 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = 2048 dcn21_clock_source_create(ctx, ctx->dc_bios, 2049 CLOCK_SOURCE_COMBO_PHY_PLL2, 2050 &clk_src_regs[2], false); 2051 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] = 2052 dcn21_clock_source_create(ctx, ctx->dc_bios, 2053 CLOCK_SOURCE_COMBO_PHY_PLL3, 2054 &clk_src_regs[3], false); 2055 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] = 2056 dcn21_clock_source_create(ctx, ctx->dc_bios, 2057 CLOCK_SOURCE_COMBO_PHY_PLL4, 2058 &clk_src_regs[4], false); 2059 2060 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21; 2061 2062 /* todo: not reuse phy_pll registers */ 2063 pool->base.dp_clock_source = 2064 dcn21_clock_source_create(ctx, ctx->dc_bios, 2065 CLOCK_SOURCE_ID_DP_DTO, 2066 &clk_src_regs[0], true); 2067 2068 for (i = 0; i < pool->base.clk_src_count; i++) { 2069 if (pool->base.clock_sources[i] == NULL) { 2070 dm_error("DC: failed to create clock sources!\n"); 2071 BREAK_TO_DEBUGGER(); 2072 goto create_fail; 2073 } 2074 } 2075 2076 pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2077 if (pool->base.dccg == NULL) { 2078 dm_error("DC: failed to create dccg!\n"); 2079 BREAK_TO_DEBUGGER(); 2080 goto create_fail; 2081 } 2082 2083 if (!dc->config.disable_dmcu) { 2084 pool->base.dmcu = dcn21_dmcu_create(ctx, 2085 &dmcu_regs, 2086 &dmcu_shift, 2087 &dmcu_mask); 2088 if (pool->base.dmcu == NULL) { 2089 dm_error("DC: failed to create dmcu!\n"); 2090 BREAK_TO_DEBUGGER(); 2091 goto create_fail; 2092 } 2093 2094 dc->debug.dmub_command_table = false; 2095 } 2096 2097 if (dc->config.disable_dmcu) { 2098 pool->base.psr = dmub_psr_create(ctx); 2099 2100 if (pool->base.psr == NULL) { 2101 dm_error("DC: failed to create psr obj!\n"); 2102 BREAK_TO_DEBUGGER(); 2103 goto create_fail; 2104 } 2105 } 2106 2107 if (dc->config.disable_dmcu) 2108 pool->base.abm = dmub_abm_create(ctx, 2109 &abm_regs, 2110 &abm_shift, 2111 &abm_mask); 2112 else 2113 pool->base.abm = dce_abm_create(ctx, 2114 &abm_regs, 2115 &abm_shift, 2116 &abm_mask); 2117 2118 pool->base.pp_smu = dcn21_pp_smu_create(ctx); 2119 2120 num_pipes = dcn2_1_ip.max_num_dpp; 2121 2122 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++) 2123 if (pipe_fuses & 1 << i) 2124 num_pipes--; 2125 dcn2_1_ip.max_num_dpp = num_pipes; 2126 dcn2_1_ip.max_num_otg = num_pipes; 2127 2128 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); 2129 2130 init_data.ctx = dc->ctx; 2131 pool->base.irqs = dal_irq_service_dcn21_create(&init_data); 2132 if (!pool->base.irqs) 2133 goto create_fail; 2134 2135 j = 0; 2136 /* mem input -> ipp -> dpp -> opp -> TG */ 2137 for (i = 0; i < pool->base.pipe_count; i++) { 2138 /* if pipe is disabled, skip instance of HW pipe, 2139 * i.e, skip ASIC register instance 2140 */ 2141 if ((pipe_fuses & (1 << i)) != 0) 2142 continue; 2143 2144 pool->base.hubps[j] = dcn21_hubp_create(ctx, i); 2145 if (pool->base.hubps[j] == NULL) { 2146 BREAK_TO_DEBUGGER(); 2147 dm_error( 2148 "DC: failed to create memory input!\n"); 2149 goto create_fail; 2150 } 2151 2152 pool->base.ipps[j] = dcn21_ipp_create(ctx, i); 2153 if (pool->base.ipps[j] == NULL) { 2154 BREAK_TO_DEBUGGER(); 2155 dm_error( 2156 "DC: failed to create input pixel processor!\n"); 2157 goto create_fail; 2158 } 2159 2160 pool->base.dpps[j] = dcn21_dpp_create(ctx, i); 2161 if (pool->base.dpps[j] == NULL) { 2162 BREAK_TO_DEBUGGER(); 2163 dm_error( 2164 "DC: failed to create dpps!\n"); 2165 goto create_fail; 2166 } 2167 2168 pool->base.opps[j] = dcn21_opp_create(ctx, i); 2169 if (pool->base.opps[j] == NULL) { 2170 BREAK_TO_DEBUGGER(); 2171 dm_error( 2172 "DC: failed to create output pixel processor!\n"); 2173 goto create_fail; 2174 } 2175 2176 pool->base.timing_generators[j] = dcn21_timing_generator_create( 2177 ctx, i); 2178 if (pool->base.timing_generators[j] == NULL) { 2179 BREAK_TO_DEBUGGER(); 2180 dm_error("DC: failed to create tg!\n"); 2181 goto create_fail; 2182 } 2183 j++; 2184 } 2185 2186 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2187 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i); 2188 if (pool->base.engines[i] == NULL) { 2189 BREAK_TO_DEBUGGER(); 2190 dm_error( 2191 "DC:failed to create aux engine!!\n"); 2192 goto create_fail; 2193 } 2194 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i); 2195 if (pool->base.hw_i2cs[i] == NULL) { 2196 BREAK_TO_DEBUGGER(); 2197 dm_error( 2198 "DC:failed to create hw i2c!!\n"); 2199 goto create_fail; 2200 } 2201 pool->base.sw_i2cs[i] = NULL; 2202 } 2203 2204 pool->base.timing_generator_count = j; 2205 pool->base.pipe_count = j; 2206 pool->base.mpcc_count = j; 2207 2208 pool->base.mpc = dcn21_mpc_create(ctx); 2209 if (pool->base.mpc == NULL) { 2210 BREAK_TO_DEBUGGER(); 2211 dm_error("DC: failed to create mpc!\n"); 2212 goto create_fail; 2213 } 2214 2215 pool->base.hubbub = dcn21_hubbub_create(ctx); 2216 if (pool->base.hubbub == NULL) { 2217 BREAK_TO_DEBUGGER(); 2218 dm_error("DC: failed to create hubbub!\n"); 2219 goto create_fail; 2220 } 2221 2222 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2223 pool->base.dscs[i] = dcn21_dsc_create(ctx, i); 2224 if (pool->base.dscs[i] == NULL) { 2225 BREAK_TO_DEBUGGER(); 2226 dm_error("DC: failed to create display stream compressor %d!\n", i); 2227 goto create_fail; 2228 } 2229 } 2230 2231 if (!dcn20_dwbc_create(ctx, &pool->base)) { 2232 BREAK_TO_DEBUGGER(); 2233 dm_error("DC: failed to create dwbc!\n"); 2234 goto create_fail; 2235 } 2236 if (!dcn20_mmhubbub_create(ctx, &pool->base)) { 2237 BREAK_TO_DEBUGGER(); 2238 dm_error("DC: failed to create mcif_wb!\n"); 2239 goto create_fail; 2240 } 2241 2242 if (!resource_construct(num_virtual_links, dc, &pool->base, 2243 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2244 &res_create_funcs : &res_create_maximus_funcs))) 2245 goto create_fail; 2246 2247 dcn21_hw_sequencer_construct(dc); 2248 2249 dc->caps.max_planes = pool->base.pipe_count; 2250 2251 for (i = 0; i < dc->caps.max_planes; ++i) 2252 dc->caps.planes[i] = plane_cap; 2253 2254 dc->cap_funcs = cap_funcs; 2255 2256 return true; 2257 2258 create_fail: 2259 2260 dcn21_resource_destruct(pool); 2261 2262 return false; 2263 } 2264 2265 struct resource_pool *dcn21_create_resource_pool( 2266 const struct dc_init_data *init_data, 2267 struct dc *dc) 2268 { 2269 struct dcn21_resource_pool *pool = 2270 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL); 2271 2272 if (!pool) 2273 return NULL; 2274 2275 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool)) 2276 return &pool->base; 2277 2278 BREAK_TO_DEBUGGER(); 2279 kfree(pool); 2280 return NULL; 2281 } 2282