1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * Copyright 2019 Raptor Engineering, LLC 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 #include "dc.h" 31 32 #include "dcn21_init.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn21/dcn21_resource.h" 38 39 #include "dml/dcn20/dcn20_fpu.h" 40 41 #include "clk_mgr.h" 42 #include "dcn10/dcn10_hubp.h" 43 #include "dcn10/dcn10_ipp.h" 44 #include "dcn20/dcn20_hubbub.h" 45 #include "dcn20/dcn20_mpc.h" 46 #include "dcn20/dcn20_hubp.h" 47 #include "dcn21_hubp.h" 48 #include "irq/dcn21/irq_service_dcn21.h" 49 #include "dcn20/dcn20_dpp.h" 50 #include "dcn20/dcn20_optc.h" 51 #include "dcn21/dcn21_hwseq.h" 52 #include "dce110/dce110_hw_sequencer.h" 53 #include "dcn20/dcn20_opp.h" 54 #include "dcn20/dcn20_dsc.h" 55 #include "dcn21/dcn21_link_encoder.h" 56 #include "dcn20/dcn20_stream_encoder.h" 57 #include "dce/dce_clock_source.h" 58 #include "dce/dce_audio.h" 59 #include "dce/dce_hwseq.h" 60 #include "virtual/virtual_stream_encoder.h" 61 #include "dml/display_mode_vba.h" 62 #include "dcn20/dcn20_dccg.h" 63 #include "dcn21/dcn21_dccg.h" 64 #include "dcn21_hubbub.h" 65 #include "dcn10/dcn10_resource.h" 66 #include "dce/dce_panel_cntl.h" 67 68 #include "dcn20/dcn20_dwb.h" 69 #include "dcn20/dcn20_mmhubbub.h" 70 #include "dpcs/dpcs_2_1_0_offset.h" 71 #include "dpcs/dpcs_2_1_0_sh_mask.h" 72 73 #include "renoir_ip_offset.h" 74 #include "dcn/dcn_2_1_0_offset.h" 75 #include "dcn/dcn_2_1_0_sh_mask.h" 76 77 #include "nbio/nbio_7_0_offset.h" 78 79 #include "mmhub/mmhub_2_0_0_offset.h" 80 #include "mmhub/mmhub_2_0_0_sh_mask.h" 81 82 #include "reg_helper.h" 83 #include "dce/dce_abm.h" 84 #include "dce/dce_dmcu.h" 85 #include "dce/dce_aux.h" 86 #include "dce/dce_i2c.h" 87 #include "dcn21_resource.h" 88 #include "vm_helper.h" 89 #include "dcn20/dcn20_vmid.h" 90 #include "dce/dmub_psr.h" 91 #include "dce/dmub_abm.h" 92 93 /* begin ********************* 94 * macros to expend register list macro defined in HW object header file */ 95 96 /* DCN */ 97 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg 98 99 #define BASE(seg) BASE_INNER(seg) 100 101 #define SR(reg_name)\ 102 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 103 mm ## reg_name 104 105 #define SRI(reg_name, block, id)\ 106 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 107 mm ## block ## id ## _ ## reg_name 108 109 #define SRIR(var_name, reg_name, block, id)\ 110 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 111 mm ## block ## id ## _ ## reg_name 112 113 #define SRII(reg_name, block, id)\ 114 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 115 mm ## block ## id ## _ ## reg_name 116 117 #define DCCG_SRII(reg_name, block, id)\ 118 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 119 mm ## block ## id ## _ ## reg_name 120 121 #define VUPDATE_SRII(reg_name, block, id)\ 122 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 123 mm ## reg_name ## _ ## block ## id 124 125 /* NBIO */ 126 #define NBIO_BASE_INNER(seg) \ 127 NBIF0_BASE__INST0_SEG ## seg 128 129 #define NBIO_BASE(seg) \ 130 NBIO_BASE_INNER(seg) 131 132 #define NBIO_SR(reg_name)\ 133 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 134 mm ## reg_name 135 136 /* MMHUB */ 137 #define MMHUB_BASE_INNER(seg) \ 138 MMHUB_BASE__INST0_SEG ## seg 139 140 #define MMHUB_BASE(seg) \ 141 MMHUB_BASE_INNER(seg) 142 143 #define MMHUB_SR(reg_name)\ 144 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 145 mmMM ## reg_name 146 147 #define clk_src_regs(index, pllid)\ 148 [index] = {\ 149 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\ 150 } 151 152 static const struct dce110_clk_src_regs clk_src_regs[] = { 153 clk_src_regs(0, A), 154 clk_src_regs(1, B), 155 clk_src_regs(2, C), 156 clk_src_regs(3, D), 157 clk_src_regs(4, E), 158 }; 159 160 static const struct dce110_clk_src_shift cs_shift = { 161 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 162 }; 163 164 static const struct dce110_clk_src_mask cs_mask = { 165 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 166 }; 167 168 static const struct bios_registers bios_regs = { 169 NBIO_SR(BIOS_SCRATCH_3), 170 NBIO_SR(BIOS_SCRATCH_6) 171 }; 172 173 static const struct dce_dmcu_registers dmcu_regs = { 174 DMCU_DCN20_REG_LIST() 175 }; 176 177 static const struct dce_dmcu_shift dmcu_shift = { 178 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 179 }; 180 181 static const struct dce_dmcu_mask dmcu_mask = { 182 DMCU_MASK_SH_LIST_DCN10(_MASK) 183 }; 184 185 static const struct dce_abm_registers abm_regs = { 186 ABM_DCN20_REG_LIST() 187 }; 188 189 static const struct dce_abm_shift abm_shift = { 190 ABM_MASK_SH_LIST_DCN20(__SHIFT) 191 }; 192 193 static const struct dce_abm_mask abm_mask = { 194 ABM_MASK_SH_LIST_DCN20(_MASK) 195 }; 196 197 #define audio_regs(id)\ 198 [id] = {\ 199 AUD_COMMON_REG_LIST(id)\ 200 } 201 202 static const struct dce_audio_registers audio_regs[] = { 203 audio_regs(0), 204 audio_regs(1), 205 audio_regs(2), 206 audio_regs(3), 207 audio_regs(4), 208 audio_regs(5), 209 }; 210 211 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 212 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 213 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 214 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 215 216 static const struct dce_audio_shift audio_shift = { 217 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 218 }; 219 220 static const struct dce_audio_mask audio_mask = { 221 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 222 }; 223 224 static const struct dccg_registers dccg_regs = { 225 DCCG_COMMON_REG_LIST_DCN_BASE() 226 }; 227 228 static const struct dccg_shift dccg_shift = { 229 DCCG_MASK_SH_LIST_DCN2_1(__SHIFT) 230 }; 231 232 static const struct dccg_mask dccg_mask = { 233 DCCG_MASK_SH_LIST_DCN2_1(_MASK) 234 }; 235 236 #define opp_regs(id)\ 237 [id] = {\ 238 OPP_REG_LIST_DCN20(id),\ 239 } 240 241 static const struct dcn20_opp_registers opp_regs[] = { 242 opp_regs(0), 243 opp_regs(1), 244 opp_regs(2), 245 opp_regs(3), 246 opp_regs(4), 247 opp_regs(5), 248 }; 249 250 static const struct dcn20_opp_shift opp_shift = { 251 OPP_MASK_SH_LIST_DCN20(__SHIFT) 252 }; 253 254 static const struct dcn20_opp_mask opp_mask = { 255 OPP_MASK_SH_LIST_DCN20(_MASK) 256 }; 257 258 #define tg_regs(id)\ 259 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)} 260 261 static const struct dcn_optc_registers tg_regs[] = { 262 tg_regs(0), 263 tg_regs(1), 264 tg_regs(2), 265 tg_regs(3) 266 }; 267 268 static const struct dcn_optc_shift tg_shift = { 269 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 270 }; 271 272 static const struct dcn_optc_mask tg_mask = { 273 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 274 }; 275 276 static const struct dcn20_mpc_registers mpc_regs = { 277 MPC_REG_LIST_DCN2_0(0), 278 MPC_REG_LIST_DCN2_0(1), 279 MPC_REG_LIST_DCN2_0(2), 280 MPC_REG_LIST_DCN2_0(3), 281 MPC_REG_LIST_DCN2_0(4), 282 MPC_REG_LIST_DCN2_0(5), 283 MPC_OUT_MUX_REG_LIST_DCN2_0(0), 284 MPC_OUT_MUX_REG_LIST_DCN2_0(1), 285 MPC_OUT_MUX_REG_LIST_DCN2_0(2), 286 MPC_OUT_MUX_REG_LIST_DCN2_0(3), 287 MPC_DBG_REG_LIST_DCN2_0() 288 }; 289 290 static const struct dcn20_mpc_shift mpc_shift = { 291 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT), 292 MPC_DEBUG_REG_LIST_SH_DCN20 293 }; 294 295 static const struct dcn20_mpc_mask mpc_mask = { 296 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK), 297 MPC_DEBUG_REG_LIST_MASK_DCN20 298 }; 299 300 #define hubp_regs(id)\ 301 [id] = {\ 302 HUBP_REG_LIST_DCN21(id)\ 303 } 304 305 static const struct dcn_hubp2_registers hubp_regs[] = { 306 hubp_regs(0), 307 hubp_regs(1), 308 hubp_regs(2), 309 hubp_regs(3) 310 }; 311 312 static const struct dcn_hubp2_shift hubp_shift = { 313 HUBP_MASK_SH_LIST_DCN21(__SHIFT) 314 }; 315 316 static const struct dcn_hubp2_mask hubp_mask = { 317 HUBP_MASK_SH_LIST_DCN21(_MASK) 318 }; 319 320 static const struct dcn_hubbub_registers hubbub_reg = { 321 HUBBUB_REG_LIST_DCN21() 322 }; 323 324 static const struct dcn_hubbub_shift hubbub_shift = { 325 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT) 326 }; 327 328 static const struct dcn_hubbub_mask hubbub_mask = { 329 HUBBUB_MASK_SH_LIST_DCN21(_MASK) 330 }; 331 332 333 #define vmid_regs(id)\ 334 [id] = {\ 335 DCN20_VMID_REG_LIST(id)\ 336 } 337 338 static const struct dcn_vmid_registers vmid_regs[] = { 339 vmid_regs(0), 340 vmid_regs(1), 341 vmid_regs(2), 342 vmid_regs(3), 343 vmid_regs(4), 344 vmid_regs(5), 345 vmid_regs(6), 346 vmid_regs(7), 347 vmid_regs(8), 348 vmid_regs(9), 349 vmid_regs(10), 350 vmid_regs(11), 351 vmid_regs(12), 352 vmid_regs(13), 353 vmid_regs(14), 354 vmid_regs(15) 355 }; 356 357 static const struct dcn20_vmid_shift vmid_shifts = { 358 DCN20_VMID_MASK_SH_LIST(__SHIFT) 359 }; 360 361 static const struct dcn20_vmid_mask vmid_masks = { 362 DCN20_VMID_MASK_SH_LIST(_MASK) 363 }; 364 365 #define dsc_regsDCN20(id)\ 366 [id] = {\ 367 DSC_REG_LIST_DCN20(id)\ 368 } 369 370 static const struct dcn20_dsc_registers dsc_regs[] = { 371 dsc_regsDCN20(0), 372 dsc_regsDCN20(1), 373 dsc_regsDCN20(2), 374 dsc_regsDCN20(3), 375 dsc_regsDCN20(4), 376 dsc_regsDCN20(5) 377 }; 378 379 static const struct dcn20_dsc_shift dsc_shift = { 380 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 381 }; 382 383 static const struct dcn20_dsc_mask dsc_mask = { 384 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 385 }; 386 387 #define ipp_regs(id)\ 388 [id] = {\ 389 IPP_REG_LIST_DCN20(id),\ 390 } 391 392 static const struct dcn10_ipp_registers ipp_regs[] = { 393 ipp_regs(0), 394 ipp_regs(1), 395 ipp_regs(2), 396 ipp_regs(3), 397 }; 398 399 static const struct dcn10_ipp_shift ipp_shift = { 400 IPP_MASK_SH_LIST_DCN20(__SHIFT) 401 }; 402 403 static const struct dcn10_ipp_mask ipp_mask = { 404 IPP_MASK_SH_LIST_DCN20(_MASK), 405 }; 406 407 #define opp_regs(id)\ 408 [id] = {\ 409 OPP_REG_LIST_DCN20(id),\ 410 } 411 412 413 #define aux_engine_regs(id)\ 414 [id] = {\ 415 AUX_COMMON_REG_LIST0(id), \ 416 .AUXN_IMPCAL = 0, \ 417 .AUXP_IMPCAL = 0, \ 418 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 419 } 420 421 static const struct dce110_aux_registers aux_engine_regs[] = { 422 aux_engine_regs(0), 423 aux_engine_regs(1), 424 aux_engine_regs(2), 425 aux_engine_regs(3), 426 aux_engine_regs(4), 427 }; 428 429 #define tf_regs(id)\ 430 [id] = {\ 431 TF_REG_LIST_DCN20(id),\ 432 TF_REG_LIST_DCN20_COMMON_APPEND(id),\ 433 } 434 435 static const struct dcn2_dpp_registers tf_regs[] = { 436 tf_regs(0), 437 tf_regs(1), 438 tf_regs(2), 439 tf_regs(3), 440 }; 441 442 static const struct dcn2_dpp_shift tf_shift = { 443 TF_REG_LIST_SH_MASK_DCN20(__SHIFT), 444 TF_DEBUG_REG_LIST_SH_DCN20 445 }; 446 447 static const struct dcn2_dpp_mask tf_mask = { 448 TF_REG_LIST_SH_MASK_DCN20(_MASK), 449 TF_DEBUG_REG_LIST_MASK_DCN20 450 }; 451 452 #define stream_enc_regs(id)\ 453 [id] = {\ 454 SE_DCN2_REG_LIST(id)\ 455 } 456 457 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 458 stream_enc_regs(0), 459 stream_enc_regs(1), 460 stream_enc_regs(2), 461 stream_enc_regs(3), 462 stream_enc_regs(4), 463 }; 464 465 static const struct dce110_aux_registers_shift aux_shift = { 466 DCN_AUX_MASK_SH_LIST(__SHIFT) 467 }; 468 469 static const struct dce110_aux_registers_mask aux_mask = { 470 DCN_AUX_MASK_SH_LIST(_MASK) 471 }; 472 473 static const struct dcn10_stream_encoder_shift se_shift = { 474 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) 475 }; 476 477 static const struct dcn10_stream_encoder_mask se_mask = { 478 SE_COMMON_MASK_SH_LIST_DCN20(_MASK) 479 }; 480 481 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu); 482 483 static struct input_pixel_processor *dcn21_ipp_create( 484 struct dc_context *ctx, uint32_t inst) 485 { 486 struct dcn10_ipp *ipp = 487 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 488 489 if (!ipp) { 490 BREAK_TO_DEBUGGER(); 491 return NULL; 492 } 493 494 dcn20_ipp_construct(ipp, ctx, inst, 495 &ipp_regs[inst], &ipp_shift, &ipp_mask); 496 return &ipp->base; 497 } 498 499 static struct dpp *dcn21_dpp_create( 500 struct dc_context *ctx, 501 uint32_t inst) 502 { 503 struct dcn20_dpp *dpp = 504 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL); 505 506 if (!dpp) 507 return NULL; 508 509 if (dpp2_construct(dpp, ctx, inst, 510 &tf_regs[inst], &tf_shift, &tf_mask)) 511 return &dpp->base; 512 513 BREAK_TO_DEBUGGER(); 514 kfree(dpp); 515 return NULL; 516 } 517 518 static struct dce_aux *dcn21_aux_engine_create( 519 struct dc_context *ctx, 520 uint32_t inst) 521 { 522 struct aux_engine_dce110 *aux_engine = 523 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 524 525 if (!aux_engine) 526 return NULL; 527 528 dce110_aux_engine_construct(aux_engine, ctx, inst, 529 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 530 &aux_engine_regs[inst], 531 &aux_mask, 532 &aux_shift, 533 ctx->dc->caps.extended_aux_timeout_support); 534 535 return &aux_engine->base; 536 } 537 538 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 539 540 static const struct dce_i2c_registers i2c_hw_regs[] = { 541 i2c_inst_regs(1), 542 i2c_inst_regs(2), 543 i2c_inst_regs(3), 544 i2c_inst_regs(4), 545 i2c_inst_regs(5), 546 }; 547 548 static const struct dce_i2c_shift i2c_shifts = { 549 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 550 }; 551 552 static const struct dce_i2c_mask i2c_masks = { 553 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 554 }; 555 556 static struct dce_i2c_hw *dcn21_i2c_hw_create(struct dc_context *ctx, 557 uint32_t inst) 558 { 559 struct dce_i2c_hw *dce_i2c_hw = 560 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 561 562 if (!dce_i2c_hw) 563 return NULL; 564 565 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 566 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 567 568 return dce_i2c_hw; 569 } 570 571 static const struct resource_caps res_cap_rn = { 572 .num_timing_generator = 4, 573 .num_opp = 4, 574 .num_video_plane = 4, 575 .num_audio = 4, // 4 audio endpoints. 4 audio streams 576 .num_stream_encoder = 5, 577 .num_pll = 5, // maybe 3 because the last two used for USB-c 578 .num_dwb = 1, 579 .num_ddc = 5, 580 .num_vmid = 16, 581 .num_dsc = 3, 582 }; 583 584 #ifdef DIAGS_BUILD 585 static const struct resource_caps res_cap_rn_FPGA_4pipe = { 586 .num_timing_generator = 4, 587 .num_opp = 4, 588 .num_video_plane = 4, 589 .num_audio = 7, 590 .num_stream_encoder = 4, 591 .num_pll = 4, 592 .num_dwb = 1, 593 .num_ddc = 4, 594 .num_dsc = 0, 595 }; 596 597 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = { 598 .num_timing_generator = 2, 599 .num_opp = 2, 600 .num_video_plane = 2, 601 .num_audio = 7, 602 .num_stream_encoder = 2, 603 .num_pll = 4, 604 .num_dwb = 1, 605 .num_ddc = 4, 606 .num_dsc = 2, 607 }; 608 #endif 609 610 static const struct dc_plane_cap plane_cap = { 611 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 612 .per_pixel_alpha = true, 613 614 .pixel_format_support = { 615 .argb8888 = true, 616 .nv12 = true, 617 .fp16 = true, 618 .p010 = true 619 }, 620 621 .max_upscale_factor = { 622 .argb8888 = 16000, 623 .nv12 = 16000, 624 .fp16 = 16000 625 }, 626 627 .max_downscale_factor = { 628 .argb8888 = 250, 629 .nv12 = 250, 630 .fp16 = 250 631 }, 632 64, 633 64 634 }; 635 636 static const struct dc_debug_options debug_defaults_drv = { 637 .disable_dmcu = false, 638 .force_abm_enable = false, 639 .timing_trace = false, 640 .clock_trace = true, 641 .disable_pplib_clock_request = true, 642 .min_disp_clk_khz = 100000, 643 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 644 .force_single_disp_pipe_split = false, 645 .disable_dcc = DCC_ENABLE, 646 .vsr_support = true, 647 .performance_trace = false, 648 .max_downscale_src_width = 4096, 649 .disable_pplib_wm_range = false, 650 .scl_reset_length10 = true, 651 .sanity_checks = true, 652 .disable_48mhz_pwrdwn = false, 653 .usbc_combo_phy_reset_wa = true, 654 .dmub_command_table = true, 655 .use_max_lb = true, 656 }; 657 658 static const struct dc_debug_options debug_defaults_diags = { 659 .disable_dmcu = false, 660 .force_abm_enable = false, 661 .timing_trace = true, 662 .clock_trace = true, 663 .disable_dpp_power_gate = true, 664 .disable_hubp_power_gate = true, 665 .disable_clock_gate = true, 666 .disable_pplib_clock_request = true, 667 .disable_pplib_wm_range = true, 668 .disable_stutter = true, 669 .disable_48mhz_pwrdwn = true, 670 .enable_tri_buf = true, 671 .use_max_lb = true 672 }; 673 674 static const struct dc_panel_config panel_config_defaults = { 675 .psr = { 676 .disable_psr = false, 677 .disallow_psrsu = false, 678 }, 679 .ilr = { 680 .optimize_edp_link_rate = true, 681 }, 682 }; 683 684 enum dcn20_clk_src_array_id { 685 DCN20_CLK_SRC_PLL0, 686 DCN20_CLK_SRC_PLL1, 687 DCN20_CLK_SRC_PLL2, 688 DCN20_CLK_SRC_PLL3, 689 DCN20_CLK_SRC_PLL4, 690 DCN20_CLK_SRC_TOTAL_DCN21 691 }; 692 693 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) 694 { 695 unsigned int i; 696 697 for (i = 0; i < pool->base.stream_enc_count; i++) { 698 if (pool->base.stream_enc[i] != NULL) { 699 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 700 pool->base.stream_enc[i] = NULL; 701 } 702 } 703 704 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 705 if (pool->base.dscs[i] != NULL) 706 dcn20_dsc_destroy(&pool->base.dscs[i]); 707 } 708 709 if (pool->base.mpc != NULL) { 710 kfree(TO_DCN20_MPC(pool->base.mpc)); 711 pool->base.mpc = NULL; 712 } 713 if (pool->base.hubbub != NULL) { 714 kfree(pool->base.hubbub); 715 pool->base.hubbub = NULL; 716 } 717 for (i = 0; i < pool->base.pipe_count; i++) { 718 if (pool->base.dpps[i] != NULL) 719 dcn20_dpp_destroy(&pool->base.dpps[i]); 720 721 if (pool->base.ipps[i] != NULL) 722 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 723 724 if (pool->base.hubps[i] != NULL) { 725 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 726 pool->base.hubps[i] = NULL; 727 } 728 729 if (pool->base.irqs != NULL) { 730 dal_irq_service_destroy(&pool->base.irqs); 731 } 732 } 733 734 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 735 if (pool->base.engines[i] != NULL) 736 dce110_engine_destroy(&pool->base.engines[i]); 737 if (pool->base.hw_i2cs[i] != NULL) { 738 kfree(pool->base.hw_i2cs[i]); 739 pool->base.hw_i2cs[i] = NULL; 740 } 741 if (pool->base.sw_i2cs[i] != NULL) { 742 kfree(pool->base.sw_i2cs[i]); 743 pool->base.sw_i2cs[i] = NULL; 744 } 745 } 746 747 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 748 if (pool->base.opps[i] != NULL) 749 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 750 } 751 752 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 753 if (pool->base.timing_generators[i] != NULL) { 754 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 755 pool->base.timing_generators[i] = NULL; 756 } 757 } 758 759 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 760 if (pool->base.dwbc[i] != NULL) { 761 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); 762 pool->base.dwbc[i] = NULL; 763 } 764 if (pool->base.mcif_wb[i] != NULL) { 765 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); 766 pool->base.mcif_wb[i] = NULL; 767 } 768 } 769 770 for (i = 0; i < pool->base.audio_count; i++) { 771 if (pool->base.audios[i]) 772 dce_aud_destroy(&pool->base.audios[i]); 773 } 774 775 for (i = 0; i < pool->base.clk_src_count; i++) { 776 if (pool->base.clock_sources[i] != NULL) { 777 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 778 pool->base.clock_sources[i] = NULL; 779 } 780 } 781 782 if (pool->base.dp_clock_source != NULL) { 783 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 784 pool->base.dp_clock_source = NULL; 785 } 786 787 if (pool->base.abm != NULL) { 788 if (pool->base.abm->ctx->dc->config.disable_dmcu) 789 dmub_abm_destroy(&pool->base.abm); 790 else 791 dce_abm_destroy(&pool->base.abm); 792 } 793 794 if (pool->base.dmcu != NULL) 795 dce_dmcu_destroy(&pool->base.dmcu); 796 797 if (pool->base.psr != NULL) 798 dmub_psr_destroy(&pool->base.psr); 799 800 if (pool->base.dccg != NULL) 801 dcn_dccg_destroy(&pool->base.dccg); 802 803 if (pool->base.pp_smu != NULL) 804 dcn21_pp_smu_destroy(&pool->base.pp_smu); 805 } 806 807 bool dcn21_fast_validate_bw(struct dc *dc, 808 struct dc_state *context, 809 display_e2e_pipe_params_st *pipes, 810 int *pipe_cnt_out, 811 int *pipe_split_from, 812 int *vlevel_out, 813 bool fast_validate) 814 { 815 bool out = false; 816 int split[MAX_PIPES] = { 0 }; 817 int pipe_cnt, i, pipe_idx, vlevel; 818 819 ASSERT(pipes); 820 if (!pipes) 821 return false; 822 823 dcn20_merge_pipes_for_validate(dc, context); 824 825 DC_FP_START(); 826 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 827 DC_FP_END(); 828 829 *pipe_cnt_out = pipe_cnt; 830 831 if (!pipe_cnt) { 832 out = true; 833 goto validate_out; 834 } 835 /* 836 * DML favors voltage over p-state, but we're more interested in 837 * supporting p-state over voltage. We can't support p-state in 838 * prefetch mode > 0 so try capping the prefetch mode to start. 839 */ 840 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = 841 dm_allow_self_refresh_and_mclk_switch; 842 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 843 844 if (vlevel > context->bw_ctx.dml.soc.num_states) { 845 /* 846 * If mode is unsupported or there's still no p-state support then 847 * fall back to favoring voltage. 848 * 849 * We don't actually support prefetch mode 2, so require that we 850 * at least support prefetch mode 1. 851 */ 852 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = 853 dm_allow_self_refresh; 854 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 855 if (vlevel > context->bw_ctx.dml.soc.num_states) 856 goto validate_fail; 857 } 858 859 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL); 860 861 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 862 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 863 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe; 864 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 865 866 if (!pipe->stream) 867 continue; 868 869 /* We only support full screen mpo with ODM */ 870 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled 871 && pipe->plane_state && mpo_pipe 872 && memcmp(&mpo_pipe->plane_res.scl_data.recout, 873 &pipe->plane_res.scl_data.recout, 874 sizeof(struct rect)) != 0) { 875 ASSERT(mpo_pipe->plane_state != pipe->plane_state); 876 goto validate_fail; 877 } 878 pipe_idx++; 879 } 880 881 /*initialize pipe_just_split_from to invalid idx*/ 882 for (i = 0; i < MAX_PIPES; i++) 883 pipe_split_from[i] = -1; 884 885 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { 886 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 887 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 888 889 if (!pipe->stream || pipe_split_from[i] >= 0) 890 continue; 891 892 pipe_idx++; 893 894 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 895 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 896 ASSERT(hsplit_pipe); 897 if (!dcn20_split_stream_for_odm( 898 dc, &context->res_ctx, 899 pipe, hsplit_pipe)) 900 goto validate_fail; 901 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 902 dcn20_build_mapped_resource(dc, context, pipe->stream); 903 } 904 905 if (!pipe->plane_state) 906 continue; 907 /* Skip 2nd half of already split pipe */ 908 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state) 909 continue; 910 911 if (split[i] == 2) { 912 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) { 913 /* pipe not split previously needs split */ 914 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 915 ASSERT(hsplit_pipe); 916 if (!hsplit_pipe) { 917 DC_FP_START(); 918 dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true); 919 DC_FP_END(); 920 continue; 921 } 922 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 923 if (!dcn20_split_stream_for_odm( 924 dc, &context->res_ctx, 925 pipe, hsplit_pipe)) 926 goto validate_fail; 927 dcn20_build_mapped_resource(dc, context, pipe->stream); 928 } else { 929 dcn20_split_stream_for_mpc( 930 &context->res_ctx, dc->res_pool, 931 pipe, hsplit_pipe); 932 resource_build_scaling_params(pipe); 933 resource_build_scaling_params(hsplit_pipe); 934 } 935 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 936 } 937 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { 938 /* merge should already have been done */ 939 ASSERT(0); 940 } 941 } 942 /* Actual dsc count per stream dsc validation*/ 943 if (!dcn20_validate_dsc(dc, context)) { 944 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = 945 DML_FAIL_DSC_VALIDATION_FAILURE; 946 goto validate_fail; 947 } 948 949 *vlevel_out = vlevel; 950 951 out = true; 952 goto validate_out; 953 954 validate_fail: 955 out = false; 956 957 validate_out: 958 return out; 959 } 960 961 /* 962 * Some of the functions further below use the FPU, so we need to wrap this 963 * with DC_FP_START()/DC_FP_END(). Use the same approach as for 964 * dcn20_validate_bandwidth in dcn20_resource.c. 965 */ 966 static bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context, 967 bool fast_validate) 968 { 969 bool voltage_supported; 970 DC_FP_START(); 971 voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate); 972 DC_FP_END(); 973 return voltage_supported; 974 } 975 976 static void dcn21_destroy_resource_pool(struct resource_pool **pool) 977 { 978 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool); 979 980 dcn21_resource_destruct(dcn21_pool); 981 kfree(dcn21_pool); 982 *pool = NULL; 983 } 984 985 static struct clock_source *dcn21_clock_source_create( 986 struct dc_context *ctx, 987 struct dc_bios *bios, 988 enum clock_source_id id, 989 const struct dce110_clk_src_regs *regs, 990 bool dp_clk_src) 991 { 992 struct dce110_clk_src *clk_src = 993 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 994 995 if (!clk_src) 996 return NULL; 997 998 if (dcn20_clk_src_construct(clk_src, ctx, bios, id, 999 regs, &cs_shift, &cs_mask)) { 1000 clk_src->base.dp_clk_src = dp_clk_src; 1001 return &clk_src->base; 1002 } 1003 1004 kfree(clk_src); 1005 BREAK_TO_DEBUGGER(); 1006 return NULL; 1007 } 1008 1009 static struct hubp *dcn21_hubp_create( 1010 struct dc_context *ctx, 1011 uint32_t inst) 1012 { 1013 struct dcn21_hubp *hubp21 = 1014 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL); 1015 1016 if (!hubp21) 1017 return NULL; 1018 1019 if (hubp21_construct(hubp21, ctx, inst, 1020 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1021 return &hubp21->base; 1022 1023 BREAK_TO_DEBUGGER(); 1024 kfree(hubp21); 1025 return NULL; 1026 } 1027 1028 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx) 1029 { 1030 int i; 1031 1032 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), 1033 GFP_KERNEL); 1034 1035 if (!hubbub) 1036 return NULL; 1037 1038 hubbub21_construct(hubbub, ctx, 1039 &hubbub_reg, 1040 &hubbub_shift, 1041 &hubbub_mask); 1042 1043 for (i = 0; i < res_cap_rn.num_vmid; i++) { 1044 struct dcn20_vmid *vmid = &hubbub->vmid[i]; 1045 1046 vmid->ctx = ctx; 1047 1048 vmid->regs = &vmid_regs[i]; 1049 vmid->shifts = &vmid_shifts; 1050 vmid->masks = &vmid_masks; 1051 } 1052 hubbub->num_vmid = res_cap_rn.num_vmid; 1053 1054 return &hubbub->base; 1055 } 1056 1057 static struct output_pixel_processor *dcn21_opp_create(struct dc_context *ctx, 1058 uint32_t inst) 1059 { 1060 struct dcn20_opp *opp = 1061 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1062 1063 if (!opp) { 1064 BREAK_TO_DEBUGGER(); 1065 return NULL; 1066 } 1067 1068 dcn20_opp_construct(opp, ctx, inst, 1069 &opp_regs[inst], &opp_shift, &opp_mask); 1070 return &opp->base; 1071 } 1072 1073 static struct timing_generator *dcn21_timing_generator_create(struct dc_context *ctx, 1074 uint32_t instance) 1075 { 1076 struct optc *tgn10 = 1077 kzalloc(sizeof(struct optc), GFP_KERNEL); 1078 1079 if (!tgn10) 1080 return NULL; 1081 1082 tgn10->base.inst = instance; 1083 tgn10->base.ctx = ctx; 1084 1085 tgn10->tg_regs = &tg_regs[instance]; 1086 tgn10->tg_shift = &tg_shift; 1087 tgn10->tg_mask = &tg_mask; 1088 1089 dcn20_timing_generator_init(tgn10); 1090 1091 return &tgn10->base; 1092 } 1093 1094 static struct mpc *dcn21_mpc_create(struct dc_context *ctx) 1095 { 1096 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), 1097 GFP_KERNEL); 1098 1099 if (!mpc20) 1100 return NULL; 1101 1102 dcn20_mpc_construct(mpc20, ctx, 1103 &mpc_regs, 1104 &mpc_shift, 1105 &mpc_mask, 1106 6); 1107 1108 return &mpc20->base; 1109 } 1110 1111 static void read_dce_straps( 1112 struct dc_context *ctx, 1113 struct resource_straps *straps) 1114 { 1115 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1116 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1117 1118 } 1119 1120 1121 static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx, 1122 uint32_t inst) 1123 { 1124 struct dcn20_dsc *dsc = 1125 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1126 1127 if (!dsc) { 1128 BREAK_TO_DEBUGGER(); 1129 return NULL; 1130 } 1131 1132 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1133 return &dsc->base; 1134 } 1135 1136 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx) 1137 { 1138 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 1139 1140 if (!pp_smu) 1141 return pp_smu; 1142 1143 dm_pp_get_funcs(ctx, pp_smu); 1144 1145 if (pp_smu->ctx.ver != PP_SMU_VER_RN) 1146 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); 1147 1148 1149 return pp_smu; 1150 } 1151 1152 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu) 1153 { 1154 if (pp_smu && *pp_smu) { 1155 kfree(*pp_smu); 1156 *pp_smu = NULL; 1157 } 1158 } 1159 1160 static struct audio *dcn21_create_audio( 1161 struct dc_context *ctx, unsigned int inst) 1162 { 1163 return dce_audio_create(ctx, inst, 1164 &audio_regs[inst], &audio_shift, &audio_mask); 1165 } 1166 1167 static struct dc_cap_funcs cap_funcs = { 1168 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1169 }; 1170 1171 static struct stream_encoder *dcn21_stream_encoder_create(enum engine_id eng_id, 1172 struct dc_context *ctx) 1173 { 1174 struct dcn10_stream_encoder *enc1 = 1175 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1176 1177 if (!enc1) 1178 return NULL; 1179 1180 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1181 &stream_enc_regs[eng_id], 1182 &se_shift, &se_mask); 1183 1184 return &enc1->base; 1185 } 1186 1187 static const struct dce_hwseq_registers hwseq_reg = { 1188 HWSEQ_DCN21_REG_LIST() 1189 }; 1190 1191 static const struct dce_hwseq_shift hwseq_shift = { 1192 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT) 1193 }; 1194 1195 static const struct dce_hwseq_mask hwseq_mask = { 1196 HWSEQ_DCN21_MASK_SH_LIST(_MASK) 1197 }; 1198 1199 static struct dce_hwseq *dcn21_hwseq_create( 1200 struct dc_context *ctx) 1201 { 1202 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1203 1204 if (hws) { 1205 hws->ctx = ctx; 1206 hws->regs = &hwseq_reg; 1207 hws->shifts = &hwseq_shift; 1208 hws->masks = &hwseq_mask; 1209 hws->wa.DEGVIDCN21 = true; 1210 hws->wa.disallow_self_refresh_during_multi_plane_transition = true; 1211 } 1212 return hws; 1213 } 1214 1215 static const struct resource_create_funcs res_create_funcs = { 1216 .read_dce_straps = read_dce_straps, 1217 .create_audio = dcn21_create_audio, 1218 .create_stream_encoder = dcn21_stream_encoder_create, 1219 .create_hwseq = dcn21_hwseq_create, 1220 }; 1221 1222 static const struct resource_create_funcs res_create_maximus_funcs = { 1223 .read_dce_straps = NULL, 1224 .create_audio = NULL, 1225 .create_stream_encoder = NULL, 1226 .create_hwseq = dcn21_hwseq_create, 1227 }; 1228 1229 static const struct encoder_feature_support link_enc_feature = { 1230 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1231 .max_hdmi_pixel_clock = 600000, 1232 .hdmi_ycbcr420_supported = true, 1233 .dp_ycbcr420_supported = true, 1234 .fec_supported = true, 1235 .flags.bits.IS_HBR2_CAPABLE = true, 1236 .flags.bits.IS_HBR3_CAPABLE = true, 1237 .flags.bits.IS_TPS3_CAPABLE = true, 1238 .flags.bits.IS_TPS4_CAPABLE = true 1239 }; 1240 1241 1242 #define link_regs(id, phyid)\ 1243 [id] = {\ 1244 LE_DCN2_REG_LIST(id), \ 1245 UNIPHY_DCN2_REG_LIST(phyid), \ 1246 DPCS_DCN21_REG_LIST(id), \ 1247 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 1248 } 1249 1250 static const struct dcn10_link_enc_registers link_enc_regs[] = { 1251 link_regs(0, A), 1252 link_regs(1, B), 1253 link_regs(2, C), 1254 link_regs(3, D), 1255 link_regs(4, E), 1256 }; 1257 1258 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 1259 { DCN_PANEL_CNTL_REG_LIST() } 1260 }; 1261 1262 static const struct dce_panel_cntl_shift panel_cntl_shift = { 1263 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 1264 }; 1265 1266 static const struct dce_panel_cntl_mask panel_cntl_mask = { 1267 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 1268 }; 1269 1270 #define aux_regs(id)\ 1271 [id] = {\ 1272 DCN2_AUX_REG_LIST(id)\ 1273 } 1274 1275 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 1276 aux_regs(0), 1277 aux_regs(1), 1278 aux_regs(2), 1279 aux_regs(3), 1280 aux_regs(4) 1281 }; 1282 1283 #define hpd_regs(id)\ 1284 [id] = {\ 1285 HPD_REG_LIST(id)\ 1286 } 1287 1288 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 1289 hpd_regs(0), 1290 hpd_regs(1), 1291 hpd_regs(2), 1292 hpd_regs(3), 1293 hpd_regs(4) 1294 }; 1295 1296 static const struct dcn10_link_enc_shift le_shift = { 1297 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\ 1298 DPCS_DCN21_MASK_SH_LIST(__SHIFT) 1299 }; 1300 1301 static const struct dcn10_link_enc_mask le_mask = { 1302 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\ 1303 DPCS_DCN21_MASK_SH_LIST(_MASK) 1304 }; 1305 1306 static int map_transmitter_id_to_phy_instance( 1307 enum transmitter transmitter) 1308 { 1309 switch (transmitter) { 1310 case TRANSMITTER_UNIPHY_A: 1311 return 0; 1312 break; 1313 case TRANSMITTER_UNIPHY_B: 1314 return 1; 1315 break; 1316 case TRANSMITTER_UNIPHY_C: 1317 return 2; 1318 break; 1319 case TRANSMITTER_UNIPHY_D: 1320 return 3; 1321 break; 1322 case TRANSMITTER_UNIPHY_E: 1323 return 4; 1324 break; 1325 default: 1326 ASSERT(0); 1327 return 0; 1328 } 1329 } 1330 1331 static struct link_encoder *dcn21_link_encoder_create( 1332 struct dc_context *ctx, 1333 const struct encoder_init_data *enc_init_data) 1334 { 1335 struct dcn21_link_encoder *enc21 = 1336 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL); 1337 int link_regs_id; 1338 1339 if (!enc21) 1340 return NULL; 1341 1342 link_regs_id = 1343 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 1344 1345 dcn21_link_encoder_construct(enc21, 1346 enc_init_data, 1347 &link_enc_feature, 1348 &link_enc_regs[link_regs_id], 1349 &link_enc_aux_regs[enc_init_data->channel - 1], 1350 &link_enc_hpd_regs[enc_init_data->hpd_source], 1351 &le_shift, 1352 &le_mask); 1353 1354 return &enc21->enc10.base; 1355 } 1356 1357 static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1358 { 1359 struct dce_panel_cntl *panel_cntl = 1360 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 1361 1362 if (!panel_cntl) 1363 return NULL; 1364 1365 dce_panel_cntl_construct(panel_cntl, 1366 init_data, 1367 &panel_cntl_regs[init_data->inst], 1368 &panel_cntl_shift, 1369 &panel_cntl_mask); 1370 1371 return &panel_cntl->base; 1372 } 1373 1374 static void dcn21_get_panel_config_defaults(struct dc_panel_config *panel_config) 1375 { 1376 *panel_config = panel_config_defaults; 1377 } 1378 1379 #define CTX ctx 1380 1381 #define REG(reg_name) \ 1382 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 1383 1384 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1385 { 1386 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 1387 /* RV1 support max 4 pipes */ 1388 value = value & 0xf; 1389 return value; 1390 } 1391 1392 static enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state) 1393 { 1394 if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) { 1395 plane_state->dcc.enable = 1; 1396 /* align to our worst case block width */ 1397 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024; 1398 } 1399 1400 return dcn20_patch_unknown_plane_state(plane_state); 1401 } 1402 1403 static const struct resource_funcs dcn21_res_pool_funcs = { 1404 .destroy = dcn21_destroy_resource_pool, 1405 .link_enc_create = dcn21_link_encoder_create, 1406 .panel_cntl_create = dcn21_panel_cntl_create, 1407 .validate_bandwidth = dcn21_validate_bandwidth, 1408 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context, 1409 .add_stream_to_ctx = dcn20_add_stream_to_ctx, 1410 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1411 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1412 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1413 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, 1414 .patch_unknown_plane_state = dcn21_patch_unknown_plane_state, 1415 .set_mcif_arb_params = dcn20_set_mcif_arb_params, 1416 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1417 .update_bw_bounding_box = dcn21_update_bw_bounding_box, 1418 .get_panel_config_defaults = dcn21_get_panel_config_defaults, 1419 }; 1420 1421 static bool dcn21_resource_construct( 1422 uint8_t num_virtual_links, 1423 struct dc *dc, 1424 struct dcn21_resource_pool *pool) 1425 { 1426 int i, j; 1427 struct dc_context *ctx = dc->ctx; 1428 struct irq_service_init_data init_data; 1429 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1430 uint32_t num_pipes; 1431 1432 ctx->dc_bios->regs = &bios_regs; 1433 1434 pool->base.res_cap = &res_cap_rn; 1435 #ifdef DIAGS_BUILD 1436 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1437 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc; 1438 pool->base.res_cap = &res_cap_rn_FPGA_4pipe; 1439 #endif 1440 1441 pool->base.funcs = &dcn21_res_pool_funcs; 1442 1443 /************************************************* 1444 * Resource + asic cap harcoding * 1445 *************************************************/ 1446 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1447 1448 /* max pipe num for ASIC before check pipe fuses */ 1449 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1450 1451 dc->caps.max_downscale_ratio = 200; 1452 dc->caps.i2c_speed_in_khz = 100; 1453 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/ 1454 dc->caps.max_cursor_size = 256; 1455 dc->caps.min_horizontal_blanking_period = 80; 1456 dc->caps.dmdata_alloc_size = 2048; 1457 1458 dc->caps.max_slave_planes = 1; 1459 dc->caps.max_slave_yuv_planes = 1; 1460 dc->caps.max_slave_rgb_planes = 1; 1461 dc->caps.post_blend_color_processing = true; 1462 dc->caps.force_dp_tps4_for_cp2520 = true; 1463 dc->caps.extended_aux_timeout_support = true; 1464 dc->caps.dmcub_support = true; 1465 dc->caps.is_apu = true; 1466 1467 /* Color pipeline capabilities */ 1468 dc->caps.color.dpp.dcn_arch = 1; 1469 dc->caps.color.dpp.input_lut_shared = 0; 1470 dc->caps.color.dpp.icsc = 1; 1471 dc->caps.color.dpp.dgam_ram = 1; 1472 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1473 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1474 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0; 1475 dc->caps.color.dpp.dgam_rom_caps.pq = 0; 1476 dc->caps.color.dpp.dgam_rom_caps.hlg = 0; 1477 dc->caps.color.dpp.post_csc = 0; 1478 dc->caps.color.dpp.gamma_corr = 0; 1479 dc->caps.color.dpp.dgam_rom_for_yuv = 1; 1480 1481 dc->caps.color.dpp.hw_3d_lut = 1; 1482 dc->caps.color.dpp.ogam_ram = 1; 1483 // no OGAM ROM on DCN2 1484 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1485 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1486 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1487 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1488 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1489 dc->caps.color.dpp.ocsc = 0; 1490 1491 dc->caps.color.mpc.gamut_remap = 0; 1492 dc->caps.color.mpc.num_3dluts = 0; 1493 dc->caps.color.mpc.shared_3d_lut = 0; 1494 dc->caps.color.mpc.ogam_ram = 1; 1495 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1496 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1497 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1498 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1499 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1500 dc->caps.color.mpc.ocsc = 1; 1501 1502 dc->caps.dp_hdmi21_pcon_support = true; 1503 1504 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1505 dc->debug = debug_defaults_drv; 1506 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1507 pool->base.pipe_count = 4; 1508 dc->debug = debug_defaults_diags; 1509 } else 1510 dc->debug = debug_defaults_diags; 1511 1512 // Init the vm_helper 1513 if (dc->vm_helper) 1514 vm_helper_init(dc->vm_helper, 16); 1515 1516 /************************************************* 1517 * Create resources * 1518 *************************************************/ 1519 1520 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = 1521 dcn21_clock_source_create(ctx, ctx->dc_bios, 1522 CLOCK_SOURCE_COMBO_PHY_PLL0, 1523 &clk_src_regs[0], false); 1524 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = 1525 dcn21_clock_source_create(ctx, ctx->dc_bios, 1526 CLOCK_SOURCE_COMBO_PHY_PLL1, 1527 &clk_src_regs[1], false); 1528 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = 1529 dcn21_clock_source_create(ctx, ctx->dc_bios, 1530 CLOCK_SOURCE_COMBO_PHY_PLL2, 1531 &clk_src_regs[2], false); 1532 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] = 1533 dcn21_clock_source_create(ctx, ctx->dc_bios, 1534 CLOCK_SOURCE_COMBO_PHY_PLL3, 1535 &clk_src_regs[3], false); 1536 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] = 1537 dcn21_clock_source_create(ctx, ctx->dc_bios, 1538 CLOCK_SOURCE_COMBO_PHY_PLL4, 1539 &clk_src_regs[4], false); 1540 1541 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21; 1542 1543 /* todo: not reuse phy_pll registers */ 1544 pool->base.dp_clock_source = 1545 dcn21_clock_source_create(ctx, ctx->dc_bios, 1546 CLOCK_SOURCE_ID_DP_DTO, 1547 &clk_src_regs[0], true); 1548 1549 for (i = 0; i < pool->base.clk_src_count; i++) { 1550 if (pool->base.clock_sources[i] == NULL) { 1551 dm_error("DC: failed to create clock sources!\n"); 1552 BREAK_TO_DEBUGGER(); 1553 goto create_fail; 1554 } 1555 } 1556 1557 pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1558 if (pool->base.dccg == NULL) { 1559 dm_error("DC: failed to create dccg!\n"); 1560 BREAK_TO_DEBUGGER(); 1561 goto create_fail; 1562 } 1563 1564 if (!dc->config.disable_dmcu) { 1565 pool->base.dmcu = dcn21_dmcu_create(ctx, 1566 &dmcu_regs, 1567 &dmcu_shift, 1568 &dmcu_mask); 1569 if (pool->base.dmcu == NULL) { 1570 dm_error("DC: failed to create dmcu!\n"); 1571 BREAK_TO_DEBUGGER(); 1572 goto create_fail; 1573 } 1574 1575 dc->debug.dmub_command_table = false; 1576 } 1577 1578 if (dc->config.disable_dmcu) { 1579 pool->base.psr = dmub_psr_create(ctx); 1580 1581 if (pool->base.psr == NULL) { 1582 dm_error("DC: failed to create psr obj!\n"); 1583 BREAK_TO_DEBUGGER(); 1584 goto create_fail; 1585 } 1586 } 1587 1588 if (dc->config.disable_dmcu) 1589 pool->base.abm = dmub_abm_create(ctx, 1590 &abm_regs, 1591 &abm_shift, 1592 &abm_mask); 1593 else 1594 pool->base.abm = dce_abm_create(ctx, 1595 &abm_regs, 1596 &abm_shift, 1597 &abm_mask); 1598 1599 pool->base.pp_smu = dcn21_pp_smu_create(ctx); 1600 1601 num_pipes = dcn2_1_ip.max_num_dpp; 1602 1603 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++) 1604 if (pipe_fuses & 1 << i) 1605 num_pipes--; 1606 dcn2_1_ip.max_num_dpp = num_pipes; 1607 dcn2_1_ip.max_num_otg = num_pipes; 1608 1609 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); 1610 1611 init_data.ctx = dc->ctx; 1612 pool->base.irqs = dal_irq_service_dcn21_create(&init_data); 1613 if (!pool->base.irqs) 1614 goto create_fail; 1615 1616 j = 0; 1617 /* mem input -> ipp -> dpp -> opp -> TG */ 1618 for (i = 0; i < pool->base.pipe_count; i++) { 1619 /* if pipe is disabled, skip instance of HW pipe, 1620 * i.e, skip ASIC register instance 1621 */ 1622 if ((pipe_fuses & (1 << i)) != 0) 1623 continue; 1624 1625 pool->base.hubps[j] = dcn21_hubp_create(ctx, i); 1626 if (pool->base.hubps[j] == NULL) { 1627 BREAK_TO_DEBUGGER(); 1628 dm_error( 1629 "DC: failed to create memory input!\n"); 1630 goto create_fail; 1631 } 1632 1633 pool->base.ipps[j] = dcn21_ipp_create(ctx, i); 1634 if (pool->base.ipps[j] == NULL) { 1635 BREAK_TO_DEBUGGER(); 1636 dm_error( 1637 "DC: failed to create input pixel processor!\n"); 1638 goto create_fail; 1639 } 1640 1641 pool->base.dpps[j] = dcn21_dpp_create(ctx, i); 1642 if (pool->base.dpps[j] == NULL) { 1643 BREAK_TO_DEBUGGER(); 1644 dm_error( 1645 "DC: failed to create dpps!\n"); 1646 goto create_fail; 1647 } 1648 1649 pool->base.opps[j] = dcn21_opp_create(ctx, i); 1650 if (pool->base.opps[j] == NULL) { 1651 BREAK_TO_DEBUGGER(); 1652 dm_error( 1653 "DC: failed to create output pixel processor!\n"); 1654 goto create_fail; 1655 } 1656 1657 pool->base.timing_generators[j] = dcn21_timing_generator_create( 1658 ctx, i); 1659 if (pool->base.timing_generators[j] == NULL) { 1660 BREAK_TO_DEBUGGER(); 1661 dm_error("DC: failed to create tg!\n"); 1662 goto create_fail; 1663 } 1664 j++; 1665 } 1666 1667 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1668 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i); 1669 if (pool->base.engines[i] == NULL) { 1670 BREAK_TO_DEBUGGER(); 1671 dm_error( 1672 "DC:failed to create aux engine!!\n"); 1673 goto create_fail; 1674 } 1675 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i); 1676 if (pool->base.hw_i2cs[i] == NULL) { 1677 BREAK_TO_DEBUGGER(); 1678 dm_error( 1679 "DC:failed to create hw i2c!!\n"); 1680 goto create_fail; 1681 } 1682 pool->base.sw_i2cs[i] = NULL; 1683 } 1684 1685 pool->base.timing_generator_count = j; 1686 pool->base.pipe_count = j; 1687 pool->base.mpcc_count = j; 1688 1689 pool->base.mpc = dcn21_mpc_create(ctx); 1690 if (pool->base.mpc == NULL) { 1691 BREAK_TO_DEBUGGER(); 1692 dm_error("DC: failed to create mpc!\n"); 1693 goto create_fail; 1694 } 1695 1696 pool->base.hubbub = dcn21_hubbub_create(ctx); 1697 if (pool->base.hubbub == NULL) { 1698 BREAK_TO_DEBUGGER(); 1699 dm_error("DC: failed to create hubbub!\n"); 1700 goto create_fail; 1701 } 1702 1703 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1704 pool->base.dscs[i] = dcn21_dsc_create(ctx, i); 1705 if (pool->base.dscs[i] == NULL) { 1706 BREAK_TO_DEBUGGER(); 1707 dm_error("DC: failed to create display stream compressor %d!\n", i); 1708 goto create_fail; 1709 } 1710 } 1711 1712 if (!dcn20_dwbc_create(ctx, &pool->base)) { 1713 BREAK_TO_DEBUGGER(); 1714 dm_error("DC: failed to create dwbc!\n"); 1715 goto create_fail; 1716 } 1717 if (!dcn20_mmhubbub_create(ctx, &pool->base)) { 1718 BREAK_TO_DEBUGGER(); 1719 dm_error("DC: failed to create mcif_wb!\n"); 1720 goto create_fail; 1721 } 1722 1723 if (!resource_construct(num_virtual_links, dc, &pool->base, 1724 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1725 &res_create_funcs : &res_create_maximus_funcs))) 1726 goto create_fail; 1727 1728 dcn21_hw_sequencer_construct(dc); 1729 1730 dc->caps.max_planes = pool->base.pipe_count; 1731 1732 for (i = 0; i < dc->caps.max_planes; ++i) 1733 dc->caps.planes[i] = plane_cap; 1734 1735 dc->cap_funcs = cap_funcs; 1736 1737 return true; 1738 1739 create_fail: 1740 1741 dcn21_resource_destruct(pool); 1742 1743 return false; 1744 } 1745 1746 struct resource_pool *dcn21_create_resource_pool( 1747 const struct dc_init_data *init_data, 1748 struct dc *dc) 1749 { 1750 struct dcn21_resource_pool *pool = 1751 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL); 1752 1753 if (!pool) 1754 return NULL; 1755 1756 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool)) 1757 return &pool->base; 1758 1759 BREAK_TO_DEBUGGER(); 1760 kfree(pool); 1761 return NULL; 1762 } 1763