1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dm_services.h"
27 #include "dc.h"
28 
29 #include "resource.h"
30 #include "include/irq_service_interface.h"
31 #include "dcn20/dcn20_resource.h"
32 
33 #include "clk_mgr.h"
34 #include "dcn10/dcn10_hubp.h"
35 #include "dcn10/dcn10_ipp.h"
36 #include "dcn20/dcn20_hubbub.h"
37 #include "dcn20/dcn20_mpc.h"
38 #include "dcn20/dcn20_hubp.h"
39 #include "dcn21_hubp.h"
40 #include "irq/dcn21/irq_service_dcn21.h"
41 #include "dcn20/dcn20_dpp.h"
42 #include "dcn20/dcn20_optc.h"
43 #include "dcn21/dcn21_hwseq.h"
44 #include "dce110/dce110_hw_sequencer.h"
45 #include "dcn20/dcn20_opp.h"
46 #include "dcn20/dcn20_dsc.h"
47 #include "dcn21/dcn21_link_encoder.h"
48 #include "dcn20/dcn20_stream_encoder.h"
49 #include "dce/dce_clock_source.h"
50 #include "dce/dce_audio.h"
51 #include "dce/dce_hwseq.h"
52 #include "virtual/virtual_stream_encoder.h"
53 #include "dce110/dce110_resource.h"
54 #include "dml/display_mode_vba.h"
55 #include "dcn20/dcn20_dccg.h"
56 #include "dcn21_hubbub.h"
57 #include "dcn10/dcn10_resource.h"
58 
59 #include "dcn20/dcn20_dwb.h"
60 #include "dcn20/dcn20_mmhubbub.h"
61 
62 #include "renoir_ip_offset.h"
63 #include "dcn/dcn_2_1_0_offset.h"
64 #include "dcn/dcn_2_1_0_sh_mask.h"
65 
66 #include "nbio/nbio_7_0_offset.h"
67 
68 #include "mmhub/mmhub_2_0_0_offset.h"
69 #include "mmhub/mmhub_2_0_0_sh_mask.h"
70 
71 #include "reg_helper.h"
72 #include "dce/dce_abm.h"
73 #include "dce/dce_dmcu.h"
74 #include "dce/dce_aux.h"
75 #include "dce/dce_i2c.h"
76 #include "dcn21_resource.h"
77 #include "vm_helper.h"
78 #include "dcn20/dcn20_vmid.h"
79 
80 #define SOC_BOUNDING_BOX_VALID false
81 #define DC_LOGGER_INIT(logger)
82 
83 
84 struct _vcs_dpi_ip_params_st dcn2_1_ip = {
85 	.odm_capable = 1,
86 	.gpuvm_enable = 1,
87 	.hostvm_enable = 1,
88 	.gpuvm_max_page_table_levels = 1,
89 	.hostvm_max_page_table_levels = 4,
90 	.hostvm_cached_page_table_levels = 2,
91 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
92 	.num_dsc = 3,
93 #else
94 	.num_dsc = 0,
95 #endif
96 	.rob_buffer_size_kbytes = 168,
97 	.det_buffer_size_kbytes = 164,
98 	.dpte_buffer_size_in_pte_reqs_luma = 44,
99 	.dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
100 	.dpp_output_buffer_pixels = 2560,
101 	.opp_output_buffer_lines = 1,
102 	.pixel_chunk_size_kbytes = 8,
103 	.pte_enable = 1,
104 	.max_page_table_levels = 4,
105 	.pte_chunk_size_kbytes = 2,
106 	.meta_chunk_size_kbytes = 2,
107 	.writeback_chunk_size_kbytes = 2,
108 	.line_buffer_size_bits = 789504,
109 	.is_line_buffer_bpp_fixed = 0,
110 	.line_buffer_fixed_bpp = 0,
111 	.dcc_supported = true,
112 	.max_line_buffer_lines = 12,
113 	.writeback_luma_buffer_size_kbytes = 12,
114 	.writeback_chroma_buffer_size_kbytes = 8,
115 	.writeback_chroma_line_buffer_width_pixels = 4,
116 	.writeback_max_hscl_ratio = 1,
117 	.writeback_max_vscl_ratio = 1,
118 	.writeback_min_hscl_ratio = 1,
119 	.writeback_min_vscl_ratio = 1,
120 	.writeback_max_hscl_taps = 12,
121 	.writeback_max_vscl_taps = 12,
122 	.writeback_line_buffer_luma_buffer_size = 0,
123 	.writeback_line_buffer_chroma_buffer_size = 14643,
124 	.cursor_buffer_size = 8,
125 	.cursor_chunk_size = 2,
126 	.max_num_otg = 4,
127 	.max_num_dpp = 4,
128 	.max_num_wb = 1,
129 	.max_dchub_pscl_bw_pix_per_clk = 4,
130 	.max_pscl_lb_bw_pix_per_clk = 2,
131 	.max_lb_vscl_bw_pix_per_clk = 4,
132 	.max_vscl_hscl_bw_pix_per_clk = 4,
133 	.max_hscl_ratio = 4,
134 	.max_vscl_ratio = 4,
135 	.hscl_mults = 4,
136 	.vscl_mults = 4,
137 	.max_hscl_taps = 8,
138 	.max_vscl_taps = 8,
139 	.dispclk_ramp_margin_percent = 1,
140 	.underscan_factor = 1.10,
141 	.min_vblank_lines = 32, //
142 	.dppclk_delay_subtotal = 77, //
143 	.dppclk_delay_scl_lb_only = 16,
144 	.dppclk_delay_scl = 50,
145 	.dppclk_delay_cnvc_formatter = 8,
146 	.dppclk_delay_cnvc_cursor = 6,
147 	.dispclk_delay_subtotal = 87, //
148 	.dcfclk_cstate_latency = 10, // SRExitTime
149 	.max_inter_dcn_tile_repeaters = 8,
150 
151 	.xfc_supported = false,
152 	.xfc_fill_bw_overhead_percent = 10.0,
153 	.xfc_fill_constant_bytes = 0,
154 	.ptoi_supported = 0
155 };
156 
157 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
158 	.clock_limits = {
159 			{
160 				.state = 0,
161 				.dcfclk_mhz = 304.0,
162 				.fabricclk_mhz = 600.0,
163 				.dispclk_mhz = 618.0,
164 				.dppclk_mhz = 440.0,
165 				.phyclk_mhz = 600.0,
166 				.socclk_mhz = 278.0,
167 				.dscclk_mhz = 205.67,
168 				.dram_speed_mts = 1600.0,
169 			},
170 			{
171 				.state = 1,
172 				.dcfclk_mhz = 304.0,
173 				.fabricclk_mhz = 600.0,
174 				.dispclk_mhz = 618.0,
175 				.dppclk_mhz = 618.0,
176 				.phyclk_mhz = 600.0,
177 				.socclk_mhz = 278.0,
178 				.dscclk_mhz = 205.67,
179 				.dram_speed_mts = 1600.0,
180 			},
181 			{
182 				.state = 2,
183 				.dcfclk_mhz = 608.0,
184 				.fabricclk_mhz = 1066.0,
185 				.dispclk_mhz = 888.0,
186 				.dppclk_mhz = 888.0,
187 				.phyclk_mhz = 810.0,
188 				.socclk_mhz = 278.0,
189 				.dscclk_mhz = 287.67,
190 				.dram_speed_mts = 2133.0,
191 			},
192 			{
193 				.state = 3,
194 				.dcfclk_mhz = 676.0,
195 				.fabricclk_mhz = 1600.0,
196 				.dispclk_mhz = 1015.0,
197 				.dppclk_mhz = 1015.0,
198 				.phyclk_mhz = 810.0,
199 				.socclk_mhz = 715.0,
200 				.dscclk_mhz = 318.334,
201 				.dram_speed_mts = 4266.0,
202 			},
203 			{
204 				.state = 4,
205 				.dcfclk_mhz = 810.0,
206 				.fabricclk_mhz = 1600.0,
207 				.dispclk_mhz = 1395.0,
208 				.dppclk_mhz = 1285.0,
209 				.phyclk_mhz = 1325.0,
210 				.socclk_mhz = 953.0,
211 				.dscclk_mhz = 489.0,
212 				.dram_speed_mts = 4266.0,
213 			},
214 			/*Extra state, no dispclk ramping*/
215 			{
216 				.state = 5,
217 				.dcfclk_mhz = 810.0,
218 				.fabricclk_mhz = 1600.0,
219 				.dispclk_mhz = 1395.0,
220 				.dppclk_mhz = 1285.0,
221 				.phyclk_mhz = 1325.0,
222 				.socclk_mhz = 953.0,
223 				.dscclk_mhz = 489.0,
224 				.dram_speed_mts = 4266.0,
225 			},
226 
227 		},
228 
229 	.sr_exit_time_us = 12.5,
230 	.sr_enter_plus_exit_time_us = 17.0,
231 	.urgent_latency_us = 4.0,
232 	.urgent_latency_pixel_data_only_us = 4.0,
233 	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
234 	.urgent_latency_vm_data_only_us = 4.0,
235 	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
236 	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
237 	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
238 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
239 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
240 	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
241 	.max_avg_sdp_bw_use_normal_percent = 60.0,
242 	.max_avg_dram_bw_use_normal_percent = 100.0,
243 	.writeback_latency_us = 12.0,
244 	.max_request_size_bytes = 256,
245 	.dram_channel_width_bytes = 4,
246 	.fabric_datapath_to_dcn_data_return_bytes = 32,
247 	.dcn_downspread_percent = 0.5,
248 	.downspread_percent = 0.5,
249 	.dram_page_open_time_ns = 50.0,
250 	.dram_rw_turnaround_time_ns = 17.5,
251 	.dram_return_buffer_per_channel_bytes = 8192,
252 	.round_trip_ping_latency_dcfclk_cycles = 128,
253 	.urgent_out_of_order_return_per_channel_bytes = 4096,
254 	.channel_interleave_bytes = 256,
255 	.num_banks = 8,
256 	.num_chans = 4,
257 	.vmm_page_size_bytes = 4096,
258 	.dram_clock_change_latency_us = 23.84,
259 	.return_bus_width_bytes = 64,
260 	.dispclk_dppclk_vco_speed_mhz = 3550,
261 	.xfc_bus_transport_time_us = 4,
262 	.xfc_xbuf_latency_tolerance_us = 4,
263 	.use_urgent_burst_bw = 1,
264 	.num_states = 5
265 };
266 
267 #ifndef MAX
268 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
269 #endif
270 #ifndef MIN
271 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
272 #endif
273 
274 /* begin *********************
275  * macros to expend register list macro defined in HW object header file */
276 
277 /* DCN */
278 /* TODO awful hack. fixup dcn20_dwb.h */
279 #undef BASE_INNER
280 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
281 
282 #define BASE(seg) BASE_INNER(seg)
283 
284 #define SR(reg_name)\
285 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
286 					mm ## reg_name
287 
288 #define SRI(reg_name, block, id)\
289 	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
290 					mm ## block ## id ## _ ## reg_name
291 
292 #define SRIR(var_name, reg_name, block, id)\
293 	.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
294 					mm ## block ## id ## _ ## reg_name
295 
296 #define SRII(reg_name, block, id)\
297 	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
298 					mm ## block ## id ## _ ## reg_name
299 
300 #define DCCG_SRII(reg_name, block, id)\
301 	.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
302 					mm ## block ## id ## _ ## reg_name
303 
304 /* NBIO */
305 #define NBIO_BASE_INNER(seg) \
306 	NBIF0_BASE__INST0_SEG ## seg
307 
308 #define NBIO_BASE(seg) \
309 	NBIO_BASE_INNER(seg)
310 
311 #define NBIO_SR(reg_name)\
312 		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
313 					mm ## reg_name
314 
315 /* MMHUB */
316 #define MMHUB_BASE_INNER(seg) \
317 	MMHUB_BASE__INST0_SEG ## seg
318 
319 #define MMHUB_BASE(seg) \
320 	MMHUB_BASE_INNER(seg)
321 
322 #define MMHUB_SR(reg_name)\
323 		.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
324 					mmMM ## reg_name
325 
326 #define clk_src_regs(index, pllid)\
327 [index] = {\
328 	CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
329 }
330 
331 static const struct dce110_clk_src_regs clk_src_regs[] = {
332 	clk_src_regs(0, A),
333 	clk_src_regs(1, B),
334 	clk_src_regs(2, C),
335 	clk_src_regs(3, D),
336 	clk_src_regs(4, E),
337 };
338 
339 static const struct dce110_clk_src_shift cs_shift = {
340 		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
341 };
342 
343 static const struct dce110_clk_src_mask cs_mask = {
344 		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
345 };
346 
347 static const struct bios_registers bios_regs = {
348 		NBIO_SR(BIOS_SCRATCH_3),
349 		NBIO_SR(BIOS_SCRATCH_6)
350 };
351 
352 static const struct dce_dmcu_registers dmcu_regs = {
353 		DMCU_DCN10_REG_LIST()
354 };
355 
356 static const struct dce_dmcu_shift dmcu_shift = {
357 		DMCU_MASK_SH_LIST_DCN10(__SHIFT)
358 };
359 
360 static const struct dce_dmcu_mask dmcu_mask = {
361 		DMCU_MASK_SH_LIST_DCN10(_MASK)
362 };
363 
364 static const struct dce_abm_registers abm_regs = {
365 		ABM_DCN20_REG_LIST()
366 };
367 
368 static const struct dce_abm_shift abm_shift = {
369 		ABM_MASK_SH_LIST_DCN20(__SHIFT)
370 };
371 
372 static const struct dce_abm_mask abm_mask = {
373 		ABM_MASK_SH_LIST_DCN20(_MASK)
374 };
375 
376 #ifdef CONFIG_DRM_AMD_DC_DMUB
377 static const struct dcn21_dmcub_registers dmcub_regs = {
378 		DMCUB_REG_LIST_DCN()
379 };
380 
381 static const struct dcn21_dmcub_shift dmcub_shift = {
382 		DMCUB_COMMON_MASK_SH_LIST_BASE(__SHIFT)
383 };
384 
385 static const struct dcn21_dmcub_mask dmcub_mask = {
386 		DMCUB_COMMON_MASK_SH_LIST_BASE(_MASK)
387 };
388 #endif
389 
390 #define audio_regs(id)\
391 [id] = {\
392 		AUD_COMMON_REG_LIST(id)\
393 }
394 
395 static const struct dce_audio_registers audio_regs[] = {
396 	audio_regs(0),
397 	audio_regs(1),
398 	audio_regs(2),
399 	audio_regs(3),
400 	audio_regs(4),
401 	audio_regs(5),
402 };
403 
404 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
405 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
406 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
407 		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
408 
409 static const struct dce_audio_shift audio_shift = {
410 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
411 };
412 
413 static const struct dce_audio_mask audio_mask = {
414 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
415 };
416 
417 static const struct dccg_registers dccg_regs = {
418 		DCCG_COMMON_REG_LIST_DCN_BASE()
419 };
420 
421 static const struct dccg_shift dccg_shift = {
422 		DCCG_MASK_SH_LIST_DCN2(__SHIFT)
423 };
424 
425 static const struct dccg_mask dccg_mask = {
426 		DCCG_MASK_SH_LIST_DCN2(_MASK)
427 };
428 
429 #define opp_regs(id)\
430 [id] = {\
431 	OPP_REG_LIST_DCN20(id),\
432 }
433 
434 static const struct dcn20_opp_registers opp_regs[] = {
435 	opp_regs(0),
436 	opp_regs(1),
437 	opp_regs(2),
438 	opp_regs(3),
439 	opp_regs(4),
440 	opp_regs(5),
441 };
442 
443 static const struct dcn20_opp_shift opp_shift = {
444 		OPP_MASK_SH_LIST_DCN20(__SHIFT)
445 };
446 
447 static const struct dcn20_opp_mask opp_mask = {
448 		OPP_MASK_SH_LIST_DCN20(_MASK)
449 };
450 
451 #define tg_regs(id)\
452 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
453 
454 static const struct dcn_optc_registers tg_regs[] = {
455 	tg_regs(0),
456 	tg_regs(1),
457 	tg_regs(2),
458 	tg_regs(3)
459 };
460 
461 static const struct dcn_optc_shift tg_shift = {
462 	TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
463 };
464 
465 static const struct dcn_optc_mask tg_mask = {
466 	TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
467 };
468 
469 static const struct dcn20_mpc_registers mpc_regs = {
470 		MPC_REG_LIST_DCN2_0(0),
471 		MPC_REG_LIST_DCN2_0(1),
472 		MPC_REG_LIST_DCN2_0(2),
473 		MPC_REG_LIST_DCN2_0(3),
474 		MPC_REG_LIST_DCN2_0(4),
475 		MPC_REG_LIST_DCN2_0(5),
476 		MPC_OUT_MUX_REG_LIST_DCN2_0(0),
477 		MPC_OUT_MUX_REG_LIST_DCN2_0(1),
478 		MPC_OUT_MUX_REG_LIST_DCN2_0(2),
479 		MPC_OUT_MUX_REG_LIST_DCN2_0(3)
480 };
481 
482 static const struct dcn20_mpc_shift mpc_shift = {
483 	MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
484 };
485 
486 static const struct dcn20_mpc_mask mpc_mask = {
487 	MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
488 };
489 
490 #define hubp_regs(id)\
491 [id] = {\
492 	HUBP_REG_LIST_DCN21(id)\
493 }
494 
495 static const struct dcn_hubp2_registers hubp_regs[] = {
496 		hubp_regs(0),
497 		hubp_regs(1),
498 		hubp_regs(2),
499 		hubp_regs(3)
500 };
501 
502 static const struct dcn_hubp2_shift hubp_shift = {
503 		HUBP_MASK_SH_LIST_DCN21(__SHIFT)
504 };
505 
506 static const struct dcn_hubp2_mask hubp_mask = {
507 		HUBP_MASK_SH_LIST_DCN21(_MASK)
508 };
509 
510 static const struct dcn_hubbub_registers hubbub_reg = {
511 		HUBBUB_REG_LIST_DCN21()
512 };
513 
514 static const struct dcn_hubbub_shift hubbub_shift = {
515 		HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
516 };
517 
518 static const struct dcn_hubbub_mask hubbub_mask = {
519 		HUBBUB_MASK_SH_LIST_DCN21(_MASK)
520 };
521 
522 
523 #define vmid_regs(id)\
524 [id] = {\
525 		DCN20_VMID_REG_LIST(id)\
526 }
527 
528 static const struct dcn_vmid_registers vmid_regs[] = {
529 	vmid_regs(0),
530 	vmid_regs(1),
531 	vmid_regs(2),
532 	vmid_regs(3),
533 	vmid_regs(4),
534 	vmid_regs(5),
535 	vmid_regs(6),
536 	vmid_regs(7),
537 	vmid_regs(8),
538 	vmid_regs(9),
539 	vmid_regs(10),
540 	vmid_regs(11),
541 	vmid_regs(12),
542 	vmid_regs(13),
543 	vmid_regs(14),
544 	vmid_regs(15)
545 };
546 
547 static const struct dcn20_vmid_shift vmid_shifts = {
548 		DCN20_VMID_MASK_SH_LIST(__SHIFT)
549 };
550 
551 static const struct dcn20_vmid_mask vmid_masks = {
552 		DCN20_VMID_MASK_SH_LIST(_MASK)
553 };
554 
555 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
556 #define dsc_regsDCN20(id)\
557 [id] = {\
558 	DSC_REG_LIST_DCN20(id)\
559 }
560 
561 static const struct dcn20_dsc_registers dsc_regs[] = {
562 	dsc_regsDCN20(0),
563 	dsc_regsDCN20(1),
564 	dsc_regsDCN20(2),
565 	dsc_regsDCN20(3),
566 	dsc_regsDCN20(4),
567 	dsc_regsDCN20(5)
568 };
569 
570 static const struct dcn20_dsc_shift dsc_shift = {
571 	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
572 };
573 
574 static const struct dcn20_dsc_mask dsc_mask = {
575 	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
576 };
577 #endif
578 
579 #define ipp_regs(id)\
580 [id] = {\
581 	IPP_REG_LIST_DCN20(id),\
582 }
583 
584 static const struct dcn10_ipp_registers ipp_regs[] = {
585 	ipp_regs(0),
586 	ipp_regs(1),
587 	ipp_regs(2),
588 	ipp_regs(3),
589 };
590 
591 static const struct dcn10_ipp_shift ipp_shift = {
592 		IPP_MASK_SH_LIST_DCN20(__SHIFT)
593 };
594 
595 static const struct dcn10_ipp_mask ipp_mask = {
596 		IPP_MASK_SH_LIST_DCN20(_MASK),
597 };
598 
599 #define opp_regs(id)\
600 [id] = {\
601 	OPP_REG_LIST_DCN20(id),\
602 }
603 
604 
605 #define aux_engine_regs(id)\
606 [id] = {\
607 	AUX_COMMON_REG_LIST0(id), \
608 	.AUXN_IMPCAL = 0, \
609 	.AUXP_IMPCAL = 0, \
610 	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
611 }
612 
613 static const struct dce110_aux_registers aux_engine_regs[] = {
614 		aux_engine_regs(0),
615 		aux_engine_regs(1),
616 		aux_engine_regs(2),
617 		aux_engine_regs(3),
618 		aux_engine_regs(4),
619 };
620 
621 #define tf_regs(id)\
622 [id] = {\
623 	TF_REG_LIST_DCN20(id),\
624 }
625 
626 static const struct dcn2_dpp_registers tf_regs[] = {
627 	tf_regs(0),
628 	tf_regs(1),
629 	tf_regs(2),
630 	tf_regs(3),
631 };
632 
633 static const struct dcn2_dpp_shift tf_shift = {
634 		TF_REG_LIST_SH_MASK_DCN20(__SHIFT)
635 };
636 
637 static const struct dcn2_dpp_mask tf_mask = {
638 		TF_REG_LIST_SH_MASK_DCN20(_MASK)
639 };
640 
641 #define stream_enc_regs(id)\
642 [id] = {\
643 	SE_DCN2_REG_LIST(id)\
644 }
645 
646 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
647 	stream_enc_regs(0),
648 	stream_enc_regs(1),
649 	stream_enc_regs(2),
650 	stream_enc_regs(3),
651 	stream_enc_regs(4),
652 };
653 
654 static const struct dce110_aux_registers_shift aux_shift = {
655 	DCN_AUX_MASK_SH_LIST(__SHIFT)
656 };
657 
658 static const struct dce110_aux_registers_mask aux_mask = {
659 	DCN_AUX_MASK_SH_LIST(_MASK)
660 };
661 
662 static const struct dcn10_stream_encoder_shift se_shift = {
663 		SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
664 };
665 
666 static const struct dcn10_stream_encoder_mask se_mask = {
667 		SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
668 };
669 
670 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
671 
672 static int dcn21_populate_dml_pipes_from_context(
673 		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
674 
675 static struct input_pixel_processor *dcn21_ipp_create(
676 	struct dc_context *ctx, uint32_t inst)
677 {
678 	struct dcn10_ipp *ipp =
679 		kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
680 
681 	if (!ipp) {
682 		BREAK_TO_DEBUGGER();
683 		return NULL;
684 	}
685 
686 	dcn20_ipp_construct(ipp, ctx, inst,
687 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
688 	return &ipp->base;
689 }
690 
691 static struct dpp *dcn21_dpp_create(
692 	struct dc_context *ctx,
693 	uint32_t inst)
694 {
695 	struct dcn20_dpp *dpp =
696 		kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
697 
698 	if (!dpp)
699 		return NULL;
700 
701 	if (dpp2_construct(dpp, ctx, inst,
702 			&tf_regs[inst], &tf_shift, &tf_mask))
703 		return &dpp->base;
704 
705 	BREAK_TO_DEBUGGER();
706 	kfree(dpp);
707 	return NULL;
708 }
709 
710 static struct dce_aux *dcn21_aux_engine_create(
711 	struct dc_context *ctx,
712 	uint32_t inst)
713 {
714 	struct aux_engine_dce110 *aux_engine =
715 		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
716 
717 	if (!aux_engine)
718 		return NULL;
719 
720 	dce110_aux_engine_construct(aux_engine, ctx, inst,
721 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
722 				    &aux_engine_regs[inst],
723 					&aux_mask,
724 					&aux_shift,
725 					ctx->dc->caps.extended_aux_timeout_support);
726 
727 	return &aux_engine->base;
728 }
729 
730 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
731 
732 static const struct dce_i2c_registers i2c_hw_regs[] = {
733 		i2c_inst_regs(1),
734 		i2c_inst_regs(2),
735 		i2c_inst_regs(3),
736 		i2c_inst_regs(4),
737 		i2c_inst_regs(5),
738 };
739 
740 static const struct dce_i2c_shift i2c_shifts = {
741 		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
742 };
743 
744 static const struct dce_i2c_mask i2c_masks = {
745 		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
746 };
747 
748 struct dce_i2c_hw *dcn21_i2c_hw_create(
749 	struct dc_context *ctx,
750 	uint32_t inst)
751 {
752 	struct dce_i2c_hw *dce_i2c_hw =
753 		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
754 
755 	if (!dce_i2c_hw)
756 		return NULL;
757 
758 	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
759 				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
760 
761 	return dce_i2c_hw;
762 }
763 
764 static const struct resource_caps res_cap_rn = {
765 		.num_timing_generator = 4,
766 		.num_opp = 4,
767 		.num_video_plane = 4,
768 		.num_audio = 4, // 4 audio endpoints.  4 audio streams
769 		.num_stream_encoder = 5,
770 		.num_pll = 5,  // maybe 3 because the last two used for USB-c
771 		.num_dwb = 1,
772 		.num_ddc = 5,
773 		.num_vmid = 1,
774 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
775 		.num_dsc = 3,
776 #endif
777 };
778 
779 #ifdef DIAGS_BUILD
780 static const struct resource_caps res_cap_rn_FPGA_4pipe = {
781 		.num_timing_generator = 4,
782 		.num_opp = 4,
783 		.num_video_plane = 4,
784 		.num_audio = 7,
785 		.num_stream_encoder = 4,
786 		.num_pll = 4,
787 		.num_dwb = 1,
788 		.num_ddc = 4,
789 		.num_dsc = 0,
790 };
791 
792 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
793 		.num_timing_generator = 2,
794 		.num_opp = 2,
795 		.num_video_plane = 2,
796 		.num_audio = 7,
797 		.num_stream_encoder = 2,
798 		.num_pll = 4,
799 		.num_dwb = 1,
800 		.num_ddc = 4,
801 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
802 		.num_dsc = 2,
803 #endif
804 };
805 #endif
806 
807 static const struct dc_plane_cap plane_cap = {
808 	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
809 	.blends_with_above = true,
810 	.blends_with_below = true,
811 	.per_pixel_alpha = true,
812 
813 	.pixel_format_support = {
814 			.argb8888 = true,
815 			.nv12 = true,
816 			.fp16 = true
817 	},
818 
819 	.max_upscale_factor = {
820 			.argb8888 = 16000,
821 			.nv12 = 16000,
822 			.fp16 = 16000
823 	},
824 
825 	.max_downscale_factor = {
826 			.argb8888 = 250,
827 			.nv12 = 250,
828 			.fp16 = 250
829 	}
830 };
831 
832 static const struct dc_debug_options debug_defaults_drv = {
833 		.disable_dmcu = true,
834 		.force_abm_enable = false,
835 		.timing_trace = false,
836 		.clock_trace = true,
837 		.disable_pplib_clock_request = true,
838 		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
839 		.force_single_disp_pipe_split = false,
840 		.disable_dcc = DCC_ENABLE,
841 		.vsr_support = true,
842 		.performance_trace = false,
843 		.max_downscale_src_width = 3840,
844 		.disable_pplib_wm_range = false,
845 		.scl_reset_length10 = true,
846 		.sanity_checks = true,
847 		.disable_48mhz_pwrdwn = false,
848 };
849 
850 static const struct dc_debug_options debug_defaults_diags = {
851 		.disable_dmcu = true,
852 		.force_abm_enable = false,
853 		.timing_trace = true,
854 		.clock_trace = true,
855 		.disable_dpp_power_gate = true,
856 		.disable_hubp_power_gate = true,
857 		.disable_clock_gate = true,
858 		.disable_pplib_clock_request = true,
859 		.disable_pplib_wm_range = true,
860 		.disable_stutter = true,
861 		.disable_48mhz_pwrdwn = true,
862 };
863 
864 enum dcn20_clk_src_array_id {
865 	DCN20_CLK_SRC_PLL0,
866 	DCN20_CLK_SRC_PLL1,
867 	DCN20_CLK_SRC_TOTAL_DCN21
868 };
869 
870 static void destruct(struct dcn21_resource_pool *pool)
871 {
872 	unsigned int i;
873 
874 	for (i = 0; i < pool->base.stream_enc_count; i++) {
875 		if (pool->base.stream_enc[i] != NULL) {
876 			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
877 			pool->base.stream_enc[i] = NULL;
878 		}
879 	}
880 
881 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
882 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
883 		if (pool->base.dscs[i] != NULL)
884 			dcn20_dsc_destroy(&pool->base.dscs[i]);
885 	}
886 #endif
887 
888 	if (pool->base.mpc != NULL) {
889 		kfree(TO_DCN20_MPC(pool->base.mpc));
890 		pool->base.mpc = NULL;
891 	}
892 	if (pool->base.hubbub != NULL) {
893 		kfree(pool->base.hubbub);
894 		pool->base.hubbub = NULL;
895 	}
896 	for (i = 0; i < pool->base.pipe_count; i++) {
897 		if (pool->base.dpps[i] != NULL)
898 			dcn20_dpp_destroy(&pool->base.dpps[i]);
899 
900 		if (pool->base.ipps[i] != NULL)
901 			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
902 
903 		if (pool->base.hubps[i] != NULL) {
904 			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
905 			pool->base.hubps[i] = NULL;
906 		}
907 
908 		if (pool->base.irqs != NULL) {
909 			dal_irq_service_destroy(&pool->base.irqs);
910 		}
911 	}
912 
913 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
914 		if (pool->base.engines[i] != NULL)
915 			dce110_engine_destroy(&pool->base.engines[i]);
916 		if (pool->base.hw_i2cs[i] != NULL) {
917 			kfree(pool->base.hw_i2cs[i]);
918 			pool->base.hw_i2cs[i] = NULL;
919 		}
920 		if (pool->base.sw_i2cs[i] != NULL) {
921 			kfree(pool->base.sw_i2cs[i]);
922 			pool->base.sw_i2cs[i] = NULL;
923 		}
924 	}
925 
926 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
927 		if (pool->base.opps[i] != NULL)
928 			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
929 	}
930 
931 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
932 		if (pool->base.timing_generators[i] != NULL)	{
933 			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
934 			pool->base.timing_generators[i] = NULL;
935 		}
936 	}
937 
938 	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
939 		if (pool->base.dwbc[i] != NULL) {
940 			kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
941 			pool->base.dwbc[i] = NULL;
942 		}
943 		if (pool->base.mcif_wb[i] != NULL) {
944 			kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
945 			pool->base.mcif_wb[i] = NULL;
946 		}
947 	}
948 
949 	for (i = 0; i < pool->base.audio_count; i++) {
950 		if (pool->base.audios[i])
951 			dce_aud_destroy(&pool->base.audios[i]);
952 	}
953 
954 	for (i = 0; i < pool->base.clk_src_count; i++) {
955 		if (pool->base.clock_sources[i] != NULL) {
956 			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
957 			pool->base.clock_sources[i] = NULL;
958 		}
959 	}
960 
961 	if (pool->base.dp_clock_source != NULL) {
962 		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
963 		pool->base.dp_clock_source = NULL;
964 	}
965 
966 
967 	if (pool->base.abm != NULL)
968 		dce_abm_destroy(&pool->base.abm);
969 
970 	if (pool->base.dmcu != NULL)
971 		dce_dmcu_destroy(&pool->base.dmcu);
972 
973 #ifdef CONFIG_DRM_AMD_DC_DMUB
974 	if (pool->base.dmcub != NULL)
975 		dcn21_dmcub_destroy(&pool->base.dmcub);
976 #endif
977 
978 	if (pool->base.dccg != NULL)
979 		dcn_dccg_destroy(&pool->base.dccg);
980 
981 	if (pool->base.pp_smu != NULL)
982 		dcn21_pp_smu_destroy(&pool->base.pp_smu);
983 }
984 
985 
986 static void calculate_wm_set_for_vlevel(
987 		int vlevel,
988 		struct wm_range_table_entry *table_entry,
989 		struct dcn_watermarks *wm_set,
990 		struct display_mode_lib *dml,
991 		display_e2e_pipe_params_st *pipes,
992 		int pipe_cnt)
993 {
994 	double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
995 
996 	ASSERT(vlevel < dml->soc.num_states);
997 	/* only pipe 0 is read for voltage and dcf/soc clocks */
998 	pipes[0].clks_cfg.voltage = vlevel;
999 	pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
1000 	pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
1001 
1002 	dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
1003 
1004 	wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
1005 	wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
1006 	wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
1007 	wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1008 	wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
1009 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
1010 	wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
1011 	wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
1012 	wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
1013 #endif
1014 	dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
1015 
1016 }
1017 
1018 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1019 {
1020 	kernel_fpu_begin();
1021 	if (dc->bb_overrides.sr_exit_time_ns) {
1022 		bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
1023 	}
1024 
1025 	if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
1026 		bb->sr_enter_plus_exit_time_us =
1027 				dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1028 	}
1029 
1030 	if (dc->bb_overrides.urgent_latency_ns) {
1031 		bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1032 	}
1033 
1034 	if (dc->bb_overrides.dram_clock_change_latency_ns) {
1035 		bb->dram_clock_change_latency_us =
1036 				dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
1037 	}
1038 	kernel_fpu_end();
1039 }
1040 
1041 void dcn21_calculate_wm(
1042 		struct dc *dc, struct dc_state *context,
1043 		display_e2e_pipe_params_st *pipes,
1044 		int *out_pipe_cnt,
1045 		int *pipe_split_from,
1046 		int vlevel_req)
1047 {
1048 	int pipe_cnt, i, pipe_idx;
1049 	int vlevel, vlevel_max;
1050 	struct wm_range_table_entry *table_entry;
1051 	struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
1052 
1053 	ASSERT(bw_params);
1054 
1055 	patch_bounding_box(dc, &context->bw_ctx.dml.soc);
1056 
1057 	for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1058 			if (!context->res_ctx.pipe_ctx[i].stream)
1059 				continue;
1060 
1061 			pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1062 			pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
1063 
1064 			if (pipe_split_from[i] < 0) {
1065 				pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1066 						context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1067 				if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1068 					pipes[pipe_cnt].pipe.dest.odm_combine =
1069 							context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
1070 				else
1071 					pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1072 				pipe_idx++;
1073 			} else {
1074 				pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1075 						context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1076 				if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1077 					pipes[pipe_cnt].pipe.dest.odm_combine =
1078 							context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
1079 				else
1080 					pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1081 			}
1082 			pipe_cnt++;
1083 	}
1084 
1085 	if (pipe_cnt != pipe_idx) {
1086 		if (dc->res_pool->funcs->populate_dml_pipes)
1087 			pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
1088 				&context->res_ctx, pipes);
1089 		else
1090 			pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
1091 				&context->res_ctx, pipes);
1092 	}
1093 
1094 	*out_pipe_cnt = pipe_cnt;
1095 
1096 	vlevel_max = bw_params->clk_table.num_entries - 1;
1097 
1098 
1099 	/* WM Set D */
1100 	table_entry = &bw_params->wm_table.entries[WM_D];
1101 	if (table_entry->wm_type == WM_TYPE_RETRAINING)
1102 		vlevel = 0;
1103 	else
1104 		vlevel = vlevel_max;
1105 	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1106 						&context->bw_ctx.dml, pipes, pipe_cnt);
1107 	/* WM Set C */
1108 	table_entry = &bw_params->wm_table.entries[WM_C];
1109 	vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
1110 	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
1111 						&context->bw_ctx.dml, pipes, pipe_cnt);
1112 	/* WM Set B */
1113 	table_entry = &bw_params->wm_table.entries[WM_B];
1114 	vlevel = MIN(MAX(vlevel_req, 1), vlevel_max);
1115 	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
1116 						&context->bw_ctx.dml, pipes, pipe_cnt);
1117 
1118 	/* WM Set A */
1119 	table_entry = &bw_params->wm_table.entries[WM_A];
1120 	vlevel = MIN(vlevel_req, vlevel_max);
1121 	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
1122 						&context->bw_ctx.dml, pipes, pipe_cnt);
1123 }
1124 
1125 
1126 bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
1127 		bool fast_validate)
1128 {
1129 	bool out = false;
1130 
1131 	BW_VAL_TRACE_SETUP();
1132 
1133 	int vlevel = 0;
1134 	int pipe_split_from[MAX_PIPES];
1135 	int pipe_cnt = 0;
1136 	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1137 	DC_LOGGER_INIT(dc->ctx->logger);
1138 
1139 	BW_VAL_TRACE_COUNT();
1140 
1141 	out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
1142 
1143 	if (pipe_cnt == 0)
1144 		goto validate_out;
1145 
1146 	if (!out)
1147 		goto validate_fail;
1148 
1149 	BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1150 
1151 	if (fast_validate) {
1152 		BW_VAL_TRACE_SKIP(fast);
1153 		goto validate_out;
1154 	}
1155 
1156 	dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
1157 	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1158 
1159 	BW_VAL_TRACE_END_WATERMARKS();
1160 
1161 	goto validate_out;
1162 
1163 validate_fail:
1164 	DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1165 		dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1166 
1167 	BW_VAL_TRACE_SKIP(fail);
1168 	out = false;
1169 
1170 validate_out:
1171 	kfree(pipes);
1172 
1173 	BW_VAL_TRACE_FINISH();
1174 
1175 	return out;
1176 }
1177 static void dcn21_destroy_resource_pool(struct resource_pool **pool)
1178 {
1179 	struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
1180 
1181 	destruct(dcn21_pool);
1182 	kfree(dcn21_pool);
1183 	*pool = NULL;
1184 }
1185 
1186 static struct clock_source *dcn21_clock_source_create(
1187 		struct dc_context *ctx,
1188 		struct dc_bios *bios,
1189 		enum clock_source_id id,
1190 		const struct dce110_clk_src_regs *regs,
1191 		bool dp_clk_src)
1192 {
1193 	struct dce110_clk_src *clk_src =
1194 		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1195 
1196 	if (!clk_src)
1197 		return NULL;
1198 
1199 	if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1200 			regs, &cs_shift, &cs_mask)) {
1201 		clk_src->base.dp_clk_src = dp_clk_src;
1202 		return &clk_src->base;
1203 	}
1204 
1205 	BREAK_TO_DEBUGGER();
1206 	return NULL;
1207 }
1208 
1209 static struct hubp *dcn21_hubp_create(
1210 	struct dc_context *ctx,
1211 	uint32_t inst)
1212 {
1213 	struct dcn21_hubp *hubp21 =
1214 		kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
1215 
1216 	if (!hubp21)
1217 		return NULL;
1218 
1219 	if (hubp21_construct(hubp21, ctx, inst,
1220 			&hubp_regs[inst], &hubp_shift, &hubp_mask))
1221 		return &hubp21->base;
1222 
1223 	BREAK_TO_DEBUGGER();
1224 	kfree(hubp21);
1225 	return NULL;
1226 }
1227 
1228 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1229 {
1230 	int i;
1231 
1232 	struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1233 					  GFP_KERNEL);
1234 
1235 	if (!hubbub)
1236 		return NULL;
1237 
1238 	hubbub21_construct(hubbub, ctx,
1239 			&hubbub_reg,
1240 			&hubbub_shift,
1241 			&hubbub_mask);
1242 
1243 	for (i = 0; i < res_cap_rn.num_vmid; i++) {
1244 		struct dcn20_vmid *vmid = &hubbub->vmid[i];
1245 
1246 		vmid->ctx = ctx;
1247 
1248 		vmid->regs = &vmid_regs[i];
1249 		vmid->shifts = &vmid_shifts;
1250 		vmid->masks = &vmid_masks;
1251 	}
1252 
1253 	return &hubbub->base;
1254 }
1255 
1256 struct output_pixel_processor *dcn21_opp_create(
1257 	struct dc_context *ctx, uint32_t inst)
1258 {
1259 	struct dcn20_opp *opp =
1260 		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1261 
1262 	if (!opp) {
1263 		BREAK_TO_DEBUGGER();
1264 		return NULL;
1265 	}
1266 
1267 	dcn20_opp_construct(opp, ctx, inst,
1268 			&opp_regs[inst], &opp_shift, &opp_mask);
1269 	return &opp->base;
1270 }
1271 
1272 struct timing_generator *dcn21_timing_generator_create(
1273 		struct dc_context *ctx,
1274 		uint32_t instance)
1275 {
1276 	struct optc *tgn10 =
1277 		kzalloc(sizeof(struct optc), GFP_KERNEL);
1278 
1279 	if (!tgn10)
1280 		return NULL;
1281 
1282 	tgn10->base.inst = instance;
1283 	tgn10->base.ctx = ctx;
1284 
1285 	tgn10->tg_regs = &tg_regs[instance];
1286 	tgn10->tg_shift = &tg_shift;
1287 	tgn10->tg_mask = &tg_mask;
1288 
1289 	dcn20_timing_generator_init(tgn10);
1290 
1291 	return &tgn10->base;
1292 }
1293 
1294 struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1295 {
1296 	struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1297 					  GFP_KERNEL);
1298 
1299 	if (!mpc20)
1300 		return NULL;
1301 
1302 	dcn20_mpc_construct(mpc20, ctx,
1303 			&mpc_regs,
1304 			&mpc_shift,
1305 			&mpc_mask,
1306 			6);
1307 
1308 	return &mpc20->base;
1309 }
1310 
1311 static void read_dce_straps(
1312 	struct dc_context *ctx,
1313 	struct resource_straps *straps)
1314 {
1315 	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1316 		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1317 
1318 }
1319 
1320 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1321 
1322 struct display_stream_compressor *dcn21_dsc_create(
1323 	struct dc_context *ctx, uint32_t inst)
1324 {
1325 	struct dcn20_dsc *dsc =
1326 		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1327 
1328 	if (!dsc) {
1329 		BREAK_TO_DEBUGGER();
1330 		return NULL;
1331 	}
1332 
1333 	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1334 	return &dsc->base;
1335 }
1336 #endif
1337 
1338 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1339 {
1340 	/*
1341 	TODO: Fix this function to calcualte correct values.
1342 	There are known issues with this function currently
1343 	that will need to be investigated. Use hardcoded known good values for now.
1344 
1345 
1346 	struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
1347 	struct clk_limit_table *clk_table = &bw_params->clk_table;
1348 	int i;
1349 
1350 	dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1351 	dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
1352 	dcn2_1_soc.num_chans = bw_params->num_channels;
1353 
1354 	for (i = 0; i < clk_table->num_entries; i++) {
1355 
1356 		dcn2_1_soc.clock_limits[i].state = i;
1357 		dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1358 		dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1359 		dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
1360 		dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 16 / 1000;
1361 	}
1362 	dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i - i];
1363 	dcn2_1_soc.num_states = i;
1364 	*/
1365 }
1366 
1367 /* Temporary Place holder until we can get them from fuse */
1368 static struct dpm_clocks dummy_clocks = {
1369 		.DcfClocks = {
1370 				{.Freq = 400, .Vol = 1},
1371 				{.Freq = 483, .Vol = 1},
1372 				{.Freq = 602, .Vol = 1},
1373 				{.Freq = 738, .Vol = 1} },
1374 		.SocClocks = {
1375 				{.Freq = 300, .Vol = 1},
1376 				{.Freq = 400, .Vol = 1},
1377 				{.Freq = 400, .Vol = 1},
1378 				{.Freq = 400, .Vol = 1} },
1379 		.FClocks = {
1380 				{.Freq = 400, .Vol = 1},
1381 				{.Freq = 800, .Vol = 1},
1382 				{.Freq = 1067, .Vol = 1},
1383 				{.Freq = 1600, .Vol = 1} },
1384 		.MemClocks = {
1385 				{.Freq = 800, .Vol = 1},
1386 				{.Freq = 1600, .Vol = 1},
1387 				{.Freq = 1067, .Vol = 1},
1388 				{.Freq = 1600, .Vol = 1} },
1389 
1390 };
1391 
1392 static enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
1393 		struct pp_smu_wm_range_sets *ranges)
1394 {
1395 	return PP_SMU_RESULT_OK;
1396 }
1397 
1398 static enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
1399 		struct dpm_clocks *clock_table)
1400 {
1401 	*clock_table = dummy_clocks;
1402 	return PP_SMU_RESULT_OK;
1403 }
1404 
1405 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
1406 {
1407 	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1408 
1409 	if (!pp_smu)
1410 		return pp_smu;
1411 
1412 	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) {
1413 		pp_smu->ctx.ver = PP_SMU_VER_RN;
1414 		pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table;
1415 		pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges;
1416 	} else {
1417 
1418 		dm_pp_get_funcs(ctx, pp_smu);
1419 
1420 		if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1421 			pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1422 	}
1423 
1424 	return pp_smu;
1425 }
1426 
1427 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
1428 {
1429 	if (pp_smu && *pp_smu) {
1430 		kfree(*pp_smu);
1431 		*pp_smu = NULL;
1432 	}
1433 }
1434 
1435 static struct audio *dcn21_create_audio(
1436 		struct dc_context *ctx, unsigned int inst)
1437 {
1438 	return dce_audio_create(ctx, inst,
1439 			&audio_regs[inst], &audio_shift, &audio_mask);
1440 }
1441 
1442 static struct dc_cap_funcs cap_funcs = {
1443 	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1444 };
1445 
1446 struct stream_encoder *dcn21_stream_encoder_create(
1447 	enum engine_id eng_id,
1448 	struct dc_context *ctx)
1449 {
1450 	struct dcn10_stream_encoder *enc1 =
1451 		kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1452 
1453 	if (!enc1)
1454 		return NULL;
1455 
1456 	dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1457 					&stream_enc_regs[eng_id],
1458 					&se_shift, &se_mask);
1459 
1460 	return &enc1->base;
1461 }
1462 
1463 static const struct dce_hwseq_registers hwseq_reg = {
1464 		HWSEQ_DCN21_REG_LIST()
1465 };
1466 
1467 static const struct dce_hwseq_shift hwseq_shift = {
1468 		HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1469 };
1470 
1471 static const struct dce_hwseq_mask hwseq_mask = {
1472 		HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1473 };
1474 
1475 static struct dce_hwseq *dcn21_hwseq_create(
1476 	struct dc_context *ctx)
1477 {
1478 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1479 
1480 	if (hws) {
1481 		hws->ctx = ctx;
1482 		hws->regs = &hwseq_reg;
1483 		hws->shifts = &hwseq_shift;
1484 		hws->masks = &hwseq_mask;
1485 		hws->wa.DEGVIDCN21 = true;
1486 	}
1487 	return hws;
1488 }
1489 
1490 static const struct resource_create_funcs res_create_funcs = {
1491 	.read_dce_straps = read_dce_straps,
1492 	.create_audio = dcn21_create_audio,
1493 	.create_stream_encoder = dcn21_stream_encoder_create,
1494 	.create_hwseq = dcn21_hwseq_create,
1495 };
1496 
1497 static const struct resource_create_funcs res_create_maximus_funcs = {
1498 	.read_dce_straps = NULL,
1499 	.create_audio = NULL,
1500 	.create_stream_encoder = NULL,
1501 	.create_hwseq = dcn21_hwseq_create,
1502 };
1503 
1504 static const struct encoder_feature_support link_enc_feature = {
1505 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
1506 		.max_hdmi_pixel_clock = 600000,
1507 		.hdmi_ycbcr420_supported = true,
1508 		.dp_ycbcr420_supported = true,
1509 		.flags.bits.IS_HBR2_CAPABLE = true,
1510 		.flags.bits.IS_HBR3_CAPABLE = true,
1511 		.flags.bits.IS_TPS3_CAPABLE = true,
1512 		.flags.bits.IS_TPS4_CAPABLE = true
1513 };
1514 
1515 
1516 #define link_regs(id, phyid)\
1517 [id] = {\
1518 	LE_DCN10_REG_LIST(id), \
1519 	UNIPHY_DCN2_REG_LIST(phyid), \
1520 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1521 }
1522 
1523 static const struct dcn10_link_enc_registers link_enc_regs[] = {
1524 	link_regs(0, A),
1525 	link_regs(1, B),
1526 	link_regs(2, C),
1527 	link_regs(3, D),
1528 	link_regs(4, E),
1529 };
1530 
1531 #define aux_regs(id)\
1532 [id] = {\
1533 	DCN2_AUX_REG_LIST(id)\
1534 }
1535 
1536 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1537 		aux_regs(0),
1538 		aux_regs(1),
1539 		aux_regs(2),
1540 		aux_regs(3),
1541 		aux_regs(4)
1542 };
1543 
1544 #define hpd_regs(id)\
1545 [id] = {\
1546 	HPD_REG_LIST(id)\
1547 }
1548 
1549 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1550 		hpd_regs(0),
1551 		hpd_regs(1),
1552 		hpd_regs(2),
1553 		hpd_regs(3),
1554 		hpd_regs(4)
1555 };
1556 
1557 static const struct dcn10_link_enc_shift le_shift = {
1558 	LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT)
1559 };
1560 
1561 static const struct dcn10_link_enc_mask le_mask = {
1562 	LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK)
1563 };
1564 
1565 static int map_transmitter_id_to_phy_instance(
1566 	enum transmitter transmitter)
1567 {
1568 	switch (transmitter) {
1569 	case TRANSMITTER_UNIPHY_A:
1570 		return 0;
1571 	break;
1572 	case TRANSMITTER_UNIPHY_B:
1573 		return 1;
1574 	break;
1575 	case TRANSMITTER_UNIPHY_C:
1576 		return 2;
1577 	break;
1578 	case TRANSMITTER_UNIPHY_D:
1579 		return 3;
1580 	break;
1581 	case TRANSMITTER_UNIPHY_E:
1582 		return 4;
1583 	break;
1584 	default:
1585 		ASSERT(0);
1586 		return 0;
1587 	}
1588 }
1589 
1590 static struct link_encoder *dcn21_link_encoder_create(
1591 	const struct encoder_init_data *enc_init_data)
1592 {
1593 	struct dcn21_link_encoder *enc21 =
1594 		kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
1595 	int link_regs_id;
1596 
1597 	if (!enc21)
1598 		return NULL;
1599 
1600 	link_regs_id =
1601 		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1602 
1603 	dcn21_link_encoder_construct(enc21,
1604 				      enc_init_data,
1605 				      &link_enc_feature,
1606 				      &link_enc_regs[link_regs_id],
1607 				      &link_enc_aux_regs[enc_init_data->channel - 1],
1608 				      &link_enc_hpd_regs[enc_init_data->hpd_source],
1609 				      &le_shift,
1610 				      &le_mask);
1611 
1612 	return &enc21->enc10.base;
1613 }
1614 #define CTX ctx
1615 
1616 #define REG(reg_name) \
1617 	(DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1618 
1619 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1620 {
1621 	uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1622 	/* RV1 support max 4 pipes */
1623 	value = value & 0xf;
1624 	return value;
1625 }
1626 
1627 static int dcn21_populate_dml_pipes_from_context(
1628 		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1629 {
1630 	uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, res_ctx, pipes);
1631 	int i;
1632 
1633 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1634 
1635 		if (!res_ctx->pipe_ctx[i].stream)
1636 			continue;
1637 
1638 		pipes[i].pipe.src.hostvm = 1;
1639 		pipes[i].pipe.src.gpuvm = 1;
1640 	}
1641 
1642 	return pipe_cnt;
1643 }
1644 
1645 static struct resource_funcs dcn21_res_pool_funcs = {
1646 	.destroy = dcn21_destroy_resource_pool,
1647 	.link_enc_create = dcn21_link_encoder_create,
1648 	.validate_bandwidth = dcn21_validate_bandwidth,
1649 	.populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
1650 	.add_stream_to_ctx = dcn20_add_stream_to_ctx,
1651 	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1652 	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1653 	.populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
1654 	.get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
1655 	.set_mcif_arb_params = dcn20_set_mcif_arb_params,
1656 	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1657 	.update_bw_bounding_box = update_bw_bounding_box
1658 };
1659 
1660 static bool construct(
1661 	uint8_t num_virtual_links,
1662 	struct dc *dc,
1663 	struct dcn21_resource_pool *pool)
1664 {
1665 	int i, j;
1666 	struct dc_context *ctx = dc->ctx;
1667 	struct irq_service_init_data init_data;
1668 	uint32_t pipe_fuses = read_pipe_fuses(ctx);
1669 	uint32_t num_pipes;
1670 
1671 	ctx->dc_bios->regs = &bios_regs;
1672 
1673 	pool->base.res_cap = &res_cap_rn;
1674 #ifdef DIAGS_BUILD
1675 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1676 		//pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
1677 		pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
1678 #endif
1679 
1680 	pool->base.funcs = &dcn21_res_pool_funcs;
1681 
1682 	/*************************************************
1683 	 *  Resource + asic cap harcoding                *
1684 	 *************************************************/
1685 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1686 
1687 	/* max pipe num for ASIC before check pipe fuses */
1688 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1689 
1690 	dc->caps.max_downscale_ratio = 200;
1691 	dc->caps.i2c_speed_in_khz = 100;
1692 	dc->caps.max_cursor_size = 256;
1693 	dc->caps.dmdata_alloc_size = 2048;
1694 	dc->caps.hw_3d_lut = true;
1695 
1696 	dc->caps.max_slave_planes = 1;
1697 	dc->caps.post_blend_color_processing = true;
1698 	dc->caps.force_dp_tps4_for_cp2520 = true;
1699 	dc->caps.extended_aux_timeout_support = true;
1700 
1701 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1702 		dc->debug = debug_defaults_drv;
1703 	else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1704 		pool->base.pipe_count = 4;
1705 		dc->debug = debug_defaults_diags;
1706 	} else
1707 		dc->debug = debug_defaults_diags;
1708 
1709 	// Init the vm_helper
1710 	if (dc->vm_helper)
1711 		vm_helper_init(dc->vm_helper, 16);
1712 
1713 	/*************************************************
1714 	 *  Create resources                             *
1715 	 *************************************************/
1716 
1717 	pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1718 			dcn21_clock_source_create(ctx, ctx->dc_bios,
1719 				CLOCK_SOURCE_COMBO_PHY_PLL0,
1720 				&clk_src_regs[0], false);
1721 	pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1722 			dcn21_clock_source_create(ctx, ctx->dc_bios,
1723 				CLOCK_SOURCE_COMBO_PHY_PLL1,
1724 				&clk_src_regs[1], false);
1725 
1726 	pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
1727 
1728 	/* todo: not reuse phy_pll registers */
1729 	pool->base.dp_clock_source =
1730 			dcn21_clock_source_create(ctx, ctx->dc_bios,
1731 				CLOCK_SOURCE_ID_DP_DTO,
1732 				&clk_src_regs[0], true);
1733 
1734 	for (i = 0; i < pool->base.clk_src_count; i++) {
1735 		if (pool->base.clock_sources[i] == NULL) {
1736 			dm_error("DC: failed to create clock sources!\n");
1737 			BREAK_TO_DEBUGGER();
1738 			goto create_fail;
1739 		}
1740 	}
1741 
1742 	pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1743 	if (pool->base.dccg == NULL) {
1744 		dm_error("DC: failed to create dccg!\n");
1745 		BREAK_TO_DEBUGGER();
1746 		goto create_fail;
1747 	}
1748 
1749 	pool->base.dmcu = dcn20_dmcu_create(ctx,
1750 			&dmcu_regs,
1751 			&dmcu_shift,
1752 			&dmcu_mask);
1753 	if (pool->base.dmcu == NULL) {
1754 		dm_error("DC: failed to create dmcu!\n");
1755 		BREAK_TO_DEBUGGER();
1756 		goto create_fail;
1757 	}
1758 
1759 	pool->base.abm = dce_abm_create(ctx,
1760 			&abm_regs,
1761 			&abm_shift,
1762 			&abm_mask);
1763 	if (pool->base.abm == NULL) {
1764 		dm_error("DC: failed to create abm!\n");
1765 		BREAK_TO_DEBUGGER();
1766 		goto create_fail;
1767 	}
1768 
1769 #ifdef CONFIG_DRM_AMD_DC_DMUB
1770 	pool->base.dmcub = dcn21_dmcub_create(ctx,
1771 			&dmcub_regs,
1772 			&dmcub_shift,
1773 			&dmcub_mask);
1774 	if (pool->base.dmcub == NULL) {
1775 		dm_error("DC: failed to create dmcub!\n");
1776 		BREAK_TO_DEBUGGER();
1777 		goto create_fail;
1778 	}
1779 #endif
1780 
1781 	pool->base.pp_smu = dcn21_pp_smu_create(ctx);
1782 
1783 	num_pipes = dcn2_1_ip.max_num_dpp;
1784 
1785 	for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
1786 		if (pipe_fuses & 1 << i)
1787 			num_pipes--;
1788 	dcn2_1_ip.max_num_dpp = num_pipes;
1789 	dcn2_1_ip.max_num_otg = num_pipes;
1790 
1791 	dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1792 
1793 	init_data.ctx = dc->ctx;
1794 	pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
1795 	if (!pool->base.irqs)
1796 		goto create_fail;
1797 
1798 	j = 0;
1799 	/* mem input -> ipp -> dpp -> opp -> TG */
1800 	for (i = 0; i < pool->base.pipe_count; i++) {
1801 		/* if pipe is disabled, skip instance of HW pipe,
1802 		 * i.e, skip ASIC register instance
1803 		 */
1804 		if ((pipe_fuses & (1 << i)) != 0)
1805 			continue;
1806 
1807 		pool->base.hubps[i] = dcn21_hubp_create(ctx, i);
1808 		if (pool->base.hubps[i] == NULL) {
1809 			BREAK_TO_DEBUGGER();
1810 			dm_error(
1811 				"DC: failed to create memory input!\n");
1812 			goto create_fail;
1813 		}
1814 
1815 		pool->base.ipps[i] = dcn21_ipp_create(ctx, i);
1816 		if (pool->base.ipps[i] == NULL) {
1817 			BREAK_TO_DEBUGGER();
1818 			dm_error(
1819 				"DC: failed to create input pixel processor!\n");
1820 			goto create_fail;
1821 		}
1822 
1823 		pool->base.dpps[i] = dcn21_dpp_create(ctx, i);
1824 		if (pool->base.dpps[i] == NULL) {
1825 			BREAK_TO_DEBUGGER();
1826 			dm_error(
1827 				"DC: failed to create dpps!\n");
1828 			goto create_fail;
1829 		}
1830 
1831 		pool->base.opps[i] = dcn21_opp_create(ctx, i);
1832 		if (pool->base.opps[i] == NULL) {
1833 			BREAK_TO_DEBUGGER();
1834 			dm_error(
1835 				"DC: failed to create output pixel processor!\n");
1836 			goto create_fail;
1837 		}
1838 
1839 		pool->base.timing_generators[i] = dcn21_timing_generator_create(
1840 				ctx, i);
1841 		if (pool->base.timing_generators[i] == NULL) {
1842 			BREAK_TO_DEBUGGER();
1843 			dm_error("DC: failed to create tg!\n");
1844 			goto create_fail;
1845 		}
1846 		j++;
1847 	}
1848 
1849 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1850 		pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
1851 		if (pool->base.engines[i] == NULL) {
1852 			BREAK_TO_DEBUGGER();
1853 			dm_error(
1854 				"DC:failed to create aux engine!!\n");
1855 			goto create_fail;
1856 		}
1857 		pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
1858 		if (pool->base.hw_i2cs[i] == NULL) {
1859 			BREAK_TO_DEBUGGER();
1860 			dm_error(
1861 				"DC:failed to create hw i2c!!\n");
1862 			goto create_fail;
1863 		}
1864 		pool->base.sw_i2cs[i] = NULL;
1865 	}
1866 
1867 	pool->base.timing_generator_count = j;
1868 	pool->base.pipe_count = j;
1869 	pool->base.mpcc_count = j;
1870 
1871 	pool->base.mpc = dcn21_mpc_create(ctx);
1872 	if (pool->base.mpc == NULL) {
1873 		BREAK_TO_DEBUGGER();
1874 		dm_error("DC: failed to create mpc!\n");
1875 		goto create_fail;
1876 	}
1877 
1878 	pool->base.hubbub = dcn21_hubbub_create(ctx);
1879 	if (pool->base.hubbub == NULL) {
1880 		BREAK_TO_DEBUGGER();
1881 		dm_error("DC: failed to create hubbub!\n");
1882 		goto create_fail;
1883 	}
1884 
1885 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1886 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1887 		pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
1888 		if (pool->base.dscs[i] == NULL) {
1889 			BREAK_TO_DEBUGGER();
1890 			dm_error("DC: failed to create display stream compressor %d!\n", i);
1891 			goto create_fail;
1892 		}
1893 	}
1894 #endif
1895 
1896 	if (!dcn20_dwbc_create(ctx, &pool->base)) {
1897 		BREAK_TO_DEBUGGER();
1898 		dm_error("DC: failed to create dwbc!\n");
1899 		goto create_fail;
1900 	}
1901 	if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
1902 		BREAK_TO_DEBUGGER();
1903 		dm_error("DC: failed to create mcif_wb!\n");
1904 		goto create_fail;
1905 	}
1906 
1907 	if (!resource_construct(num_virtual_links, dc, &pool->base,
1908 			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1909 			&res_create_funcs : &res_create_maximus_funcs)))
1910 			goto create_fail;
1911 
1912 	dcn21_hw_sequencer_construct(dc);
1913 
1914 	dc->caps.max_planes =  pool->base.pipe_count;
1915 
1916 	for (i = 0; i < dc->caps.max_planes; ++i)
1917 		dc->caps.planes[i] = plane_cap;
1918 
1919 	dc->cap_funcs = cap_funcs;
1920 
1921 	return true;
1922 
1923 create_fail:
1924 
1925 	destruct(pool);
1926 
1927 	return false;
1928 }
1929 
1930 struct resource_pool *dcn21_create_resource_pool(
1931 		const struct dc_init_data *init_data,
1932 		struct dc *dc)
1933 {
1934 	struct dcn21_resource_pool *pool =
1935 		kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
1936 
1937 	if (!pool)
1938 		return NULL;
1939 
1940 	if (construct(init_data->num_virtual_links, dc, pool))
1941 		return &pool->base;
1942 
1943 	BREAK_TO_DEBUGGER();
1944 	kfree(pool);
1945 	return NULL;
1946 }
1947