1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 28 #include <linux/delay.h> 29 #include "core_types.h" 30 #include "link_encoder.h" 31 #include "dcn21_link_encoder.h" 32 #include "stream_encoder.h" 33 34 #include "dc_bios_types.h" 35 36 #include "gpio_service_interface.h" 37 38 #define CTX \ 39 enc10->base.ctx 40 #define DC_LOGGER \ 41 enc10->base.ctx->logger 42 43 #define REG(reg)\ 44 (enc10->link_regs->reg) 45 46 #undef FN 47 #define FN(reg_name, field_name) \ 48 enc10->link_shift->field_name, enc10->link_mask->field_name 49 50 #define IND_REG(index) \ 51 (enc10->link_regs->index) 52 53 static struct mpll_cfg dcn21_mpll_cfg_ref[] = { 54 // RBR 55 { 56 .hdmimode_enable = 0, 57 .ref_range = 1, 58 .ref_clk_mpllb_div = 1, 59 .mpllb_ssc_en = 1, 60 .mpllb_div5_clk_en = 1, 61 .mpllb_multiplier = 238, 62 .mpllb_fracn_en = 0, 63 .mpllb_fracn_quot = 0, 64 .mpllb_fracn_rem = 0, 65 .mpllb_fracn_den = 1, 66 .mpllb_ssc_up_spread = 0, 67 .mpllb_ssc_peak = 44237, 68 .mpllb_ssc_stepsize = 59454, 69 .mpllb_div_clk_en = 0, 70 .mpllb_div_multiplier = 0, 71 .mpllb_hdmi_div = 0, 72 .mpllb_tx_clk_div = 2, 73 .tx_vboost_lvl = 5, 74 .mpllb_pmix_en = 1, 75 .mpllb_word_div2_en = 0, 76 .mpllb_ana_v2i = 2, 77 .mpllb_ana_freq_vco = 2, 78 .mpllb_ana_cp_int = 9, 79 .mpllb_ana_cp_prop = 15, 80 .hdmi_pixel_clk_div = 0, 81 }, 82 // HBR 83 { 84 .hdmimode_enable = 0, 85 .ref_range = 1, 86 .ref_clk_mpllb_div = 1, 87 .mpllb_ssc_en = 1, 88 .mpllb_div5_clk_en = 1, 89 .mpllb_multiplier = 192, 90 .mpllb_fracn_en = 1, 91 .mpllb_fracn_quot = 32768, 92 .mpllb_fracn_rem = 0, 93 .mpllb_fracn_den = 1, 94 .mpllb_ssc_up_spread = 0, 95 .mpllb_ssc_peak = 36864, 96 .mpllb_ssc_stepsize = 49545, 97 .mpllb_div_clk_en = 0, 98 .mpllb_div_multiplier = 0, 99 .mpllb_hdmi_div = 0, 100 .mpllb_tx_clk_div = 1, 101 .tx_vboost_lvl = 5, 102 .mpllb_pmix_en = 1, 103 .mpllb_word_div2_en = 0, 104 .mpllb_ana_v2i = 2, 105 .mpllb_ana_freq_vco = 3, 106 .mpllb_ana_cp_int = 9, 107 .mpllb_ana_cp_prop = 15, 108 .hdmi_pixel_clk_div = 0, 109 }, 110 //HBR2 111 { 112 .hdmimode_enable = 0, 113 .ref_range = 1, 114 .ref_clk_mpllb_div = 1, 115 .mpllb_ssc_en = 1, 116 .mpllb_div5_clk_en = 1, 117 .mpllb_multiplier = 192, 118 .mpllb_fracn_en = 1, 119 .mpllb_fracn_quot = 32768, 120 .mpllb_fracn_rem = 0, 121 .mpllb_fracn_den = 1, 122 .mpllb_ssc_up_spread = 0, 123 .mpllb_ssc_peak = 36864, 124 .mpllb_ssc_stepsize = 49545, 125 .mpllb_div_clk_en = 0, 126 .mpllb_div_multiplier = 0, 127 .mpllb_hdmi_div = 0, 128 .mpllb_tx_clk_div = 0, 129 .tx_vboost_lvl = 5, 130 .mpllb_pmix_en = 1, 131 .mpllb_word_div2_en = 0, 132 .mpllb_ana_v2i = 2, 133 .mpllb_ana_freq_vco = 3, 134 .mpllb_ana_cp_int = 9, 135 .mpllb_ana_cp_prop = 15, 136 .hdmi_pixel_clk_div = 0, 137 }, 138 //HBR3 139 { 140 .hdmimode_enable = 0, 141 .ref_range = 1, 142 .ref_clk_mpllb_div = 1, 143 .mpllb_ssc_en = 1, 144 .mpllb_div5_clk_en = 1, 145 .mpllb_multiplier = 304, 146 .mpllb_fracn_en = 1, 147 .mpllb_fracn_quot = 49152, 148 .mpllb_fracn_rem = 0, 149 .mpllb_fracn_den = 1, 150 .mpllb_ssc_up_spread = 0, 151 .mpllb_ssc_peak = 55296, 152 .mpllb_ssc_stepsize = 74318, 153 .mpllb_div_clk_en = 0, 154 .mpllb_div_multiplier = 0, 155 .mpllb_hdmi_div = 0, 156 .mpllb_tx_clk_div = 0, 157 .tx_vboost_lvl = 5, 158 .mpllb_pmix_en = 1, 159 .mpllb_word_div2_en = 0, 160 .mpllb_ana_v2i = 2, 161 .mpllb_ana_freq_vco = 1, 162 .mpllb_ana_cp_int = 7, 163 .mpllb_ana_cp_prop = 16, 164 .hdmi_pixel_clk_div = 0, 165 }, 166 }; 167 168 169 static bool update_cfg_data( 170 struct dcn10_link_encoder *enc10, 171 const struct dc_link_settings *link_settings, 172 struct dpcssys_phy_seq_cfg *cfg) 173 { 174 int i; 175 176 cfg->load_sram_fw = false; 177 cfg->use_calibration_setting = true; 178 179 //TODO: need to implement a proper lane mapping for Renoir. 180 for (i = 0; i < 4; i++) 181 cfg->lane_en[i] = true; 182 183 switch (link_settings->link_rate) { 184 case LINK_RATE_LOW: 185 cfg->mpll_cfg = dcn21_mpll_cfg_ref[0]; 186 break; 187 case LINK_RATE_HIGH: 188 cfg->mpll_cfg = dcn21_mpll_cfg_ref[1]; 189 break; 190 case LINK_RATE_HIGH2: 191 cfg->mpll_cfg = dcn21_mpll_cfg_ref[2]; 192 break; 193 case LINK_RATE_HIGH3: 194 cfg->mpll_cfg = dcn21_mpll_cfg_ref[3]; 195 break; 196 default: 197 DC_LOG_ERROR("%s: No supported link rate found %X!\n", 198 __func__, link_settings->link_rate); 199 return false; 200 } 201 202 return true; 203 } 204 205 static bool dcn21_link_encoder_acquire_phy(struct link_encoder *enc) 206 { 207 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 208 int value; 209 210 if (enc->features.flags.bits.DP_IS_USB_C) { 211 REG_GET(RDPCSTX_PHY_CNTL6, 212 RDPCS_PHY_DPALT_DISABLE, &value); 213 214 if (value == 1) { 215 ASSERT(0); 216 return false; 217 } 218 REG_UPDATE(RDPCSTX_PHY_CNTL6, 219 RDPCS_PHY_DPALT_DISABLE_ACK, 0); 220 221 udelay(40); 222 223 REG_GET(RDPCSTX_PHY_CNTL6, 224 RDPCS_PHY_DPALT_DISABLE, &value); 225 if (value == 1) { 226 ASSERT(0); 227 REG_UPDATE(RDPCSTX_PHY_CNTL6, 228 RDPCS_PHY_DPALT_DISABLE_ACK, 1); 229 return false; 230 } 231 } 232 233 REG_UPDATE(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, 1); 234 235 return true; 236 } 237 238 239 240 static void dcn21_link_encoder_release_phy(struct link_encoder *enc) 241 { 242 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 243 244 if (enc->features.flags.bits.DP_IS_USB_C) { 245 REG_UPDATE(RDPCSTX_PHY_CNTL6, 246 RDPCS_PHY_DPALT_DISABLE_ACK, 1); 247 } 248 249 REG_UPDATE(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, 0); 250 251 } 252 253 void dcn21_link_encoder_enable_dp_output( 254 struct link_encoder *enc, 255 const struct dc_link_settings *link_settings, 256 enum clock_source_id clock_source) 257 { 258 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 259 struct dcn21_link_encoder *enc21 = (struct dcn21_link_encoder *) enc10; 260 struct dpcssys_phy_seq_cfg *cfg = &enc21->phy_seq_cfg; 261 262 if (!dcn21_link_encoder_acquire_phy(enc)) 263 return; 264 265 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { 266 dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source); 267 return; 268 } 269 270 if (!update_cfg_data(enc10, link_settings, cfg)) 271 return; 272 273 enc1_configure_encoder(enc10, link_settings); 274 275 dcn10_link_encoder_setup(enc, SIGNAL_TYPE_DISPLAY_PORT); 276 277 } 278 279 static void dcn21_link_encoder_enable_dp_mst_output( 280 struct link_encoder *enc, 281 const struct dc_link_settings *link_settings, 282 enum clock_source_id clock_source) 283 { 284 if (!dcn21_link_encoder_acquire_phy(enc)) 285 return; 286 287 dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source); 288 } 289 290 static void dcn21_link_encoder_disable_output(struct link_encoder *enc, 291 enum signal_type signal) 292 { 293 dcn10_link_encoder_disable_output(enc, signal); 294 295 if (dc_is_dp_signal(signal)) 296 dcn21_link_encoder_release_phy(enc); 297 } 298 299 300 static const struct link_encoder_funcs dcn21_link_enc_funcs = { 301 .read_state = link_enc2_read_state, 302 .validate_output_with_stream = 303 dcn10_link_encoder_validate_output_with_stream, 304 .hw_init = enc2_hw_init, 305 .setup = dcn10_link_encoder_setup, 306 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output, 307 .enable_dp_output = dcn21_link_encoder_enable_dp_output, 308 .enable_dp_mst_output = dcn21_link_encoder_enable_dp_mst_output, 309 .disable_output = dcn21_link_encoder_disable_output, 310 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings, 311 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern, 312 .update_mst_stream_allocation_table = 313 dcn10_link_encoder_update_mst_stream_allocation_table, 314 .psr_program_dp_dphy_fast_training = 315 dcn10_psr_program_dp_dphy_fast_training, 316 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet, 317 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe, 318 .enable_hpd = dcn10_link_encoder_enable_hpd, 319 .disable_hpd = dcn10_link_encoder_disable_hpd, 320 .is_dig_enabled = dcn10_is_dig_enabled, 321 .destroy = dcn10_link_encoder_destroy, 322 .fec_set_enable = enc2_fec_set_enable, 323 .fec_set_ready = enc2_fec_set_ready, 324 .fec_is_active = enc2_fec_is_active, 325 .get_dig_frontend = dcn10_get_dig_frontend, 326 .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode, 327 .get_max_link_cap = dcn20_link_encoder_get_max_link_cap, 328 }; 329 330 void dcn21_link_encoder_construct( 331 struct dcn21_link_encoder *enc21, 332 const struct encoder_init_data *init_data, 333 const struct encoder_feature_support *enc_features, 334 const struct dcn10_link_enc_registers *link_regs, 335 const struct dcn10_link_enc_aux_registers *aux_regs, 336 const struct dcn10_link_enc_hpd_registers *hpd_regs, 337 const struct dcn10_link_enc_shift *link_shift, 338 const struct dcn10_link_enc_mask *link_mask) 339 { 340 struct bp_encoder_cap_info bp_cap_info = {0}; 341 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; 342 enum bp_result result = BP_RESULT_OK; 343 struct dcn10_link_encoder *enc10 = &enc21->enc10; 344 345 enc10->base.funcs = &dcn21_link_enc_funcs; 346 enc10->base.ctx = init_data->ctx; 347 enc10->base.id = init_data->encoder; 348 349 enc10->base.hpd_source = init_data->hpd_source; 350 enc10->base.connector = init_data->connector; 351 352 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; 353 354 enc10->base.features = *enc_features; 355 356 enc10->base.transmitter = init_data->transmitter; 357 358 /* set the flag to indicate whether driver poll the I2C data pin 359 * while doing the DP sink detect 360 */ 361 362 /* if (dal_adapter_service_is_feature_supported(as, 363 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) 364 enc10->base.features.flags.bits. 365 DP_SINK_DETECT_POLL_DATA_PIN = true;*/ 366 367 enc10->base.output_signals = 368 SIGNAL_TYPE_DVI_SINGLE_LINK | 369 SIGNAL_TYPE_DVI_DUAL_LINK | 370 SIGNAL_TYPE_LVDS | 371 SIGNAL_TYPE_DISPLAY_PORT | 372 SIGNAL_TYPE_DISPLAY_PORT_MST | 373 SIGNAL_TYPE_EDP | 374 SIGNAL_TYPE_HDMI_TYPE_A; 375 376 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. 377 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. 378 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer 379 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. 380 * Prefer DIG assignment is decided by board design. 381 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design 382 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. 383 * By this, adding DIGG should not hurt DCE 8.0. 384 * This will let DCE 8.1 share DCE 8.0 as much as possible 385 */ 386 387 enc10->link_regs = link_regs; 388 enc10->aux_regs = aux_regs; 389 enc10->hpd_regs = hpd_regs; 390 enc10->link_shift = link_shift; 391 enc10->link_mask = link_mask; 392 393 switch (enc10->base.transmitter) { 394 case TRANSMITTER_UNIPHY_A: 395 enc10->base.preferred_engine = ENGINE_ID_DIGA; 396 break; 397 case TRANSMITTER_UNIPHY_B: 398 enc10->base.preferred_engine = ENGINE_ID_DIGB; 399 break; 400 case TRANSMITTER_UNIPHY_C: 401 enc10->base.preferred_engine = ENGINE_ID_DIGC; 402 break; 403 case TRANSMITTER_UNIPHY_D: 404 enc10->base.preferred_engine = ENGINE_ID_DIGD; 405 break; 406 case TRANSMITTER_UNIPHY_E: 407 enc10->base.preferred_engine = ENGINE_ID_DIGE; 408 break; 409 case TRANSMITTER_UNIPHY_F: 410 enc10->base.preferred_engine = ENGINE_ID_DIGF; 411 break; 412 case TRANSMITTER_UNIPHY_G: 413 enc10->base.preferred_engine = ENGINE_ID_DIGG; 414 break; 415 default: 416 ASSERT_CRITICAL(false); 417 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; 418 } 419 420 /* default to one to mirror Windows behavior */ 421 enc10->base.features.flags.bits.HDMI_6GB_EN = 1; 422 423 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios, 424 enc10->base.id, &bp_cap_info); 425 426 /* Override features with DCE-specific values */ 427 if (result == BP_RESULT_OK) { 428 enc10->base.features.flags.bits.IS_HBR2_CAPABLE = 429 bp_cap_info.DP_HBR2_EN; 430 enc10->base.features.flags.bits.IS_HBR3_CAPABLE = 431 bp_cap_info.DP_HBR3_EN; 432 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; 433 enc10->base.features.flags.bits.DP_IS_USB_C = 434 bp_cap_info.DP_IS_USB_C; 435 } else { 436 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", 437 __func__, 438 result); 439 } 440 if (enc10->base.ctx->dc->debug.hdmi20_disable) { 441 enc10->base.features.flags.bits.HDMI_6GB_EN = 0; 442 } 443 } 444