1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dm_helpers.h" 28 #include "core_types.h" 29 #include "resource.h" 30 #include "dce/dce_hwseq.h" 31 #include "dcn21_hwseq.h" 32 #include "vmid.h" 33 #include "reg_helper.h" 34 #include "hw/clk_mgr.h" 35 36 37 #define DC_LOGGER_INIT(logger) 38 39 #define CTX \ 40 hws->ctx 41 #define REG(reg)\ 42 hws->regs->reg 43 44 #undef FN 45 #define FN(reg_name, field_name) \ 46 hws->shifts->field_name, hws->masks->field_name 47 48 /* Temporary read settings, future will get values from kmd directly */ 49 static void mmhub_update_page_table_config(struct dcn_hubbub_phys_addr_config *config, 50 struct dce_hwseq *hws) 51 { 52 uint32_t page_table_base_hi; 53 uint32_t page_table_base_lo; 54 55 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 56 PAGE_DIRECTORY_ENTRY_HI32, &page_table_base_hi); 57 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 58 PAGE_DIRECTORY_ENTRY_LO32, &page_table_base_lo); 59 60 config->gart_config.page_table_base_addr = ((uint64_t)page_table_base_hi << 32) | page_table_base_lo; 61 62 } 63 64 int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 65 { 66 struct dcn_hubbub_phys_addr_config config; 67 68 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 69 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 70 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 71 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 72 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 73 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 74 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 75 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 76 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 77 78 mmhub_update_page_table_config(&config, hws); 79 80 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 81 } 82 83 // work around for Renoir s0i3, if register is programmed, bypass golden init. 84 85 bool dcn21_s0i3_golden_init_wa(struct dc *dc) 86 { 87 struct dce_hwseq *hws = dc->hwseq; 88 uint32_t value = 0; 89 90 value = REG_READ(MICROSECOND_TIME_BASE_DIV); 91 92 return value != 0x00120464; 93 } 94 95 void dcn21_exit_optimized_pwr_state( 96 const struct dc *dc, 97 struct dc_state *context) 98 { 99 dc->clk_mgr->funcs->update_clocks( 100 dc->clk_mgr, 101 context, 102 false); 103 } 104 105 void dcn21_optimize_pwr_state( 106 const struct dc *dc, 107 struct dc_state *context) 108 { 109 dc->clk_mgr->funcs->update_clocks( 110 dc->clk_mgr, 111 context, 112 true); 113 } 114 115 /* If user hotplug a HDMI monitor while in monitor off, 116 * OS will do a mode set (with output timing) but keep output off. 117 * In this case DAL will ask vbios to power up the pll in the PHY. 118 * If user unplug the monitor (while we are on monitor off) or 119 * system attempt to enter modern standby (which we will disable PLL), 120 * PHY will hang on the next mode set attempt. 121 * if enable PLL follow by disable PLL (without executing lane enable/disable), 122 * RDPCS_PHY_DP_MPLLB_STATE remains 1, 123 * which indicate that PLL disable attempt actually didn�t go through. 124 * As a workaround, insert PHY lane enable/disable before PLL disable. 125 */ 126 void dcn21_PLAT_58856_wa(struct dc_state *context, struct pipe_ctx *pipe_ctx) 127 { 128 if (!pipe_ctx->stream->dpms_off) 129 return; 130 131 pipe_ctx->stream->dpms_off = false; 132 core_link_enable_stream(context, pipe_ctx); 133 core_link_disable_stream(pipe_ctx); 134 pipe_ctx->stream->dpms_off = true; 135 } 136 137