16f451b60SBhawanpreet Lakha /* 26f451b60SBhawanpreet Lakha * Copyright 2018 Advanced Micro Devices, Inc. 36f451b60SBhawanpreet Lakha * 46f451b60SBhawanpreet Lakha * Permission is hereby granted, free of charge, to any person obtaining a 56f451b60SBhawanpreet Lakha * copy of this software and associated documentation files (the "Software"), 66f451b60SBhawanpreet Lakha * to deal in the Software without restriction, including without limitation 76f451b60SBhawanpreet Lakha * the rights to use, copy, modify, merge, publish, distribute, sublicense, 86f451b60SBhawanpreet Lakha * and/or sell copies of the Software, and to permit persons to whom the 96f451b60SBhawanpreet Lakha * Software is furnished to do so, subject to the following conditions: 106f451b60SBhawanpreet Lakha * 116f451b60SBhawanpreet Lakha * The above copyright notice and this permission notice shall be included in 126f451b60SBhawanpreet Lakha * all copies or substantial portions of the Software. 136f451b60SBhawanpreet Lakha * 146f451b60SBhawanpreet Lakha * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 156f451b60SBhawanpreet Lakha * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 166f451b60SBhawanpreet Lakha * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 176f451b60SBhawanpreet Lakha * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 186f451b60SBhawanpreet Lakha * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 196f451b60SBhawanpreet Lakha * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 206f451b60SBhawanpreet Lakha * OTHER DEALINGS IN THE SOFTWARE. 216f451b60SBhawanpreet Lakha * 226f451b60SBhawanpreet Lakha * Authors: AMD 236f451b60SBhawanpreet Lakha * 246f451b60SBhawanpreet Lakha */ 256f451b60SBhawanpreet Lakha #ifndef DAL_DC_DCN21_DCN21_HUBBUB_H_ 266f451b60SBhawanpreet Lakha #define DAL_DC_DCN21_DCN21_HUBBUB_H_ 276f451b60SBhawanpreet Lakha 286f451b60SBhawanpreet Lakha #include "dcn20/dcn20_hubbub.h" 296f451b60SBhawanpreet Lakha 306f451b60SBhawanpreet Lakha #define HUBBUB_HVM_REG_LIST() \ 316f451b60SBhawanpreet Lakha SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\ 326f451b60SBhawanpreet Lakha SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\ 336f451b60SBhawanpreet Lakha SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\ 346f451b60SBhawanpreet Lakha SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\ 356f451b60SBhawanpreet Lakha SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\ 366f451b60SBhawanpreet Lakha SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\ 376f451b60SBhawanpreet Lakha SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\ 386f451b60SBhawanpreet Lakha SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\ 39f6586223SBhawanpreet Lakha SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\ 40f6586223SBhawanpreet Lakha SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\ 41f6586223SBhawanpreet Lakha SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C),\ 42f6586223SBhawanpreet Lakha SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D),\ 436f451b60SBhawanpreet Lakha SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 446f451b60SBhawanpreet Lakha SR(DCHVM_CTRL0), \ 456f451b60SBhawanpreet Lakha SR(DCHVM_MEM_CTRL), \ 466f451b60SBhawanpreet Lakha SR(DCHVM_CLK_CTRL), \ 476f451b60SBhawanpreet Lakha SR(DCHVM_RIOMMU_CTRL0), \ 486f451b60SBhawanpreet Lakha SR(DCHVM_RIOMMU_STAT0) 496f451b60SBhawanpreet Lakha 506f451b60SBhawanpreet Lakha #define HUBBUB_REG_LIST_DCN21()\ 51f6586223SBhawanpreet Lakha HUBBUB_REG_LIST_DCN20_COMMON(), \ 526f451b60SBhawanpreet Lakha HUBBUB_SR_WATERMARK_REG_LIST(), \ 53f6586223SBhawanpreet Lakha HUBBUB_HVM_REG_LIST() 546f451b60SBhawanpreet Lakha 556f451b60SBhawanpreet Lakha #define HUBBUB_MASK_SH_LIST_HVM(mask_sh) \ 566f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, mask_sh), \ 576f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, mask_sh), \ 586f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, mask_sh), \ 596f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, mask_sh), \ 606f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, mask_sh), \ 616f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, mask_sh), \ 626f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, mask_sh), \ 636f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, mask_sh), \ 646f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, mask_sh), \ 656f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A, mask_sh), \ 666f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B, mask_sh), \ 676f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C, mask_sh), \ 686f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D, mask_sh), \ 696f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A, mask_sh), \ 706f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B, mask_sh), \ 716f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C, mask_sh), \ 726f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D, mask_sh), \ 736f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, mask_sh), \ 746f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B, mask_sh), \ 756f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C, mask_sh), \ 766f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D, mask_sh), \ 776f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, mask_sh), \ 786f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, mask_sh), \ 796f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, mask_sh), \ 806f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, mask_sh), \ 816f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, mask_sh), \ 826f451b60SBhawanpreet Lakha HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh), \ 836f451b60SBhawanpreet Lakha HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, mask_sh), \ 846f451b60SBhawanpreet Lakha HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_FORCE_REQ, mask_sh), \ 856f451b60SBhawanpreet Lakha HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_POWER_STATUS, mask_sh), \ 866f451b60SBhawanpreet Lakha HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_R_GATE_DIS, mask_sh), \ 876f451b60SBhawanpreet Lakha HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_G_GATE_DIS, mask_sh), \ 886f451b60SBhawanpreet Lakha HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_R_GATE_DIS, mask_sh), \ 896f451b60SBhawanpreet Lakha HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_G_GATE_DIS, mask_sh), \ 906f451b60SBhawanpreet Lakha HUBBUB_SF(DCHVM_CLK_CTRL, TR_REQ_REQCLKREQ_MODE, mask_sh), \ 916f451b60SBhawanpreet Lakha HUBBUB_SF(DCHVM_CLK_CTRL, TW_RSP_COMPCLKREQ_MODE, mask_sh), \ 926f451b60SBhawanpreet Lakha HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, mask_sh), \ 936f451b60SBhawanpreet Lakha HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, mask_sh), \ 946f451b60SBhawanpreet Lakha HUBBUB_SF(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, mask_sh), \ 956f451b60SBhawanpreet Lakha HUBBUB_SF(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, mask_sh), \ 966f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, mask_sh), \ 976f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, mask_sh), \ 986f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, mask_sh), \ 996f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh) 1006f451b60SBhawanpreet Lakha 1016f451b60SBhawanpreet Lakha #define HUBBUB_MASK_SH_LIST_DCN21(mask_sh)\ 1026f451b60SBhawanpreet Lakha HUBBUB_MASK_SH_LIST_HVM(mask_sh), \ 1036f451b60SBhawanpreet Lakha HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \ 1046f451b60SBhawanpreet Lakha HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \ 1056f451b60SBhawanpreet Lakha HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 1066f451b60SBhawanpreet Lakha HUBBUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh), \ 1076f451b60SBhawanpreet Lakha HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \ 1086f451b60SBhawanpreet Lakha HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \ 1096f451b60SBhawanpreet Lakha HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \ 1106f451b60SBhawanpreet Lakha HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \ 111*98e95e4fSJosip Pavic HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \ 112*98e95e4fSJosip Pavic HUBBUB_SF(DCN_VM_FAULT_ADDR_MSB, DCN_VM_FAULT_ADDR_MSB, mask_sh), \ 113*98e95e4fSJosip Pavic HUBBUB_SF(DCN_VM_FAULT_ADDR_LSB, DCN_VM_FAULT_ADDR_LSB, mask_sh), \ 114*98e95e4fSJosip Pavic HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_CLEAR, mask_sh), \ 115*98e95e4fSJosip Pavic HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, mask_sh), \ 116*98e95e4fSJosip Pavic HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_INTERRUPT_ENABLE, mask_sh), \ 117*98e95e4fSJosip Pavic HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_RANGE_FAULT_DISABLE, mask_sh), \ 118*98e95e4fSJosip Pavic HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_PRQ_FAULT_DISABLE, mask_sh), \ 119*98e95e4fSJosip Pavic HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, mask_sh), \ 120*98e95e4fSJosip Pavic HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, mask_sh), \ 121*98e95e4fSJosip Pavic HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_TABLE_LEVEL, mask_sh), \ 122*98e95e4fSJosip Pavic HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, mask_sh), \ 123*98e95e4fSJosip Pavic HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh) 1246f451b60SBhawanpreet Lakha 1256f451b60SBhawanpreet Lakha void dcn21_dchvm_init(struct hubbub *hubbub); 1264de094eeSBhawanpreet Lakha int hubbub21_init_dchub(struct hubbub *hubbub, 1274de094eeSBhawanpreet Lakha struct dcn_hubbub_phys_addr_config *pa_config); 12889e94bc5SYongqiang Sun bool hubbub21_program_watermarks( 1296f451b60SBhawanpreet Lakha struct hubbub *hubbub, 1306f451b60SBhawanpreet Lakha struct dcn_watermark_set *watermarks, 1316f451b60SBhawanpreet Lakha unsigned int refclk_mhz, 1326f451b60SBhawanpreet Lakha bool safe_to_lower); 13389e94bc5SYongqiang Sun bool hubbub21_program_urgent_watermarks( 1344de094eeSBhawanpreet Lakha struct hubbub *hubbub, 1354de094eeSBhawanpreet Lakha struct dcn_watermark_set *watermarks, 1364de094eeSBhawanpreet Lakha unsigned int refclk_mhz, 1374de094eeSBhawanpreet Lakha bool safe_to_lower); 13889e94bc5SYongqiang Sun bool hubbub21_program_stutter_watermarks( 1394de094eeSBhawanpreet Lakha struct hubbub *hubbub, 1404de094eeSBhawanpreet Lakha struct dcn_watermark_set *watermarks, 1414de094eeSBhawanpreet Lakha unsigned int refclk_mhz, 1424de094eeSBhawanpreet Lakha bool safe_to_lower); 14389e94bc5SYongqiang Sun bool hubbub21_program_pstate_watermarks( 1444de094eeSBhawanpreet Lakha struct hubbub *hubbub, 1454de094eeSBhawanpreet Lakha struct dcn_watermark_set *watermarks, 1464de094eeSBhawanpreet Lakha unsigned int refclk_mhz, 1474de094eeSBhawanpreet Lakha bool safe_to_lower); 1486f451b60SBhawanpreet Lakha 1496f451b60SBhawanpreet Lakha void hubbub21_wm_read_state(struct hubbub *hubbub, 1506f451b60SBhawanpreet Lakha struct dcn_hubbub_wm *wm); 1516f451b60SBhawanpreet Lakha 1526f451b60SBhawanpreet Lakha void hubbub21_construct(struct dcn20_hubbub *hubbub, 1536f451b60SBhawanpreet Lakha struct dc_context *ctx, 1546f451b60SBhawanpreet Lakha const struct dcn_hubbub_registers *hubbub_regs, 1556f451b60SBhawanpreet Lakha const struct dcn_hubbub_shift *hubbub_shift, 1566f451b60SBhawanpreet Lakha const struct dcn_hubbub_mask *hubbub_mask); 1576f451b60SBhawanpreet Lakha 1586f451b60SBhawanpreet Lakha #endif /* DAL_DC_DCN21_DCN21_HUBBUB_H_ */ 159