1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "reg_helper.h"
27 #include "dcn201_optc.h"
28 #include "dcn10/dcn10_optc.h"
29 #include "dc.h"
30 
31 #define REG(reg)\
32 	optc1->tg_regs->reg
33 
34 #define CTX \
35 	optc1->base.ctx
36 
37 #undef FN
38 #define FN(reg_name, field_name) \
39 	optc1->tg_shift->field_name, optc1->tg_mask->field_name
40 
41 /*TEMP: Need to figure out inheritance model here.*/
42 bool optc201_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
43 {
44 	return optc1_is_two_pixels_per_containter(timing);
45 }
46 
47 static void optc201_triplebuffer_lock(struct timing_generator *optc)
48 {
49 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
50 
51 	REG_SET(OTG_GLOBAL_CONTROL0, 0,
52 		OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
53 	REG_SET(OTG_VUPDATE_KEEPOUT, 0,
54 		OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
55 	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
56 		OTG_MASTER_UPDATE_LOCK, 1);
57 
58 	REG_WAIT(OTG_MASTER_UPDATE_LOCK,
59 			UPDATE_LOCK_STATUS, 1,
60 			1, 10);
61 }
62 
63 static void optc201_triplebuffer_unlock(struct timing_generator *optc)
64 {
65 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
66 
67 	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
68 		OTG_MASTER_UPDATE_LOCK, 0);
69 	REG_SET(OTG_VUPDATE_KEEPOUT, 0,
70 		OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 0);
71 
72 }
73 
74 static bool optc201_validate_timing(
75 	struct timing_generator *optc,
76 	const struct dc_crtc_timing *timing)
77 {
78 	uint32_t v_blank;
79 	uint32_t h_blank;
80 	uint32_t min_v_blank;
81 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
82 
83 	ASSERT(timing != NULL);
84 
85 	v_blank = (timing->v_total - timing->v_addressable -
86 					timing->v_border_top - timing->v_border_bottom);
87 
88 	h_blank = (timing->h_total - timing->h_addressable -
89 		timing->h_border_right -
90 		timing->h_border_left);
91 
92 	if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
93 		timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&
94 		timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&
95 		timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&
96 		timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&
97 		timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
98 		return false;
99 
100 	/* Check maximum number of pixels supported by Timing Generator
101 	 * (Currently will never fail, in order to fail needs display which
102 	 * needs more than 8192 horizontal and
103 	 * more than 8192 vertical total pixels)
104 	 */
105 	if (timing->h_total > optc1->max_h_total ||
106 		timing->v_total > optc1->max_v_total)
107 		return false;
108 
109 	if (h_blank < optc1->min_h_blank)
110 		return false;
111 
112 	if (timing->h_sync_width  < optc1->min_h_sync_width ||
113 		 timing->v_sync_width  < optc1->min_v_sync_width)
114 		return false;
115 
116 	min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;
117 
118 	if (v_blank < min_v_blank)
119 		return false;
120 
121 	return true;
122 
123 }
124 
125 static void optc201_get_optc_source(struct timing_generator *optc,
126 		uint32_t *num_of_src_opp,
127 		uint32_t *src_opp_id_0,
128 		uint32_t *src_opp_id_1)
129 {
130 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
131 
132 	REG_GET(OPTC_DATA_SOURCE_SELECT,
133 			OPTC_SEG0_SRC_SEL, src_opp_id_0);
134 
135 	*num_of_src_opp = 1;
136 }
137 
138 static struct timing_generator_funcs dcn201_tg_funcs = {
139 		.validate_timing = optc201_validate_timing,
140 		.program_timing = optc1_program_timing,
141 		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
142 		.setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
143 		.setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
144 		.program_global_sync = optc1_program_global_sync,
145 		.enable_crtc = optc2_enable_crtc,
146 		.disable_crtc = optc1_disable_crtc,
147 		/* used by enable_timing_synchronization. Not need for FPGA */
148 		.is_counter_moving = optc1_is_counter_moving,
149 		.get_position = optc1_get_position,
150 		.get_frame_count = optc1_get_vblank_counter,
151 		.get_scanoutpos = optc1_get_crtc_scanoutpos,
152 		.get_otg_active_size = optc1_get_otg_active_size,
153 		.set_early_control = optc1_set_early_control,
154 		/* used by enable_timing_synchronization. Not need for FPGA */
155 		.wait_for_state = optc1_wait_for_state,
156 		.set_blank = optc1_set_blank,
157 		.is_blanked = optc1_is_blanked,
158 		.set_blank_color = optc1_program_blank_color,
159 		.did_triggered_reset_occur = optc1_did_triggered_reset_occur,
160 		.enable_reset_trigger = optc1_enable_reset_trigger,
161 		.enable_crtc_reset = optc1_enable_crtc_reset,
162 		.disable_reset_trigger = optc1_disable_reset_trigger,
163 		.triplebuffer_lock = optc201_triplebuffer_lock,
164 		.triplebuffer_unlock = optc201_triplebuffer_unlock,
165 		.lock = optc1_lock,
166 		.unlock = optc1_unlock,
167 		.enable_optc_clock = optc1_enable_optc_clock,
168 		.set_drr = optc1_set_drr,
169 		.get_last_used_drr_vtotal = NULL,
170 		.set_vtotal_min_max = optc1_set_vtotal_min_max,
171 		.set_static_screen_control = optc1_set_static_screen_control,
172 		.program_stereo = optc1_program_stereo,
173 		.is_stereo_left_eye = optc1_is_stereo_left_eye,
174 		.set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
175 		.tg_init = optc1_tg_init,
176 		.is_tg_enabled = optc1_is_tg_enabled,
177 		.is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
178 		.clear_optc_underflow = optc1_clear_optc_underflow,
179 		.get_crc = optc1_get_crc,
180 		.configure_crc = optc2_configure_crc,
181 		.set_dsc_config = optc2_set_dsc_config,
182 		.set_dwb_source = NULL,
183 		.get_optc_source = optc201_get_optc_source,
184 		.set_vtg_params = optc1_set_vtg_params,
185 		.program_manual_trigger = optc2_program_manual_trigger,
186 		.setup_manual_trigger = optc2_setup_manual_trigger,
187 		.get_hw_timing = optc1_get_hw_timing,
188 };
189 
190 void dcn201_timing_generator_init(struct optc *optc1)
191 {
192 	optc1->base.funcs = &dcn201_tg_funcs;
193 
194 	optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
195 	optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
196 
197 	optc1->min_h_blank = 32;
198 	optc1->min_v_blank = 3;
199 	optc1->min_v_blank_interlace = 5;
200 	optc1->min_h_sync_width = 8;
201 	optc1->min_v_sync_width = 1;
202 }
203