1 /* Copyright 2012-15 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #ifndef __DC_MPCC_DCN201_H__ 26 #define __DC_MPCC_DCN201_H__ 27 28 #include "dcn20/dcn20_mpc.h" 29 30 #define TO_DCN201_MPC(mpc_base) \ 31 container_of(mpc_base, struct dcn201_mpc, base) 32 33 #define MPC_REG_LIST_DCN201(inst) \ 34 MPC_REG_LIST_DCN2_0(inst) 35 36 #define MPC_OUT_MUX_REG_LIST_DCN201(inst) \ 37 MPC_OUT_MUX_REG_LIST_DCN2_0(inst) 38 39 #define MPC_REG_VARIABLE_LIST_DCN201 \ 40 MPC_REG_VARIABLE_LIST_DCN2_0 41 42 #define MPC_COMMON_MASK_SH_LIST_DCN201(mask_sh) \ 43 MPC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh),\ 44 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\ 45 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\ 46 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\ 47 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT0, mask_sh),\ 48 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT1, mask_sh) 49 50 #define MPC_REG_FIELD_LIST_DCN201(type) \ 51 MPC_REG_FIELD_LIST_DCN2_0(type) \ 52 type MPC_OUT_RATE_CONTROL;\ 53 type MPC_OUT_RATE_CONTROL_DISABLE;\ 54 type MPC_OUT_FLOW_CONTROL_MODE;\ 55 type MPC_OUT_FLOW_CONTROL_COUNT0;\ 56 type MPC_OUT_FLOW_CONTROL_COUNT1; 57 58 struct dcn201_mpc_registers { 59 MPC_REG_VARIABLE_LIST_DCN201 60 }; 61 62 struct dcn201_mpc_shift { 63 MPC_REG_FIELD_LIST_DCN201(uint8_t) 64 }; 65 66 struct dcn201_mpc_mask { 67 MPC_REG_FIELD_LIST_DCN201(uint32_t) 68 }; 69 70 struct dcn201_mpc { 71 struct mpc base; 72 int mpcc_in_use_mask; 73 int num_mpcc; 74 const struct dcn201_mpc_registers *mpc_regs; 75 const struct dcn201_mpc_shift *mpc_shift; 76 const struct dcn201_mpc_mask *mpc_mask; 77 }; 78 79 void dcn201_mpc_construct(struct dcn201_mpc *mpc201, 80 struct dc_context *ctx, 81 const struct dcn201_mpc_registers *mpc_regs, 82 const struct dcn201_mpc_shift *mpc_shift, 83 const struct dcn201_mpc_mask *mpc_mask, 84 int num_mpcc); 85 86 #endif 87