1*3f68c01bSZhan Liu /* 2*3f68c01bSZhan Liu * Copyright 2016 Advanced Micro Devices, Inc. 3*3f68c01bSZhan Liu * 4*3f68c01bSZhan Liu * Permission is hereby granted, free of charge, to any person obtaining a 5*3f68c01bSZhan Liu * copy of this software and associated documentation files (the "Software"), 6*3f68c01bSZhan Liu * to deal in the Software without restriction, including without limitation 7*3f68c01bSZhan Liu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*3f68c01bSZhan Liu * and/or sell copies of the Software, and to permit persons to whom the 9*3f68c01bSZhan Liu * Software is furnished to do so, subject to the following conditions: 10*3f68c01bSZhan Liu * 11*3f68c01bSZhan Liu * The above copyright notice and this permission notice shall be included in 12*3f68c01bSZhan Liu * all copies or substantial portions of the Software. 13*3f68c01bSZhan Liu * 14*3f68c01bSZhan Liu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*3f68c01bSZhan Liu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*3f68c01bSZhan Liu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*3f68c01bSZhan Liu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*3f68c01bSZhan Liu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*3f68c01bSZhan Liu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*3f68c01bSZhan Liu * OTHER DEALINGS IN THE SOFTWARE. 21*3f68c01bSZhan Liu * 22*3f68c01bSZhan Liu * Authors: AMD 23*3f68c01bSZhan Liu * 24*3f68c01bSZhan Liu */ 25*3f68c01bSZhan Liu 26*3f68c01bSZhan Liu #include "dce110/dce110_hw_sequencer.h" 27*3f68c01bSZhan Liu #include "dcn10/dcn10_hw_sequencer.h" 28*3f68c01bSZhan Liu #include "dcn20/dcn20_hwseq.h" 29*3f68c01bSZhan Liu #include "dcn201_hwseq.h" 30*3f68c01bSZhan Liu 31*3f68c01bSZhan Liu static const struct hw_sequencer_funcs dcn201_funcs = { 32*3f68c01bSZhan Liu .program_gamut_remap = dcn10_program_gamut_remap, 33*3f68c01bSZhan Liu .init_hw = dcn201_init_hw, 34*3f68c01bSZhan Liu .power_down_on_boot = NULL, 35*3f68c01bSZhan Liu .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 36*3f68c01bSZhan Liu .apply_ctx_for_surface = NULL, 37*3f68c01bSZhan Liu .program_front_end_for_ctx = dcn20_program_front_end_for_ctx, 38*3f68c01bSZhan Liu .wait_for_pending_cleared = dcn10_wait_for_pending_cleared, 39*3f68c01bSZhan Liu .post_unlock_program_front_end = dcn10_post_unlock_program_front_end, 40*3f68c01bSZhan Liu .update_plane_addr = dcn201_update_plane_addr, 41*3f68c01bSZhan Liu .update_dchub = dcn10_update_dchub, 42*3f68c01bSZhan Liu .update_pending_status = dcn10_update_pending_status, 43*3f68c01bSZhan Liu .program_output_csc = dcn20_program_output_csc, 44*3f68c01bSZhan Liu .enable_accelerated_mode = dce110_enable_accelerated_mode, 45*3f68c01bSZhan Liu .enable_timing_synchronization = dcn10_enable_timing_synchronization, 46*3f68c01bSZhan Liu .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset, 47*3f68c01bSZhan Liu .update_info_frame = dce110_update_info_frame, 48*3f68c01bSZhan Liu .send_immediate_sdp_message = dcn10_send_immediate_sdp_message, 49*3f68c01bSZhan Liu .enable_stream = dce110_enable_stream, 50*3f68c01bSZhan Liu .disable_stream = dce110_disable_stream, 51*3f68c01bSZhan Liu .unblank_stream = dcn201_unblank_stream, 52*3f68c01bSZhan Liu .blank_stream = dce110_blank_stream, 53*3f68c01bSZhan Liu .enable_audio_stream = dce110_enable_audio_stream, 54*3f68c01bSZhan Liu .disable_audio_stream = dce110_disable_audio_stream, 55*3f68c01bSZhan Liu .disable_plane = dcn10_disable_plane, 56*3f68c01bSZhan Liu .pipe_control_lock = dcn201_pipe_control_lock, 57*3f68c01bSZhan Liu .interdependent_update_lock = dcn10_lock_all_pipes, 58*3f68c01bSZhan Liu .cursor_lock = dcn10_cursor_lock, 59*3f68c01bSZhan Liu .prepare_bandwidth = dcn20_prepare_bandwidth, 60*3f68c01bSZhan Liu .optimize_bandwidth = dcn20_optimize_bandwidth, 61*3f68c01bSZhan Liu .update_bandwidth = dcn20_update_bandwidth, 62*3f68c01bSZhan Liu .set_drr = dcn10_set_drr, 63*3f68c01bSZhan Liu .get_position = dcn10_get_position, 64*3f68c01bSZhan Liu .set_static_screen_control = dcn10_set_static_screen_control, 65*3f68c01bSZhan Liu .setup_stereo = dcn10_setup_stereo, 66*3f68c01bSZhan Liu .set_avmute = dce110_set_avmute, 67*3f68c01bSZhan Liu .log_hw_state = dcn10_log_hw_state, 68*3f68c01bSZhan Liu .get_hw_state = dcn10_get_hw_state, 69*3f68c01bSZhan Liu .clear_status_bits = dcn10_clear_status_bits, 70*3f68c01bSZhan Liu .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, 71*3f68c01bSZhan Liu .edp_backlight_control = dce110_edp_backlight_control, 72*3f68c01bSZhan Liu .edp_power_control = dce110_edp_power_control, 73*3f68c01bSZhan Liu .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, 74*3f68c01bSZhan Liu .setup_periodic_interrupt = dcn10_setup_periodic_interrupt, 75*3f68c01bSZhan Liu .set_clock = dcn10_set_clock, 76*3f68c01bSZhan Liu .get_clock = dcn10_get_clock, 77*3f68c01bSZhan Liu .program_triplebuffer = dcn20_program_triple_buffer, 78*3f68c01bSZhan Liu .dmdata_status_done = dcn20_dmdata_status_done, 79*3f68c01bSZhan Liu .set_dmdata_attributes = dcn201_set_dmdata_attributes, 80*3f68c01bSZhan Liu .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync, 81*3f68c01bSZhan Liu .calc_vupdate_position = dcn10_calc_vupdate_position, 82*3f68c01bSZhan Liu .set_cursor_position = dcn10_set_cursor_position, 83*3f68c01bSZhan Liu .set_cursor_attribute = dcn201_set_cursor_attribute, 84*3f68c01bSZhan Liu .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level, 85*3f68c01bSZhan Liu .set_backlight_level = dce110_set_backlight_level, 86*3f68c01bSZhan Liu .set_abm_immediate_disable = dce110_set_abm_immediate_disable, 87*3f68c01bSZhan Liu .set_pipe = dce110_set_pipe, 88*3f68c01bSZhan Liu .set_disp_pattern_generator = dcn20_set_disp_pattern_generator, 89*3f68c01bSZhan Liu .update_visual_confirm_color = dcn20_update_visual_confirm_color, 90*3f68c01bSZhan Liu }; 91*3f68c01bSZhan Liu 92*3f68c01bSZhan Liu static const struct hwseq_private_funcs dcn201_private_funcs = { 93*3f68c01bSZhan Liu .init_pipes = NULL, 94*3f68c01bSZhan Liu .update_plane_addr = dcn201_update_plane_addr, 95*3f68c01bSZhan Liu .plane_atomic_disconnect = dcn201_plane_atomic_disconnect, 96*3f68c01bSZhan Liu .program_pipe = dcn10_program_pipe, 97*3f68c01bSZhan Liu .update_mpcc = dcn201_update_mpcc, 98*3f68c01bSZhan Liu .set_input_transfer_func = dcn20_set_input_transfer_func, 99*3f68c01bSZhan Liu .set_output_transfer_func = dcn20_set_output_transfer_func, 100*3f68c01bSZhan Liu .power_down = dce110_power_down, 101*3f68c01bSZhan Liu .enable_display_power_gating = dcn10_dummy_display_power_gating, 102*3f68c01bSZhan Liu .blank_pixel_data = dcn20_blank_pixel_data, 103*3f68c01bSZhan Liu .reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap, 104*3f68c01bSZhan Liu .enable_stream_timing = dcn20_enable_stream_timing, 105*3f68c01bSZhan Liu .edp_backlight_control = dce110_edp_backlight_control, 106*3f68c01bSZhan Liu .disable_stream_gating = NULL, 107*3f68c01bSZhan Liu .enable_stream_gating = NULL, 108*3f68c01bSZhan Liu .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt, 109*3f68c01bSZhan Liu .did_underflow_occur = dcn10_did_underflow_occur, 110*3f68c01bSZhan Liu .init_blank = dcn201_init_blank, 111*3f68c01bSZhan Liu .disable_vga = dcn10_disable_vga, 112*3f68c01bSZhan Liu .bios_golden_init = dcn10_bios_golden_init, 113*3f68c01bSZhan Liu .plane_atomic_disable = dcn10_plane_atomic_disable, 114*3f68c01bSZhan Liu .plane_atomic_power_down = dcn10_plane_atomic_power_down, 115*3f68c01bSZhan Liu .enable_power_gating_plane = dcn10_enable_power_gating_plane, 116*3f68c01bSZhan Liu .dpp_pg_control = dcn10_dpp_pg_control, 117*3f68c01bSZhan Liu .hubp_pg_control = dcn10_hubp_pg_control, 118*3f68c01bSZhan Liu .dsc_pg_control = NULL, 119*3f68c01bSZhan Liu .set_hdr_multiplier = dcn10_set_hdr_multiplier, 120*3f68c01bSZhan Liu .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, 121*3f68c01bSZhan Liu .wait_for_blank_complete = dcn20_wait_for_blank_complete, 122*3f68c01bSZhan Liu .dccg_init = dcn20_dccg_init, 123*3f68c01bSZhan Liu .set_blend_lut = dcn20_set_blend_lut, 124*3f68c01bSZhan Liu .set_shaper_3dlut = dcn20_set_shaper_3dlut, 125*3f68c01bSZhan Liu }; 126*3f68c01bSZhan Liu 127*3f68c01bSZhan Liu void dcn201_hw_sequencer_construct(struct dc *dc) 128*3f68c01bSZhan Liu { 129*3f68c01bSZhan Liu dc->hwss = dcn201_funcs; 130*3f68c01bSZhan Liu dc->hwseq->funcs = dcn201_private_funcs; 131*3f68c01bSZhan Liu } 132