1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * Copyright 2019 Raptor Engineering, LLC 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 #include "dc.h" 31 32 #include "dcn20_init.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dcn20/dcn20_resource.h" 37 38 #include "dcn10/dcn10_hubp.h" 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn20_hubbub.h" 41 #include "dcn20_mpc.h" 42 #include "dcn20_hubp.h" 43 #include "irq/dcn20/irq_service_dcn20.h" 44 #include "dcn20_dpp.h" 45 #include "dcn20_optc.h" 46 #include "dcn20_hwseq.h" 47 #include "dce110/dce110_hw_sequencer.h" 48 #include "dcn10/dcn10_resource.h" 49 #include "dcn20_opp.h" 50 51 #include "dcn20_dsc.h" 52 53 #include "dcn20_link_encoder.h" 54 #include "dcn20_stream_encoder.h" 55 #include "dce/dce_clock_source.h" 56 #include "dce/dce_audio.h" 57 #include "dce/dce_hwseq.h" 58 #include "virtual/virtual_stream_encoder.h" 59 #include "dce110/dce110_resource.h" 60 #include "dml/display_mode_vba.h" 61 #include "dcn20_dccg.h" 62 #include "dcn20_vmid.h" 63 #include "dc_link_ddc.h" 64 #include "dce/dce_panel_cntl.h" 65 66 #include "navi10_ip_offset.h" 67 68 #include "dcn/dcn_2_0_0_offset.h" 69 #include "dcn/dcn_2_0_0_sh_mask.h" 70 #include "dpcs/dpcs_2_0_0_offset.h" 71 #include "dpcs/dpcs_2_0_0_sh_mask.h" 72 73 #include "nbio/nbio_2_3_offset.h" 74 75 #include "dcn20/dcn20_dwb.h" 76 #include "dcn20/dcn20_mmhubbub.h" 77 78 #include "mmhub/mmhub_2_0_0_offset.h" 79 #include "mmhub/mmhub_2_0_0_sh_mask.h" 80 81 #include "reg_helper.h" 82 #include "dce/dce_abm.h" 83 #include "dce/dce_dmcu.h" 84 #include "dce/dce_aux.h" 85 #include "dce/dce_i2c.h" 86 #include "vm_helper.h" 87 88 #include "amdgpu_socbb.h" 89 90 #define DC_LOGGER_INIT(logger) 91 92 struct _vcs_dpi_ip_params_st dcn2_0_ip = { 93 .odm_capable = 1, 94 .gpuvm_enable = 0, 95 .hostvm_enable = 0, 96 .gpuvm_max_page_table_levels = 4, 97 .hostvm_max_page_table_levels = 4, 98 .hostvm_cached_page_table_levels = 0, 99 .pte_group_size_bytes = 2048, 100 .num_dsc = 6, 101 .rob_buffer_size_kbytes = 168, 102 .det_buffer_size_kbytes = 164, 103 .dpte_buffer_size_in_pte_reqs_luma = 84, 104 .pde_proc_buffer_size_64k_reqs = 48, 105 .dpp_output_buffer_pixels = 2560, 106 .opp_output_buffer_lines = 1, 107 .pixel_chunk_size_kbytes = 8, 108 .pte_chunk_size_kbytes = 2, 109 .meta_chunk_size_kbytes = 2, 110 .writeback_chunk_size_kbytes = 2, 111 .line_buffer_size_bits = 789504, 112 .is_line_buffer_bpp_fixed = 0, 113 .line_buffer_fixed_bpp = 0, 114 .dcc_supported = true, 115 .max_line_buffer_lines = 12, 116 .writeback_luma_buffer_size_kbytes = 12, 117 .writeback_chroma_buffer_size_kbytes = 8, 118 .writeback_chroma_line_buffer_width_pixels = 4, 119 .writeback_max_hscl_ratio = 1, 120 .writeback_max_vscl_ratio = 1, 121 .writeback_min_hscl_ratio = 1, 122 .writeback_min_vscl_ratio = 1, 123 .writeback_max_hscl_taps = 12, 124 .writeback_max_vscl_taps = 12, 125 .writeback_line_buffer_luma_buffer_size = 0, 126 .writeback_line_buffer_chroma_buffer_size = 14643, 127 .cursor_buffer_size = 8, 128 .cursor_chunk_size = 2, 129 .max_num_otg = 6, 130 .max_num_dpp = 6, 131 .max_num_wb = 1, 132 .max_dchub_pscl_bw_pix_per_clk = 4, 133 .max_pscl_lb_bw_pix_per_clk = 2, 134 .max_lb_vscl_bw_pix_per_clk = 4, 135 .max_vscl_hscl_bw_pix_per_clk = 4, 136 .max_hscl_ratio = 8, 137 .max_vscl_ratio = 8, 138 .hscl_mults = 4, 139 .vscl_mults = 4, 140 .max_hscl_taps = 8, 141 .max_vscl_taps = 8, 142 .dispclk_ramp_margin_percent = 1, 143 .underscan_factor = 1.10, 144 .min_vblank_lines = 32, // 145 .dppclk_delay_subtotal = 77, // 146 .dppclk_delay_scl_lb_only = 16, 147 .dppclk_delay_scl = 50, 148 .dppclk_delay_cnvc_formatter = 8, 149 .dppclk_delay_cnvc_cursor = 6, 150 .dispclk_delay_subtotal = 87, // 151 .dcfclk_cstate_latency = 10, // SRExitTime 152 .max_inter_dcn_tile_repeaters = 8, 153 154 .xfc_supported = true, 155 .xfc_fill_bw_overhead_percent = 10.0, 156 .xfc_fill_constant_bytes = 0, 157 .number_of_cursors = 1, 158 }; 159 160 struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = { 161 .odm_capable = 1, 162 .gpuvm_enable = 0, 163 .hostvm_enable = 0, 164 .gpuvm_max_page_table_levels = 4, 165 .hostvm_max_page_table_levels = 4, 166 .hostvm_cached_page_table_levels = 0, 167 .num_dsc = 5, 168 .rob_buffer_size_kbytes = 168, 169 .det_buffer_size_kbytes = 164, 170 .dpte_buffer_size_in_pte_reqs_luma = 84, 171 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo 172 .dpp_output_buffer_pixels = 2560, 173 .opp_output_buffer_lines = 1, 174 .pixel_chunk_size_kbytes = 8, 175 .pte_enable = 1, 176 .max_page_table_levels = 4, 177 .pte_chunk_size_kbytes = 2, 178 .meta_chunk_size_kbytes = 2, 179 .writeback_chunk_size_kbytes = 2, 180 .line_buffer_size_bits = 789504, 181 .is_line_buffer_bpp_fixed = 0, 182 .line_buffer_fixed_bpp = 0, 183 .dcc_supported = true, 184 .max_line_buffer_lines = 12, 185 .writeback_luma_buffer_size_kbytes = 12, 186 .writeback_chroma_buffer_size_kbytes = 8, 187 .writeback_chroma_line_buffer_width_pixels = 4, 188 .writeback_max_hscl_ratio = 1, 189 .writeback_max_vscl_ratio = 1, 190 .writeback_min_hscl_ratio = 1, 191 .writeback_min_vscl_ratio = 1, 192 .writeback_max_hscl_taps = 12, 193 .writeback_max_vscl_taps = 12, 194 .writeback_line_buffer_luma_buffer_size = 0, 195 .writeback_line_buffer_chroma_buffer_size = 14643, 196 .cursor_buffer_size = 8, 197 .cursor_chunk_size = 2, 198 .max_num_otg = 5, 199 .max_num_dpp = 5, 200 .max_num_wb = 1, 201 .max_dchub_pscl_bw_pix_per_clk = 4, 202 .max_pscl_lb_bw_pix_per_clk = 2, 203 .max_lb_vscl_bw_pix_per_clk = 4, 204 .max_vscl_hscl_bw_pix_per_clk = 4, 205 .max_hscl_ratio = 8, 206 .max_vscl_ratio = 8, 207 .hscl_mults = 4, 208 .vscl_mults = 4, 209 .max_hscl_taps = 8, 210 .max_vscl_taps = 8, 211 .dispclk_ramp_margin_percent = 1, 212 .underscan_factor = 1.10, 213 .min_vblank_lines = 32, // 214 .dppclk_delay_subtotal = 77, // 215 .dppclk_delay_scl_lb_only = 16, 216 .dppclk_delay_scl = 50, 217 .dppclk_delay_cnvc_formatter = 8, 218 .dppclk_delay_cnvc_cursor = 6, 219 .dispclk_delay_subtotal = 87, // 220 .dcfclk_cstate_latency = 10, // SRExitTime 221 .max_inter_dcn_tile_repeaters = 8, 222 .xfc_supported = true, 223 .xfc_fill_bw_overhead_percent = 10.0, 224 .xfc_fill_constant_bytes = 0, 225 .ptoi_supported = 0, 226 .number_of_cursors = 1, 227 }; 228 229 struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { 230 /* Defaults that get patched on driver load from firmware. */ 231 .clock_limits = { 232 { 233 .state = 0, 234 .dcfclk_mhz = 560.0, 235 .fabricclk_mhz = 560.0, 236 .dispclk_mhz = 513.0, 237 .dppclk_mhz = 513.0, 238 .phyclk_mhz = 540.0, 239 .socclk_mhz = 560.0, 240 .dscclk_mhz = 171.0, 241 .dram_speed_mts = 8960.0, 242 }, 243 { 244 .state = 1, 245 .dcfclk_mhz = 694.0, 246 .fabricclk_mhz = 694.0, 247 .dispclk_mhz = 642.0, 248 .dppclk_mhz = 642.0, 249 .phyclk_mhz = 600.0, 250 .socclk_mhz = 694.0, 251 .dscclk_mhz = 214.0, 252 .dram_speed_mts = 11104.0, 253 }, 254 { 255 .state = 2, 256 .dcfclk_mhz = 875.0, 257 .fabricclk_mhz = 875.0, 258 .dispclk_mhz = 734.0, 259 .dppclk_mhz = 734.0, 260 .phyclk_mhz = 810.0, 261 .socclk_mhz = 875.0, 262 .dscclk_mhz = 245.0, 263 .dram_speed_mts = 14000.0, 264 }, 265 { 266 .state = 3, 267 .dcfclk_mhz = 1000.0, 268 .fabricclk_mhz = 1000.0, 269 .dispclk_mhz = 1100.0, 270 .dppclk_mhz = 1100.0, 271 .phyclk_mhz = 810.0, 272 .socclk_mhz = 1000.0, 273 .dscclk_mhz = 367.0, 274 .dram_speed_mts = 16000.0, 275 }, 276 { 277 .state = 4, 278 .dcfclk_mhz = 1200.0, 279 .fabricclk_mhz = 1200.0, 280 .dispclk_mhz = 1284.0, 281 .dppclk_mhz = 1284.0, 282 .phyclk_mhz = 810.0, 283 .socclk_mhz = 1200.0, 284 .dscclk_mhz = 428.0, 285 .dram_speed_mts = 16000.0, 286 }, 287 /*Extra state, no dispclk ramping*/ 288 { 289 .state = 5, 290 .dcfclk_mhz = 1200.0, 291 .fabricclk_mhz = 1200.0, 292 .dispclk_mhz = 1284.0, 293 .dppclk_mhz = 1284.0, 294 .phyclk_mhz = 810.0, 295 .socclk_mhz = 1200.0, 296 .dscclk_mhz = 428.0, 297 .dram_speed_mts = 16000.0, 298 }, 299 }, 300 .num_states = 5, 301 .sr_exit_time_us = 8.6, 302 .sr_enter_plus_exit_time_us = 10.9, 303 .urgent_latency_us = 4.0, 304 .urgent_latency_pixel_data_only_us = 4.0, 305 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 306 .urgent_latency_vm_data_only_us = 4.0, 307 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 308 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 309 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 310 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0, 311 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0, 312 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 313 .max_avg_sdp_bw_use_normal_percent = 40.0, 314 .max_avg_dram_bw_use_normal_percent = 40.0, 315 .writeback_latency_us = 12.0, 316 .ideal_dram_bw_after_urgent_percent = 40.0, 317 .max_request_size_bytes = 256, 318 .dram_channel_width_bytes = 2, 319 .fabric_datapath_to_dcn_data_return_bytes = 64, 320 .dcn_downspread_percent = 0.5, 321 .downspread_percent = 0.38, 322 .dram_page_open_time_ns = 50.0, 323 .dram_rw_turnaround_time_ns = 17.5, 324 .dram_return_buffer_per_channel_bytes = 8192, 325 .round_trip_ping_latency_dcfclk_cycles = 131, 326 .urgent_out_of_order_return_per_channel_bytes = 256, 327 .channel_interleave_bytes = 256, 328 .num_banks = 8, 329 .num_chans = 16, 330 .vmm_page_size_bytes = 4096, 331 .dram_clock_change_latency_us = 404.0, 332 .dummy_pstate_latency_us = 5.0, 333 .writeback_dram_clock_change_latency_us = 23.0, 334 .return_bus_width_bytes = 64, 335 .dispclk_dppclk_vco_speed_mhz = 3850, 336 .xfc_bus_transport_time_us = 20, 337 .xfc_xbuf_latency_tolerance_us = 4, 338 .use_urgent_burst_bw = 0 339 }; 340 341 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = { 342 .clock_limits = { 343 { 344 .state = 0, 345 .dcfclk_mhz = 560.0, 346 .fabricclk_mhz = 560.0, 347 .dispclk_mhz = 513.0, 348 .dppclk_mhz = 513.0, 349 .phyclk_mhz = 540.0, 350 .socclk_mhz = 560.0, 351 .dscclk_mhz = 171.0, 352 .dram_speed_mts = 8960.0, 353 }, 354 { 355 .state = 1, 356 .dcfclk_mhz = 694.0, 357 .fabricclk_mhz = 694.0, 358 .dispclk_mhz = 642.0, 359 .dppclk_mhz = 642.0, 360 .phyclk_mhz = 600.0, 361 .socclk_mhz = 694.0, 362 .dscclk_mhz = 214.0, 363 .dram_speed_mts = 11104.0, 364 }, 365 { 366 .state = 2, 367 .dcfclk_mhz = 875.0, 368 .fabricclk_mhz = 875.0, 369 .dispclk_mhz = 734.0, 370 .dppclk_mhz = 734.0, 371 .phyclk_mhz = 810.0, 372 .socclk_mhz = 875.0, 373 .dscclk_mhz = 245.0, 374 .dram_speed_mts = 14000.0, 375 }, 376 { 377 .state = 3, 378 .dcfclk_mhz = 1000.0, 379 .fabricclk_mhz = 1000.0, 380 .dispclk_mhz = 1100.0, 381 .dppclk_mhz = 1100.0, 382 .phyclk_mhz = 810.0, 383 .socclk_mhz = 1000.0, 384 .dscclk_mhz = 367.0, 385 .dram_speed_mts = 16000.0, 386 }, 387 { 388 .state = 4, 389 .dcfclk_mhz = 1200.0, 390 .fabricclk_mhz = 1200.0, 391 .dispclk_mhz = 1284.0, 392 .dppclk_mhz = 1284.0, 393 .phyclk_mhz = 810.0, 394 .socclk_mhz = 1200.0, 395 .dscclk_mhz = 428.0, 396 .dram_speed_mts = 16000.0, 397 }, 398 /*Extra state, no dispclk ramping*/ 399 { 400 .state = 5, 401 .dcfclk_mhz = 1200.0, 402 .fabricclk_mhz = 1200.0, 403 .dispclk_mhz = 1284.0, 404 .dppclk_mhz = 1284.0, 405 .phyclk_mhz = 810.0, 406 .socclk_mhz = 1200.0, 407 .dscclk_mhz = 428.0, 408 .dram_speed_mts = 16000.0, 409 }, 410 }, 411 .num_states = 5, 412 .sr_exit_time_us = 8.6, 413 .sr_enter_plus_exit_time_us = 10.9, 414 .urgent_latency_us = 4.0, 415 .urgent_latency_pixel_data_only_us = 4.0, 416 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 417 .urgent_latency_vm_data_only_us = 4.0, 418 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 419 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 420 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 421 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0, 422 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0, 423 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 424 .max_avg_sdp_bw_use_normal_percent = 40.0, 425 .max_avg_dram_bw_use_normal_percent = 40.0, 426 .writeback_latency_us = 12.0, 427 .ideal_dram_bw_after_urgent_percent = 40.0, 428 .max_request_size_bytes = 256, 429 .dram_channel_width_bytes = 2, 430 .fabric_datapath_to_dcn_data_return_bytes = 64, 431 .dcn_downspread_percent = 0.5, 432 .downspread_percent = 0.38, 433 .dram_page_open_time_ns = 50.0, 434 .dram_rw_turnaround_time_ns = 17.5, 435 .dram_return_buffer_per_channel_bytes = 8192, 436 .round_trip_ping_latency_dcfclk_cycles = 131, 437 .urgent_out_of_order_return_per_channel_bytes = 256, 438 .channel_interleave_bytes = 256, 439 .num_banks = 8, 440 .num_chans = 8, 441 .vmm_page_size_bytes = 4096, 442 .dram_clock_change_latency_us = 404.0, 443 .dummy_pstate_latency_us = 5.0, 444 .writeback_dram_clock_change_latency_us = 23.0, 445 .return_bus_width_bytes = 64, 446 .dispclk_dppclk_vco_speed_mhz = 3850, 447 .xfc_bus_transport_time_us = 20, 448 .xfc_xbuf_latency_tolerance_us = 4, 449 .use_urgent_burst_bw = 0 450 }; 451 452 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 }; 453 454 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 455 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 456 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 457 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 458 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 459 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 460 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 461 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 462 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 463 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 464 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 465 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 466 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 467 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 468 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 469 #endif 470 471 472 enum dcn20_clk_src_array_id { 473 DCN20_CLK_SRC_PLL0, 474 DCN20_CLK_SRC_PLL1, 475 DCN20_CLK_SRC_PLL2, 476 DCN20_CLK_SRC_PLL3, 477 DCN20_CLK_SRC_PLL4, 478 DCN20_CLK_SRC_PLL5, 479 DCN20_CLK_SRC_TOTAL 480 }; 481 482 /* begin ********************* 483 * macros to expend register list macro defined in HW object header file */ 484 485 /* DCN */ 486 /* TODO awful hack. fixup dcn20_dwb.h */ 487 #undef BASE_INNER 488 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 489 490 #define BASE(seg) BASE_INNER(seg) 491 492 #define SR(reg_name)\ 493 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 494 mm ## reg_name 495 496 #define SRI(reg_name, block, id)\ 497 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 498 mm ## block ## id ## _ ## reg_name 499 500 #define SRIR(var_name, reg_name, block, id)\ 501 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 502 mm ## block ## id ## _ ## reg_name 503 504 #define SRII(reg_name, block, id)\ 505 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 506 mm ## block ## id ## _ ## reg_name 507 508 #define DCCG_SRII(reg_name, block, id)\ 509 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 510 mm ## block ## id ## _ ## reg_name 511 512 #define VUPDATE_SRII(reg_name, block, id)\ 513 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 514 mm ## reg_name ## _ ## block ## id 515 516 /* NBIO */ 517 #define NBIO_BASE_INNER(seg) \ 518 NBIO_BASE__INST0_SEG ## seg 519 520 #define NBIO_BASE(seg) \ 521 NBIO_BASE_INNER(seg) 522 523 #define NBIO_SR(reg_name)\ 524 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 525 mm ## reg_name 526 527 /* MMHUB */ 528 #define MMHUB_BASE_INNER(seg) \ 529 MMHUB_BASE__INST0_SEG ## seg 530 531 #define MMHUB_BASE(seg) \ 532 MMHUB_BASE_INNER(seg) 533 534 #define MMHUB_SR(reg_name)\ 535 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 536 mmMM ## reg_name 537 538 static const struct bios_registers bios_regs = { 539 NBIO_SR(BIOS_SCRATCH_3), 540 NBIO_SR(BIOS_SCRATCH_6) 541 }; 542 543 #define clk_src_regs(index, pllid)\ 544 [index] = {\ 545 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\ 546 } 547 548 static const struct dce110_clk_src_regs clk_src_regs[] = { 549 clk_src_regs(0, A), 550 clk_src_regs(1, B), 551 clk_src_regs(2, C), 552 clk_src_regs(3, D), 553 clk_src_regs(4, E), 554 clk_src_regs(5, F) 555 }; 556 557 static const struct dce110_clk_src_shift cs_shift = { 558 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 559 }; 560 561 static const struct dce110_clk_src_mask cs_mask = { 562 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 563 }; 564 565 static const struct dce_dmcu_registers dmcu_regs = { 566 DMCU_DCN10_REG_LIST() 567 }; 568 569 static const struct dce_dmcu_shift dmcu_shift = { 570 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 571 }; 572 573 static const struct dce_dmcu_mask dmcu_mask = { 574 DMCU_MASK_SH_LIST_DCN10(_MASK) 575 }; 576 577 static const struct dce_abm_registers abm_regs = { 578 ABM_DCN20_REG_LIST() 579 }; 580 581 static const struct dce_abm_shift abm_shift = { 582 ABM_MASK_SH_LIST_DCN20(__SHIFT) 583 }; 584 585 static const struct dce_abm_mask abm_mask = { 586 ABM_MASK_SH_LIST_DCN20(_MASK) 587 }; 588 589 #define audio_regs(id)\ 590 [id] = {\ 591 AUD_COMMON_REG_LIST(id)\ 592 } 593 594 static const struct dce_audio_registers audio_regs[] = { 595 audio_regs(0), 596 audio_regs(1), 597 audio_regs(2), 598 audio_regs(3), 599 audio_regs(4), 600 audio_regs(5), 601 audio_regs(6), 602 }; 603 604 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 605 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 606 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 607 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 608 609 static const struct dce_audio_shift audio_shift = { 610 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 611 }; 612 613 static const struct dce_audio_mask audio_mask = { 614 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 615 }; 616 617 #define stream_enc_regs(id)\ 618 [id] = {\ 619 SE_DCN2_REG_LIST(id)\ 620 } 621 622 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 623 stream_enc_regs(0), 624 stream_enc_regs(1), 625 stream_enc_regs(2), 626 stream_enc_regs(3), 627 stream_enc_regs(4), 628 stream_enc_regs(5), 629 }; 630 631 static const struct dcn10_stream_encoder_shift se_shift = { 632 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) 633 }; 634 635 static const struct dcn10_stream_encoder_mask se_mask = { 636 SE_COMMON_MASK_SH_LIST_DCN20(_MASK) 637 }; 638 639 640 #define aux_regs(id)\ 641 [id] = {\ 642 DCN2_AUX_REG_LIST(id)\ 643 } 644 645 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 646 aux_regs(0), 647 aux_regs(1), 648 aux_regs(2), 649 aux_regs(3), 650 aux_regs(4), 651 aux_regs(5) 652 }; 653 654 #define hpd_regs(id)\ 655 [id] = {\ 656 HPD_REG_LIST(id)\ 657 } 658 659 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 660 hpd_regs(0), 661 hpd_regs(1), 662 hpd_regs(2), 663 hpd_regs(3), 664 hpd_regs(4), 665 hpd_regs(5) 666 }; 667 668 #define link_regs(id, phyid)\ 669 [id] = {\ 670 LE_DCN10_REG_LIST(id), \ 671 UNIPHY_DCN2_REG_LIST(phyid), \ 672 DPCS_DCN2_REG_LIST(id), \ 673 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 674 } 675 676 static const struct dcn10_link_enc_registers link_enc_regs[] = { 677 link_regs(0, A), 678 link_regs(1, B), 679 link_regs(2, C), 680 link_regs(3, D), 681 link_regs(4, E), 682 link_regs(5, F) 683 }; 684 685 static const struct dcn10_link_enc_shift le_shift = { 686 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\ 687 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 688 }; 689 690 static const struct dcn10_link_enc_mask le_mask = { 691 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\ 692 DPCS_DCN2_MASK_SH_LIST(_MASK) 693 }; 694 695 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 696 { DCN_PANEL_CNTL_REG_LIST() } 697 }; 698 699 static const struct dce_panel_cntl_shift panel_cntl_shift = { 700 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 701 }; 702 703 static const struct dce_panel_cntl_mask panel_cntl_mask = { 704 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 705 }; 706 707 #define ipp_regs(id)\ 708 [id] = {\ 709 IPP_REG_LIST_DCN20(id),\ 710 } 711 712 static const struct dcn10_ipp_registers ipp_regs[] = { 713 ipp_regs(0), 714 ipp_regs(1), 715 ipp_regs(2), 716 ipp_regs(3), 717 ipp_regs(4), 718 ipp_regs(5), 719 }; 720 721 static const struct dcn10_ipp_shift ipp_shift = { 722 IPP_MASK_SH_LIST_DCN20(__SHIFT) 723 }; 724 725 static const struct dcn10_ipp_mask ipp_mask = { 726 IPP_MASK_SH_LIST_DCN20(_MASK), 727 }; 728 729 #define opp_regs(id)\ 730 [id] = {\ 731 OPP_REG_LIST_DCN20(id),\ 732 } 733 734 static const struct dcn20_opp_registers opp_regs[] = { 735 opp_regs(0), 736 opp_regs(1), 737 opp_regs(2), 738 opp_regs(3), 739 opp_regs(4), 740 opp_regs(5), 741 }; 742 743 static const struct dcn20_opp_shift opp_shift = { 744 OPP_MASK_SH_LIST_DCN20(__SHIFT) 745 }; 746 747 static const struct dcn20_opp_mask opp_mask = { 748 OPP_MASK_SH_LIST_DCN20(_MASK) 749 }; 750 751 #define aux_engine_regs(id)\ 752 [id] = {\ 753 AUX_COMMON_REG_LIST0(id), \ 754 .AUXN_IMPCAL = 0, \ 755 .AUXP_IMPCAL = 0, \ 756 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 757 } 758 759 static const struct dce110_aux_registers aux_engine_regs[] = { 760 aux_engine_regs(0), 761 aux_engine_regs(1), 762 aux_engine_regs(2), 763 aux_engine_regs(3), 764 aux_engine_regs(4), 765 aux_engine_regs(5) 766 }; 767 768 #define tf_regs(id)\ 769 [id] = {\ 770 TF_REG_LIST_DCN20(id),\ 771 TF_REG_LIST_DCN20_COMMON_APPEND(id),\ 772 } 773 774 static const struct dcn2_dpp_registers tf_regs[] = { 775 tf_regs(0), 776 tf_regs(1), 777 tf_regs(2), 778 tf_regs(3), 779 tf_regs(4), 780 tf_regs(5), 781 }; 782 783 static const struct dcn2_dpp_shift tf_shift = { 784 TF_REG_LIST_SH_MASK_DCN20(__SHIFT), 785 TF_DEBUG_REG_LIST_SH_DCN20 786 }; 787 788 static const struct dcn2_dpp_mask tf_mask = { 789 TF_REG_LIST_SH_MASK_DCN20(_MASK), 790 TF_DEBUG_REG_LIST_MASK_DCN20 791 }; 792 793 #define dwbc_regs_dcn2(id)\ 794 [id] = {\ 795 DWBC_COMMON_REG_LIST_DCN2_0(id),\ 796 } 797 798 static const struct dcn20_dwbc_registers dwbc20_regs[] = { 799 dwbc_regs_dcn2(0), 800 }; 801 802 static const struct dcn20_dwbc_shift dwbc20_shift = { 803 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 804 }; 805 806 static const struct dcn20_dwbc_mask dwbc20_mask = { 807 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 808 }; 809 810 #define mcif_wb_regs_dcn2(id)\ 811 [id] = {\ 812 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\ 813 } 814 815 static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = { 816 mcif_wb_regs_dcn2(0), 817 }; 818 819 static const struct dcn20_mmhubbub_shift mcif_wb20_shift = { 820 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 821 }; 822 823 static const struct dcn20_mmhubbub_mask mcif_wb20_mask = { 824 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 825 }; 826 827 static const struct dcn20_mpc_registers mpc_regs = { 828 MPC_REG_LIST_DCN2_0(0), 829 MPC_REG_LIST_DCN2_0(1), 830 MPC_REG_LIST_DCN2_0(2), 831 MPC_REG_LIST_DCN2_0(3), 832 MPC_REG_LIST_DCN2_0(4), 833 MPC_REG_LIST_DCN2_0(5), 834 MPC_OUT_MUX_REG_LIST_DCN2_0(0), 835 MPC_OUT_MUX_REG_LIST_DCN2_0(1), 836 MPC_OUT_MUX_REG_LIST_DCN2_0(2), 837 MPC_OUT_MUX_REG_LIST_DCN2_0(3), 838 MPC_OUT_MUX_REG_LIST_DCN2_0(4), 839 MPC_OUT_MUX_REG_LIST_DCN2_0(5), 840 MPC_DBG_REG_LIST_DCN2_0() 841 }; 842 843 static const struct dcn20_mpc_shift mpc_shift = { 844 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT), 845 MPC_DEBUG_REG_LIST_SH_DCN20 846 }; 847 848 static const struct dcn20_mpc_mask mpc_mask = { 849 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK), 850 MPC_DEBUG_REG_LIST_MASK_DCN20 851 }; 852 853 #define tg_regs(id)\ 854 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)} 855 856 857 static const struct dcn_optc_registers tg_regs[] = { 858 tg_regs(0), 859 tg_regs(1), 860 tg_regs(2), 861 tg_regs(3), 862 tg_regs(4), 863 tg_regs(5) 864 }; 865 866 static const struct dcn_optc_shift tg_shift = { 867 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 868 }; 869 870 static const struct dcn_optc_mask tg_mask = { 871 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 872 }; 873 874 #define hubp_regs(id)\ 875 [id] = {\ 876 HUBP_REG_LIST_DCN20(id)\ 877 } 878 879 static const struct dcn_hubp2_registers hubp_regs[] = { 880 hubp_regs(0), 881 hubp_regs(1), 882 hubp_regs(2), 883 hubp_regs(3), 884 hubp_regs(4), 885 hubp_regs(5) 886 }; 887 888 static const struct dcn_hubp2_shift hubp_shift = { 889 HUBP_MASK_SH_LIST_DCN20(__SHIFT) 890 }; 891 892 static const struct dcn_hubp2_mask hubp_mask = { 893 HUBP_MASK_SH_LIST_DCN20(_MASK) 894 }; 895 896 static const struct dcn_hubbub_registers hubbub_reg = { 897 HUBBUB_REG_LIST_DCN20(0) 898 }; 899 900 static const struct dcn_hubbub_shift hubbub_shift = { 901 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT) 902 }; 903 904 static const struct dcn_hubbub_mask hubbub_mask = { 905 HUBBUB_MASK_SH_LIST_DCN20(_MASK) 906 }; 907 908 #define vmid_regs(id)\ 909 [id] = {\ 910 DCN20_VMID_REG_LIST(id)\ 911 } 912 913 static const struct dcn_vmid_registers vmid_regs[] = { 914 vmid_regs(0), 915 vmid_regs(1), 916 vmid_regs(2), 917 vmid_regs(3), 918 vmid_regs(4), 919 vmid_regs(5), 920 vmid_regs(6), 921 vmid_regs(7), 922 vmid_regs(8), 923 vmid_regs(9), 924 vmid_regs(10), 925 vmid_regs(11), 926 vmid_regs(12), 927 vmid_regs(13), 928 vmid_regs(14), 929 vmid_regs(15) 930 }; 931 932 static const struct dcn20_vmid_shift vmid_shifts = { 933 DCN20_VMID_MASK_SH_LIST(__SHIFT) 934 }; 935 936 static const struct dcn20_vmid_mask vmid_masks = { 937 DCN20_VMID_MASK_SH_LIST(_MASK) 938 }; 939 940 static const struct dce110_aux_registers_shift aux_shift = { 941 DCN_AUX_MASK_SH_LIST(__SHIFT) 942 }; 943 944 static const struct dce110_aux_registers_mask aux_mask = { 945 DCN_AUX_MASK_SH_LIST(_MASK) 946 }; 947 948 static int map_transmitter_id_to_phy_instance( 949 enum transmitter transmitter) 950 { 951 switch (transmitter) { 952 case TRANSMITTER_UNIPHY_A: 953 return 0; 954 break; 955 case TRANSMITTER_UNIPHY_B: 956 return 1; 957 break; 958 case TRANSMITTER_UNIPHY_C: 959 return 2; 960 break; 961 case TRANSMITTER_UNIPHY_D: 962 return 3; 963 break; 964 case TRANSMITTER_UNIPHY_E: 965 return 4; 966 break; 967 case TRANSMITTER_UNIPHY_F: 968 return 5; 969 break; 970 default: 971 ASSERT(0); 972 return 0; 973 } 974 } 975 976 #define dsc_regsDCN20(id)\ 977 [id] = {\ 978 DSC_REG_LIST_DCN20(id)\ 979 } 980 981 static const struct dcn20_dsc_registers dsc_regs[] = { 982 dsc_regsDCN20(0), 983 dsc_regsDCN20(1), 984 dsc_regsDCN20(2), 985 dsc_regsDCN20(3), 986 dsc_regsDCN20(4), 987 dsc_regsDCN20(5) 988 }; 989 990 static const struct dcn20_dsc_shift dsc_shift = { 991 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 992 }; 993 994 static const struct dcn20_dsc_mask dsc_mask = { 995 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 996 }; 997 998 static const struct dccg_registers dccg_regs = { 999 DCCG_REG_LIST_DCN2() 1000 }; 1001 1002 static const struct dccg_shift dccg_shift = { 1003 DCCG_MASK_SH_LIST_DCN2(__SHIFT) 1004 }; 1005 1006 static const struct dccg_mask dccg_mask = { 1007 DCCG_MASK_SH_LIST_DCN2(_MASK) 1008 }; 1009 1010 static const struct resource_caps res_cap_nv10 = { 1011 .num_timing_generator = 6, 1012 .num_opp = 6, 1013 .num_video_plane = 6, 1014 .num_audio = 7, 1015 .num_stream_encoder = 6, 1016 .num_pll = 6, 1017 .num_dwb = 1, 1018 .num_ddc = 6, 1019 .num_vmid = 16, 1020 .num_dsc = 6, 1021 }; 1022 1023 static const struct dc_plane_cap plane_cap = { 1024 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 1025 .blends_with_above = true, 1026 .blends_with_below = true, 1027 .per_pixel_alpha = true, 1028 1029 .pixel_format_support = { 1030 .argb8888 = true, 1031 .nv12 = true, 1032 .fp16 = true, 1033 .p010 = true 1034 }, 1035 1036 .max_upscale_factor = { 1037 .argb8888 = 16000, 1038 .nv12 = 16000, 1039 .fp16 = 1 1040 }, 1041 1042 .max_downscale_factor = { 1043 .argb8888 = 250, 1044 .nv12 = 250, 1045 .fp16 = 1 1046 } 1047 }; 1048 static const struct resource_caps res_cap_nv14 = { 1049 .num_timing_generator = 5, 1050 .num_opp = 5, 1051 .num_video_plane = 5, 1052 .num_audio = 6, 1053 .num_stream_encoder = 5, 1054 .num_pll = 5, 1055 .num_dwb = 1, 1056 .num_ddc = 5, 1057 .num_vmid = 16, 1058 .num_dsc = 5, 1059 }; 1060 1061 static const struct dc_debug_options debug_defaults_drv = { 1062 .disable_dmcu = false, 1063 .force_abm_enable = false, 1064 .timing_trace = false, 1065 .clock_trace = true, 1066 .disable_pplib_clock_request = true, 1067 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 1068 .force_single_disp_pipe_split = false, 1069 .disable_dcc = DCC_ENABLE, 1070 .vsr_support = true, 1071 .performance_trace = false, 1072 .max_downscale_src_width = 5120,/*upto 5K*/ 1073 .disable_pplib_wm_range = false, 1074 .scl_reset_length10 = true, 1075 .sanity_checks = false, 1076 .disable_tri_buf = true, 1077 .underflow_assert_delay_us = 0xFFFFFFFF, 1078 }; 1079 1080 static const struct dc_debug_options debug_defaults_diags = { 1081 .disable_dmcu = false, 1082 .force_abm_enable = false, 1083 .timing_trace = true, 1084 .clock_trace = true, 1085 .disable_dpp_power_gate = true, 1086 .disable_hubp_power_gate = true, 1087 .disable_clock_gate = true, 1088 .disable_pplib_clock_request = true, 1089 .disable_pplib_wm_range = true, 1090 .disable_stutter = true, 1091 .scl_reset_length10 = true, 1092 .underflow_assert_delay_us = 0xFFFFFFFF, 1093 }; 1094 1095 void dcn20_dpp_destroy(struct dpp **dpp) 1096 { 1097 kfree(TO_DCN20_DPP(*dpp)); 1098 *dpp = NULL; 1099 } 1100 1101 struct dpp *dcn20_dpp_create( 1102 struct dc_context *ctx, 1103 uint32_t inst) 1104 { 1105 struct dcn20_dpp *dpp = 1106 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL); 1107 1108 if (!dpp) 1109 return NULL; 1110 1111 if (dpp2_construct(dpp, ctx, inst, 1112 &tf_regs[inst], &tf_shift, &tf_mask)) 1113 return &dpp->base; 1114 1115 BREAK_TO_DEBUGGER(); 1116 kfree(dpp); 1117 return NULL; 1118 } 1119 1120 struct input_pixel_processor *dcn20_ipp_create( 1121 struct dc_context *ctx, uint32_t inst) 1122 { 1123 struct dcn10_ipp *ipp = 1124 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 1125 1126 if (!ipp) { 1127 BREAK_TO_DEBUGGER(); 1128 return NULL; 1129 } 1130 1131 dcn20_ipp_construct(ipp, ctx, inst, 1132 &ipp_regs[inst], &ipp_shift, &ipp_mask); 1133 return &ipp->base; 1134 } 1135 1136 1137 struct output_pixel_processor *dcn20_opp_create( 1138 struct dc_context *ctx, uint32_t inst) 1139 { 1140 struct dcn20_opp *opp = 1141 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1142 1143 if (!opp) { 1144 BREAK_TO_DEBUGGER(); 1145 return NULL; 1146 } 1147 1148 dcn20_opp_construct(opp, ctx, inst, 1149 &opp_regs[inst], &opp_shift, &opp_mask); 1150 return &opp->base; 1151 } 1152 1153 struct dce_aux *dcn20_aux_engine_create( 1154 struct dc_context *ctx, 1155 uint32_t inst) 1156 { 1157 struct aux_engine_dce110 *aux_engine = 1158 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 1159 1160 if (!aux_engine) 1161 return NULL; 1162 1163 dce110_aux_engine_construct(aux_engine, ctx, inst, 1164 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1165 &aux_engine_regs[inst], 1166 &aux_mask, 1167 &aux_shift, 1168 ctx->dc->caps.extended_aux_timeout_support); 1169 1170 return &aux_engine->base; 1171 } 1172 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 1173 1174 static const struct dce_i2c_registers i2c_hw_regs[] = { 1175 i2c_inst_regs(1), 1176 i2c_inst_regs(2), 1177 i2c_inst_regs(3), 1178 i2c_inst_regs(4), 1179 i2c_inst_regs(5), 1180 i2c_inst_regs(6), 1181 }; 1182 1183 static const struct dce_i2c_shift i2c_shifts = { 1184 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 1185 }; 1186 1187 static const struct dce_i2c_mask i2c_masks = { 1188 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 1189 }; 1190 1191 struct dce_i2c_hw *dcn20_i2c_hw_create( 1192 struct dc_context *ctx, 1193 uint32_t inst) 1194 { 1195 struct dce_i2c_hw *dce_i2c_hw = 1196 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1197 1198 if (!dce_i2c_hw) 1199 return NULL; 1200 1201 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1202 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1203 1204 return dce_i2c_hw; 1205 } 1206 struct mpc *dcn20_mpc_create(struct dc_context *ctx) 1207 { 1208 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), 1209 GFP_KERNEL); 1210 1211 if (!mpc20) 1212 return NULL; 1213 1214 dcn20_mpc_construct(mpc20, ctx, 1215 &mpc_regs, 1216 &mpc_shift, 1217 &mpc_mask, 1218 6); 1219 1220 return &mpc20->base; 1221 } 1222 1223 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx) 1224 { 1225 int i; 1226 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), 1227 GFP_KERNEL); 1228 1229 if (!hubbub) 1230 return NULL; 1231 1232 hubbub2_construct(hubbub, ctx, 1233 &hubbub_reg, 1234 &hubbub_shift, 1235 &hubbub_mask); 1236 1237 for (i = 0; i < res_cap_nv10.num_vmid; i++) { 1238 struct dcn20_vmid *vmid = &hubbub->vmid[i]; 1239 1240 vmid->ctx = ctx; 1241 1242 vmid->regs = &vmid_regs[i]; 1243 vmid->shifts = &vmid_shifts; 1244 vmid->masks = &vmid_masks; 1245 } 1246 1247 return &hubbub->base; 1248 } 1249 1250 struct timing_generator *dcn20_timing_generator_create( 1251 struct dc_context *ctx, 1252 uint32_t instance) 1253 { 1254 struct optc *tgn10 = 1255 kzalloc(sizeof(struct optc), GFP_KERNEL); 1256 1257 if (!tgn10) 1258 return NULL; 1259 1260 tgn10->base.inst = instance; 1261 tgn10->base.ctx = ctx; 1262 1263 tgn10->tg_regs = &tg_regs[instance]; 1264 tgn10->tg_shift = &tg_shift; 1265 tgn10->tg_mask = &tg_mask; 1266 1267 dcn20_timing_generator_init(tgn10); 1268 1269 return &tgn10->base; 1270 } 1271 1272 static const struct encoder_feature_support link_enc_feature = { 1273 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1274 .max_hdmi_pixel_clock = 600000, 1275 .hdmi_ycbcr420_supported = true, 1276 .dp_ycbcr420_supported = true, 1277 .fec_supported = true, 1278 .flags.bits.IS_HBR2_CAPABLE = true, 1279 .flags.bits.IS_HBR3_CAPABLE = true, 1280 .flags.bits.IS_TPS3_CAPABLE = true, 1281 .flags.bits.IS_TPS4_CAPABLE = true 1282 }; 1283 1284 struct link_encoder *dcn20_link_encoder_create( 1285 const struct encoder_init_data *enc_init_data) 1286 { 1287 struct dcn20_link_encoder *enc20 = 1288 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1289 int link_regs_id; 1290 1291 if (!enc20) 1292 return NULL; 1293 1294 link_regs_id = 1295 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 1296 1297 dcn20_link_encoder_construct(enc20, 1298 enc_init_data, 1299 &link_enc_feature, 1300 &link_enc_regs[link_regs_id], 1301 &link_enc_aux_regs[enc_init_data->channel - 1], 1302 &link_enc_hpd_regs[enc_init_data->hpd_source], 1303 &le_shift, 1304 &le_mask); 1305 1306 return &enc20->enc10.base; 1307 } 1308 1309 static struct panel_cntl *dcn20_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1310 { 1311 struct dce_panel_cntl *panel_cntl = 1312 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 1313 1314 if (!panel_cntl) 1315 return NULL; 1316 1317 dce_panel_cntl_construct(panel_cntl, 1318 init_data, 1319 &panel_cntl_regs[init_data->inst], 1320 &panel_cntl_shift, 1321 &panel_cntl_mask); 1322 1323 return &panel_cntl->base; 1324 } 1325 1326 struct clock_source *dcn20_clock_source_create( 1327 struct dc_context *ctx, 1328 struct dc_bios *bios, 1329 enum clock_source_id id, 1330 const struct dce110_clk_src_regs *regs, 1331 bool dp_clk_src) 1332 { 1333 struct dce110_clk_src *clk_src = 1334 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1335 1336 if (!clk_src) 1337 return NULL; 1338 1339 if (dcn20_clk_src_construct(clk_src, ctx, bios, id, 1340 regs, &cs_shift, &cs_mask)) { 1341 clk_src->base.dp_clk_src = dp_clk_src; 1342 return &clk_src->base; 1343 } 1344 1345 kfree(clk_src); 1346 BREAK_TO_DEBUGGER(); 1347 return NULL; 1348 } 1349 1350 static void read_dce_straps( 1351 struct dc_context *ctx, 1352 struct resource_straps *straps) 1353 { 1354 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1355 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1356 } 1357 1358 static struct audio *dcn20_create_audio( 1359 struct dc_context *ctx, unsigned int inst) 1360 { 1361 return dce_audio_create(ctx, inst, 1362 &audio_regs[inst], &audio_shift, &audio_mask); 1363 } 1364 1365 struct stream_encoder *dcn20_stream_encoder_create( 1366 enum engine_id eng_id, 1367 struct dc_context *ctx) 1368 { 1369 struct dcn10_stream_encoder *enc1 = 1370 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1371 1372 if (!enc1) 1373 return NULL; 1374 1375 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) { 1376 if (eng_id >= ENGINE_ID_DIGD) 1377 eng_id++; 1378 } 1379 1380 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1381 &stream_enc_regs[eng_id], 1382 &se_shift, &se_mask); 1383 1384 return &enc1->base; 1385 } 1386 1387 static const struct dce_hwseq_registers hwseq_reg = { 1388 HWSEQ_DCN2_REG_LIST() 1389 }; 1390 1391 static const struct dce_hwseq_shift hwseq_shift = { 1392 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT) 1393 }; 1394 1395 static const struct dce_hwseq_mask hwseq_mask = { 1396 HWSEQ_DCN2_MASK_SH_LIST(_MASK) 1397 }; 1398 1399 struct dce_hwseq *dcn20_hwseq_create( 1400 struct dc_context *ctx) 1401 { 1402 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1403 1404 if (hws) { 1405 hws->ctx = ctx; 1406 hws->regs = &hwseq_reg; 1407 hws->shifts = &hwseq_shift; 1408 hws->masks = &hwseq_mask; 1409 } 1410 return hws; 1411 } 1412 1413 static const struct resource_create_funcs res_create_funcs = { 1414 .read_dce_straps = read_dce_straps, 1415 .create_audio = dcn20_create_audio, 1416 .create_stream_encoder = dcn20_stream_encoder_create, 1417 .create_hwseq = dcn20_hwseq_create, 1418 }; 1419 1420 static const struct resource_create_funcs res_create_maximus_funcs = { 1421 .read_dce_straps = NULL, 1422 .create_audio = NULL, 1423 .create_stream_encoder = NULL, 1424 .create_hwseq = dcn20_hwseq_create, 1425 }; 1426 1427 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu); 1428 1429 void dcn20_clock_source_destroy(struct clock_source **clk_src) 1430 { 1431 kfree(TO_DCE110_CLK_SRC(*clk_src)); 1432 *clk_src = NULL; 1433 } 1434 1435 1436 struct display_stream_compressor *dcn20_dsc_create( 1437 struct dc_context *ctx, uint32_t inst) 1438 { 1439 struct dcn20_dsc *dsc = 1440 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1441 1442 if (!dsc) { 1443 BREAK_TO_DEBUGGER(); 1444 return NULL; 1445 } 1446 1447 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1448 return &dsc->base; 1449 } 1450 1451 void dcn20_dsc_destroy(struct display_stream_compressor **dsc) 1452 { 1453 kfree(container_of(*dsc, struct dcn20_dsc, base)); 1454 *dsc = NULL; 1455 } 1456 1457 1458 static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) 1459 { 1460 unsigned int i; 1461 1462 for (i = 0; i < pool->base.stream_enc_count; i++) { 1463 if (pool->base.stream_enc[i] != NULL) { 1464 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1465 pool->base.stream_enc[i] = NULL; 1466 } 1467 } 1468 1469 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1470 if (pool->base.dscs[i] != NULL) 1471 dcn20_dsc_destroy(&pool->base.dscs[i]); 1472 } 1473 1474 if (pool->base.mpc != NULL) { 1475 kfree(TO_DCN20_MPC(pool->base.mpc)); 1476 pool->base.mpc = NULL; 1477 } 1478 if (pool->base.hubbub != NULL) { 1479 kfree(pool->base.hubbub); 1480 pool->base.hubbub = NULL; 1481 } 1482 for (i = 0; i < pool->base.pipe_count; i++) { 1483 if (pool->base.dpps[i] != NULL) 1484 dcn20_dpp_destroy(&pool->base.dpps[i]); 1485 1486 if (pool->base.ipps[i] != NULL) 1487 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1488 1489 if (pool->base.hubps[i] != NULL) { 1490 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1491 pool->base.hubps[i] = NULL; 1492 } 1493 1494 if (pool->base.irqs != NULL) { 1495 dal_irq_service_destroy(&pool->base.irqs); 1496 } 1497 } 1498 1499 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1500 if (pool->base.engines[i] != NULL) 1501 dce110_engine_destroy(&pool->base.engines[i]); 1502 if (pool->base.hw_i2cs[i] != NULL) { 1503 kfree(pool->base.hw_i2cs[i]); 1504 pool->base.hw_i2cs[i] = NULL; 1505 } 1506 if (pool->base.sw_i2cs[i] != NULL) { 1507 kfree(pool->base.sw_i2cs[i]); 1508 pool->base.sw_i2cs[i] = NULL; 1509 } 1510 } 1511 1512 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1513 if (pool->base.opps[i] != NULL) 1514 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1515 } 1516 1517 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1518 if (pool->base.timing_generators[i] != NULL) { 1519 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1520 pool->base.timing_generators[i] = NULL; 1521 } 1522 } 1523 1524 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1525 if (pool->base.dwbc[i] != NULL) { 1526 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); 1527 pool->base.dwbc[i] = NULL; 1528 } 1529 if (pool->base.mcif_wb[i] != NULL) { 1530 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); 1531 pool->base.mcif_wb[i] = NULL; 1532 } 1533 } 1534 1535 for (i = 0; i < pool->base.audio_count; i++) { 1536 if (pool->base.audios[i]) 1537 dce_aud_destroy(&pool->base.audios[i]); 1538 } 1539 1540 for (i = 0; i < pool->base.clk_src_count; i++) { 1541 if (pool->base.clock_sources[i] != NULL) { 1542 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1543 pool->base.clock_sources[i] = NULL; 1544 } 1545 } 1546 1547 if (pool->base.dp_clock_source != NULL) { 1548 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1549 pool->base.dp_clock_source = NULL; 1550 } 1551 1552 1553 if (pool->base.abm != NULL) 1554 dce_abm_destroy(&pool->base.abm); 1555 1556 if (pool->base.dmcu != NULL) 1557 dce_dmcu_destroy(&pool->base.dmcu); 1558 1559 if (pool->base.dccg != NULL) 1560 dcn_dccg_destroy(&pool->base.dccg); 1561 1562 if (pool->base.pp_smu != NULL) 1563 dcn20_pp_smu_destroy(&pool->base.pp_smu); 1564 1565 if (pool->base.oem_device != NULL) 1566 dal_ddc_service_destroy(&pool->base.oem_device); 1567 } 1568 1569 struct hubp *dcn20_hubp_create( 1570 struct dc_context *ctx, 1571 uint32_t inst) 1572 { 1573 struct dcn20_hubp *hubp2 = 1574 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1575 1576 if (!hubp2) 1577 return NULL; 1578 1579 if (hubp2_construct(hubp2, ctx, inst, 1580 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1581 return &hubp2->base; 1582 1583 BREAK_TO_DEBUGGER(); 1584 kfree(hubp2); 1585 return NULL; 1586 } 1587 1588 static void get_pixel_clock_parameters( 1589 struct pipe_ctx *pipe_ctx, 1590 struct pixel_clk_params *pixel_clk_params) 1591 { 1592 const struct dc_stream_state *stream = pipe_ctx->stream; 1593 struct pipe_ctx *odm_pipe; 1594 int opp_cnt = 1; 1595 1596 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1597 opp_cnt++; 1598 1599 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 1600 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 1601 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 1602 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 1603 /* TODO: un-hardcode*/ 1604 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 1605 LINK_RATE_REF_FREQ_IN_KHZ; 1606 pixel_clk_params->flags.ENABLE_SS = 0; 1607 pixel_clk_params->color_depth = 1608 stream->timing.display_color_depth; 1609 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 1610 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 1611 1612 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1613 pixel_clk_params->color_depth = COLOR_DEPTH_888; 1614 1615 if (opp_cnt == 4) 1616 pixel_clk_params->requested_pix_clk_100hz /= 4; 1617 else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2) 1618 pixel_clk_params->requested_pix_clk_100hz /= 2; 1619 1620 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1621 pixel_clk_params->requested_pix_clk_100hz *= 2; 1622 1623 } 1624 1625 static void build_clamping_params(struct dc_stream_state *stream) 1626 { 1627 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1628 stream->clamping.c_depth = stream->timing.display_color_depth; 1629 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1630 } 1631 1632 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1633 { 1634 1635 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1636 1637 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1638 pipe_ctx->clock_source, 1639 &pipe_ctx->stream_res.pix_clk_params, 1640 &pipe_ctx->pll_settings); 1641 1642 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1643 1644 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1645 &pipe_ctx->stream->bit_depth_params); 1646 build_clamping_params(pipe_ctx->stream); 1647 1648 return DC_OK; 1649 } 1650 1651 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream) 1652 { 1653 enum dc_status status = DC_OK; 1654 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1655 1656 if (!pipe_ctx) 1657 return DC_ERROR_UNEXPECTED; 1658 1659 1660 status = build_pipe_hw_param(pipe_ctx); 1661 1662 return status; 1663 } 1664 1665 1666 void dcn20_acquire_dsc(const struct dc *dc, 1667 struct resource_context *res_ctx, 1668 struct display_stream_compressor **dsc, 1669 int pipe_idx) 1670 { 1671 int i; 1672 const struct resource_pool *pool = dc->res_pool; 1673 struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc; 1674 1675 ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */ 1676 *dsc = NULL; 1677 1678 /* Always do 1-to-1 mapping when number of DSCs is same as number of pipes */ 1679 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { 1680 *dsc = pool->dscs[pipe_idx]; 1681 res_ctx->is_dsc_acquired[pipe_idx] = true; 1682 return; 1683 } 1684 1685 /* Return old DSC to avoid the need for re-programming */ 1686 if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) { 1687 *dsc = dsc_old; 1688 res_ctx->is_dsc_acquired[dsc_old->inst] = true; 1689 return ; 1690 } 1691 1692 /* Find first free DSC */ 1693 for (i = 0; i < pool->res_cap->num_dsc; i++) 1694 if (!res_ctx->is_dsc_acquired[i]) { 1695 *dsc = pool->dscs[i]; 1696 res_ctx->is_dsc_acquired[i] = true; 1697 break; 1698 } 1699 } 1700 1701 void dcn20_release_dsc(struct resource_context *res_ctx, 1702 const struct resource_pool *pool, 1703 struct display_stream_compressor **dsc) 1704 { 1705 int i; 1706 1707 for (i = 0; i < pool->res_cap->num_dsc; i++) 1708 if (pool->dscs[i] == *dsc) { 1709 res_ctx->is_dsc_acquired[i] = false; 1710 *dsc = NULL; 1711 break; 1712 } 1713 } 1714 1715 1716 1717 enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, 1718 struct dc_state *dc_ctx, 1719 struct dc_stream_state *dc_stream) 1720 { 1721 enum dc_status result = DC_OK; 1722 int i; 1723 1724 /* Get a DSC if required and available */ 1725 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1726 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i]; 1727 1728 if (pipe_ctx->stream != dc_stream) 1729 continue; 1730 1731 if (pipe_ctx->stream_res.dsc) 1732 continue; 1733 1734 dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i); 1735 1736 /* The number of DSCs can be less than the number of pipes */ 1737 if (!pipe_ctx->stream_res.dsc) { 1738 result = DC_NO_DSC_RESOURCE; 1739 } 1740 1741 break; 1742 } 1743 1744 return result; 1745 } 1746 1747 1748 static enum dc_status remove_dsc_from_stream_resource(struct dc *dc, 1749 struct dc_state *new_ctx, 1750 struct dc_stream_state *dc_stream) 1751 { 1752 struct pipe_ctx *pipe_ctx = NULL; 1753 int i; 1754 1755 for (i = 0; i < MAX_PIPES; i++) { 1756 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { 1757 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; 1758 1759 if (pipe_ctx->stream_res.dsc) 1760 dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); 1761 } 1762 } 1763 1764 if (!pipe_ctx) 1765 return DC_ERROR_UNEXPECTED; 1766 else 1767 return DC_OK; 1768 } 1769 1770 1771 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) 1772 { 1773 enum dc_status result = DC_ERROR_UNEXPECTED; 1774 1775 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1776 1777 if (result == DC_OK) 1778 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1779 1780 /* Get a DSC if required and available */ 1781 if (result == DC_OK && dc_stream->timing.flags.DSC) 1782 result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream); 1783 1784 if (result == DC_OK) 1785 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream); 1786 1787 return result; 1788 } 1789 1790 1791 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) 1792 { 1793 enum dc_status result = DC_OK; 1794 1795 result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream); 1796 1797 return result; 1798 } 1799 1800 1801 static void swizzle_to_dml_params( 1802 enum swizzle_mode_values swizzle, 1803 unsigned int *sw_mode) 1804 { 1805 switch (swizzle) { 1806 case DC_SW_LINEAR: 1807 *sw_mode = dm_sw_linear; 1808 break; 1809 case DC_SW_4KB_S: 1810 *sw_mode = dm_sw_4kb_s; 1811 break; 1812 case DC_SW_4KB_S_X: 1813 *sw_mode = dm_sw_4kb_s_x; 1814 break; 1815 case DC_SW_4KB_D: 1816 *sw_mode = dm_sw_4kb_d; 1817 break; 1818 case DC_SW_4KB_D_X: 1819 *sw_mode = dm_sw_4kb_d_x; 1820 break; 1821 case DC_SW_64KB_S: 1822 *sw_mode = dm_sw_64kb_s; 1823 break; 1824 case DC_SW_64KB_S_X: 1825 *sw_mode = dm_sw_64kb_s_x; 1826 break; 1827 case DC_SW_64KB_S_T: 1828 *sw_mode = dm_sw_64kb_s_t; 1829 break; 1830 case DC_SW_64KB_D: 1831 *sw_mode = dm_sw_64kb_d; 1832 break; 1833 case DC_SW_64KB_D_X: 1834 *sw_mode = dm_sw_64kb_d_x; 1835 break; 1836 case DC_SW_64KB_D_T: 1837 *sw_mode = dm_sw_64kb_d_t; 1838 break; 1839 case DC_SW_64KB_R_X: 1840 *sw_mode = dm_sw_64kb_r_x; 1841 break; 1842 case DC_SW_VAR_S: 1843 *sw_mode = dm_sw_var_s; 1844 break; 1845 case DC_SW_VAR_S_X: 1846 *sw_mode = dm_sw_var_s_x; 1847 break; 1848 case DC_SW_VAR_D: 1849 *sw_mode = dm_sw_var_d; 1850 break; 1851 case DC_SW_VAR_D_X: 1852 *sw_mode = dm_sw_var_d_x; 1853 break; 1854 1855 default: 1856 ASSERT(0); /* Not supported */ 1857 break; 1858 } 1859 } 1860 1861 bool dcn20_split_stream_for_odm( 1862 const struct dc *dc, 1863 struct resource_context *res_ctx, 1864 struct pipe_ctx *prev_odm_pipe, 1865 struct pipe_ctx *next_odm_pipe) 1866 { 1867 int pipe_idx = next_odm_pipe->pipe_idx; 1868 const struct resource_pool *pool = dc->res_pool; 1869 1870 *next_odm_pipe = *prev_odm_pipe; 1871 1872 next_odm_pipe->pipe_idx = pipe_idx; 1873 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; 1874 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; 1875 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; 1876 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; 1877 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; 1878 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; 1879 next_odm_pipe->stream_res.dsc = NULL; 1880 if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) { 1881 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe; 1882 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe; 1883 } 1884 prev_odm_pipe->next_odm_pipe = next_odm_pipe; 1885 next_odm_pipe->prev_odm_pipe = prev_odm_pipe; 1886 ASSERT(next_odm_pipe->top_pipe == NULL); 1887 1888 if (prev_odm_pipe->plane_state) { 1889 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; 1890 int new_width; 1891 1892 /* HACTIVE halved for odm combine */ 1893 sd->h_active /= 2; 1894 /* Calculate new vp and recout for left pipe */ 1895 /* Need at least 16 pixels width per side */ 1896 if (sd->recout.x + 16 >= sd->h_active) 1897 return false; 1898 new_width = sd->h_active - sd->recout.x; 1899 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1900 sd->ratios.horz, sd->recout.width - new_width)); 1901 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1902 sd->ratios.horz_c, sd->recout.width - new_width)); 1903 sd->recout.width = new_width; 1904 1905 /* Calculate new vp and recout for right pipe */ 1906 sd = &next_odm_pipe->plane_res.scl_data; 1907 /* HACTIVE halved for odm combine */ 1908 sd->h_active /= 2; 1909 /* Need at least 16 pixels width per side */ 1910 if (new_width <= 16) 1911 return false; 1912 new_width = sd->recout.width + sd->recout.x - sd->h_active; 1913 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1914 sd->ratios.horz, sd->recout.width - new_width)); 1915 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1916 sd->ratios.horz_c, sd->recout.width - new_width)); 1917 sd->recout.width = new_width; 1918 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int( 1919 sd->ratios.horz, sd->h_active - sd->recout.x)); 1920 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int( 1921 sd->ratios.horz_c, sd->h_active - sd->recout.x)); 1922 sd->recout.x = 0; 1923 } 1924 next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; 1925 if (next_odm_pipe->stream->timing.flags.DSC == 1) { 1926 dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx); 1927 ASSERT(next_odm_pipe->stream_res.dsc); 1928 if (next_odm_pipe->stream_res.dsc == NULL) 1929 return false; 1930 } 1931 1932 return true; 1933 } 1934 1935 void dcn20_split_stream_for_mpc( 1936 struct resource_context *res_ctx, 1937 const struct resource_pool *pool, 1938 struct pipe_ctx *primary_pipe, 1939 struct pipe_ctx *secondary_pipe) 1940 { 1941 int pipe_idx = secondary_pipe->pipe_idx; 1942 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe; 1943 1944 *secondary_pipe = *primary_pipe; 1945 secondary_pipe->bottom_pipe = sec_bot_pipe; 1946 1947 secondary_pipe->pipe_idx = pipe_idx; 1948 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; 1949 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; 1950 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; 1951 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; 1952 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; 1953 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; 1954 secondary_pipe->stream_res.dsc = NULL; 1955 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { 1956 ASSERT(!secondary_pipe->bottom_pipe); 1957 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; 1958 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe; 1959 } 1960 primary_pipe->bottom_pipe = secondary_pipe; 1961 secondary_pipe->top_pipe = primary_pipe; 1962 1963 ASSERT(primary_pipe->plane_state); 1964 } 1965 1966 void dcn20_populate_dml_writeback_from_context( 1967 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) 1968 { 1969 int pipe_cnt, i; 1970 1971 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1972 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; 1973 1974 if (!res_ctx->pipe_ctx[i].stream) 1975 continue; 1976 1977 /* Set writeback information */ 1978 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; 1979 pipes[pipe_cnt].dout.num_active_wb++; 1980 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; 1981 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; 1982 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; 1983 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; 1984 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1; 1985 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1; 1986 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c; 1987 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c; 1988 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0; 1989 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0; 1990 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) { 1991 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) 1992 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8; 1993 else 1994 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10; 1995 } else 1996 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32; 1997 1998 pipe_cnt++; 1999 } 2000 2001 } 2002 2003 int dcn20_populate_dml_pipes_from_context( 2004 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes) 2005 { 2006 int pipe_cnt, i; 2007 bool synchronized_vblank = true; 2008 struct resource_context *res_ctx = &context->res_ctx; 2009 2010 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) { 2011 if (!res_ctx->pipe_ctx[i].stream) 2012 continue; 2013 2014 if (pipe_cnt < 0) { 2015 pipe_cnt = i; 2016 continue; 2017 } 2018 if (dc->debug.disable_timing_sync || !resource_are_streams_timing_synchronizable( 2019 res_ctx->pipe_ctx[pipe_cnt].stream, 2020 res_ctx->pipe_ctx[i].stream)) { 2021 synchronized_vblank = false; 2022 break; 2023 } 2024 } 2025 2026 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 2027 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing; 2028 unsigned int v_total; 2029 unsigned int front_porch; 2030 int output_bpc; 2031 2032 if (!res_ctx->pipe_ctx[i].stream) 2033 continue; 2034 2035 v_total = timing->v_total; 2036 front_porch = timing->v_front_porch; 2037 /* todo: 2038 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0; 2039 pipes[pipe_cnt].pipe.src.dcc = 0; 2040 pipes[pipe_cnt].pipe.src.vm = 0;*/ 2041 2042 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 2043 2044 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC; 2045 /* todo: rotation?*/ 2046 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; 2047 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) { 2048 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true; 2049 /* 1/2 vblank */ 2050 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active = 2051 (v_total - timing->v_addressable 2052 - timing->v_border_top - timing->v_border_bottom) / 2; 2053 /* 36 bytes dp, 32 hdmi */ 2054 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes = 2055 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32; 2056 } 2057 pipes[pipe_cnt].pipe.src.dcc = false; 2058 pipes[pipe_cnt].pipe.src.dcc_rate = 1; 2059 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank; 2060 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch; 2061 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start 2062 - timing->h_addressable 2063 - timing->h_border_left 2064 - timing->h_border_right; 2065 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch; 2066 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start 2067 - timing->v_addressable 2068 - timing->v_border_top 2069 - timing->v_border_bottom; 2070 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total; 2071 pipes[pipe_cnt].pipe.dest.vtotal = v_total; 2072 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable; 2073 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable; 2074 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE; 2075 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0; 2076 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 2077 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2; 2078 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst; 2079 pipes[pipe_cnt].dout.dp_lanes = 4; 2080 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min; 2081 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max; 2082 switch (get_num_odm_splits(&res_ctx->pipe_ctx[i])) { 2083 case 1: 2084 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1; 2085 break; 2086 default: 2087 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled; 2088 } 2089 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; 2090 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state 2091 == res_ctx->pipe_ctx[i].plane_state) { 2092 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe; 2093 2094 while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state 2095 == res_ctx->pipe_ctx[i].plane_state) 2096 first_pipe = first_pipe->top_pipe; 2097 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx; 2098 } else if (res_ctx->pipe_ctx[i].prev_odm_pipe) { 2099 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe; 2100 2101 while (first_pipe->prev_odm_pipe) 2102 first_pipe = first_pipe->prev_odm_pipe; 2103 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx; 2104 } 2105 2106 switch (res_ctx->pipe_ctx[i].stream->signal) { 2107 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2108 case SIGNAL_TYPE_DISPLAY_PORT: 2109 pipes[pipe_cnt].dout.output_type = dm_dp; 2110 break; 2111 case SIGNAL_TYPE_EDP: 2112 pipes[pipe_cnt].dout.output_type = dm_edp; 2113 break; 2114 case SIGNAL_TYPE_HDMI_TYPE_A: 2115 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2116 case SIGNAL_TYPE_DVI_DUAL_LINK: 2117 pipes[pipe_cnt].dout.output_type = dm_hdmi; 2118 break; 2119 default: 2120 /* In case there is no signal, set dp with 4 lanes to allow max config */ 2121 pipes[pipe_cnt].dout.output_type = dm_dp; 2122 pipes[pipe_cnt].dout.dp_lanes = 4; 2123 } 2124 2125 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) { 2126 case COLOR_DEPTH_666: 2127 output_bpc = 6; 2128 break; 2129 case COLOR_DEPTH_888: 2130 output_bpc = 8; 2131 break; 2132 case COLOR_DEPTH_101010: 2133 output_bpc = 10; 2134 break; 2135 case COLOR_DEPTH_121212: 2136 output_bpc = 12; 2137 break; 2138 case COLOR_DEPTH_141414: 2139 output_bpc = 14; 2140 break; 2141 case COLOR_DEPTH_161616: 2142 output_bpc = 16; 2143 break; 2144 case COLOR_DEPTH_999: 2145 output_bpc = 9; 2146 break; 2147 case COLOR_DEPTH_111111: 2148 output_bpc = 11; 2149 break; 2150 default: 2151 output_bpc = 8; 2152 break; 2153 } 2154 2155 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) { 2156 case PIXEL_ENCODING_RGB: 2157 case PIXEL_ENCODING_YCBCR444: 2158 pipes[pipe_cnt].dout.output_format = dm_444; 2159 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3; 2160 break; 2161 case PIXEL_ENCODING_YCBCR420: 2162 pipes[pipe_cnt].dout.output_format = dm_420; 2163 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2; 2164 break; 2165 case PIXEL_ENCODING_YCBCR422: 2166 if (true) /* todo */ 2167 pipes[pipe_cnt].dout.output_format = dm_s422; 2168 else 2169 pipes[pipe_cnt].dout.output_format = dm_n422; 2170 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2; 2171 break; 2172 default: 2173 pipes[pipe_cnt].dout.output_format = dm_444; 2174 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3; 2175 } 2176 2177 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC) 2178 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0; 2179 2180 /* todo: default max for now, until there is logic reflecting this in dc*/ 2181 pipes[pipe_cnt].dout.output_bpc = 12; 2182 /* 2183 * For graphic plane, cursor number is 1, nv12 is 0 2184 * bw calculations due to cursor on/off 2185 */ 2186 if (res_ctx->pipe_ctx[i].plane_state && 2187 res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 2188 pipes[pipe_cnt].pipe.src.num_cursors = 0; 2189 else 2190 pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors; 2191 2192 pipes[pipe_cnt].pipe.src.cur0_src_width = 256; 2193 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit; 2194 2195 if (!res_ctx->pipe_ctx[i].plane_state) { 2196 pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled; 2197 pipes[pipe_cnt].pipe.src.source_scan = dm_horz; 2198 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear; 2199 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile; 2200 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable; 2201 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920) 2202 pipes[pipe_cnt].pipe.src.viewport_width = 1920; 2203 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable; 2204 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080) 2205 pipes[pipe_cnt].pipe.src.viewport_height = 1080; 2206 pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height; 2207 pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width; 2208 pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height; 2209 pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width; 2210 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */ 2211 pipes[pipe_cnt].pipe.src.source_format = dm_444_32; 2212 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/ 2213 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/ 2214 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/ 2215 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/ 2216 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16; 2217 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0; 2218 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0; 2219 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/ 2220 pipes[pipe_cnt].pipe.scale_taps.htaps = 1; 2221 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1; 2222 pipes[pipe_cnt].pipe.dest.vtotal_min = v_total; 2223 pipes[pipe_cnt].pipe.dest.vtotal_max = v_total; 2224 2225 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) { 2226 pipes[pipe_cnt].pipe.src.viewport_width /= 2; 2227 pipes[pipe_cnt].pipe.dest.recout_width /= 2; 2228 } 2229 } else { 2230 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state; 2231 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data; 2232 2233 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate; 2234 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) 2235 || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) 2236 || pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled; 2237 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90 2238 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz; 2239 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport_unadjusted.y; 2240 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c_unadjusted.y; 2241 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport_unadjusted.width; 2242 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c_unadjusted.width; 2243 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport_unadjusted.height; 2244 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c_unadjusted.height; 2245 pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width; 2246 pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height; 2247 pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width; 2248 pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height; 2249 if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 2250 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch; 2251 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch; 2252 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; 2253 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c; 2254 } else { 2255 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch; 2256 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; 2257 } 2258 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable; 2259 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width; 2260 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height; 2261 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height; 2262 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width; 2263 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) 2264 pipes[pipe_cnt].pipe.dest.full_recout_width *= 2; 2265 else { 2266 struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe; 2267 2268 while (split_pipe && split_pipe->plane_state == pln) { 2269 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; 2270 split_pipe = split_pipe->bottom_pipe; 2271 } 2272 split_pipe = res_ctx->pipe_ctx[i].top_pipe; 2273 while (split_pipe && split_pipe->plane_state == pln) { 2274 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; 2275 split_pipe = split_pipe->top_pipe; 2276 } 2277 } 2278 2279 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16; 2280 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32); 2281 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32); 2282 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32); 2283 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32); 2284 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 2285 scl->ratios.vert.value != dc_fixpt_one.value 2286 || scl->ratios.horz.value != dc_fixpt_one.value 2287 || scl->ratios.vert_c.value != dc_fixpt_one.value 2288 || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/ 2289 || dc->debug.always_scale; /*support always scale*/ 2290 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps; 2291 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c; 2292 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps; 2293 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c; 2294 2295 pipes[pipe_cnt].pipe.src.macro_tile_size = 2296 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); 2297 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, 2298 &pipes[pipe_cnt].pipe.src.sw_mode); 2299 2300 switch (pln->format) { 2301 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 2302 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 2303 pipes[pipe_cnt].pipe.src.source_format = dm_420_8; 2304 break; 2305 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 2306 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 2307 pipes[pipe_cnt].pipe.src.source_format = dm_420_10; 2308 break; 2309 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 2310 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 2311 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2312 pipes[pipe_cnt].pipe.src.source_format = dm_444_64; 2313 break; 2314 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 2315 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 2316 pipes[pipe_cnt].pipe.src.source_format = dm_444_16; 2317 break; 2318 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 2319 pipes[pipe_cnt].pipe.src.source_format = dm_444_8; 2320 break; 2321 default: 2322 pipes[pipe_cnt].pipe.src.source_format = dm_444_32; 2323 break; 2324 } 2325 } 2326 2327 pipe_cnt++; 2328 } 2329 2330 /* populate writeback information */ 2331 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes); 2332 2333 return pipe_cnt; 2334 } 2335 2336 unsigned int dcn20_calc_max_scaled_time( 2337 unsigned int time_per_pixel, 2338 enum mmhubbub_wbif_mode mode, 2339 unsigned int urgent_watermark) 2340 { 2341 unsigned int time_per_byte = 0; 2342 unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */ 2343 unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */ 2344 unsigned int small_free_entry, max_free_entry; 2345 unsigned int buf_lh_capability; 2346 unsigned int max_scaled_time; 2347 2348 if (mode == PACKED_444) /* packed mode */ 2349 time_per_byte = time_per_pixel/4; 2350 else if (mode == PLANAR_420_8BPC) 2351 time_per_byte = time_per_pixel; 2352 else if (mode == PLANAR_420_10BPC) /* p010 */ 2353 time_per_byte = time_per_pixel * 819/1024; 2354 2355 if (time_per_byte == 0) 2356 time_per_byte = 1; 2357 2358 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry; 2359 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry; 2360 buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */ 2361 max_scaled_time = buf_lh_capability - urgent_watermark; 2362 return max_scaled_time; 2363 } 2364 2365 void dcn20_set_mcif_arb_params( 2366 struct dc *dc, 2367 struct dc_state *context, 2368 display_e2e_pipe_params_st *pipes, 2369 int pipe_cnt) 2370 { 2371 enum mmhubbub_wbif_mode wbif_mode; 2372 struct mcif_arb_params *wb_arb_params; 2373 int i, j, k, dwb_pipe; 2374 2375 /* Writeback MCIF_WB arbitration parameters */ 2376 dwb_pipe = 0; 2377 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2378 2379 if (!context->res_ctx.pipe_ctx[i].stream) 2380 continue; 2381 2382 for (j = 0; j < MAX_DWB_PIPES; j++) { 2383 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false) 2384 continue; 2385 2386 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params; 2387 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe]; 2388 2389 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) { 2390 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) 2391 wbif_mode = PLANAR_420_8BPC; 2392 else 2393 wbif_mode = PLANAR_420_10BPC; 2394 } else 2395 wbif_mode = PACKED_444; 2396 2397 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) { 2398 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2399 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2400 } 2401 wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */ 2402 wb_arb_params->slice_lines = 32; 2403 wb_arb_params->arbitration_slice = 2; 2404 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel, 2405 wbif_mode, 2406 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */ 2407 2408 dwb_pipe++; 2409 2410 if (dwb_pipe >= MAX_DWB_PIPES) 2411 return; 2412 } 2413 if (dwb_pipe >= MAX_DWB_PIPES) 2414 return; 2415 } 2416 } 2417 2418 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) 2419 { 2420 int i; 2421 2422 /* Validate DSC config, dsc count validation is already done */ 2423 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2424 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; 2425 struct dc_stream_state *stream = pipe_ctx->stream; 2426 struct dsc_config dsc_cfg; 2427 struct pipe_ctx *odm_pipe; 2428 int opp_cnt = 1; 2429 2430 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 2431 opp_cnt++; 2432 2433 /* Only need to validate top pipe */ 2434 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC) 2435 continue; 2436 2437 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left 2438 + stream->timing.h_border_right) / opp_cnt; 2439 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top 2440 + stream->timing.v_border_bottom; 2441 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 2442 dsc_cfg.color_depth = stream->timing.display_color_depth; 2443 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 2444 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 2445 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 2446 2447 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg)) 2448 return false; 2449 } 2450 return true; 2451 } 2452 2453 struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, 2454 struct resource_context *res_ctx, 2455 const struct resource_pool *pool, 2456 const struct pipe_ctx *primary_pipe) 2457 { 2458 struct pipe_ctx *secondary_pipe = NULL; 2459 2460 if (dc && primary_pipe) { 2461 int j; 2462 int preferred_pipe_idx = 0; 2463 2464 /* first check the prev dc state: 2465 * if this primary pipe has a bottom pipe in prev. state 2466 * and if the bottom pipe is still available (which it should be), 2467 * pick that pipe as secondary 2468 * Same logic applies for ODM pipes. Since mpo is not allowed with odm 2469 * check in else case. 2470 */ 2471 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) { 2472 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx; 2473 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2474 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2475 secondary_pipe->pipe_idx = preferred_pipe_idx; 2476 } 2477 } else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) { 2478 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx; 2479 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2480 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2481 secondary_pipe->pipe_idx = preferred_pipe_idx; 2482 } 2483 } 2484 2485 /* 2486 * if this primary pipe does not have a bottom pipe in prev. state 2487 * start backward and find a pipe that did not used to be a bottom pipe in 2488 * prev. dc state. This way we make sure we keep the same assignment as 2489 * last state and will not have to reprogram every pipe 2490 */ 2491 if (secondary_pipe == NULL) { 2492 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { 2493 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL 2494 && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) { 2495 preferred_pipe_idx = j; 2496 2497 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2498 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2499 secondary_pipe->pipe_idx = preferred_pipe_idx; 2500 break; 2501 } 2502 } 2503 } 2504 } 2505 /* 2506 * We should never hit this assert unless assignments are shuffled around 2507 * if this happens we will prob. hit a vsync tdr 2508 */ 2509 ASSERT(secondary_pipe); 2510 /* 2511 * search backwards for the second pipe to keep pipe 2512 * assignment more consistent 2513 */ 2514 if (secondary_pipe == NULL) { 2515 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { 2516 preferred_pipe_idx = j; 2517 2518 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2519 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2520 secondary_pipe->pipe_idx = preferred_pipe_idx; 2521 break; 2522 } 2523 } 2524 } 2525 } 2526 2527 return secondary_pipe; 2528 } 2529 2530 static void dcn20_merge_pipes_for_validate( 2531 struct dc *dc, 2532 struct dc_state *context) 2533 { 2534 int i; 2535 2536 /* merge previously split odm pipes since mode support needs to make the decision */ 2537 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2538 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2539 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe; 2540 2541 if (pipe->prev_odm_pipe) 2542 continue; 2543 2544 pipe->next_odm_pipe = NULL; 2545 while (odm_pipe) { 2546 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe; 2547 2548 odm_pipe->plane_state = NULL; 2549 odm_pipe->stream = NULL; 2550 odm_pipe->top_pipe = NULL; 2551 odm_pipe->bottom_pipe = NULL; 2552 odm_pipe->prev_odm_pipe = NULL; 2553 odm_pipe->next_odm_pipe = NULL; 2554 if (odm_pipe->stream_res.dsc) 2555 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); 2556 /* Clear plane_res and stream_res */ 2557 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res)); 2558 memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res)); 2559 odm_pipe = next_odm_pipe; 2560 } 2561 if (pipe->plane_state) 2562 resource_build_scaling_params(pipe); 2563 } 2564 2565 /* merge previously mpc split pipes since mode support needs to make the decision */ 2566 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2567 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2568 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 2569 2570 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) 2571 continue; 2572 2573 pipe->bottom_pipe = hsplit_pipe->bottom_pipe; 2574 if (hsplit_pipe->bottom_pipe) 2575 hsplit_pipe->bottom_pipe->top_pipe = pipe; 2576 hsplit_pipe->plane_state = NULL; 2577 hsplit_pipe->stream = NULL; 2578 hsplit_pipe->top_pipe = NULL; 2579 hsplit_pipe->bottom_pipe = NULL; 2580 2581 /* Clear plane_res and stream_res */ 2582 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res)); 2583 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res)); 2584 if (pipe->plane_state) 2585 resource_build_scaling_params(pipe); 2586 } 2587 } 2588 2589 int dcn20_validate_apply_pipe_split_flags( 2590 struct dc *dc, 2591 struct dc_state *context, 2592 int vlevel, 2593 int *split, 2594 bool *merge) 2595 { 2596 int i, pipe_idx, vlevel_split; 2597 int plane_count = 0; 2598 bool force_split = false; 2599 bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID; 2600 struct vba_vars_st *v = &context->bw_ctx.dml.vba; 2601 int max_mpc_comb = v->maxMpcComb; 2602 2603 if (context->stream_count > 1) { 2604 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) 2605 avoid_split = true; 2606 } else if (dc->debug.force_single_disp_pipe_split) 2607 force_split = true; 2608 2609 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2610 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2611 2612 /** 2613 * Workaround for avoiding pipe-split in cases where we'd split 2614 * planes that are too small, resulting in splits that aren't 2615 * valid for the scaler. 2616 */ 2617 if (pipe->plane_state && 2618 (pipe->plane_state->dst_rect.width <= 16 || 2619 pipe->plane_state->dst_rect.height <= 16 || 2620 pipe->plane_state->src_rect.width <= 16 || 2621 pipe->plane_state->src_rect.height <= 16)) 2622 avoid_split = true; 2623 2624 /* TODO: fix dc bugs and remove this split threshold thing */ 2625 if (pipe->stream && !pipe->prev_odm_pipe && 2626 (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state)) 2627 ++plane_count; 2628 } 2629 if (plane_count > dc->res_pool->pipe_count / 2) 2630 avoid_split = true; 2631 2632 /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */ 2633 if (avoid_split) { 2634 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2635 if (!context->res_ctx.pipe_ctx[i].stream) 2636 continue; 2637 2638 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) 2639 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 && 2640 v->ModeSupport[vlevel][0]) 2641 break; 2642 /* Impossible to not split this pipe */ 2643 if (vlevel > context->bw_ctx.dml.soc.num_states) 2644 vlevel = vlevel_split; 2645 else 2646 max_mpc_comb = 0; 2647 pipe_idx++; 2648 } 2649 v->maxMpcComb = max_mpc_comb; 2650 } 2651 2652 /* Split loop sets which pipe should be split based on dml outputs and dc flags */ 2653 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2654 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2655 int pipe_plane = v->pipe_plane[pipe_idx]; 2656 bool split4mpc = context->stream_count == 1 && plane_count == 1 2657 && dc->config.enable_4to1MPC && dc->res_pool->pipe_count >= 4; 2658 2659 if (!context->res_ctx.pipe_ctx[i].stream) 2660 continue; 2661 2662 if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] > 1) { 2663 if (split4mpc) 2664 split[i] = 4; 2665 else 2666 split[i] = 2; 2667 } 2668 if ((pipe->stream->view_format == 2669 VIEW_3D_FORMAT_SIDE_BY_SIDE || 2670 pipe->stream->view_format == 2671 VIEW_3D_FORMAT_TOP_AND_BOTTOM) && 2672 (pipe->stream->timing.timing_3d_format == 2673 TIMING_3D_FORMAT_TOP_AND_BOTTOM || 2674 pipe->stream->timing.timing_3d_format == 2675 TIMING_3D_FORMAT_SIDE_BY_SIDE)) 2676 split[i] = 2; 2677 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) { 2678 split[i] = 2; 2679 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1; 2680 } 2681 v->ODMCombineEnabled[pipe_plane] = 2682 v->ODMCombineEnablePerState[vlevel][pipe_plane]; 2683 2684 if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) { 2685 if (get_num_mpc_splits(pipe) == 1) { 2686 /*If need split for mpc but 2 way split already*/ 2687 if (split[i] == 4) 2688 split[i] = 2; /* 2 -> 4 MPC */ 2689 else if (split[i] == 2) 2690 split[i] = 0; /* 2 -> 2 MPC */ 2691 else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) 2692 merge[i] = true; /* 2 -> 1 MPC */ 2693 } else if (get_num_mpc_splits(pipe) == 3) { 2694 /*If need split for mpc but 4 way split already*/ 2695 if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe) 2696 || !pipe->bottom_pipe)) { 2697 merge[i] = true; /* 4 -> 2 MPC */ 2698 } else if (split[i] == 0 && pipe->top_pipe && 2699 pipe->top_pipe->plane_state == pipe->plane_state) 2700 merge[i] = true; /* 4 -> 1 MPC */ 2701 split[i] = 0; 2702 } else if (get_num_odm_splits(pipe)) { 2703 /* ODM -> MPC transition */ 2704 ASSERT(0); /* NOT expected yet */ 2705 if (pipe->prev_odm_pipe) { 2706 split[i] = 0; 2707 merge[i] = true; 2708 } 2709 } 2710 } else { 2711 if (get_num_odm_splits(pipe) == 1) { 2712 /*If need split for odm but 2 way split already*/ 2713 if (split[i] == 4) 2714 split[i] = 2; /* 2 -> 4 ODM */ 2715 else if (split[i] == 2) 2716 split[i] = 0; /* 2 -> 2 ODM */ 2717 else if (pipe->prev_odm_pipe) { 2718 ASSERT(0); /* NOT expected yet */ 2719 merge[i] = true; /* exit ODM */ 2720 } 2721 } else if (get_num_odm_splits(pipe) == 3) { 2722 /*If need split for odm but 4 way split already*/ 2723 if (split[i] == 2 && ((pipe->prev_odm_pipe && !pipe->prev_odm_pipe->prev_odm_pipe) 2724 || !pipe->next_odm_pipe)) { 2725 ASSERT(0); /* NOT expected yet */ 2726 merge[i] = true; /* 4 -> 2 ODM */ 2727 } else if (split[i] == 0 && pipe->prev_odm_pipe) { 2728 ASSERT(0); /* NOT expected yet */ 2729 merge[i] = true; /* exit ODM */ 2730 } 2731 split[i] = 0; 2732 } else if (get_num_mpc_splits(pipe)) { 2733 /* MPC -> ODM transition */ 2734 ASSERT(0); /* NOT expected yet */ 2735 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { 2736 split[i] = 0; 2737 merge[i] = true; 2738 } 2739 } 2740 } 2741 2742 /* Adjust dppclk when split is forced, do not bother with dispclk */ 2743 if (split[i] != 0 && v->NoOfDPP[vlevel][max_mpc_comb][pipe_idx] == 1) 2744 v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2; 2745 pipe_idx++; 2746 } 2747 2748 return vlevel; 2749 } 2750 2751 bool dcn20_fast_validate_bw( 2752 struct dc *dc, 2753 struct dc_state *context, 2754 display_e2e_pipe_params_st *pipes, 2755 int *pipe_cnt_out, 2756 int *pipe_split_from, 2757 int *vlevel_out) 2758 { 2759 bool out = false; 2760 int split[MAX_PIPES] = { 0 }; 2761 int pipe_cnt, i, pipe_idx, vlevel; 2762 2763 ASSERT(pipes); 2764 if (!pipes) 2765 return false; 2766 2767 dcn20_merge_pipes_for_validate(dc, context); 2768 2769 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes); 2770 2771 *pipe_cnt_out = pipe_cnt; 2772 2773 if (!pipe_cnt) { 2774 out = true; 2775 goto validate_out; 2776 } 2777 2778 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 2779 2780 if (vlevel > context->bw_ctx.dml.soc.num_states) 2781 goto validate_fail; 2782 2783 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL); 2784 2785 /*initialize pipe_just_split_from to invalid idx*/ 2786 for (i = 0; i < MAX_PIPES; i++) 2787 pipe_split_from[i] = -1; 2788 2789 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { 2790 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2791 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 2792 2793 if (!pipe->stream || pipe_split_from[i] >= 0) 2794 continue; 2795 2796 pipe_idx++; 2797 2798 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 2799 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 2800 ASSERT(hsplit_pipe); 2801 if (!dcn20_split_stream_for_odm( 2802 dc, &context->res_ctx, 2803 pipe, hsplit_pipe)) 2804 goto validate_fail; 2805 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 2806 dcn20_build_mapped_resource(dc, context, pipe->stream); 2807 } 2808 2809 if (!pipe->plane_state) 2810 continue; 2811 /* Skip 2nd half of already split pipe */ 2812 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state) 2813 continue; 2814 2815 /* We do not support mpo + odm at the moment */ 2816 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state 2817 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) 2818 goto validate_fail; 2819 2820 if (split[i] == 2) { 2821 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) { 2822 /* pipe not split previously needs split */ 2823 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 2824 ASSERT(hsplit_pipe); 2825 if (!hsplit_pipe) { 2826 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2; 2827 continue; 2828 } 2829 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 2830 if (!dcn20_split_stream_for_odm( 2831 dc, &context->res_ctx, 2832 pipe, hsplit_pipe)) 2833 goto validate_fail; 2834 dcn20_build_mapped_resource(dc, context, pipe->stream); 2835 } else { 2836 dcn20_split_stream_for_mpc( 2837 &context->res_ctx, dc->res_pool, 2838 pipe, hsplit_pipe); 2839 if (!resource_build_scaling_params(pipe) || !resource_build_scaling_params(hsplit_pipe)) 2840 goto validate_fail; 2841 } 2842 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 2843 } 2844 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { 2845 /* merge should already have been done */ 2846 ASSERT(0); 2847 } 2848 } 2849 /* Actual dsc count per stream dsc validation*/ 2850 if (!dcn20_validate_dsc(dc, context)) { 2851 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = 2852 DML_FAIL_DSC_VALIDATION_FAILURE; 2853 goto validate_fail; 2854 } 2855 2856 *vlevel_out = vlevel; 2857 2858 out = true; 2859 goto validate_out; 2860 2861 validate_fail: 2862 out = false; 2863 2864 validate_out: 2865 return out; 2866 } 2867 2868 static void dcn20_calculate_wm( 2869 struct dc *dc, struct dc_state *context, 2870 display_e2e_pipe_params_st *pipes, 2871 int *out_pipe_cnt, 2872 int *pipe_split_from, 2873 int vlevel) 2874 { 2875 int pipe_cnt, i, pipe_idx; 2876 2877 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 2878 if (!context->res_ctx.pipe_ctx[i].stream) 2879 continue; 2880 2881 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 2882 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 2883 2884 if (pipe_split_from[i] < 0) { 2885 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 2886 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; 2887 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) 2888 pipes[pipe_cnt].pipe.dest.odm_combine = 2889 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]; 2890 else 2891 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 2892 pipe_idx++; 2893 } else { 2894 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 2895 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; 2896 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) 2897 pipes[pipe_cnt].pipe.dest.odm_combine = 2898 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]]; 2899 else 2900 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 2901 } 2902 2903 if (dc->config.forced_clocks) { 2904 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 2905 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 2906 } 2907 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000) 2908 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 2909 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000) 2910 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 2911 2912 pipe_cnt++; 2913 } 2914 2915 if (pipe_cnt != pipe_idx) { 2916 if (dc->res_pool->funcs->populate_dml_pipes) 2917 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, 2918 context, pipes); 2919 else 2920 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, 2921 context, pipes); 2922 } 2923 2924 *out_pipe_cnt = pipe_cnt; 2925 2926 pipes[0].clks_cfg.voltage = vlevel; 2927 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; 2928 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 2929 2930 /* only pipe 0 is read for voltage and dcf/soc clocks */ 2931 if (vlevel < 1) { 2932 pipes[0].clks_cfg.voltage = 1; 2933 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz; 2934 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz; 2935 } 2936 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2937 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2938 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2939 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2940 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2941 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2942 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2943 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2944 2945 if (vlevel < 2) { 2946 pipes[0].clks_cfg.voltage = 2; 2947 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; 2948 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; 2949 } 2950 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2951 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2952 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2953 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2954 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2955 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2956 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2957 2958 if (vlevel < 3) { 2959 pipes[0].clks_cfg.voltage = 3; 2960 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; 2961 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; 2962 } 2963 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2964 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2965 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2966 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2967 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2968 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2969 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2970 2971 pipes[0].clks_cfg.voltage = vlevel; 2972 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; 2973 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 2974 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2975 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2976 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2977 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2978 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2979 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2980 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2981 } 2982 2983 void dcn20_calculate_dlg_params( 2984 struct dc *dc, struct dc_state *context, 2985 display_e2e_pipe_params_st *pipes, 2986 int pipe_cnt, 2987 int vlevel) 2988 { 2989 int i, j, pipe_idx, pipe_idx_unsplit; 2990 bool visited[MAX_PIPES] = { 0 }; 2991 2992 /* Writeback MCIF_WB arbitration parameters */ 2993 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); 2994 2995 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; 2996 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; 2997 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; 2998 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; 2999 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; 3000 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; 3001 context->bw_ctx.bw.dcn.clk.p_state_change_support = 3002 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] 3003 != dm_dram_clock_change_unsupported; 3004 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 3005 3006 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) 3007 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; 3008 3009 /* 3010 * An artifact of dml pipe split/odm is that pipes get merged back together for 3011 * calculation. Therefore we need to only extract for first pipe in ascending index order 3012 * and copy into the other split half. 3013 */ 3014 for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) { 3015 if (!context->res_ctx.pipe_ctx[i].stream) 3016 continue; 3017 3018 if (!visited[pipe_idx]) { 3019 display_pipe_source_params_st *src = &pipes[pipe_idx].pipe.src; 3020 display_pipe_dest_params_st *dst = &pipes[pipe_idx].pipe.dest; 3021 3022 dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit]; 3023 dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit]; 3024 dst->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit]; 3025 dst->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit]; 3026 /* 3027 * j iterates inside pipes array, unlike i which iterates inside 3028 * pipe_ctx array 3029 */ 3030 if (src->is_hsplit) 3031 for (j = pipe_idx + 1; j < pipe_cnt; j++) { 3032 display_pipe_source_params_st *src_j = &pipes[j].pipe.src; 3033 display_pipe_dest_params_st *dst_j = &pipes[j].pipe.dest; 3034 3035 if (src_j->is_hsplit && !visited[j] 3036 && src->hsplit_grp == src_j->hsplit_grp) { 3037 dst_j->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit]; 3038 dst_j->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit]; 3039 dst_j->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit]; 3040 dst_j->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit]; 3041 visited[j] = true; 3042 } 3043 } 3044 visited[pipe_idx] = true; 3045 pipe_idx_unsplit++; 3046 } 3047 pipe_idx++; 3048 } 3049 3050 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 3051 if (!context->res_ctx.pipe_ctx[i].stream) 3052 continue; 3053 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 3054 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 3055 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 3056 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 3057 ASSERT(visited[pipe_idx]); 3058 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; 3059 pipe_idx++; 3060 } 3061 /*save a original dppclock copy*/ 3062 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; 3063 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; 3064 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000; 3065 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000; 3066 3067 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 3068 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2; 3069 3070 if (!context->res_ctx.pipe_ctx[i].stream) 3071 continue; 3072 3073 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml, 3074 &context->res_ctx.pipe_ctx[i].dlg_regs, 3075 &context->res_ctx.pipe_ctx[i].ttu_regs, 3076 pipes, 3077 pipe_cnt, 3078 pipe_idx, 3079 cstate_en, 3080 context->bw_ctx.bw.dcn.clk.p_state_change_support, 3081 false, false, true); 3082 3083 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml, 3084 &context->res_ctx.pipe_ctx[i].rq_regs, 3085 pipes[pipe_idx].pipe); 3086 pipe_idx++; 3087 } 3088 } 3089 3090 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context, 3091 bool fast_validate) 3092 { 3093 bool out = false; 3094 3095 BW_VAL_TRACE_SETUP(); 3096 3097 int vlevel = 0; 3098 int pipe_split_from[MAX_PIPES]; 3099 int pipe_cnt = 0; 3100 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 3101 DC_LOGGER_INIT(dc->ctx->logger); 3102 3103 BW_VAL_TRACE_COUNT(); 3104 3105 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel); 3106 3107 if (pipe_cnt == 0) 3108 goto validate_out; 3109 3110 if (!out) 3111 goto validate_fail; 3112 3113 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 3114 3115 if (fast_validate) { 3116 BW_VAL_TRACE_SKIP(fast); 3117 goto validate_out; 3118 } 3119 3120 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel); 3121 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 3122 3123 BW_VAL_TRACE_END_WATERMARKS(); 3124 3125 goto validate_out; 3126 3127 validate_fail: 3128 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 3129 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 3130 3131 BW_VAL_TRACE_SKIP(fail); 3132 out = false; 3133 3134 validate_out: 3135 kfree(pipes); 3136 3137 BW_VAL_TRACE_FINISH(); 3138 3139 return out; 3140 } 3141 3142 /* 3143 * This must be noinline to ensure anything that deals with FP registers 3144 * is contained within this call; previously our compiling with hard-float 3145 * would result in fp instructions being emitted outside of the boundaries 3146 * of the DC_FP_START/END macros, which makes sense as the compiler has no 3147 * idea about what is wrapped and what is not 3148 * 3149 * This is largely just a workaround to avoid breakage introduced with 5.6, 3150 * ideally all fp-using code should be moved into its own file, only that 3151 * should be compiled with hard-float, and all code exported from there 3152 * should be strictly wrapped with DC_FP_START/END 3153 */ 3154 static noinline bool dcn20_validate_bandwidth_fp(struct dc *dc, 3155 struct dc_state *context, bool fast_validate) 3156 { 3157 bool voltage_supported = false; 3158 bool full_pstate_supported = false; 3159 bool dummy_pstate_supported = false; 3160 double p_state_latency_us; 3161 3162 p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us; 3163 context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support = 3164 dc->debug.disable_dram_clock_change_vactive_support; 3165 context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive = 3166 dc->debug.enable_dram_clock_change_one_display_vactive; 3167 3168 if (fast_validate) { 3169 return dcn20_validate_bandwidth_internal(dc, context, true); 3170 } 3171 3172 // Best case, we support full UCLK switch latency 3173 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); 3174 full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; 3175 3176 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 || 3177 (voltage_supported && full_pstate_supported)) { 3178 context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported; 3179 goto restore_dml_state; 3180 } 3181 3182 // Fallback: Try to only support G6 temperature read latency 3183 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us; 3184 3185 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); 3186 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; 3187 3188 if (voltage_supported && dummy_pstate_supported) { 3189 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; 3190 goto restore_dml_state; 3191 } 3192 3193 // ERROR: fallback is supposed to always work. 3194 ASSERT(false); 3195 3196 restore_dml_state: 3197 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us; 3198 return voltage_supported; 3199 } 3200 3201 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, 3202 bool fast_validate) 3203 { 3204 bool voltage_supported = false; 3205 DC_FP_START(); 3206 voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate); 3207 DC_FP_END(); 3208 return voltage_supported; 3209 } 3210 3211 struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer( 3212 struct dc_state *state, 3213 const struct resource_pool *pool, 3214 struct dc_stream_state *stream) 3215 { 3216 struct resource_context *res_ctx = &state->res_ctx; 3217 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 3218 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe); 3219 3220 if (!head_pipe) 3221 ASSERT(0); 3222 3223 if (!idle_pipe) 3224 return NULL; 3225 3226 idle_pipe->stream = head_pipe->stream; 3227 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 3228 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 3229 3230 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 3231 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 3232 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 3233 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 3234 3235 return idle_pipe; 3236 } 3237 3238 bool dcn20_get_dcc_compression_cap(const struct dc *dc, 3239 const struct dc_dcc_surface_param *input, 3240 struct dc_surface_dcc_cap *output) 3241 { 3242 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 3243 dc->res_pool->hubbub, 3244 input, 3245 output); 3246 } 3247 3248 static void dcn20_destroy_resource_pool(struct resource_pool **pool) 3249 { 3250 struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool); 3251 3252 dcn20_resource_destruct(dcn20_pool); 3253 kfree(dcn20_pool); 3254 *pool = NULL; 3255 } 3256 3257 3258 static struct dc_cap_funcs cap_funcs = { 3259 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 3260 }; 3261 3262 3263 enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state) 3264 { 3265 enum surface_pixel_format surf_pix_format = plane_state->format; 3266 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 3267 3268 enum swizzle_mode_values swizzle = DC_SW_LINEAR; 3269 3270 if (bpp == 64) 3271 swizzle = DC_SW_64KB_D; 3272 else 3273 swizzle = DC_SW_64KB_S; 3274 3275 plane_state->tiling_info.gfx9.swizzle = swizzle; 3276 return DC_OK; 3277 } 3278 3279 static struct resource_funcs dcn20_res_pool_funcs = { 3280 .destroy = dcn20_destroy_resource_pool, 3281 .link_enc_create = dcn20_link_encoder_create, 3282 .panel_cntl_create = dcn20_panel_cntl_create, 3283 .validate_bandwidth = dcn20_validate_bandwidth, 3284 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 3285 .add_stream_to_ctx = dcn20_add_stream_to_ctx, 3286 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 3287 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, 3288 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 3289 .set_mcif_arb_params = dcn20_set_mcif_arb_params, 3290 .populate_dml_pipes = dcn20_populate_dml_pipes_from_context, 3291 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link 3292 }; 3293 3294 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 3295 { 3296 int i; 3297 uint32_t pipe_count = pool->res_cap->num_dwb; 3298 3299 for (i = 0; i < pipe_count; i++) { 3300 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc), 3301 GFP_KERNEL); 3302 3303 if (!dwbc20) { 3304 dm_error("DC: failed to create dwbc20!\n"); 3305 return false; 3306 } 3307 dcn20_dwbc_construct(dwbc20, ctx, 3308 &dwbc20_regs[i], 3309 &dwbc20_shift, 3310 &dwbc20_mask, 3311 i); 3312 pool->dwbc[i] = &dwbc20->base; 3313 } 3314 return true; 3315 } 3316 3317 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 3318 { 3319 int i; 3320 uint32_t pipe_count = pool->res_cap->num_dwb; 3321 3322 ASSERT(pipe_count > 0); 3323 3324 for (i = 0; i < pipe_count; i++) { 3325 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub), 3326 GFP_KERNEL); 3327 3328 if (!mcif_wb20) { 3329 dm_error("DC: failed to create mcif_wb20!\n"); 3330 return false; 3331 } 3332 3333 dcn20_mmhubbub_construct(mcif_wb20, ctx, 3334 &mcif_wb20_regs[i], 3335 &mcif_wb20_shift, 3336 &mcif_wb20_mask, 3337 i); 3338 3339 pool->mcif_wb[i] = &mcif_wb20->base; 3340 } 3341 return true; 3342 } 3343 3344 static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx) 3345 { 3346 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 3347 3348 if (!pp_smu) 3349 return pp_smu; 3350 3351 dm_pp_get_funcs(ctx, pp_smu); 3352 3353 if (pp_smu->ctx.ver != PP_SMU_VER_NV) 3354 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); 3355 3356 return pp_smu; 3357 } 3358 3359 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu) 3360 { 3361 if (pp_smu && *pp_smu) { 3362 kfree(*pp_smu); 3363 *pp_smu = NULL; 3364 } 3365 } 3366 3367 void dcn20_cap_soc_clocks( 3368 struct _vcs_dpi_soc_bounding_box_st *bb, 3369 struct pp_smu_nv_clock_table max_clocks) 3370 { 3371 int i; 3372 3373 // First pass - cap all clocks higher than the reported max 3374 for (i = 0; i < bb->num_states; i++) { 3375 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000)) 3376 && max_clocks.dcfClockInKhz != 0) 3377 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000); 3378 3379 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16) 3380 && max_clocks.uClockInKhz != 0) 3381 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16; 3382 3383 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000)) 3384 && max_clocks.fabricClockInKhz != 0) 3385 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000); 3386 3387 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000)) 3388 && max_clocks.displayClockInKhz != 0) 3389 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000); 3390 3391 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000)) 3392 && max_clocks.dppClockInKhz != 0) 3393 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000); 3394 3395 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000)) 3396 && max_clocks.phyClockInKhz != 0) 3397 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000); 3398 3399 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000)) 3400 && max_clocks.socClockInKhz != 0) 3401 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000); 3402 3403 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000)) 3404 && max_clocks.dscClockInKhz != 0) 3405 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000); 3406 } 3407 3408 // Second pass - remove all duplicate clock states 3409 for (i = bb->num_states - 1; i > 1; i--) { 3410 bool duplicate = true; 3411 3412 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz) 3413 duplicate = false; 3414 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz) 3415 duplicate = false; 3416 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz) 3417 duplicate = false; 3418 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts) 3419 duplicate = false; 3420 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz) 3421 duplicate = false; 3422 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz) 3423 duplicate = false; 3424 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz) 3425 duplicate = false; 3426 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz) 3427 duplicate = false; 3428 3429 if (duplicate) 3430 bb->num_states--; 3431 } 3432 } 3433 3434 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb, 3435 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) 3436 { 3437 struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES]; 3438 int i; 3439 int num_calculated_states = 0; 3440 int min_dcfclk = 0; 3441 3442 if (num_states == 0) 3443 return; 3444 3445 memset(calculated_states, 0, sizeof(calculated_states)); 3446 3447 if (dc->bb_overrides.min_dcfclk_mhz > 0) 3448 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz; 3449 else { 3450 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) 3451 min_dcfclk = 310; 3452 else 3453 // Accounting for SOC/DCF relationship, we can go as high as 3454 // 506Mhz in Vmin. 3455 min_dcfclk = 506; 3456 } 3457 3458 for (i = 0; i < num_states; i++) { 3459 int min_fclk_required_by_uclk; 3460 calculated_states[i].state = i; 3461 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000; 3462 3463 // FCLK:UCLK ratio is 1.08 3464 min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32); 3465 3466 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? 3467 min_dcfclk : min_fclk_required_by_uclk; 3468 3469 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ? 3470 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; 3471 3472 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ? 3473 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; 3474 3475 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000; 3476 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000; 3477 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3); 3478 3479 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000; 3480 3481 num_calculated_states++; 3482 } 3483 3484 calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000; 3485 calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000; 3486 calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000; 3487 3488 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits)); 3489 bb->num_states = num_calculated_states; 3490 3491 // Duplicate the last state, DML always an extra state identical to max state to work 3492 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st)); 3493 bb->clock_limits[num_calculated_states].state = bb->num_states; 3494 } 3495 3496 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) 3497 { 3498 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns 3499 && dc->bb_overrides.sr_exit_time_ns) { 3500 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; 3501 } 3502 3503 if ((int)(bb->sr_enter_plus_exit_time_us * 1000) 3504 != dc->bb_overrides.sr_enter_plus_exit_time_ns 3505 && dc->bb_overrides.sr_enter_plus_exit_time_ns) { 3506 bb->sr_enter_plus_exit_time_us = 3507 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 3508 } 3509 3510 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns 3511 && dc->bb_overrides.urgent_latency_ns) { 3512 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 3513 } 3514 3515 if ((int)(bb->dram_clock_change_latency_us * 1000) 3516 != dc->bb_overrides.dram_clock_change_latency_ns 3517 && dc->bb_overrides.dram_clock_change_latency_ns) { 3518 bb->dram_clock_change_latency_us = 3519 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 3520 } 3521 3522 if ((int)(bb->dummy_pstate_latency_us * 1000) 3523 != dc->bb_overrides.dummy_clock_change_latency_ns 3524 && dc->bb_overrides.dummy_clock_change_latency_ns) { 3525 bb->dummy_pstate_latency_us = 3526 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0; 3527 } 3528 } 3529 3530 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb( 3531 uint32_t hw_internal_rev) 3532 { 3533 if (ASICREV_IS_NAVI14_M(hw_internal_rev)) 3534 return &dcn2_0_nv14_soc; 3535 3536 if (ASICREV_IS_NAVI12_P(hw_internal_rev)) 3537 return &dcn2_0_nv12_soc; 3538 3539 return &dcn2_0_soc; 3540 } 3541 3542 static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params( 3543 uint32_t hw_internal_rev) 3544 { 3545 /* NV14 */ 3546 if (ASICREV_IS_NAVI14_M(hw_internal_rev)) 3547 return &dcn2_0_nv14_ip; 3548 3549 /* NV12 and NV10 */ 3550 return &dcn2_0_ip; 3551 } 3552 3553 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev) 3554 { 3555 return DML_PROJECT_NAVI10v2; 3556 } 3557 3558 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16))) 3559 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) 3560 3561 static bool init_soc_bounding_box(struct dc *dc, 3562 struct dcn20_resource_pool *pool) 3563 { 3564 const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box; 3565 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = 3566 get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev); 3567 struct _vcs_dpi_ip_params_st *loaded_ip = 3568 get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev); 3569 3570 DC_LOGGER_INIT(dc->ctx->logger); 3571 3572 /* TODO: upstream NV12 bounding box when its launched */ 3573 if (!bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) { 3574 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); 3575 return false; 3576 } 3577 3578 if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) { 3579 int i; 3580 3581 dcn2_0_nv12_soc.sr_exit_time_us = 3582 fixed16_to_double_to_cpu(bb->sr_exit_time_us); 3583 dcn2_0_nv12_soc.sr_enter_plus_exit_time_us = 3584 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us); 3585 dcn2_0_nv12_soc.urgent_latency_us = 3586 fixed16_to_double_to_cpu(bb->urgent_latency_us); 3587 dcn2_0_nv12_soc.urgent_latency_pixel_data_only_us = 3588 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us); 3589 dcn2_0_nv12_soc.urgent_latency_pixel_mixed_with_vm_data_us = 3590 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us); 3591 dcn2_0_nv12_soc.urgent_latency_vm_data_only_us = 3592 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us); 3593 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes = 3594 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes); 3595 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 3596 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes); 3597 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_vm_only_bytes = 3598 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes); 3599 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 3600 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only); 3601 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 3602 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm); 3603 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 3604 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only); 3605 dcn2_0_nv12_soc.max_avg_sdp_bw_use_normal_percent = 3606 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent); 3607 dcn2_0_nv12_soc.max_avg_dram_bw_use_normal_percent = 3608 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent); 3609 dcn2_0_nv12_soc.writeback_latency_us = 3610 fixed16_to_double_to_cpu(bb->writeback_latency_us); 3611 dcn2_0_nv12_soc.ideal_dram_bw_after_urgent_percent = 3612 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent); 3613 dcn2_0_nv12_soc.max_request_size_bytes = 3614 le32_to_cpu(bb->max_request_size_bytes); 3615 dcn2_0_nv12_soc.dram_channel_width_bytes = 3616 le32_to_cpu(bb->dram_channel_width_bytes); 3617 dcn2_0_nv12_soc.fabric_datapath_to_dcn_data_return_bytes = 3618 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes); 3619 dcn2_0_nv12_soc.dcn_downspread_percent = 3620 fixed16_to_double_to_cpu(bb->dcn_downspread_percent); 3621 dcn2_0_nv12_soc.downspread_percent = 3622 fixed16_to_double_to_cpu(bb->downspread_percent); 3623 dcn2_0_nv12_soc.dram_page_open_time_ns = 3624 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns); 3625 dcn2_0_nv12_soc.dram_rw_turnaround_time_ns = 3626 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns); 3627 dcn2_0_nv12_soc.dram_return_buffer_per_channel_bytes = 3628 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes); 3629 dcn2_0_nv12_soc.round_trip_ping_latency_dcfclk_cycles = 3630 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles); 3631 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_bytes = 3632 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes); 3633 dcn2_0_nv12_soc.channel_interleave_bytes = 3634 le32_to_cpu(bb->channel_interleave_bytes); 3635 dcn2_0_nv12_soc.num_banks = 3636 le32_to_cpu(bb->num_banks); 3637 dcn2_0_nv12_soc.num_chans = 3638 le32_to_cpu(bb->num_chans); 3639 dcn2_0_nv12_soc.vmm_page_size_bytes = 3640 le32_to_cpu(bb->vmm_page_size_bytes); 3641 dcn2_0_nv12_soc.dram_clock_change_latency_us = 3642 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us); 3643 // HACK!! Lower uclock latency switch time so we don't switch 3644 dcn2_0_nv12_soc.dram_clock_change_latency_us = 10; 3645 dcn2_0_nv12_soc.writeback_dram_clock_change_latency_us = 3646 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us); 3647 dcn2_0_nv12_soc.return_bus_width_bytes = 3648 le32_to_cpu(bb->return_bus_width_bytes); 3649 dcn2_0_nv12_soc.dispclk_dppclk_vco_speed_mhz = 3650 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz); 3651 dcn2_0_nv12_soc.xfc_bus_transport_time_us = 3652 le32_to_cpu(bb->xfc_bus_transport_time_us); 3653 dcn2_0_nv12_soc.xfc_xbuf_latency_tolerance_us = 3654 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us); 3655 dcn2_0_nv12_soc.use_urgent_burst_bw = 3656 le32_to_cpu(bb->use_urgent_burst_bw); 3657 dcn2_0_nv12_soc.num_states = 3658 le32_to_cpu(bb->num_states); 3659 3660 for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) { 3661 dcn2_0_nv12_soc.clock_limits[i].state = 3662 le32_to_cpu(bb->clock_limits[i].state); 3663 dcn2_0_nv12_soc.clock_limits[i].dcfclk_mhz = 3664 fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz); 3665 dcn2_0_nv12_soc.clock_limits[i].fabricclk_mhz = 3666 fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz); 3667 dcn2_0_nv12_soc.clock_limits[i].dispclk_mhz = 3668 fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz); 3669 dcn2_0_nv12_soc.clock_limits[i].dppclk_mhz = 3670 fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz); 3671 dcn2_0_nv12_soc.clock_limits[i].phyclk_mhz = 3672 fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz); 3673 dcn2_0_nv12_soc.clock_limits[i].socclk_mhz = 3674 fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz); 3675 dcn2_0_nv12_soc.clock_limits[i].dscclk_mhz = 3676 fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz); 3677 dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts = 3678 fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts); 3679 } 3680 } 3681 3682 if (pool->base.pp_smu) { 3683 struct pp_smu_nv_clock_table max_clocks = {0}; 3684 unsigned int uclk_states[8] = {0}; 3685 unsigned int num_states = 0; 3686 enum pp_smu_status status; 3687 bool clock_limits_available = false; 3688 bool uclk_states_available = false; 3689 3690 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) { 3691 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) 3692 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); 3693 3694 uclk_states_available = (status == PP_SMU_RESULT_OK); 3695 } 3696 3697 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) { 3698 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) 3699 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks); 3700 /* SMU cannot set DCF clock to anything equal to or higher than SOC clock 3701 */ 3702 if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz) 3703 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000; 3704 clock_limits_available = (status == PP_SMU_RESULT_OK); 3705 } 3706 3707 if (clock_limits_available && uclk_states_available && num_states) 3708 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states); 3709 else if (clock_limits_available) 3710 dcn20_cap_soc_clocks(loaded_bb, max_clocks); 3711 } 3712 3713 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; 3714 loaded_ip->max_num_dpp = pool->base.pipe_count; 3715 dcn20_patch_bounding_box(dc, loaded_bb); 3716 3717 return true; 3718 } 3719 3720 static bool dcn20_resource_construct( 3721 uint8_t num_virtual_links, 3722 struct dc *dc, 3723 struct dcn20_resource_pool *pool) 3724 { 3725 int i; 3726 struct dc_context *ctx = dc->ctx; 3727 struct irq_service_init_data init_data; 3728 struct ddc_service_init_data ddc_init_data; 3729 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = 3730 get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev); 3731 struct _vcs_dpi_ip_params_st *loaded_ip = 3732 get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev); 3733 enum dml_project dml_project_version = 3734 get_dml_project_version(ctx->asic_id.hw_internal_rev); 3735 3736 DC_FP_START(); 3737 3738 ctx->dc_bios->regs = &bios_regs; 3739 pool->base.funcs = &dcn20_res_pool_funcs; 3740 3741 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) { 3742 pool->base.res_cap = &res_cap_nv14; 3743 pool->base.pipe_count = 5; 3744 pool->base.mpcc_count = 5; 3745 } else { 3746 pool->base.res_cap = &res_cap_nv10; 3747 pool->base.pipe_count = 6; 3748 pool->base.mpcc_count = 6; 3749 } 3750 /************************************************* 3751 * Resource + asic cap harcoding * 3752 *************************************************/ 3753 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 3754 3755 dc->caps.max_downscale_ratio = 200; 3756 dc->caps.i2c_speed_in_khz = 100; 3757 dc->caps.max_cursor_size = 256; 3758 dc->caps.dmdata_alloc_size = 2048; 3759 3760 dc->caps.max_slave_planes = 1; 3761 dc->caps.post_blend_color_processing = true; 3762 dc->caps.force_dp_tps4_for_cp2520 = true; 3763 dc->caps.extended_aux_timeout_support = true; 3764 3765 /* Color pipeline capabilities */ 3766 dc->caps.color.dpp.dcn_arch = 1; 3767 dc->caps.color.dpp.input_lut_shared = 0; 3768 dc->caps.color.dpp.icsc = 1; 3769 dc->caps.color.dpp.dgam_ram = 1; 3770 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 3771 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 3772 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0; 3773 dc->caps.color.dpp.dgam_rom_caps.pq = 0; 3774 dc->caps.color.dpp.dgam_rom_caps.hlg = 0; 3775 dc->caps.color.dpp.post_csc = 0; 3776 dc->caps.color.dpp.gamma_corr = 0; 3777 3778 dc->caps.color.dpp.hw_3d_lut = 1; 3779 dc->caps.color.dpp.ogam_ram = 1; 3780 // no OGAM ROM on DCN2, only MPC ROM 3781 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 3782 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 3783 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 3784 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 3785 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 3786 dc->caps.color.dpp.ocsc = 0; 3787 3788 dc->caps.color.mpc.gamut_remap = 0; 3789 dc->caps.color.mpc.num_3dluts = 0; 3790 dc->caps.color.mpc.shared_3d_lut = 0; 3791 dc->caps.color.mpc.ogam_ram = 1; 3792 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 3793 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 3794 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 3795 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 3796 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 3797 dc->caps.color.mpc.ocsc = 1; 3798 3799 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) { 3800 dc->debug = debug_defaults_drv; 3801 } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 3802 pool->base.pipe_count = 4; 3803 pool->base.mpcc_count = pool->base.pipe_count; 3804 dc->debug = debug_defaults_diags; 3805 } else { 3806 dc->debug = debug_defaults_diags; 3807 } 3808 //dcn2.0x 3809 dc->work_arounds.dedcn20_305_wa = true; 3810 3811 // Init the vm_helper 3812 if (dc->vm_helper) 3813 vm_helper_init(dc->vm_helper, 16); 3814 3815 /************************************************* 3816 * Create resources * 3817 *************************************************/ 3818 3819 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = 3820 dcn20_clock_source_create(ctx, ctx->dc_bios, 3821 CLOCK_SOURCE_COMBO_PHY_PLL0, 3822 &clk_src_regs[0], false); 3823 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = 3824 dcn20_clock_source_create(ctx, ctx->dc_bios, 3825 CLOCK_SOURCE_COMBO_PHY_PLL1, 3826 &clk_src_regs[1], false); 3827 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = 3828 dcn20_clock_source_create(ctx, ctx->dc_bios, 3829 CLOCK_SOURCE_COMBO_PHY_PLL2, 3830 &clk_src_regs[2], false); 3831 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] = 3832 dcn20_clock_source_create(ctx, ctx->dc_bios, 3833 CLOCK_SOURCE_COMBO_PHY_PLL3, 3834 &clk_src_regs[3], false); 3835 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] = 3836 dcn20_clock_source_create(ctx, ctx->dc_bios, 3837 CLOCK_SOURCE_COMBO_PHY_PLL4, 3838 &clk_src_regs[4], false); 3839 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] = 3840 dcn20_clock_source_create(ctx, ctx->dc_bios, 3841 CLOCK_SOURCE_COMBO_PHY_PLL5, 3842 &clk_src_regs[5], false); 3843 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL; 3844 /* todo: not reuse phy_pll registers */ 3845 pool->base.dp_clock_source = 3846 dcn20_clock_source_create(ctx, ctx->dc_bios, 3847 CLOCK_SOURCE_ID_DP_DTO, 3848 &clk_src_regs[0], true); 3849 3850 for (i = 0; i < pool->base.clk_src_count; i++) { 3851 if (pool->base.clock_sources[i] == NULL) { 3852 dm_error("DC: failed to create clock sources!\n"); 3853 BREAK_TO_DEBUGGER(); 3854 goto create_fail; 3855 } 3856 } 3857 3858 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 3859 if (pool->base.dccg == NULL) { 3860 dm_error("DC: failed to create dccg!\n"); 3861 BREAK_TO_DEBUGGER(); 3862 goto create_fail; 3863 } 3864 3865 pool->base.dmcu = dcn20_dmcu_create(ctx, 3866 &dmcu_regs, 3867 &dmcu_shift, 3868 &dmcu_mask); 3869 if (pool->base.dmcu == NULL) { 3870 dm_error("DC: failed to create dmcu!\n"); 3871 BREAK_TO_DEBUGGER(); 3872 goto create_fail; 3873 } 3874 3875 pool->base.abm = dce_abm_create(ctx, 3876 &abm_regs, 3877 &abm_shift, 3878 &abm_mask); 3879 if (pool->base.abm == NULL) { 3880 dm_error("DC: failed to create abm!\n"); 3881 BREAK_TO_DEBUGGER(); 3882 goto create_fail; 3883 } 3884 3885 pool->base.pp_smu = dcn20_pp_smu_create(ctx); 3886 3887 3888 if (!init_soc_bounding_box(dc, pool)) { 3889 dm_error("DC: failed to initialize soc bounding box!\n"); 3890 BREAK_TO_DEBUGGER(); 3891 goto create_fail; 3892 } 3893 3894 dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version); 3895 3896 if (!dc->debug.disable_pplib_wm_range) { 3897 struct pp_smu_wm_range_sets ranges = {0}; 3898 int i = 0; 3899 3900 ranges.num_reader_wm_sets = 0; 3901 3902 if (loaded_bb->num_states == 1) { 3903 ranges.reader_wm_sets[0].wm_inst = i; 3904 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3905 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3906 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3907 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3908 3909 ranges.num_reader_wm_sets = 1; 3910 } else if (loaded_bb->num_states > 1) { 3911 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { 3912 ranges.reader_wm_sets[i].wm_inst = i; 3913 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3914 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3915 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; 3916 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; 3917 3918 ranges.num_reader_wm_sets = i + 1; 3919 } 3920 3921 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3922 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3923 } 3924 3925 ranges.num_writer_wm_sets = 1; 3926 3927 ranges.writer_wm_sets[0].wm_inst = 0; 3928 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3929 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3930 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3931 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3932 3933 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 3934 if (pool->base.pp_smu->nv_funcs.set_wm_ranges) 3935 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges); 3936 } 3937 3938 init_data.ctx = dc->ctx; 3939 pool->base.irqs = dal_irq_service_dcn20_create(&init_data); 3940 if (!pool->base.irqs) 3941 goto create_fail; 3942 3943 /* mem input -> ipp -> dpp -> opp -> TG */ 3944 for (i = 0; i < pool->base.pipe_count; i++) { 3945 pool->base.hubps[i] = dcn20_hubp_create(ctx, i); 3946 if (pool->base.hubps[i] == NULL) { 3947 BREAK_TO_DEBUGGER(); 3948 dm_error( 3949 "DC: failed to create memory input!\n"); 3950 goto create_fail; 3951 } 3952 3953 pool->base.ipps[i] = dcn20_ipp_create(ctx, i); 3954 if (pool->base.ipps[i] == NULL) { 3955 BREAK_TO_DEBUGGER(); 3956 dm_error( 3957 "DC: failed to create input pixel processor!\n"); 3958 goto create_fail; 3959 } 3960 3961 pool->base.dpps[i] = dcn20_dpp_create(ctx, i); 3962 if (pool->base.dpps[i] == NULL) { 3963 BREAK_TO_DEBUGGER(); 3964 dm_error( 3965 "DC: failed to create dpps!\n"); 3966 goto create_fail; 3967 } 3968 } 3969 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 3970 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i); 3971 if (pool->base.engines[i] == NULL) { 3972 BREAK_TO_DEBUGGER(); 3973 dm_error( 3974 "DC:failed to create aux engine!!\n"); 3975 goto create_fail; 3976 } 3977 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i); 3978 if (pool->base.hw_i2cs[i] == NULL) { 3979 BREAK_TO_DEBUGGER(); 3980 dm_error( 3981 "DC:failed to create hw i2c!!\n"); 3982 goto create_fail; 3983 } 3984 pool->base.sw_i2cs[i] = NULL; 3985 } 3986 3987 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 3988 pool->base.opps[i] = dcn20_opp_create(ctx, i); 3989 if (pool->base.opps[i] == NULL) { 3990 BREAK_TO_DEBUGGER(); 3991 dm_error( 3992 "DC: failed to create output pixel processor!\n"); 3993 goto create_fail; 3994 } 3995 } 3996 3997 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 3998 pool->base.timing_generators[i] = dcn20_timing_generator_create( 3999 ctx, i); 4000 if (pool->base.timing_generators[i] == NULL) { 4001 BREAK_TO_DEBUGGER(); 4002 dm_error("DC: failed to create tg!\n"); 4003 goto create_fail; 4004 } 4005 } 4006 4007 pool->base.timing_generator_count = i; 4008 4009 pool->base.mpc = dcn20_mpc_create(ctx); 4010 if (pool->base.mpc == NULL) { 4011 BREAK_TO_DEBUGGER(); 4012 dm_error("DC: failed to create mpc!\n"); 4013 goto create_fail; 4014 } 4015 4016 pool->base.hubbub = dcn20_hubbub_create(ctx); 4017 if (pool->base.hubbub == NULL) { 4018 BREAK_TO_DEBUGGER(); 4019 dm_error("DC: failed to create hubbub!\n"); 4020 goto create_fail; 4021 } 4022 4023 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 4024 pool->base.dscs[i] = dcn20_dsc_create(ctx, i); 4025 if (pool->base.dscs[i] == NULL) { 4026 BREAK_TO_DEBUGGER(); 4027 dm_error("DC: failed to create display stream compressor %d!\n", i); 4028 goto create_fail; 4029 } 4030 } 4031 4032 if (!dcn20_dwbc_create(ctx, &pool->base)) { 4033 BREAK_TO_DEBUGGER(); 4034 dm_error("DC: failed to create dwbc!\n"); 4035 goto create_fail; 4036 } 4037 if (!dcn20_mmhubbub_create(ctx, &pool->base)) { 4038 BREAK_TO_DEBUGGER(); 4039 dm_error("DC: failed to create mcif_wb!\n"); 4040 goto create_fail; 4041 } 4042 4043 if (!resource_construct(num_virtual_links, dc, &pool->base, 4044 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 4045 &res_create_funcs : &res_create_maximus_funcs))) 4046 goto create_fail; 4047 4048 dcn20_hw_sequencer_construct(dc); 4049 4050 // IF NV12, set PG function pointer to NULL. It's not that 4051 // PG isn't supported for NV12, it's that we don't want to 4052 // program the registers because that will cause more power 4053 // to be consumed. We could have created dcn20_init_hw to get 4054 // the same effect by checking ASIC rev, but there was a 4055 // request at some point to not check ASIC rev on hw sequencer. 4056 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) 4057 dc->hwseq->funcs.enable_power_gating_plane = NULL; 4058 4059 dc->caps.max_planes = pool->base.pipe_count; 4060 4061 for (i = 0; i < dc->caps.max_planes; ++i) 4062 dc->caps.planes[i] = plane_cap; 4063 4064 dc->cap_funcs = cap_funcs; 4065 4066 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 4067 ddc_init_data.ctx = dc->ctx; 4068 ddc_init_data.link = NULL; 4069 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 4070 ddc_init_data.id.enum_id = 0; 4071 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 4072 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); 4073 } else { 4074 pool->base.oem_device = NULL; 4075 } 4076 4077 DC_FP_END(); 4078 return true; 4079 4080 create_fail: 4081 4082 DC_FP_END(); 4083 dcn20_resource_destruct(pool); 4084 4085 return false; 4086 } 4087 4088 struct resource_pool *dcn20_create_resource_pool( 4089 const struct dc_init_data *init_data, 4090 struct dc *dc) 4091 { 4092 struct dcn20_resource_pool *pool = 4093 kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL); 4094 4095 if (!pool) 4096 return NULL; 4097 4098 if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool)) 4099 return &pool->base; 4100 4101 BREAK_TO_DEBUGGER(); 4102 kfree(pool); 4103 return NULL; 4104 } 4105