1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * Copyright 2019 Raptor Engineering, LLC 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 #include "dc.h" 31 32 #include "dcn20_init.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dcn20/dcn20_resource.h" 37 38 #include "dml/dcn2x/dcn2x.h" 39 40 #include "dcn10/dcn10_hubp.h" 41 #include "dcn10/dcn10_ipp.h" 42 #include "dcn20_hubbub.h" 43 #include "dcn20_mpc.h" 44 #include "dcn20_hubp.h" 45 #include "irq/dcn20/irq_service_dcn20.h" 46 #include "dcn20_dpp.h" 47 #include "dcn20_optc.h" 48 #include "dcn20_hwseq.h" 49 #include "dce110/dce110_hw_sequencer.h" 50 #include "dcn10/dcn10_resource.h" 51 #include "dcn20_opp.h" 52 53 #include "dcn20_dsc.h" 54 55 #include "dcn20_link_encoder.h" 56 #include "dcn20_stream_encoder.h" 57 #include "dce/dce_clock_source.h" 58 #include "dce/dce_audio.h" 59 #include "dce/dce_hwseq.h" 60 #include "virtual/virtual_stream_encoder.h" 61 #include "dce110/dce110_resource.h" 62 #include "dml/display_mode_vba.h" 63 #include "dcn20_dccg.h" 64 #include "dcn20_vmid.h" 65 #include "dc_link_ddc.h" 66 #include "dc_link_dp.h" 67 #include "dce/dce_panel_cntl.h" 68 69 #include "navi10_ip_offset.h" 70 71 #include "dcn/dcn_2_0_0_offset.h" 72 #include "dcn/dcn_2_0_0_sh_mask.h" 73 #include "dpcs/dpcs_2_0_0_offset.h" 74 #include "dpcs/dpcs_2_0_0_sh_mask.h" 75 76 #include "nbio/nbio_2_3_offset.h" 77 78 #include "dcn20/dcn20_dwb.h" 79 #include "dcn20/dcn20_mmhubbub.h" 80 81 #include "mmhub/mmhub_2_0_0_offset.h" 82 #include "mmhub/mmhub_2_0_0_sh_mask.h" 83 84 #include "reg_helper.h" 85 #include "dce/dce_abm.h" 86 #include "dce/dce_dmcu.h" 87 #include "dce/dce_aux.h" 88 #include "dce/dce_i2c.h" 89 #include "vm_helper.h" 90 #include "link_enc_cfg.h" 91 92 #include "amdgpu_socbb.h" 93 94 #define DC_LOGGER_INIT(logger) 95 96 struct _vcs_dpi_ip_params_st dcn2_0_ip = { 97 .odm_capable = 1, 98 .gpuvm_enable = 0, 99 .hostvm_enable = 0, 100 .gpuvm_max_page_table_levels = 4, 101 .hostvm_max_page_table_levels = 4, 102 .hostvm_cached_page_table_levels = 0, 103 .pte_group_size_bytes = 2048, 104 .num_dsc = 6, 105 .rob_buffer_size_kbytes = 168, 106 .det_buffer_size_kbytes = 164, 107 .dpte_buffer_size_in_pte_reqs_luma = 84, 108 .pde_proc_buffer_size_64k_reqs = 48, 109 .dpp_output_buffer_pixels = 2560, 110 .opp_output_buffer_lines = 1, 111 .pixel_chunk_size_kbytes = 8, 112 .pte_chunk_size_kbytes = 2, 113 .meta_chunk_size_kbytes = 2, 114 .writeback_chunk_size_kbytes = 2, 115 .line_buffer_size_bits = 789504, 116 .is_line_buffer_bpp_fixed = 0, 117 .line_buffer_fixed_bpp = 0, 118 .dcc_supported = true, 119 .max_line_buffer_lines = 12, 120 .writeback_luma_buffer_size_kbytes = 12, 121 .writeback_chroma_buffer_size_kbytes = 8, 122 .writeback_chroma_line_buffer_width_pixels = 4, 123 .writeback_max_hscl_ratio = 1, 124 .writeback_max_vscl_ratio = 1, 125 .writeback_min_hscl_ratio = 1, 126 .writeback_min_vscl_ratio = 1, 127 .writeback_max_hscl_taps = 12, 128 .writeback_max_vscl_taps = 12, 129 .writeback_line_buffer_luma_buffer_size = 0, 130 .writeback_line_buffer_chroma_buffer_size = 14643, 131 .cursor_buffer_size = 8, 132 .cursor_chunk_size = 2, 133 .max_num_otg = 6, 134 .max_num_dpp = 6, 135 .max_num_wb = 1, 136 .max_dchub_pscl_bw_pix_per_clk = 4, 137 .max_pscl_lb_bw_pix_per_clk = 2, 138 .max_lb_vscl_bw_pix_per_clk = 4, 139 .max_vscl_hscl_bw_pix_per_clk = 4, 140 .max_hscl_ratio = 8, 141 .max_vscl_ratio = 8, 142 .hscl_mults = 4, 143 .vscl_mults = 4, 144 .max_hscl_taps = 8, 145 .max_vscl_taps = 8, 146 .dispclk_ramp_margin_percent = 1, 147 .underscan_factor = 1.10, 148 .min_vblank_lines = 32, // 149 .dppclk_delay_subtotal = 77, // 150 .dppclk_delay_scl_lb_only = 16, 151 .dppclk_delay_scl = 50, 152 .dppclk_delay_cnvc_formatter = 8, 153 .dppclk_delay_cnvc_cursor = 6, 154 .dispclk_delay_subtotal = 87, // 155 .dcfclk_cstate_latency = 10, // SRExitTime 156 .max_inter_dcn_tile_repeaters = 8, 157 .xfc_supported = true, 158 .xfc_fill_bw_overhead_percent = 10.0, 159 .xfc_fill_constant_bytes = 0, 160 .number_of_cursors = 1, 161 }; 162 163 static struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = { 164 .odm_capable = 1, 165 .gpuvm_enable = 0, 166 .hostvm_enable = 0, 167 .gpuvm_max_page_table_levels = 4, 168 .hostvm_max_page_table_levels = 4, 169 .hostvm_cached_page_table_levels = 0, 170 .num_dsc = 5, 171 .rob_buffer_size_kbytes = 168, 172 .det_buffer_size_kbytes = 164, 173 .dpte_buffer_size_in_pte_reqs_luma = 84, 174 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo 175 .dpp_output_buffer_pixels = 2560, 176 .opp_output_buffer_lines = 1, 177 .pixel_chunk_size_kbytes = 8, 178 .pte_enable = 1, 179 .max_page_table_levels = 4, 180 .pte_chunk_size_kbytes = 2, 181 .meta_chunk_size_kbytes = 2, 182 .writeback_chunk_size_kbytes = 2, 183 .line_buffer_size_bits = 789504, 184 .is_line_buffer_bpp_fixed = 0, 185 .line_buffer_fixed_bpp = 0, 186 .dcc_supported = true, 187 .max_line_buffer_lines = 12, 188 .writeback_luma_buffer_size_kbytes = 12, 189 .writeback_chroma_buffer_size_kbytes = 8, 190 .writeback_chroma_line_buffer_width_pixels = 4, 191 .writeback_max_hscl_ratio = 1, 192 .writeback_max_vscl_ratio = 1, 193 .writeback_min_hscl_ratio = 1, 194 .writeback_min_vscl_ratio = 1, 195 .writeback_max_hscl_taps = 12, 196 .writeback_max_vscl_taps = 12, 197 .writeback_line_buffer_luma_buffer_size = 0, 198 .writeback_line_buffer_chroma_buffer_size = 14643, 199 .cursor_buffer_size = 8, 200 .cursor_chunk_size = 2, 201 .max_num_otg = 5, 202 .max_num_dpp = 5, 203 .max_num_wb = 1, 204 .max_dchub_pscl_bw_pix_per_clk = 4, 205 .max_pscl_lb_bw_pix_per_clk = 2, 206 .max_lb_vscl_bw_pix_per_clk = 4, 207 .max_vscl_hscl_bw_pix_per_clk = 4, 208 .max_hscl_ratio = 8, 209 .max_vscl_ratio = 8, 210 .hscl_mults = 4, 211 .vscl_mults = 4, 212 .max_hscl_taps = 8, 213 .max_vscl_taps = 8, 214 .dispclk_ramp_margin_percent = 1, 215 .underscan_factor = 1.10, 216 .min_vblank_lines = 32, // 217 .dppclk_delay_subtotal = 77, // 218 .dppclk_delay_scl_lb_only = 16, 219 .dppclk_delay_scl = 50, 220 .dppclk_delay_cnvc_formatter = 8, 221 .dppclk_delay_cnvc_cursor = 6, 222 .dispclk_delay_subtotal = 87, // 223 .dcfclk_cstate_latency = 10, // SRExitTime 224 .max_inter_dcn_tile_repeaters = 8, 225 .xfc_supported = true, 226 .xfc_fill_bw_overhead_percent = 10.0, 227 .xfc_fill_constant_bytes = 0, 228 .ptoi_supported = 0, 229 .number_of_cursors = 1, 230 }; 231 232 static struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { 233 /* Defaults that get patched on driver load from firmware. */ 234 .clock_limits = { 235 { 236 .state = 0, 237 .dcfclk_mhz = 560.0, 238 .fabricclk_mhz = 560.0, 239 .dispclk_mhz = 513.0, 240 .dppclk_mhz = 513.0, 241 .phyclk_mhz = 540.0, 242 .socclk_mhz = 560.0, 243 .dscclk_mhz = 171.0, 244 .dram_speed_mts = 8960.0, 245 }, 246 { 247 .state = 1, 248 .dcfclk_mhz = 694.0, 249 .fabricclk_mhz = 694.0, 250 .dispclk_mhz = 642.0, 251 .dppclk_mhz = 642.0, 252 .phyclk_mhz = 600.0, 253 .socclk_mhz = 694.0, 254 .dscclk_mhz = 214.0, 255 .dram_speed_mts = 11104.0, 256 }, 257 { 258 .state = 2, 259 .dcfclk_mhz = 875.0, 260 .fabricclk_mhz = 875.0, 261 .dispclk_mhz = 734.0, 262 .dppclk_mhz = 734.0, 263 .phyclk_mhz = 810.0, 264 .socclk_mhz = 875.0, 265 .dscclk_mhz = 245.0, 266 .dram_speed_mts = 14000.0, 267 }, 268 { 269 .state = 3, 270 .dcfclk_mhz = 1000.0, 271 .fabricclk_mhz = 1000.0, 272 .dispclk_mhz = 1100.0, 273 .dppclk_mhz = 1100.0, 274 .phyclk_mhz = 810.0, 275 .socclk_mhz = 1000.0, 276 .dscclk_mhz = 367.0, 277 .dram_speed_mts = 16000.0, 278 }, 279 { 280 .state = 4, 281 .dcfclk_mhz = 1200.0, 282 .fabricclk_mhz = 1200.0, 283 .dispclk_mhz = 1284.0, 284 .dppclk_mhz = 1284.0, 285 .phyclk_mhz = 810.0, 286 .socclk_mhz = 1200.0, 287 .dscclk_mhz = 428.0, 288 .dram_speed_mts = 16000.0, 289 }, 290 /*Extra state, no dispclk ramping*/ 291 { 292 .state = 5, 293 .dcfclk_mhz = 1200.0, 294 .fabricclk_mhz = 1200.0, 295 .dispclk_mhz = 1284.0, 296 .dppclk_mhz = 1284.0, 297 .phyclk_mhz = 810.0, 298 .socclk_mhz = 1200.0, 299 .dscclk_mhz = 428.0, 300 .dram_speed_mts = 16000.0, 301 }, 302 }, 303 .num_states = 5, 304 .sr_exit_time_us = 8.6, 305 .sr_enter_plus_exit_time_us = 10.9, 306 .urgent_latency_us = 4.0, 307 .urgent_latency_pixel_data_only_us = 4.0, 308 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 309 .urgent_latency_vm_data_only_us = 4.0, 310 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 311 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 312 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 313 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0, 314 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0, 315 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 316 .max_avg_sdp_bw_use_normal_percent = 40.0, 317 .max_avg_dram_bw_use_normal_percent = 40.0, 318 .writeback_latency_us = 12.0, 319 .ideal_dram_bw_after_urgent_percent = 40.0, 320 .max_request_size_bytes = 256, 321 .dram_channel_width_bytes = 2, 322 .fabric_datapath_to_dcn_data_return_bytes = 64, 323 .dcn_downspread_percent = 0.5, 324 .downspread_percent = 0.38, 325 .dram_page_open_time_ns = 50.0, 326 .dram_rw_turnaround_time_ns = 17.5, 327 .dram_return_buffer_per_channel_bytes = 8192, 328 .round_trip_ping_latency_dcfclk_cycles = 131, 329 .urgent_out_of_order_return_per_channel_bytes = 256, 330 .channel_interleave_bytes = 256, 331 .num_banks = 8, 332 .num_chans = 16, 333 .vmm_page_size_bytes = 4096, 334 .dram_clock_change_latency_us = 404.0, 335 .dummy_pstate_latency_us = 5.0, 336 .writeback_dram_clock_change_latency_us = 23.0, 337 .return_bus_width_bytes = 64, 338 .dispclk_dppclk_vco_speed_mhz = 3850, 339 .xfc_bus_transport_time_us = 20, 340 .xfc_xbuf_latency_tolerance_us = 4, 341 .use_urgent_burst_bw = 0 342 }; 343 344 static struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = { 345 .clock_limits = { 346 { 347 .state = 0, 348 .dcfclk_mhz = 560.0, 349 .fabricclk_mhz = 560.0, 350 .dispclk_mhz = 513.0, 351 .dppclk_mhz = 513.0, 352 .phyclk_mhz = 540.0, 353 .socclk_mhz = 560.0, 354 .dscclk_mhz = 171.0, 355 .dram_speed_mts = 8960.0, 356 }, 357 { 358 .state = 1, 359 .dcfclk_mhz = 694.0, 360 .fabricclk_mhz = 694.0, 361 .dispclk_mhz = 642.0, 362 .dppclk_mhz = 642.0, 363 .phyclk_mhz = 600.0, 364 .socclk_mhz = 694.0, 365 .dscclk_mhz = 214.0, 366 .dram_speed_mts = 11104.0, 367 }, 368 { 369 .state = 2, 370 .dcfclk_mhz = 875.0, 371 .fabricclk_mhz = 875.0, 372 .dispclk_mhz = 734.0, 373 .dppclk_mhz = 734.0, 374 .phyclk_mhz = 810.0, 375 .socclk_mhz = 875.0, 376 .dscclk_mhz = 245.0, 377 .dram_speed_mts = 14000.0, 378 }, 379 { 380 .state = 3, 381 .dcfclk_mhz = 1000.0, 382 .fabricclk_mhz = 1000.0, 383 .dispclk_mhz = 1100.0, 384 .dppclk_mhz = 1100.0, 385 .phyclk_mhz = 810.0, 386 .socclk_mhz = 1000.0, 387 .dscclk_mhz = 367.0, 388 .dram_speed_mts = 16000.0, 389 }, 390 { 391 .state = 4, 392 .dcfclk_mhz = 1200.0, 393 .fabricclk_mhz = 1200.0, 394 .dispclk_mhz = 1284.0, 395 .dppclk_mhz = 1284.0, 396 .phyclk_mhz = 810.0, 397 .socclk_mhz = 1200.0, 398 .dscclk_mhz = 428.0, 399 .dram_speed_mts = 16000.0, 400 }, 401 /*Extra state, no dispclk ramping*/ 402 { 403 .state = 5, 404 .dcfclk_mhz = 1200.0, 405 .fabricclk_mhz = 1200.0, 406 .dispclk_mhz = 1284.0, 407 .dppclk_mhz = 1284.0, 408 .phyclk_mhz = 810.0, 409 .socclk_mhz = 1200.0, 410 .dscclk_mhz = 428.0, 411 .dram_speed_mts = 16000.0, 412 }, 413 }, 414 .num_states = 5, 415 .sr_exit_time_us = 11.6, 416 .sr_enter_plus_exit_time_us = 13.9, 417 .urgent_latency_us = 4.0, 418 .urgent_latency_pixel_data_only_us = 4.0, 419 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 420 .urgent_latency_vm_data_only_us = 4.0, 421 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 422 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 423 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 424 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0, 425 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0, 426 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 427 .max_avg_sdp_bw_use_normal_percent = 40.0, 428 .max_avg_dram_bw_use_normal_percent = 40.0, 429 .writeback_latency_us = 12.0, 430 .ideal_dram_bw_after_urgent_percent = 40.0, 431 .max_request_size_bytes = 256, 432 .dram_channel_width_bytes = 2, 433 .fabric_datapath_to_dcn_data_return_bytes = 64, 434 .dcn_downspread_percent = 0.5, 435 .downspread_percent = 0.38, 436 .dram_page_open_time_ns = 50.0, 437 .dram_rw_turnaround_time_ns = 17.5, 438 .dram_return_buffer_per_channel_bytes = 8192, 439 .round_trip_ping_latency_dcfclk_cycles = 131, 440 .urgent_out_of_order_return_per_channel_bytes = 256, 441 .channel_interleave_bytes = 256, 442 .num_banks = 8, 443 .num_chans = 8, 444 .vmm_page_size_bytes = 4096, 445 .dram_clock_change_latency_us = 404.0, 446 .dummy_pstate_latency_us = 5.0, 447 .writeback_dram_clock_change_latency_us = 23.0, 448 .return_bus_width_bytes = 64, 449 .dispclk_dppclk_vco_speed_mhz = 3850, 450 .xfc_bus_transport_time_us = 20, 451 .xfc_xbuf_latency_tolerance_us = 4, 452 .use_urgent_burst_bw = 0 453 }; 454 455 static struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 }; 456 457 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 458 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 459 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 460 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 461 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 462 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 463 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 464 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 465 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 466 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 467 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 468 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 469 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 470 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 471 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 472 #endif 473 474 475 enum dcn20_clk_src_array_id { 476 DCN20_CLK_SRC_PLL0, 477 DCN20_CLK_SRC_PLL1, 478 DCN20_CLK_SRC_PLL2, 479 DCN20_CLK_SRC_PLL3, 480 DCN20_CLK_SRC_PLL4, 481 DCN20_CLK_SRC_PLL5, 482 DCN20_CLK_SRC_TOTAL 483 }; 484 485 /* begin ********************* 486 * macros to expend register list macro defined in HW object header file */ 487 488 /* DCN */ 489 /* TODO awful hack. fixup dcn20_dwb.h */ 490 #undef BASE_INNER 491 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 492 493 #define BASE(seg) BASE_INNER(seg) 494 495 #define SR(reg_name)\ 496 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 497 mm ## reg_name 498 499 #define SRI(reg_name, block, id)\ 500 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 501 mm ## block ## id ## _ ## reg_name 502 503 #define SRIR(var_name, reg_name, block, id)\ 504 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 505 mm ## block ## id ## _ ## reg_name 506 507 #define SRII(reg_name, block, id)\ 508 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 509 mm ## block ## id ## _ ## reg_name 510 511 #define DCCG_SRII(reg_name, block, id)\ 512 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 513 mm ## block ## id ## _ ## reg_name 514 515 #define VUPDATE_SRII(reg_name, block, id)\ 516 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 517 mm ## reg_name ## _ ## block ## id 518 519 /* NBIO */ 520 #define NBIO_BASE_INNER(seg) \ 521 NBIO_BASE__INST0_SEG ## seg 522 523 #define NBIO_BASE(seg) \ 524 NBIO_BASE_INNER(seg) 525 526 #define NBIO_SR(reg_name)\ 527 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 528 mm ## reg_name 529 530 /* MMHUB */ 531 #define MMHUB_BASE_INNER(seg) \ 532 MMHUB_BASE__INST0_SEG ## seg 533 534 #define MMHUB_BASE(seg) \ 535 MMHUB_BASE_INNER(seg) 536 537 #define MMHUB_SR(reg_name)\ 538 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 539 mmMM ## reg_name 540 541 static const struct bios_registers bios_regs = { 542 NBIO_SR(BIOS_SCRATCH_3), 543 NBIO_SR(BIOS_SCRATCH_6) 544 }; 545 546 #define clk_src_regs(index, pllid)\ 547 [index] = {\ 548 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\ 549 } 550 551 static const struct dce110_clk_src_regs clk_src_regs[] = { 552 clk_src_regs(0, A), 553 clk_src_regs(1, B), 554 clk_src_regs(2, C), 555 clk_src_regs(3, D), 556 clk_src_regs(4, E), 557 clk_src_regs(5, F) 558 }; 559 560 static const struct dce110_clk_src_shift cs_shift = { 561 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 562 }; 563 564 static const struct dce110_clk_src_mask cs_mask = { 565 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 566 }; 567 568 static const struct dce_dmcu_registers dmcu_regs = { 569 DMCU_DCN10_REG_LIST() 570 }; 571 572 static const struct dce_dmcu_shift dmcu_shift = { 573 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 574 }; 575 576 static const struct dce_dmcu_mask dmcu_mask = { 577 DMCU_MASK_SH_LIST_DCN10(_MASK) 578 }; 579 580 static const struct dce_abm_registers abm_regs = { 581 ABM_DCN20_REG_LIST() 582 }; 583 584 static const struct dce_abm_shift abm_shift = { 585 ABM_MASK_SH_LIST_DCN20(__SHIFT) 586 }; 587 588 static const struct dce_abm_mask abm_mask = { 589 ABM_MASK_SH_LIST_DCN20(_MASK) 590 }; 591 592 #define audio_regs(id)\ 593 [id] = {\ 594 AUD_COMMON_REG_LIST(id)\ 595 } 596 597 static const struct dce_audio_registers audio_regs[] = { 598 audio_regs(0), 599 audio_regs(1), 600 audio_regs(2), 601 audio_regs(3), 602 audio_regs(4), 603 audio_regs(5), 604 audio_regs(6), 605 }; 606 607 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 608 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 609 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 610 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 611 612 static const struct dce_audio_shift audio_shift = { 613 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 614 }; 615 616 static const struct dce_audio_mask audio_mask = { 617 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 618 }; 619 620 #define stream_enc_regs(id)\ 621 [id] = {\ 622 SE_DCN2_REG_LIST(id)\ 623 } 624 625 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 626 stream_enc_regs(0), 627 stream_enc_regs(1), 628 stream_enc_regs(2), 629 stream_enc_regs(3), 630 stream_enc_regs(4), 631 stream_enc_regs(5), 632 }; 633 634 static const struct dcn10_stream_encoder_shift se_shift = { 635 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) 636 }; 637 638 static const struct dcn10_stream_encoder_mask se_mask = { 639 SE_COMMON_MASK_SH_LIST_DCN20(_MASK) 640 }; 641 642 643 #define aux_regs(id)\ 644 [id] = {\ 645 DCN2_AUX_REG_LIST(id)\ 646 } 647 648 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 649 aux_regs(0), 650 aux_regs(1), 651 aux_regs(2), 652 aux_regs(3), 653 aux_regs(4), 654 aux_regs(5) 655 }; 656 657 #define hpd_regs(id)\ 658 [id] = {\ 659 HPD_REG_LIST(id)\ 660 } 661 662 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 663 hpd_regs(0), 664 hpd_regs(1), 665 hpd_regs(2), 666 hpd_regs(3), 667 hpd_regs(4), 668 hpd_regs(5) 669 }; 670 671 #define link_regs(id, phyid)\ 672 [id] = {\ 673 LE_DCN10_REG_LIST(id), \ 674 UNIPHY_DCN2_REG_LIST(phyid), \ 675 DPCS_DCN2_REG_LIST(id), \ 676 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 677 } 678 679 static const struct dcn10_link_enc_registers link_enc_regs[] = { 680 link_regs(0, A), 681 link_regs(1, B), 682 link_regs(2, C), 683 link_regs(3, D), 684 link_regs(4, E), 685 link_regs(5, F) 686 }; 687 688 static const struct dcn10_link_enc_shift le_shift = { 689 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\ 690 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 691 }; 692 693 static const struct dcn10_link_enc_mask le_mask = { 694 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\ 695 DPCS_DCN2_MASK_SH_LIST(_MASK) 696 }; 697 698 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 699 { DCN_PANEL_CNTL_REG_LIST() } 700 }; 701 702 static const struct dce_panel_cntl_shift panel_cntl_shift = { 703 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 704 }; 705 706 static const struct dce_panel_cntl_mask panel_cntl_mask = { 707 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 708 }; 709 710 #define ipp_regs(id)\ 711 [id] = {\ 712 IPP_REG_LIST_DCN20(id),\ 713 } 714 715 static const struct dcn10_ipp_registers ipp_regs[] = { 716 ipp_regs(0), 717 ipp_regs(1), 718 ipp_regs(2), 719 ipp_regs(3), 720 ipp_regs(4), 721 ipp_regs(5), 722 }; 723 724 static const struct dcn10_ipp_shift ipp_shift = { 725 IPP_MASK_SH_LIST_DCN20(__SHIFT) 726 }; 727 728 static const struct dcn10_ipp_mask ipp_mask = { 729 IPP_MASK_SH_LIST_DCN20(_MASK), 730 }; 731 732 #define opp_regs(id)\ 733 [id] = {\ 734 OPP_REG_LIST_DCN20(id),\ 735 } 736 737 static const struct dcn20_opp_registers opp_regs[] = { 738 opp_regs(0), 739 opp_regs(1), 740 opp_regs(2), 741 opp_regs(3), 742 opp_regs(4), 743 opp_regs(5), 744 }; 745 746 static const struct dcn20_opp_shift opp_shift = { 747 OPP_MASK_SH_LIST_DCN20(__SHIFT) 748 }; 749 750 static const struct dcn20_opp_mask opp_mask = { 751 OPP_MASK_SH_LIST_DCN20(_MASK) 752 }; 753 754 #define aux_engine_regs(id)\ 755 [id] = {\ 756 AUX_COMMON_REG_LIST0(id), \ 757 .AUXN_IMPCAL = 0, \ 758 .AUXP_IMPCAL = 0, \ 759 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 760 } 761 762 static const struct dce110_aux_registers aux_engine_regs[] = { 763 aux_engine_regs(0), 764 aux_engine_regs(1), 765 aux_engine_regs(2), 766 aux_engine_regs(3), 767 aux_engine_regs(4), 768 aux_engine_regs(5) 769 }; 770 771 #define tf_regs(id)\ 772 [id] = {\ 773 TF_REG_LIST_DCN20(id),\ 774 TF_REG_LIST_DCN20_COMMON_APPEND(id),\ 775 } 776 777 static const struct dcn2_dpp_registers tf_regs[] = { 778 tf_regs(0), 779 tf_regs(1), 780 tf_regs(2), 781 tf_regs(3), 782 tf_regs(4), 783 tf_regs(5), 784 }; 785 786 static const struct dcn2_dpp_shift tf_shift = { 787 TF_REG_LIST_SH_MASK_DCN20(__SHIFT), 788 TF_DEBUG_REG_LIST_SH_DCN20 789 }; 790 791 static const struct dcn2_dpp_mask tf_mask = { 792 TF_REG_LIST_SH_MASK_DCN20(_MASK), 793 TF_DEBUG_REG_LIST_MASK_DCN20 794 }; 795 796 #define dwbc_regs_dcn2(id)\ 797 [id] = {\ 798 DWBC_COMMON_REG_LIST_DCN2_0(id),\ 799 } 800 801 static const struct dcn20_dwbc_registers dwbc20_regs[] = { 802 dwbc_regs_dcn2(0), 803 }; 804 805 static const struct dcn20_dwbc_shift dwbc20_shift = { 806 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 807 }; 808 809 static const struct dcn20_dwbc_mask dwbc20_mask = { 810 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 811 }; 812 813 #define mcif_wb_regs_dcn2(id)\ 814 [id] = {\ 815 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\ 816 } 817 818 static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = { 819 mcif_wb_regs_dcn2(0), 820 }; 821 822 static const struct dcn20_mmhubbub_shift mcif_wb20_shift = { 823 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 824 }; 825 826 static const struct dcn20_mmhubbub_mask mcif_wb20_mask = { 827 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 828 }; 829 830 static const struct dcn20_mpc_registers mpc_regs = { 831 MPC_REG_LIST_DCN2_0(0), 832 MPC_REG_LIST_DCN2_0(1), 833 MPC_REG_LIST_DCN2_0(2), 834 MPC_REG_LIST_DCN2_0(3), 835 MPC_REG_LIST_DCN2_0(4), 836 MPC_REG_LIST_DCN2_0(5), 837 MPC_OUT_MUX_REG_LIST_DCN2_0(0), 838 MPC_OUT_MUX_REG_LIST_DCN2_0(1), 839 MPC_OUT_MUX_REG_LIST_DCN2_0(2), 840 MPC_OUT_MUX_REG_LIST_DCN2_0(3), 841 MPC_OUT_MUX_REG_LIST_DCN2_0(4), 842 MPC_OUT_MUX_REG_LIST_DCN2_0(5), 843 MPC_DBG_REG_LIST_DCN2_0() 844 }; 845 846 static const struct dcn20_mpc_shift mpc_shift = { 847 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT), 848 MPC_DEBUG_REG_LIST_SH_DCN20 849 }; 850 851 static const struct dcn20_mpc_mask mpc_mask = { 852 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK), 853 MPC_DEBUG_REG_LIST_MASK_DCN20 854 }; 855 856 #define tg_regs(id)\ 857 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)} 858 859 860 static const struct dcn_optc_registers tg_regs[] = { 861 tg_regs(0), 862 tg_regs(1), 863 tg_regs(2), 864 tg_regs(3), 865 tg_regs(4), 866 tg_regs(5) 867 }; 868 869 static const struct dcn_optc_shift tg_shift = { 870 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 871 }; 872 873 static const struct dcn_optc_mask tg_mask = { 874 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 875 }; 876 877 #define hubp_regs(id)\ 878 [id] = {\ 879 HUBP_REG_LIST_DCN20(id)\ 880 } 881 882 static const struct dcn_hubp2_registers hubp_regs[] = { 883 hubp_regs(0), 884 hubp_regs(1), 885 hubp_regs(2), 886 hubp_regs(3), 887 hubp_regs(4), 888 hubp_regs(5) 889 }; 890 891 static const struct dcn_hubp2_shift hubp_shift = { 892 HUBP_MASK_SH_LIST_DCN20(__SHIFT) 893 }; 894 895 static const struct dcn_hubp2_mask hubp_mask = { 896 HUBP_MASK_SH_LIST_DCN20(_MASK) 897 }; 898 899 static const struct dcn_hubbub_registers hubbub_reg = { 900 HUBBUB_REG_LIST_DCN20(0) 901 }; 902 903 static const struct dcn_hubbub_shift hubbub_shift = { 904 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT) 905 }; 906 907 static const struct dcn_hubbub_mask hubbub_mask = { 908 HUBBUB_MASK_SH_LIST_DCN20(_MASK) 909 }; 910 911 #define vmid_regs(id)\ 912 [id] = {\ 913 DCN20_VMID_REG_LIST(id)\ 914 } 915 916 static const struct dcn_vmid_registers vmid_regs[] = { 917 vmid_regs(0), 918 vmid_regs(1), 919 vmid_regs(2), 920 vmid_regs(3), 921 vmid_regs(4), 922 vmid_regs(5), 923 vmid_regs(6), 924 vmid_regs(7), 925 vmid_regs(8), 926 vmid_regs(9), 927 vmid_regs(10), 928 vmid_regs(11), 929 vmid_regs(12), 930 vmid_regs(13), 931 vmid_regs(14), 932 vmid_regs(15) 933 }; 934 935 static const struct dcn20_vmid_shift vmid_shifts = { 936 DCN20_VMID_MASK_SH_LIST(__SHIFT) 937 }; 938 939 static const struct dcn20_vmid_mask vmid_masks = { 940 DCN20_VMID_MASK_SH_LIST(_MASK) 941 }; 942 943 static const struct dce110_aux_registers_shift aux_shift = { 944 DCN_AUX_MASK_SH_LIST(__SHIFT) 945 }; 946 947 static const struct dce110_aux_registers_mask aux_mask = { 948 DCN_AUX_MASK_SH_LIST(_MASK) 949 }; 950 951 static int map_transmitter_id_to_phy_instance( 952 enum transmitter transmitter) 953 { 954 switch (transmitter) { 955 case TRANSMITTER_UNIPHY_A: 956 return 0; 957 break; 958 case TRANSMITTER_UNIPHY_B: 959 return 1; 960 break; 961 case TRANSMITTER_UNIPHY_C: 962 return 2; 963 break; 964 case TRANSMITTER_UNIPHY_D: 965 return 3; 966 break; 967 case TRANSMITTER_UNIPHY_E: 968 return 4; 969 break; 970 case TRANSMITTER_UNIPHY_F: 971 return 5; 972 break; 973 default: 974 ASSERT(0); 975 return 0; 976 } 977 } 978 979 #define dsc_regsDCN20(id)\ 980 [id] = {\ 981 DSC_REG_LIST_DCN20(id)\ 982 } 983 984 static const struct dcn20_dsc_registers dsc_regs[] = { 985 dsc_regsDCN20(0), 986 dsc_regsDCN20(1), 987 dsc_regsDCN20(2), 988 dsc_regsDCN20(3), 989 dsc_regsDCN20(4), 990 dsc_regsDCN20(5) 991 }; 992 993 static const struct dcn20_dsc_shift dsc_shift = { 994 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 995 }; 996 997 static const struct dcn20_dsc_mask dsc_mask = { 998 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 999 }; 1000 1001 static const struct dccg_registers dccg_regs = { 1002 DCCG_REG_LIST_DCN2() 1003 }; 1004 1005 static const struct dccg_shift dccg_shift = { 1006 DCCG_MASK_SH_LIST_DCN2(__SHIFT) 1007 }; 1008 1009 static const struct dccg_mask dccg_mask = { 1010 DCCG_MASK_SH_LIST_DCN2(_MASK) 1011 }; 1012 1013 static const struct resource_caps res_cap_nv10 = { 1014 .num_timing_generator = 6, 1015 .num_opp = 6, 1016 .num_video_plane = 6, 1017 .num_audio = 7, 1018 .num_stream_encoder = 6, 1019 .num_pll = 6, 1020 .num_dwb = 1, 1021 .num_ddc = 6, 1022 .num_vmid = 16, 1023 .num_dsc = 6, 1024 }; 1025 1026 static const struct dc_plane_cap plane_cap = { 1027 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 1028 .blends_with_above = true, 1029 .blends_with_below = true, 1030 .per_pixel_alpha = true, 1031 1032 .pixel_format_support = { 1033 .argb8888 = true, 1034 .nv12 = true, 1035 .fp16 = true, 1036 .p010 = true 1037 }, 1038 1039 .max_upscale_factor = { 1040 .argb8888 = 16000, 1041 .nv12 = 16000, 1042 .fp16 = 1 1043 }, 1044 1045 .max_downscale_factor = { 1046 .argb8888 = 250, 1047 .nv12 = 250, 1048 .fp16 = 1 1049 }, 1050 16, 1051 16 1052 }; 1053 static const struct resource_caps res_cap_nv14 = { 1054 .num_timing_generator = 5, 1055 .num_opp = 5, 1056 .num_video_plane = 5, 1057 .num_audio = 6, 1058 .num_stream_encoder = 5, 1059 .num_pll = 5, 1060 .num_dwb = 1, 1061 .num_ddc = 5, 1062 .num_vmid = 16, 1063 .num_dsc = 5, 1064 }; 1065 1066 static const struct dc_debug_options debug_defaults_drv = { 1067 .disable_dmcu = false, 1068 .force_abm_enable = false, 1069 .timing_trace = false, 1070 .clock_trace = true, 1071 .disable_pplib_clock_request = true, 1072 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 1073 .force_single_disp_pipe_split = false, 1074 .disable_dcc = DCC_ENABLE, 1075 .vsr_support = true, 1076 .performance_trace = false, 1077 .max_downscale_src_width = 5120,/*upto 5K*/ 1078 .disable_pplib_wm_range = false, 1079 .scl_reset_length10 = true, 1080 .sanity_checks = false, 1081 .underflow_assert_delay_us = 0xFFFFFFFF, 1082 }; 1083 1084 static const struct dc_debug_options debug_defaults_diags = { 1085 .disable_dmcu = false, 1086 .force_abm_enable = false, 1087 .timing_trace = true, 1088 .clock_trace = true, 1089 .disable_dpp_power_gate = true, 1090 .disable_hubp_power_gate = true, 1091 .disable_clock_gate = true, 1092 .disable_pplib_clock_request = true, 1093 .disable_pplib_wm_range = true, 1094 .disable_stutter = true, 1095 .scl_reset_length10 = true, 1096 .underflow_assert_delay_us = 0xFFFFFFFF, 1097 .enable_tri_buf = true, 1098 }; 1099 1100 void dcn20_dpp_destroy(struct dpp **dpp) 1101 { 1102 kfree(TO_DCN20_DPP(*dpp)); 1103 *dpp = NULL; 1104 } 1105 1106 struct dpp *dcn20_dpp_create( 1107 struct dc_context *ctx, 1108 uint32_t inst) 1109 { 1110 struct dcn20_dpp *dpp = 1111 kzalloc(sizeof(struct dcn20_dpp), GFP_ATOMIC); 1112 1113 if (!dpp) 1114 return NULL; 1115 1116 if (dpp2_construct(dpp, ctx, inst, 1117 &tf_regs[inst], &tf_shift, &tf_mask)) 1118 return &dpp->base; 1119 1120 BREAK_TO_DEBUGGER(); 1121 kfree(dpp); 1122 return NULL; 1123 } 1124 1125 struct input_pixel_processor *dcn20_ipp_create( 1126 struct dc_context *ctx, uint32_t inst) 1127 { 1128 struct dcn10_ipp *ipp = 1129 kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC); 1130 1131 if (!ipp) { 1132 BREAK_TO_DEBUGGER(); 1133 return NULL; 1134 } 1135 1136 dcn20_ipp_construct(ipp, ctx, inst, 1137 &ipp_regs[inst], &ipp_shift, &ipp_mask); 1138 return &ipp->base; 1139 } 1140 1141 1142 struct output_pixel_processor *dcn20_opp_create( 1143 struct dc_context *ctx, uint32_t inst) 1144 { 1145 struct dcn20_opp *opp = 1146 kzalloc(sizeof(struct dcn20_opp), GFP_ATOMIC); 1147 1148 if (!opp) { 1149 BREAK_TO_DEBUGGER(); 1150 return NULL; 1151 } 1152 1153 dcn20_opp_construct(opp, ctx, inst, 1154 &opp_regs[inst], &opp_shift, &opp_mask); 1155 return &opp->base; 1156 } 1157 1158 struct dce_aux *dcn20_aux_engine_create( 1159 struct dc_context *ctx, 1160 uint32_t inst) 1161 { 1162 struct aux_engine_dce110 *aux_engine = 1163 kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC); 1164 1165 if (!aux_engine) 1166 return NULL; 1167 1168 dce110_aux_engine_construct(aux_engine, ctx, inst, 1169 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1170 &aux_engine_regs[inst], 1171 &aux_mask, 1172 &aux_shift, 1173 ctx->dc->caps.extended_aux_timeout_support); 1174 1175 return &aux_engine->base; 1176 } 1177 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 1178 1179 static const struct dce_i2c_registers i2c_hw_regs[] = { 1180 i2c_inst_regs(1), 1181 i2c_inst_regs(2), 1182 i2c_inst_regs(3), 1183 i2c_inst_regs(4), 1184 i2c_inst_regs(5), 1185 i2c_inst_regs(6), 1186 }; 1187 1188 static const struct dce_i2c_shift i2c_shifts = { 1189 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 1190 }; 1191 1192 static const struct dce_i2c_mask i2c_masks = { 1193 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 1194 }; 1195 1196 struct dce_i2c_hw *dcn20_i2c_hw_create( 1197 struct dc_context *ctx, 1198 uint32_t inst) 1199 { 1200 struct dce_i2c_hw *dce_i2c_hw = 1201 kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC); 1202 1203 if (!dce_i2c_hw) 1204 return NULL; 1205 1206 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1207 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1208 1209 return dce_i2c_hw; 1210 } 1211 struct mpc *dcn20_mpc_create(struct dc_context *ctx) 1212 { 1213 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), 1214 GFP_ATOMIC); 1215 1216 if (!mpc20) 1217 return NULL; 1218 1219 dcn20_mpc_construct(mpc20, ctx, 1220 &mpc_regs, 1221 &mpc_shift, 1222 &mpc_mask, 1223 6); 1224 1225 return &mpc20->base; 1226 } 1227 1228 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx) 1229 { 1230 int i; 1231 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), 1232 GFP_ATOMIC); 1233 1234 if (!hubbub) 1235 return NULL; 1236 1237 hubbub2_construct(hubbub, ctx, 1238 &hubbub_reg, 1239 &hubbub_shift, 1240 &hubbub_mask); 1241 1242 for (i = 0; i < res_cap_nv10.num_vmid; i++) { 1243 struct dcn20_vmid *vmid = &hubbub->vmid[i]; 1244 1245 vmid->ctx = ctx; 1246 1247 vmid->regs = &vmid_regs[i]; 1248 vmid->shifts = &vmid_shifts; 1249 vmid->masks = &vmid_masks; 1250 } 1251 1252 return &hubbub->base; 1253 } 1254 1255 struct timing_generator *dcn20_timing_generator_create( 1256 struct dc_context *ctx, 1257 uint32_t instance) 1258 { 1259 struct optc *tgn10 = 1260 kzalloc(sizeof(struct optc), GFP_ATOMIC); 1261 1262 if (!tgn10) 1263 return NULL; 1264 1265 tgn10->base.inst = instance; 1266 tgn10->base.ctx = ctx; 1267 1268 tgn10->tg_regs = &tg_regs[instance]; 1269 tgn10->tg_shift = &tg_shift; 1270 tgn10->tg_mask = &tg_mask; 1271 1272 dcn20_timing_generator_init(tgn10); 1273 1274 return &tgn10->base; 1275 } 1276 1277 static const struct encoder_feature_support link_enc_feature = { 1278 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1279 .max_hdmi_pixel_clock = 600000, 1280 .hdmi_ycbcr420_supported = true, 1281 .dp_ycbcr420_supported = true, 1282 .fec_supported = true, 1283 .flags.bits.IS_HBR2_CAPABLE = true, 1284 .flags.bits.IS_HBR3_CAPABLE = true, 1285 .flags.bits.IS_TPS3_CAPABLE = true, 1286 .flags.bits.IS_TPS4_CAPABLE = true 1287 }; 1288 1289 struct link_encoder *dcn20_link_encoder_create( 1290 const struct encoder_init_data *enc_init_data) 1291 { 1292 struct dcn20_link_encoder *enc20 = 1293 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1294 int link_regs_id; 1295 1296 if (!enc20) 1297 return NULL; 1298 1299 link_regs_id = 1300 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 1301 1302 dcn20_link_encoder_construct(enc20, 1303 enc_init_data, 1304 &link_enc_feature, 1305 &link_enc_regs[link_regs_id], 1306 &link_enc_aux_regs[enc_init_data->channel - 1], 1307 &link_enc_hpd_regs[enc_init_data->hpd_source], 1308 &le_shift, 1309 &le_mask); 1310 1311 return &enc20->enc10.base; 1312 } 1313 1314 static struct panel_cntl *dcn20_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1315 { 1316 struct dce_panel_cntl *panel_cntl = 1317 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 1318 1319 if (!panel_cntl) 1320 return NULL; 1321 1322 dce_panel_cntl_construct(panel_cntl, 1323 init_data, 1324 &panel_cntl_regs[init_data->inst], 1325 &panel_cntl_shift, 1326 &panel_cntl_mask); 1327 1328 return &panel_cntl->base; 1329 } 1330 1331 static struct clock_source *dcn20_clock_source_create( 1332 struct dc_context *ctx, 1333 struct dc_bios *bios, 1334 enum clock_source_id id, 1335 const struct dce110_clk_src_regs *regs, 1336 bool dp_clk_src) 1337 { 1338 struct dce110_clk_src *clk_src = 1339 kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC); 1340 1341 if (!clk_src) 1342 return NULL; 1343 1344 if (dcn20_clk_src_construct(clk_src, ctx, bios, id, 1345 regs, &cs_shift, &cs_mask)) { 1346 clk_src->base.dp_clk_src = dp_clk_src; 1347 return &clk_src->base; 1348 } 1349 1350 kfree(clk_src); 1351 BREAK_TO_DEBUGGER(); 1352 return NULL; 1353 } 1354 1355 static void read_dce_straps( 1356 struct dc_context *ctx, 1357 struct resource_straps *straps) 1358 { 1359 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1360 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1361 } 1362 1363 static struct audio *dcn20_create_audio( 1364 struct dc_context *ctx, unsigned int inst) 1365 { 1366 return dce_audio_create(ctx, inst, 1367 &audio_regs[inst], &audio_shift, &audio_mask); 1368 } 1369 1370 struct stream_encoder *dcn20_stream_encoder_create( 1371 enum engine_id eng_id, 1372 struct dc_context *ctx) 1373 { 1374 struct dcn10_stream_encoder *enc1 = 1375 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1376 1377 if (!enc1) 1378 return NULL; 1379 1380 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) { 1381 if (eng_id >= ENGINE_ID_DIGD) 1382 eng_id++; 1383 } 1384 1385 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1386 &stream_enc_regs[eng_id], 1387 &se_shift, &se_mask); 1388 1389 return &enc1->base; 1390 } 1391 1392 static const struct dce_hwseq_registers hwseq_reg = { 1393 HWSEQ_DCN2_REG_LIST() 1394 }; 1395 1396 static const struct dce_hwseq_shift hwseq_shift = { 1397 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT) 1398 }; 1399 1400 static const struct dce_hwseq_mask hwseq_mask = { 1401 HWSEQ_DCN2_MASK_SH_LIST(_MASK) 1402 }; 1403 1404 struct dce_hwseq *dcn20_hwseq_create( 1405 struct dc_context *ctx) 1406 { 1407 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1408 1409 if (hws) { 1410 hws->ctx = ctx; 1411 hws->regs = &hwseq_reg; 1412 hws->shifts = &hwseq_shift; 1413 hws->masks = &hwseq_mask; 1414 } 1415 return hws; 1416 } 1417 1418 static const struct resource_create_funcs res_create_funcs = { 1419 .read_dce_straps = read_dce_straps, 1420 .create_audio = dcn20_create_audio, 1421 .create_stream_encoder = dcn20_stream_encoder_create, 1422 .create_hwseq = dcn20_hwseq_create, 1423 }; 1424 1425 static const struct resource_create_funcs res_create_maximus_funcs = { 1426 .read_dce_straps = NULL, 1427 .create_audio = NULL, 1428 .create_stream_encoder = NULL, 1429 .create_hwseq = dcn20_hwseq_create, 1430 }; 1431 1432 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu); 1433 1434 void dcn20_clock_source_destroy(struct clock_source **clk_src) 1435 { 1436 kfree(TO_DCE110_CLK_SRC(*clk_src)); 1437 *clk_src = NULL; 1438 } 1439 1440 1441 struct display_stream_compressor *dcn20_dsc_create( 1442 struct dc_context *ctx, uint32_t inst) 1443 { 1444 struct dcn20_dsc *dsc = 1445 kzalloc(sizeof(struct dcn20_dsc), GFP_ATOMIC); 1446 1447 if (!dsc) { 1448 BREAK_TO_DEBUGGER(); 1449 return NULL; 1450 } 1451 1452 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1453 return &dsc->base; 1454 } 1455 1456 void dcn20_dsc_destroy(struct display_stream_compressor **dsc) 1457 { 1458 kfree(container_of(*dsc, struct dcn20_dsc, base)); 1459 *dsc = NULL; 1460 } 1461 1462 1463 static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) 1464 { 1465 unsigned int i; 1466 1467 for (i = 0; i < pool->base.stream_enc_count; i++) { 1468 if (pool->base.stream_enc[i] != NULL) { 1469 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1470 pool->base.stream_enc[i] = NULL; 1471 } 1472 } 1473 1474 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1475 if (pool->base.dscs[i] != NULL) 1476 dcn20_dsc_destroy(&pool->base.dscs[i]); 1477 } 1478 1479 if (pool->base.mpc != NULL) { 1480 kfree(TO_DCN20_MPC(pool->base.mpc)); 1481 pool->base.mpc = NULL; 1482 } 1483 if (pool->base.hubbub != NULL) { 1484 kfree(pool->base.hubbub); 1485 pool->base.hubbub = NULL; 1486 } 1487 for (i = 0; i < pool->base.pipe_count; i++) { 1488 if (pool->base.dpps[i] != NULL) 1489 dcn20_dpp_destroy(&pool->base.dpps[i]); 1490 1491 if (pool->base.ipps[i] != NULL) 1492 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1493 1494 if (pool->base.hubps[i] != NULL) { 1495 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1496 pool->base.hubps[i] = NULL; 1497 } 1498 1499 if (pool->base.irqs != NULL) { 1500 dal_irq_service_destroy(&pool->base.irqs); 1501 } 1502 } 1503 1504 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1505 if (pool->base.engines[i] != NULL) 1506 dce110_engine_destroy(&pool->base.engines[i]); 1507 if (pool->base.hw_i2cs[i] != NULL) { 1508 kfree(pool->base.hw_i2cs[i]); 1509 pool->base.hw_i2cs[i] = NULL; 1510 } 1511 if (pool->base.sw_i2cs[i] != NULL) { 1512 kfree(pool->base.sw_i2cs[i]); 1513 pool->base.sw_i2cs[i] = NULL; 1514 } 1515 } 1516 1517 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1518 if (pool->base.opps[i] != NULL) 1519 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1520 } 1521 1522 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1523 if (pool->base.timing_generators[i] != NULL) { 1524 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1525 pool->base.timing_generators[i] = NULL; 1526 } 1527 } 1528 1529 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1530 if (pool->base.dwbc[i] != NULL) { 1531 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); 1532 pool->base.dwbc[i] = NULL; 1533 } 1534 if (pool->base.mcif_wb[i] != NULL) { 1535 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); 1536 pool->base.mcif_wb[i] = NULL; 1537 } 1538 } 1539 1540 for (i = 0; i < pool->base.audio_count; i++) { 1541 if (pool->base.audios[i]) 1542 dce_aud_destroy(&pool->base.audios[i]); 1543 } 1544 1545 for (i = 0; i < pool->base.clk_src_count; i++) { 1546 if (pool->base.clock_sources[i] != NULL) { 1547 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1548 pool->base.clock_sources[i] = NULL; 1549 } 1550 } 1551 1552 if (pool->base.dp_clock_source != NULL) { 1553 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1554 pool->base.dp_clock_source = NULL; 1555 } 1556 1557 1558 if (pool->base.abm != NULL) 1559 dce_abm_destroy(&pool->base.abm); 1560 1561 if (pool->base.dmcu != NULL) 1562 dce_dmcu_destroy(&pool->base.dmcu); 1563 1564 if (pool->base.dccg != NULL) 1565 dcn_dccg_destroy(&pool->base.dccg); 1566 1567 if (pool->base.pp_smu != NULL) 1568 dcn20_pp_smu_destroy(&pool->base.pp_smu); 1569 1570 if (pool->base.oem_device != NULL) 1571 dal_ddc_service_destroy(&pool->base.oem_device); 1572 } 1573 1574 struct hubp *dcn20_hubp_create( 1575 struct dc_context *ctx, 1576 uint32_t inst) 1577 { 1578 struct dcn20_hubp *hubp2 = 1579 kzalloc(sizeof(struct dcn20_hubp), GFP_ATOMIC); 1580 1581 if (!hubp2) 1582 return NULL; 1583 1584 if (hubp2_construct(hubp2, ctx, inst, 1585 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1586 return &hubp2->base; 1587 1588 BREAK_TO_DEBUGGER(); 1589 kfree(hubp2); 1590 return NULL; 1591 } 1592 1593 static void get_pixel_clock_parameters( 1594 struct pipe_ctx *pipe_ctx, 1595 struct pixel_clk_params *pixel_clk_params) 1596 { 1597 const struct dc_stream_state *stream = pipe_ctx->stream; 1598 struct pipe_ctx *odm_pipe; 1599 int opp_cnt = 1; 1600 struct dc_link *link = stream->link; 1601 struct link_encoder *link_enc = NULL; 1602 1603 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1604 opp_cnt++; 1605 1606 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 1607 1608 /* Links supporting dynamically assigned link encoder will be assigned next 1609 * available encoder if one not already assigned. 1610 */ 1611 if (link->is_dig_mapping_flexible && 1612 link->dc->res_pool->funcs->link_encs_assign) { 1613 link_enc = link_enc_cfg_get_link_enc_used_by_stream(stream->link->dc->current_state, stream); 1614 if (link_enc == NULL) 1615 link_enc = link_enc_cfg_get_next_avail_link_enc(stream->link->dc, 1616 stream->link->dc->current_state); 1617 } else 1618 link_enc = stream->link->link_enc; 1619 ASSERT(link_enc); 1620 1621 if (link_enc) 1622 pixel_clk_params->encoder_object_id = link_enc->id; 1623 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 1624 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 1625 /* TODO: un-hardcode*/ 1626 /* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */ 1627 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 1628 LINK_RATE_REF_FREQ_IN_KHZ; 1629 pixel_clk_params->flags.ENABLE_SS = 0; 1630 pixel_clk_params->color_depth = 1631 stream->timing.display_color_depth; 1632 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 1633 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 1634 1635 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1636 pixel_clk_params->color_depth = COLOR_DEPTH_888; 1637 1638 if (opp_cnt == 4) 1639 pixel_clk_params->requested_pix_clk_100hz /= 4; 1640 else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2) 1641 pixel_clk_params->requested_pix_clk_100hz /= 2; 1642 1643 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1644 pixel_clk_params->requested_pix_clk_100hz *= 2; 1645 1646 } 1647 1648 static void build_clamping_params(struct dc_stream_state *stream) 1649 { 1650 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1651 stream->clamping.c_depth = stream->timing.display_color_depth; 1652 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1653 } 1654 1655 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1656 { 1657 1658 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1659 1660 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1661 pipe_ctx->clock_source, 1662 &pipe_ctx->stream_res.pix_clk_params, 1663 &pipe_ctx->pll_settings); 1664 1665 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1666 1667 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1668 &pipe_ctx->stream->bit_depth_params); 1669 build_clamping_params(pipe_ctx->stream); 1670 1671 return DC_OK; 1672 } 1673 1674 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream) 1675 { 1676 enum dc_status status = DC_OK; 1677 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1678 1679 if (!pipe_ctx) 1680 return DC_ERROR_UNEXPECTED; 1681 1682 1683 status = build_pipe_hw_param(pipe_ctx); 1684 1685 return status; 1686 } 1687 1688 1689 void dcn20_acquire_dsc(const struct dc *dc, 1690 struct resource_context *res_ctx, 1691 struct display_stream_compressor **dsc, 1692 int pipe_idx) 1693 { 1694 int i; 1695 const struct resource_pool *pool = dc->res_pool; 1696 struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc; 1697 1698 ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */ 1699 *dsc = NULL; 1700 1701 /* Always do 1-to-1 mapping when number of DSCs is same as number of pipes */ 1702 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { 1703 *dsc = pool->dscs[pipe_idx]; 1704 res_ctx->is_dsc_acquired[pipe_idx] = true; 1705 return; 1706 } 1707 1708 /* Return old DSC to avoid the need for re-programming */ 1709 if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) { 1710 *dsc = dsc_old; 1711 res_ctx->is_dsc_acquired[dsc_old->inst] = true; 1712 return ; 1713 } 1714 1715 /* Find first free DSC */ 1716 for (i = 0; i < pool->res_cap->num_dsc; i++) 1717 if (!res_ctx->is_dsc_acquired[i]) { 1718 *dsc = pool->dscs[i]; 1719 res_ctx->is_dsc_acquired[i] = true; 1720 break; 1721 } 1722 } 1723 1724 void dcn20_release_dsc(struct resource_context *res_ctx, 1725 const struct resource_pool *pool, 1726 struct display_stream_compressor **dsc) 1727 { 1728 int i; 1729 1730 for (i = 0; i < pool->res_cap->num_dsc; i++) 1731 if (pool->dscs[i] == *dsc) { 1732 res_ctx->is_dsc_acquired[i] = false; 1733 *dsc = NULL; 1734 break; 1735 } 1736 } 1737 1738 1739 1740 enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, 1741 struct dc_state *dc_ctx, 1742 struct dc_stream_state *dc_stream) 1743 { 1744 enum dc_status result = DC_OK; 1745 int i; 1746 1747 /* Get a DSC if required and available */ 1748 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1749 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i]; 1750 1751 if (pipe_ctx->stream != dc_stream) 1752 continue; 1753 1754 if (pipe_ctx->stream_res.dsc) 1755 continue; 1756 1757 dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i); 1758 1759 /* The number of DSCs can be less than the number of pipes */ 1760 if (!pipe_ctx->stream_res.dsc) { 1761 result = DC_NO_DSC_RESOURCE; 1762 } 1763 1764 break; 1765 } 1766 1767 return result; 1768 } 1769 1770 1771 static enum dc_status remove_dsc_from_stream_resource(struct dc *dc, 1772 struct dc_state *new_ctx, 1773 struct dc_stream_state *dc_stream) 1774 { 1775 struct pipe_ctx *pipe_ctx = NULL; 1776 int i; 1777 1778 for (i = 0; i < MAX_PIPES; i++) { 1779 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { 1780 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; 1781 1782 if (pipe_ctx->stream_res.dsc) 1783 dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); 1784 } 1785 } 1786 1787 if (!pipe_ctx) 1788 return DC_ERROR_UNEXPECTED; 1789 else 1790 return DC_OK; 1791 } 1792 1793 1794 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) 1795 { 1796 enum dc_status result = DC_ERROR_UNEXPECTED; 1797 1798 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1799 1800 if (result == DC_OK) 1801 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1802 1803 /* Get a DSC if required and available */ 1804 if (result == DC_OK && dc_stream->timing.flags.DSC) 1805 result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream); 1806 1807 if (result == DC_OK) 1808 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream); 1809 1810 return result; 1811 } 1812 1813 1814 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) 1815 { 1816 enum dc_status result = DC_OK; 1817 1818 result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream); 1819 1820 return result; 1821 } 1822 1823 1824 static void swizzle_to_dml_params( 1825 enum swizzle_mode_values swizzle, 1826 unsigned int *sw_mode) 1827 { 1828 switch (swizzle) { 1829 case DC_SW_LINEAR: 1830 *sw_mode = dm_sw_linear; 1831 break; 1832 case DC_SW_4KB_S: 1833 *sw_mode = dm_sw_4kb_s; 1834 break; 1835 case DC_SW_4KB_S_X: 1836 *sw_mode = dm_sw_4kb_s_x; 1837 break; 1838 case DC_SW_4KB_D: 1839 *sw_mode = dm_sw_4kb_d; 1840 break; 1841 case DC_SW_4KB_D_X: 1842 *sw_mode = dm_sw_4kb_d_x; 1843 break; 1844 case DC_SW_64KB_S: 1845 *sw_mode = dm_sw_64kb_s; 1846 break; 1847 case DC_SW_64KB_S_X: 1848 *sw_mode = dm_sw_64kb_s_x; 1849 break; 1850 case DC_SW_64KB_S_T: 1851 *sw_mode = dm_sw_64kb_s_t; 1852 break; 1853 case DC_SW_64KB_D: 1854 *sw_mode = dm_sw_64kb_d; 1855 break; 1856 case DC_SW_64KB_D_X: 1857 *sw_mode = dm_sw_64kb_d_x; 1858 break; 1859 case DC_SW_64KB_D_T: 1860 *sw_mode = dm_sw_64kb_d_t; 1861 break; 1862 case DC_SW_64KB_R_X: 1863 *sw_mode = dm_sw_64kb_r_x; 1864 break; 1865 case DC_SW_VAR_S: 1866 *sw_mode = dm_sw_var_s; 1867 break; 1868 case DC_SW_VAR_S_X: 1869 *sw_mode = dm_sw_var_s_x; 1870 break; 1871 case DC_SW_VAR_D: 1872 *sw_mode = dm_sw_var_d; 1873 break; 1874 case DC_SW_VAR_D_X: 1875 *sw_mode = dm_sw_var_d_x; 1876 break; 1877 case DC_SW_VAR_R_X: 1878 *sw_mode = dm_sw_var_r_x; 1879 break; 1880 default: 1881 ASSERT(0); /* Not supported */ 1882 break; 1883 } 1884 } 1885 1886 bool dcn20_split_stream_for_odm( 1887 const struct dc *dc, 1888 struct resource_context *res_ctx, 1889 struct pipe_ctx *prev_odm_pipe, 1890 struct pipe_ctx *next_odm_pipe) 1891 { 1892 int pipe_idx = next_odm_pipe->pipe_idx; 1893 const struct resource_pool *pool = dc->res_pool; 1894 1895 *next_odm_pipe = *prev_odm_pipe; 1896 1897 next_odm_pipe->pipe_idx = pipe_idx; 1898 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; 1899 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; 1900 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; 1901 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; 1902 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; 1903 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; 1904 next_odm_pipe->stream_res.dsc = NULL; 1905 if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) { 1906 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe; 1907 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe; 1908 } 1909 if (prev_odm_pipe->top_pipe && prev_odm_pipe->top_pipe->next_odm_pipe) { 1910 prev_odm_pipe->top_pipe->next_odm_pipe->bottom_pipe = next_odm_pipe; 1911 next_odm_pipe->top_pipe = prev_odm_pipe->top_pipe->next_odm_pipe; 1912 } 1913 if (prev_odm_pipe->bottom_pipe && prev_odm_pipe->bottom_pipe->next_odm_pipe) { 1914 prev_odm_pipe->bottom_pipe->next_odm_pipe->top_pipe = next_odm_pipe; 1915 next_odm_pipe->bottom_pipe = prev_odm_pipe->bottom_pipe->next_odm_pipe; 1916 } 1917 prev_odm_pipe->next_odm_pipe = next_odm_pipe; 1918 next_odm_pipe->prev_odm_pipe = prev_odm_pipe; 1919 1920 if (prev_odm_pipe->plane_state) { 1921 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; 1922 int new_width; 1923 1924 /* HACTIVE halved for odm combine */ 1925 sd->h_active /= 2; 1926 /* Calculate new vp and recout for left pipe */ 1927 /* Need at least 16 pixels width per side */ 1928 if (sd->recout.x + 16 >= sd->h_active) 1929 return false; 1930 new_width = sd->h_active - sd->recout.x; 1931 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1932 sd->ratios.horz, sd->recout.width - new_width)); 1933 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1934 sd->ratios.horz_c, sd->recout.width - new_width)); 1935 sd->recout.width = new_width; 1936 1937 /* Calculate new vp and recout for right pipe */ 1938 sd = &next_odm_pipe->plane_res.scl_data; 1939 /* HACTIVE halved for odm combine */ 1940 sd->h_active /= 2; 1941 /* Need at least 16 pixels width per side */ 1942 if (new_width <= 16) 1943 return false; 1944 new_width = sd->recout.width + sd->recout.x - sd->h_active; 1945 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1946 sd->ratios.horz, sd->recout.width - new_width)); 1947 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1948 sd->ratios.horz_c, sd->recout.width - new_width)); 1949 sd->recout.width = new_width; 1950 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int( 1951 sd->ratios.horz, sd->h_active - sd->recout.x)); 1952 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int( 1953 sd->ratios.horz_c, sd->h_active - sd->recout.x)); 1954 sd->recout.x = 0; 1955 } 1956 if (!next_odm_pipe->top_pipe) 1957 next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; 1958 else 1959 next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp; 1960 if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) { 1961 dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx); 1962 ASSERT(next_odm_pipe->stream_res.dsc); 1963 if (next_odm_pipe->stream_res.dsc == NULL) 1964 return false; 1965 } 1966 1967 return true; 1968 } 1969 1970 void dcn20_split_stream_for_mpc( 1971 struct resource_context *res_ctx, 1972 const struct resource_pool *pool, 1973 struct pipe_ctx *primary_pipe, 1974 struct pipe_ctx *secondary_pipe) 1975 { 1976 int pipe_idx = secondary_pipe->pipe_idx; 1977 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe; 1978 1979 *secondary_pipe = *primary_pipe; 1980 secondary_pipe->bottom_pipe = sec_bot_pipe; 1981 1982 secondary_pipe->pipe_idx = pipe_idx; 1983 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; 1984 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; 1985 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; 1986 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; 1987 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; 1988 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; 1989 secondary_pipe->stream_res.dsc = NULL; 1990 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { 1991 ASSERT(!secondary_pipe->bottom_pipe); 1992 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; 1993 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe; 1994 } 1995 primary_pipe->bottom_pipe = secondary_pipe; 1996 secondary_pipe->top_pipe = primary_pipe; 1997 1998 ASSERT(primary_pipe->plane_state); 1999 } 2000 2001 int dcn20_populate_dml_pipes_from_context( 2002 struct dc *dc, 2003 struct dc_state *context, 2004 display_e2e_pipe_params_st *pipes, 2005 bool fast_validate) 2006 { 2007 int pipe_cnt, i; 2008 bool synchronized_vblank = true; 2009 struct resource_context *res_ctx = &context->res_ctx; 2010 2011 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) { 2012 if (!res_ctx->pipe_ctx[i].stream) 2013 continue; 2014 2015 if (pipe_cnt < 0) { 2016 pipe_cnt = i; 2017 continue; 2018 } 2019 2020 if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream) 2021 continue; 2022 2023 if (dc->debug.disable_timing_sync || 2024 (!resource_are_streams_timing_synchronizable( 2025 res_ctx->pipe_ctx[pipe_cnt].stream, 2026 res_ctx->pipe_ctx[i].stream) && 2027 !resource_are_vblanks_synchronizable( 2028 res_ctx->pipe_ctx[pipe_cnt].stream, 2029 res_ctx->pipe_ctx[i].stream))) { 2030 synchronized_vblank = false; 2031 break; 2032 } 2033 } 2034 2035 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 2036 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing; 2037 unsigned int v_total; 2038 unsigned int front_porch; 2039 int output_bpc; 2040 struct audio_check aud_check = {0}; 2041 2042 if (!res_ctx->pipe_ctx[i].stream) 2043 continue; 2044 2045 v_total = timing->v_total; 2046 front_porch = timing->v_front_porch; 2047 2048 /* todo: 2049 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0; 2050 pipes[pipe_cnt].pipe.src.dcc = 0; 2051 pipes[pipe_cnt].pipe.src.vm = 0;*/ 2052 2053 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 2054 2055 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC; 2056 /* todo: rotation?*/ 2057 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; 2058 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) { 2059 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true; 2060 /* 1/2 vblank */ 2061 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active = 2062 (v_total - timing->v_addressable 2063 - timing->v_border_top - timing->v_border_bottom) / 2; 2064 /* 36 bytes dp, 32 hdmi */ 2065 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes = 2066 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32; 2067 } 2068 pipes[pipe_cnt].pipe.src.dcc = false; 2069 pipes[pipe_cnt].pipe.src.dcc_rate = 1; 2070 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank; 2071 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch; 2072 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start 2073 - timing->h_addressable 2074 - timing->h_border_left 2075 - timing->h_border_right; 2076 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch; 2077 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start 2078 - timing->v_addressable 2079 - timing->v_border_top 2080 - timing->v_border_bottom; 2081 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total; 2082 pipes[pipe_cnt].pipe.dest.vtotal = v_total; 2083 pipes[pipe_cnt].pipe.dest.hactive = 2084 timing->h_addressable + timing->h_border_left + timing->h_border_right; 2085 pipes[pipe_cnt].pipe.dest.vactive = 2086 timing->v_addressable + timing->v_border_top + timing->v_border_bottom; 2087 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE; 2088 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0; 2089 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 2090 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2; 2091 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst; 2092 pipes[pipe_cnt].dout.dp_lanes = 4; 2093 pipes[pipe_cnt].dout.is_virtual = 0; 2094 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min; 2095 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max; 2096 switch (get_num_odm_splits(&res_ctx->pipe_ctx[i])) { 2097 case 1: 2098 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1; 2099 break; 2100 case 3: 2101 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1; 2102 break; 2103 default: 2104 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled; 2105 } 2106 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; 2107 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state 2108 == res_ctx->pipe_ctx[i].plane_state) { 2109 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe; 2110 int split_idx = 0; 2111 2112 while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state 2113 == res_ctx->pipe_ctx[i].plane_state) { 2114 first_pipe = first_pipe->top_pipe; 2115 split_idx++; 2116 } 2117 /* Treat 4to1 mpc combine as an mpo of 2 2-to-1 combines */ 2118 if (split_idx == 0) 2119 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx; 2120 else if (split_idx == 1) 2121 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; 2122 else if (split_idx == 2) 2123 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx; 2124 } else if (res_ctx->pipe_ctx[i].prev_odm_pipe) { 2125 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe; 2126 2127 while (first_pipe->prev_odm_pipe) 2128 first_pipe = first_pipe->prev_odm_pipe; 2129 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx; 2130 } 2131 2132 switch (res_ctx->pipe_ctx[i].stream->signal) { 2133 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2134 case SIGNAL_TYPE_DISPLAY_PORT: 2135 pipes[pipe_cnt].dout.output_type = dm_dp; 2136 break; 2137 case SIGNAL_TYPE_EDP: 2138 pipes[pipe_cnt].dout.output_type = dm_edp; 2139 break; 2140 case SIGNAL_TYPE_HDMI_TYPE_A: 2141 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2142 case SIGNAL_TYPE_DVI_DUAL_LINK: 2143 pipes[pipe_cnt].dout.output_type = dm_hdmi; 2144 break; 2145 default: 2146 /* In case there is no signal, set dp with 4 lanes to allow max config */ 2147 pipes[pipe_cnt].dout.is_virtual = 1; 2148 pipes[pipe_cnt].dout.output_type = dm_dp; 2149 pipes[pipe_cnt].dout.dp_lanes = 4; 2150 } 2151 2152 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) { 2153 case COLOR_DEPTH_666: 2154 output_bpc = 6; 2155 break; 2156 case COLOR_DEPTH_888: 2157 output_bpc = 8; 2158 break; 2159 case COLOR_DEPTH_101010: 2160 output_bpc = 10; 2161 break; 2162 case COLOR_DEPTH_121212: 2163 output_bpc = 12; 2164 break; 2165 case COLOR_DEPTH_141414: 2166 output_bpc = 14; 2167 break; 2168 case COLOR_DEPTH_161616: 2169 output_bpc = 16; 2170 break; 2171 case COLOR_DEPTH_999: 2172 output_bpc = 9; 2173 break; 2174 case COLOR_DEPTH_111111: 2175 output_bpc = 11; 2176 break; 2177 default: 2178 output_bpc = 8; 2179 break; 2180 } 2181 2182 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) { 2183 case PIXEL_ENCODING_RGB: 2184 case PIXEL_ENCODING_YCBCR444: 2185 pipes[pipe_cnt].dout.output_format = dm_444; 2186 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3; 2187 break; 2188 case PIXEL_ENCODING_YCBCR420: 2189 pipes[pipe_cnt].dout.output_format = dm_420; 2190 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2; 2191 break; 2192 case PIXEL_ENCODING_YCBCR422: 2193 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC && 2194 !res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.ycbcr422_simple) 2195 pipes[pipe_cnt].dout.output_format = dm_n422; 2196 else 2197 pipes[pipe_cnt].dout.output_format = dm_s422; 2198 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2; 2199 break; 2200 default: 2201 pipes[pipe_cnt].dout.output_format = dm_444; 2202 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3; 2203 } 2204 2205 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC) 2206 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0; 2207 2208 /* todo: default max for now, until there is logic reflecting this in dc*/ 2209 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 2210 /*fill up the audio sample rate (unit in kHz)*/ 2211 get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check); 2212 pipes[pipe_cnt].dout.max_audio_sample_rate = aud_check.max_audiosample_rate / 1000; 2213 /* 2214 * For graphic plane, cursor number is 1, nv12 is 0 2215 * bw calculations due to cursor on/off 2216 */ 2217 if (res_ctx->pipe_ctx[i].plane_state && 2218 res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 2219 pipes[pipe_cnt].pipe.src.num_cursors = 0; 2220 else 2221 pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors; 2222 2223 pipes[pipe_cnt].pipe.src.cur0_src_width = 256; 2224 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit; 2225 2226 if (!res_ctx->pipe_ctx[i].plane_state) { 2227 pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled; 2228 pipes[pipe_cnt].pipe.src.source_scan = dm_horz; 2229 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_4kb_s; 2230 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile; 2231 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable; 2232 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920) 2233 pipes[pipe_cnt].pipe.src.viewport_width = 1920; 2234 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable; 2235 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080) 2236 pipes[pipe_cnt].pipe.src.viewport_height = 1080; 2237 pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height; 2238 pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width; 2239 pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height; 2240 pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width; 2241 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 255) / 256) * 256; 2242 pipes[pipe_cnt].pipe.src.source_format = dm_444_32; 2243 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/ 2244 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/ 2245 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/ 2246 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/ 2247 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16; 2248 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0; 2249 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0; 2250 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/ 2251 pipes[pipe_cnt].pipe.scale_taps.htaps = 1; 2252 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1; 2253 pipes[pipe_cnt].pipe.dest.vtotal_min = v_total; 2254 pipes[pipe_cnt].pipe.dest.vtotal_max = v_total; 2255 2256 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) { 2257 pipes[pipe_cnt].pipe.src.viewport_width /= 2; 2258 pipes[pipe_cnt].pipe.dest.recout_width /= 2; 2259 } else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) { 2260 pipes[pipe_cnt].pipe.src.viewport_width /= 4; 2261 pipes[pipe_cnt].pipe.dest.recout_width /= 4; 2262 } 2263 } else { 2264 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state; 2265 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data; 2266 2267 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate; 2268 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) 2269 || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) 2270 || pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled; 2271 2272 /* stereo is not split */ 2273 if (pln->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE || 2274 pln->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) { 2275 pipes[pipe_cnt].pipe.src.is_hsplit = false; 2276 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; 2277 } 2278 2279 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90 2280 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz; 2281 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y; 2282 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y; 2283 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width; 2284 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width; 2285 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height; 2286 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height; 2287 pipes[pipe_cnt].pipe.src.viewport_width_max = pln->src_rect.width; 2288 pipes[pipe_cnt].pipe.src.viewport_height_max = pln->src_rect.height; 2289 pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width; 2290 pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height; 2291 pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width; 2292 pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height; 2293 if (pln->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA 2294 || pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 2295 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch; 2296 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch; 2297 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; 2298 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c; 2299 } else { 2300 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch; 2301 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; 2302 } 2303 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable; 2304 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width; 2305 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height; 2306 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height; 2307 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width; 2308 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) 2309 pipes[pipe_cnt].pipe.dest.full_recout_width *= 2; 2310 else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) 2311 pipes[pipe_cnt].pipe.dest.full_recout_width *= 4; 2312 else { 2313 struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe; 2314 2315 while (split_pipe && split_pipe->plane_state == pln) { 2316 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; 2317 split_pipe = split_pipe->bottom_pipe; 2318 } 2319 split_pipe = res_ctx->pipe_ctx[i].top_pipe; 2320 while (split_pipe && split_pipe->plane_state == pln) { 2321 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; 2322 split_pipe = split_pipe->top_pipe; 2323 } 2324 } 2325 2326 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16; 2327 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32); 2328 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32); 2329 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32); 2330 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32); 2331 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 2332 scl->ratios.vert.value != dc_fixpt_one.value 2333 || scl->ratios.horz.value != dc_fixpt_one.value 2334 || scl->ratios.vert_c.value != dc_fixpt_one.value 2335 || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/ 2336 || dc->debug.always_scale; /*support always scale*/ 2337 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps; 2338 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c; 2339 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps; 2340 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c; 2341 2342 pipes[pipe_cnt].pipe.src.macro_tile_size = 2343 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); 2344 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, 2345 &pipes[pipe_cnt].pipe.src.sw_mode); 2346 2347 switch (pln->format) { 2348 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 2349 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 2350 pipes[pipe_cnt].pipe.src.source_format = dm_420_8; 2351 break; 2352 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 2353 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 2354 pipes[pipe_cnt].pipe.src.source_format = dm_420_10; 2355 break; 2356 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 2357 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 2358 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 2359 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2360 pipes[pipe_cnt].pipe.src.source_format = dm_444_64; 2361 break; 2362 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 2363 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 2364 pipes[pipe_cnt].pipe.src.source_format = dm_444_16; 2365 break; 2366 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 2367 pipes[pipe_cnt].pipe.src.source_format = dm_444_8; 2368 break; 2369 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 2370 pipes[pipe_cnt].pipe.src.source_format = dm_rgbe_alpha; 2371 break; 2372 default: 2373 pipes[pipe_cnt].pipe.src.source_format = dm_444_32; 2374 break; 2375 } 2376 } 2377 2378 pipe_cnt++; 2379 } 2380 2381 /* populate writeback information */ 2382 DC_FP_START(); 2383 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes); 2384 DC_FP_END(); 2385 2386 return pipe_cnt; 2387 } 2388 2389 unsigned int dcn20_calc_max_scaled_time( 2390 unsigned int time_per_pixel, 2391 enum mmhubbub_wbif_mode mode, 2392 unsigned int urgent_watermark) 2393 { 2394 unsigned int time_per_byte = 0; 2395 unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */ 2396 unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */ 2397 unsigned int small_free_entry, max_free_entry; 2398 unsigned int buf_lh_capability; 2399 unsigned int max_scaled_time; 2400 2401 if (mode == PACKED_444) /* packed mode */ 2402 time_per_byte = time_per_pixel/4; 2403 else if (mode == PLANAR_420_8BPC) 2404 time_per_byte = time_per_pixel; 2405 else if (mode == PLANAR_420_10BPC) /* p010 */ 2406 time_per_byte = time_per_pixel * 819/1024; 2407 2408 if (time_per_byte == 0) 2409 time_per_byte = 1; 2410 2411 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry; 2412 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry; 2413 buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */ 2414 max_scaled_time = buf_lh_capability - urgent_watermark; 2415 return max_scaled_time; 2416 } 2417 2418 void dcn20_set_mcif_arb_params( 2419 struct dc *dc, 2420 struct dc_state *context, 2421 display_e2e_pipe_params_st *pipes, 2422 int pipe_cnt) 2423 { 2424 enum mmhubbub_wbif_mode wbif_mode; 2425 struct mcif_arb_params *wb_arb_params; 2426 int i, j, k, dwb_pipe; 2427 2428 /* Writeback MCIF_WB arbitration parameters */ 2429 dwb_pipe = 0; 2430 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2431 2432 if (!context->res_ctx.pipe_ctx[i].stream) 2433 continue; 2434 2435 for (j = 0; j < MAX_DWB_PIPES; j++) { 2436 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false) 2437 continue; 2438 2439 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params; 2440 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe]; 2441 2442 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) { 2443 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) 2444 wbif_mode = PLANAR_420_8BPC; 2445 else 2446 wbif_mode = PLANAR_420_10BPC; 2447 } else 2448 wbif_mode = PACKED_444; 2449 2450 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) { 2451 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2452 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2453 } 2454 wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction, ms */ 2455 wb_arb_params->slice_lines = 32; 2456 wb_arb_params->arbitration_slice = 2; 2457 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel, 2458 wbif_mode, 2459 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */ 2460 2461 dwb_pipe++; 2462 2463 if (dwb_pipe >= MAX_DWB_PIPES) 2464 return; 2465 } 2466 if (dwb_pipe >= MAX_DWB_PIPES) 2467 return; 2468 } 2469 } 2470 2471 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) 2472 { 2473 int i; 2474 2475 /* Validate DSC config, dsc count validation is already done */ 2476 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2477 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; 2478 struct dc_stream_state *stream = pipe_ctx->stream; 2479 struct dsc_config dsc_cfg; 2480 struct pipe_ctx *odm_pipe; 2481 int opp_cnt = 1; 2482 2483 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 2484 opp_cnt++; 2485 2486 /* Only need to validate top pipe */ 2487 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC) 2488 continue; 2489 2490 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left 2491 + stream->timing.h_border_right) / opp_cnt; 2492 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top 2493 + stream->timing.v_border_bottom; 2494 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 2495 dsc_cfg.color_depth = stream->timing.display_color_depth; 2496 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 2497 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 2498 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 2499 2500 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg)) 2501 return false; 2502 } 2503 return true; 2504 } 2505 2506 struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, 2507 struct resource_context *res_ctx, 2508 const struct resource_pool *pool, 2509 const struct pipe_ctx *primary_pipe) 2510 { 2511 struct pipe_ctx *secondary_pipe = NULL; 2512 2513 if (dc && primary_pipe) { 2514 int j; 2515 int preferred_pipe_idx = 0; 2516 2517 /* first check the prev dc state: 2518 * if this primary pipe has a bottom pipe in prev. state 2519 * and if the bottom pipe is still available (which it should be), 2520 * pick that pipe as secondary 2521 * Same logic applies for ODM pipes 2522 */ 2523 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) { 2524 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx; 2525 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2526 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2527 secondary_pipe->pipe_idx = preferred_pipe_idx; 2528 } 2529 } 2530 if (secondary_pipe == NULL && 2531 dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) { 2532 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx; 2533 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2534 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2535 secondary_pipe->pipe_idx = preferred_pipe_idx; 2536 } 2537 } 2538 2539 /* 2540 * if this primary pipe does not have a bottom pipe in prev. state 2541 * start backward and find a pipe that did not used to be a bottom pipe in 2542 * prev. dc state. This way we make sure we keep the same assignment as 2543 * last state and will not have to reprogram every pipe 2544 */ 2545 if (secondary_pipe == NULL) { 2546 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { 2547 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL 2548 && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) { 2549 preferred_pipe_idx = j; 2550 2551 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2552 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2553 secondary_pipe->pipe_idx = preferred_pipe_idx; 2554 break; 2555 } 2556 } 2557 } 2558 } 2559 /* 2560 * We should never hit this assert unless assignments are shuffled around 2561 * if this happens we will prob. hit a vsync tdr 2562 */ 2563 ASSERT(secondary_pipe); 2564 /* 2565 * search backwards for the second pipe to keep pipe 2566 * assignment more consistent 2567 */ 2568 if (secondary_pipe == NULL) { 2569 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { 2570 preferred_pipe_idx = j; 2571 2572 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2573 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2574 secondary_pipe->pipe_idx = preferred_pipe_idx; 2575 break; 2576 } 2577 } 2578 } 2579 } 2580 2581 return secondary_pipe; 2582 } 2583 2584 void dcn20_merge_pipes_for_validate( 2585 struct dc *dc, 2586 struct dc_state *context) 2587 { 2588 int i; 2589 2590 /* merge previously split odm pipes since mode support needs to make the decision */ 2591 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2592 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2593 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe; 2594 2595 if (pipe->prev_odm_pipe) 2596 continue; 2597 2598 pipe->next_odm_pipe = NULL; 2599 while (odm_pipe) { 2600 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe; 2601 2602 odm_pipe->plane_state = NULL; 2603 odm_pipe->stream = NULL; 2604 odm_pipe->top_pipe = NULL; 2605 odm_pipe->bottom_pipe = NULL; 2606 odm_pipe->prev_odm_pipe = NULL; 2607 odm_pipe->next_odm_pipe = NULL; 2608 if (odm_pipe->stream_res.dsc) 2609 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); 2610 /* Clear plane_res and stream_res */ 2611 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res)); 2612 memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res)); 2613 odm_pipe = next_odm_pipe; 2614 } 2615 if (pipe->plane_state) 2616 resource_build_scaling_params(pipe); 2617 } 2618 2619 /* merge previously mpc split pipes since mode support needs to make the decision */ 2620 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2621 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2622 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 2623 2624 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) 2625 continue; 2626 2627 pipe->bottom_pipe = hsplit_pipe->bottom_pipe; 2628 if (hsplit_pipe->bottom_pipe) 2629 hsplit_pipe->bottom_pipe->top_pipe = pipe; 2630 hsplit_pipe->plane_state = NULL; 2631 hsplit_pipe->stream = NULL; 2632 hsplit_pipe->top_pipe = NULL; 2633 hsplit_pipe->bottom_pipe = NULL; 2634 2635 /* Clear plane_res and stream_res */ 2636 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res)); 2637 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res)); 2638 if (pipe->plane_state) 2639 resource_build_scaling_params(pipe); 2640 } 2641 } 2642 2643 int dcn20_validate_apply_pipe_split_flags( 2644 struct dc *dc, 2645 struct dc_state *context, 2646 int vlevel, 2647 int *split, 2648 bool *merge) 2649 { 2650 int i, pipe_idx, vlevel_split; 2651 int plane_count = 0; 2652 bool force_split = false; 2653 bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID; 2654 struct vba_vars_st *v = &context->bw_ctx.dml.vba; 2655 int max_mpc_comb = v->maxMpcComb; 2656 2657 if (context->stream_count > 1) { 2658 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) 2659 avoid_split = true; 2660 } else if (dc->debug.force_single_disp_pipe_split) 2661 force_split = true; 2662 2663 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2664 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2665 2666 /** 2667 * Workaround for avoiding pipe-split in cases where we'd split 2668 * planes that are too small, resulting in splits that aren't 2669 * valid for the scaler. 2670 */ 2671 if (pipe->plane_state && 2672 (pipe->plane_state->dst_rect.width <= 16 || 2673 pipe->plane_state->dst_rect.height <= 16 || 2674 pipe->plane_state->src_rect.width <= 16 || 2675 pipe->plane_state->src_rect.height <= 16)) 2676 avoid_split = true; 2677 2678 /* TODO: fix dc bugs and remove this split threshold thing */ 2679 if (pipe->stream && !pipe->prev_odm_pipe && 2680 (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state)) 2681 ++plane_count; 2682 } 2683 if (plane_count > dc->res_pool->pipe_count / 2) 2684 avoid_split = true; 2685 2686 /* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */ 2687 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2688 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2689 struct dc_crtc_timing timing; 2690 2691 if (!pipe->stream) 2692 continue; 2693 else { 2694 timing = pipe->stream->timing; 2695 if (timing.h_border_left + timing.h_border_right 2696 + timing.v_border_top + timing.v_border_bottom > 0) { 2697 avoid_split = true; 2698 break; 2699 } 2700 } 2701 } 2702 2703 /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */ 2704 if (avoid_split) { 2705 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2706 if (!context->res_ctx.pipe_ctx[i].stream) 2707 continue; 2708 2709 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) 2710 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 && 2711 v->ModeSupport[vlevel][0]) 2712 break; 2713 /* Impossible to not split this pipe */ 2714 if (vlevel > context->bw_ctx.dml.soc.num_states) 2715 vlevel = vlevel_split; 2716 else 2717 max_mpc_comb = 0; 2718 pipe_idx++; 2719 } 2720 v->maxMpcComb = max_mpc_comb; 2721 } 2722 2723 /* Split loop sets which pipe should be split based on dml outputs and dc flags */ 2724 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2725 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2726 int pipe_plane = v->pipe_plane[pipe_idx]; 2727 bool split4mpc = context->stream_count == 1 && plane_count == 1 2728 && dc->config.enable_4to1MPC && dc->res_pool->pipe_count >= 4; 2729 2730 if (!context->res_ctx.pipe_ctx[i].stream) 2731 continue; 2732 2733 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4) 2734 split[i] = 4; 2735 else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2) 2736 split[i] = 2; 2737 2738 if ((pipe->stream->view_format == 2739 VIEW_3D_FORMAT_SIDE_BY_SIDE || 2740 pipe->stream->view_format == 2741 VIEW_3D_FORMAT_TOP_AND_BOTTOM) && 2742 (pipe->stream->timing.timing_3d_format == 2743 TIMING_3D_FORMAT_TOP_AND_BOTTOM || 2744 pipe->stream->timing.timing_3d_format == 2745 TIMING_3D_FORMAT_SIDE_BY_SIDE)) 2746 split[i] = 2; 2747 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) { 2748 split[i] = 2; 2749 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1; 2750 } 2751 if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) { 2752 split[i] = 4; 2753 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1; 2754 } 2755 /*420 format workaround*/ 2756 if (pipe->stream->timing.h_addressable > 7680 && 2757 pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 2758 split[i] = 4; 2759 } 2760 v->ODMCombineEnabled[pipe_plane] = 2761 v->ODMCombineEnablePerState[vlevel][pipe_plane]; 2762 2763 if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) { 2764 if (get_num_mpc_splits(pipe) == 1) { 2765 /*If need split for mpc but 2 way split already*/ 2766 if (split[i] == 4) 2767 split[i] = 2; /* 2 -> 4 MPC */ 2768 else if (split[i] == 2) 2769 split[i] = 0; /* 2 -> 2 MPC */ 2770 else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) 2771 merge[i] = true; /* 2 -> 1 MPC */ 2772 } else if (get_num_mpc_splits(pipe) == 3) { 2773 /*If need split for mpc but 4 way split already*/ 2774 if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe) 2775 || !pipe->bottom_pipe)) { 2776 merge[i] = true; /* 4 -> 2 MPC */ 2777 } else if (split[i] == 0 && pipe->top_pipe && 2778 pipe->top_pipe->plane_state == pipe->plane_state) 2779 merge[i] = true; /* 4 -> 1 MPC */ 2780 split[i] = 0; 2781 } else if (get_num_odm_splits(pipe)) { 2782 /* ODM -> MPC transition */ 2783 if (pipe->prev_odm_pipe) { 2784 split[i] = 0; 2785 merge[i] = true; 2786 } 2787 } 2788 } else { 2789 if (get_num_odm_splits(pipe) == 1) { 2790 /*If need split for odm but 2 way split already*/ 2791 if (split[i] == 4) 2792 split[i] = 2; /* 2 -> 4 ODM */ 2793 else if (split[i] == 2) 2794 split[i] = 0; /* 2 -> 2 ODM */ 2795 else if (pipe->prev_odm_pipe) { 2796 ASSERT(0); /* NOT expected yet */ 2797 merge[i] = true; /* exit ODM */ 2798 } 2799 } else if (get_num_odm_splits(pipe) == 3) { 2800 /*If need split for odm but 4 way split already*/ 2801 if (split[i] == 2 && ((pipe->prev_odm_pipe && !pipe->prev_odm_pipe->prev_odm_pipe) 2802 || !pipe->next_odm_pipe)) { 2803 ASSERT(0); /* NOT expected yet */ 2804 merge[i] = true; /* 4 -> 2 ODM */ 2805 } else if (split[i] == 0 && pipe->prev_odm_pipe) { 2806 ASSERT(0); /* NOT expected yet */ 2807 merge[i] = true; /* exit ODM */ 2808 } 2809 split[i] = 0; 2810 } else if (get_num_mpc_splits(pipe)) { 2811 /* MPC -> ODM transition */ 2812 ASSERT(0); /* NOT expected yet */ 2813 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { 2814 split[i] = 0; 2815 merge[i] = true; 2816 } 2817 } 2818 } 2819 2820 /* Adjust dppclk when split is forced, do not bother with dispclk */ 2821 if (split[i] != 0 && v->NoOfDPP[vlevel][max_mpc_comb][pipe_idx] == 1) 2822 v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2; 2823 pipe_idx++; 2824 } 2825 2826 return vlevel; 2827 } 2828 2829 bool dcn20_fast_validate_bw( 2830 struct dc *dc, 2831 struct dc_state *context, 2832 display_e2e_pipe_params_st *pipes, 2833 int *pipe_cnt_out, 2834 int *pipe_split_from, 2835 int *vlevel_out, 2836 bool fast_validate) 2837 { 2838 bool out = false; 2839 int split[MAX_PIPES] = { 0 }; 2840 int pipe_cnt, i, pipe_idx, vlevel; 2841 2842 ASSERT(pipes); 2843 if (!pipes) 2844 return false; 2845 2846 dcn20_merge_pipes_for_validate(dc, context); 2847 2848 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 2849 2850 *pipe_cnt_out = pipe_cnt; 2851 2852 if (!pipe_cnt) { 2853 out = true; 2854 goto validate_out; 2855 } 2856 2857 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 2858 2859 if (vlevel > context->bw_ctx.dml.soc.num_states) 2860 goto validate_fail; 2861 2862 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL); 2863 2864 /*initialize pipe_just_split_from to invalid idx*/ 2865 for (i = 0; i < MAX_PIPES; i++) 2866 pipe_split_from[i] = -1; 2867 2868 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { 2869 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2870 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 2871 2872 if (!pipe->stream || pipe_split_from[i] >= 0) 2873 continue; 2874 2875 pipe_idx++; 2876 2877 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 2878 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 2879 ASSERT(hsplit_pipe); 2880 if (!dcn20_split_stream_for_odm( 2881 dc, &context->res_ctx, 2882 pipe, hsplit_pipe)) 2883 goto validate_fail; 2884 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 2885 dcn20_build_mapped_resource(dc, context, pipe->stream); 2886 } 2887 2888 if (!pipe->plane_state) 2889 continue; 2890 /* Skip 2nd half of already split pipe */ 2891 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state) 2892 continue; 2893 2894 /* We do not support mpo + odm at the moment */ 2895 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state 2896 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) 2897 goto validate_fail; 2898 2899 if (split[i] == 2) { 2900 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) { 2901 /* pipe not split previously needs split */ 2902 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 2903 ASSERT(hsplit_pipe); 2904 if (!hsplit_pipe) { 2905 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2; 2906 continue; 2907 } 2908 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 2909 if (!dcn20_split_stream_for_odm( 2910 dc, &context->res_ctx, 2911 pipe, hsplit_pipe)) 2912 goto validate_fail; 2913 dcn20_build_mapped_resource(dc, context, pipe->stream); 2914 } else { 2915 dcn20_split_stream_for_mpc( 2916 &context->res_ctx, dc->res_pool, 2917 pipe, hsplit_pipe); 2918 resource_build_scaling_params(pipe); 2919 resource_build_scaling_params(hsplit_pipe); 2920 } 2921 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 2922 } 2923 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { 2924 /* merge should already have been done */ 2925 ASSERT(0); 2926 } 2927 } 2928 /* Actual dsc count per stream dsc validation*/ 2929 if (!dcn20_validate_dsc(dc, context)) { 2930 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = 2931 DML_FAIL_DSC_VALIDATION_FAILURE; 2932 goto validate_fail; 2933 } 2934 2935 *vlevel_out = vlevel; 2936 2937 out = true; 2938 goto validate_out; 2939 2940 validate_fail: 2941 out = false; 2942 2943 validate_out: 2944 return out; 2945 } 2946 2947 static void dcn20_calculate_wm( 2948 struct dc *dc, struct dc_state *context, 2949 display_e2e_pipe_params_st *pipes, 2950 int *out_pipe_cnt, 2951 int *pipe_split_from, 2952 int vlevel, 2953 bool fast_validate) 2954 { 2955 int pipe_cnt, i, pipe_idx; 2956 2957 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 2958 if (!context->res_ctx.pipe_ctx[i].stream) 2959 continue; 2960 2961 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 2962 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 2963 2964 if (pipe_split_from[i] < 0) { 2965 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 2966 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; 2967 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) 2968 pipes[pipe_cnt].pipe.dest.odm_combine = 2969 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]; 2970 else 2971 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 2972 pipe_idx++; 2973 } else { 2974 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 2975 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; 2976 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) 2977 pipes[pipe_cnt].pipe.dest.odm_combine = 2978 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]]; 2979 else 2980 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 2981 } 2982 2983 if (dc->config.forced_clocks) { 2984 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 2985 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 2986 } 2987 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000) 2988 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 2989 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000) 2990 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 2991 2992 pipe_cnt++; 2993 } 2994 2995 if (pipe_cnt != pipe_idx) { 2996 if (dc->res_pool->funcs->populate_dml_pipes) 2997 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, 2998 context, pipes, fast_validate); 2999 else 3000 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, 3001 context, pipes, fast_validate); 3002 } 3003 3004 *out_pipe_cnt = pipe_cnt; 3005 3006 pipes[0].clks_cfg.voltage = vlevel; 3007 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; 3008 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 3009 3010 /* only pipe 0 is read for voltage and dcf/soc clocks */ 3011 if (vlevel < 1) { 3012 pipes[0].clks_cfg.voltage = 1; 3013 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz; 3014 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz; 3015 } 3016 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3017 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3018 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3019 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3020 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3021 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3022 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3023 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3024 3025 if (vlevel < 2) { 3026 pipes[0].clks_cfg.voltage = 2; 3027 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; 3028 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; 3029 } 3030 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3031 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3032 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3033 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3034 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3035 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3036 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3037 3038 if (vlevel < 3) { 3039 pipes[0].clks_cfg.voltage = 3; 3040 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; 3041 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; 3042 } 3043 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3044 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3045 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3046 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3047 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3048 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3049 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3050 3051 pipes[0].clks_cfg.voltage = vlevel; 3052 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; 3053 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 3054 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3055 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3056 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3057 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3058 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3059 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3060 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3061 } 3062 3063 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context) 3064 { 3065 int i; 3066 for (i = 0; i < dc->res_pool->pipe_count; i++) { 3067 if (!context->res_ctx.pipe_ctx[i].stream) 3068 continue; 3069 if (is_dp_128b_132b_signal(&context->res_ctx.pipe_ctx[i])) 3070 return true; 3071 } 3072 return false; 3073 } 3074 3075 static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struct dc_state *context) 3076 { 3077 int plane_count; 3078 int i; 3079 3080 plane_count = 0; 3081 for (i = 0; i < dc->res_pool->pipe_count; i++) { 3082 if (context->res_ctx.pipe_ctx[i].plane_state) 3083 plane_count++; 3084 } 3085 3086 /* 3087 * Zstate is allowed in following scenarios: 3088 * 1. Single eDP with PSR enabled 3089 * 2. 0 planes (No memory requests) 3090 * 3. Single eDP without PSR but > 5ms stutter period 3091 */ 3092 if (plane_count == 0) 3093 return DCN_ZSTATE_SUPPORT_ALLOW; 3094 else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) { 3095 struct dc_link *link = context->streams[0]->sink->link; 3096 3097 if ((link->link_index == 0 && link->psr_settings.psr_feature_enabled) 3098 || context->bw_ctx.dml.vba.StutterPeriod > 5000.0) 3099 return DCN_ZSTATE_SUPPORT_ALLOW; 3100 else 3101 return DCN_ZSTATE_SUPPORT_DISALLOW; 3102 } else 3103 return DCN_ZSTATE_SUPPORT_DISALLOW; 3104 } 3105 3106 void dcn20_calculate_dlg_params( 3107 struct dc *dc, struct dc_state *context, 3108 display_e2e_pipe_params_st *pipes, 3109 int pipe_cnt, 3110 int vlevel) 3111 { 3112 int i, pipe_idx; 3113 3114 /* Writeback MCIF_WB arbitration parameters */ 3115 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); 3116 3117 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; 3118 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; 3119 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; 3120 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; 3121 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; 3122 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; 3123 context->bw_ctx.bw.dcn.clk.p_state_change_support = 3124 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] 3125 != dm_dram_clock_change_unsupported; 3126 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 3127 3128 context->bw_ctx.bw.dcn.clk.zstate_support = decide_zstate_support(dc, context); 3129 3130 context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); 3131 3132 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) 3133 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; 3134 3135 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 3136 if (!context->res_ctx.pipe_ctx[i].stream) 3137 continue; 3138 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 3139 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 3140 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 3141 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 3142 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes; 3143 context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode; 3144 3145 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 3146 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 3147 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 3148 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 3149 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; 3150 pipe_idx++; 3151 } 3152 /*save a original dppclock copy*/ 3153 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; 3154 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; 3155 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000; 3156 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000; 3157 3158 context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes 3159 - context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx; 3160 3161 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 3162 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2; 3163 3164 if (!context->res_ctx.pipe_ctx[i].stream) 3165 continue; 3166 3167 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml, 3168 &context->res_ctx.pipe_ctx[i].dlg_regs, 3169 &context->res_ctx.pipe_ctx[i].ttu_regs, 3170 pipes, 3171 pipe_cnt, 3172 pipe_idx, 3173 cstate_en, 3174 context->bw_ctx.bw.dcn.clk.p_state_change_support, 3175 false, false, true); 3176 3177 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml, 3178 &context->res_ctx.pipe_ctx[i].rq_regs, 3179 pipes[pipe_idx].pipe); 3180 pipe_idx++; 3181 } 3182 } 3183 3184 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context, 3185 bool fast_validate) 3186 { 3187 bool out = false; 3188 3189 BW_VAL_TRACE_SETUP(); 3190 3191 int vlevel = 0; 3192 int pipe_split_from[MAX_PIPES]; 3193 int pipe_cnt = 0; 3194 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC); 3195 DC_LOGGER_INIT(dc->ctx->logger); 3196 3197 BW_VAL_TRACE_COUNT(); 3198 3199 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate); 3200 3201 if (pipe_cnt == 0) 3202 goto validate_out; 3203 3204 if (!out) 3205 goto validate_fail; 3206 3207 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 3208 3209 if (fast_validate) { 3210 BW_VAL_TRACE_SKIP(fast); 3211 goto validate_out; 3212 } 3213 3214 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate); 3215 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 3216 3217 BW_VAL_TRACE_END_WATERMARKS(); 3218 3219 goto validate_out; 3220 3221 validate_fail: 3222 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 3223 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 3224 3225 BW_VAL_TRACE_SKIP(fail); 3226 out = false; 3227 3228 validate_out: 3229 kfree(pipes); 3230 3231 BW_VAL_TRACE_FINISH(); 3232 3233 return out; 3234 } 3235 3236 /* 3237 * This must be noinline to ensure anything that deals with FP registers 3238 * is contained within this call; previously our compiling with hard-float 3239 * would result in fp instructions being emitted outside of the boundaries 3240 * of the DC_FP_START/END macros, which makes sense as the compiler has no 3241 * idea about what is wrapped and what is not 3242 * 3243 * This is largely just a workaround to avoid breakage introduced with 5.6, 3244 * ideally all fp-using code should be moved into its own file, only that 3245 * should be compiled with hard-float, and all code exported from there 3246 * should be strictly wrapped with DC_FP_START/END 3247 */ 3248 static noinline bool dcn20_validate_bandwidth_fp(struct dc *dc, 3249 struct dc_state *context, bool fast_validate) 3250 { 3251 bool voltage_supported = false; 3252 bool full_pstate_supported = false; 3253 bool dummy_pstate_supported = false; 3254 double p_state_latency_us; 3255 3256 p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us; 3257 context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support = 3258 dc->debug.disable_dram_clock_change_vactive_support; 3259 context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive = 3260 dc->debug.enable_dram_clock_change_one_display_vactive; 3261 3262 /*Unsafe due to current pipe merge and split logic*/ 3263 ASSERT(context != dc->current_state); 3264 3265 if (fast_validate) { 3266 return dcn20_validate_bandwidth_internal(dc, context, true); 3267 } 3268 3269 // Best case, we support full UCLK switch latency 3270 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); 3271 full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; 3272 3273 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 || 3274 (voltage_supported && full_pstate_supported)) { 3275 context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported; 3276 goto restore_dml_state; 3277 } 3278 3279 // Fallback: Try to only support G6 temperature read latency 3280 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us; 3281 3282 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); 3283 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; 3284 3285 if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) { 3286 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; 3287 goto restore_dml_state; 3288 } 3289 3290 // ERROR: fallback is supposed to always work. 3291 ASSERT(false); 3292 3293 restore_dml_state: 3294 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us; 3295 return voltage_supported; 3296 } 3297 3298 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, 3299 bool fast_validate) 3300 { 3301 bool voltage_supported; 3302 DC_FP_START(); 3303 voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate); 3304 DC_FP_END(); 3305 return voltage_supported; 3306 } 3307 3308 struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer( 3309 struct dc_state *state, 3310 const struct resource_pool *pool, 3311 struct dc_stream_state *stream) 3312 { 3313 struct resource_context *res_ctx = &state->res_ctx; 3314 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 3315 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe); 3316 3317 if (!head_pipe) 3318 ASSERT(0); 3319 3320 if (!idle_pipe) 3321 return NULL; 3322 3323 idle_pipe->stream = head_pipe->stream; 3324 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 3325 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 3326 3327 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 3328 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 3329 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 3330 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 3331 3332 return idle_pipe; 3333 } 3334 3335 bool dcn20_get_dcc_compression_cap(const struct dc *dc, 3336 const struct dc_dcc_surface_param *input, 3337 struct dc_surface_dcc_cap *output) 3338 { 3339 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 3340 dc->res_pool->hubbub, 3341 input, 3342 output); 3343 } 3344 3345 static void dcn20_destroy_resource_pool(struct resource_pool **pool) 3346 { 3347 struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool); 3348 3349 dcn20_resource_destruct(dcn20_pool); 3350 kfree(dcn20_pool); 3351 *pool = NULL; 3352 } 3353 3354 3355 static struct dc_cap_funcs cap_funcs = { 3356 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 3357 }; 3358 3359 3360 enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state) 3361 { 3362 enum surface_pixel_format surf_pix_format = plane_state->format; 3363 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 3364 3365 enum swizzle_mode_values swizzle = DC_SW_LINEAR; 3366 3367 if (bpp == 64) 3368 swizzle = DC_SW_64KB_D; 3369 else 3370 swizzle = DC_SW_64KB_S; 3371 3372 plane_state->tiling_info.gfx9.swizzle = swizzle; 3373 return DC_OK; 3374 } 3375 3376 static const struct resource_funcs dcn20_res_pool_funcs = { 3377 .destroy = dcn20_destroy_resource_pool, 3378 .link_enc_create = dcn20_link_encoder_create, 3379 .panel_cntl_create = dcn20_panel_cntl_create, 3380 .validate_bandwidth = dcn20_validate_bandwidth, 3381 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 3382 .add_stream_to_ctx = dcn20_add_stream_to_ctx, 3383 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 3384 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 3385 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, 3386 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 3387 .set_mcif_arb_params = dcn20_set_mcif_arb_params, 3388 .populate_dml_pipes = dcn20_populate_dml_pipes_from_context, 3389 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link 3390 }; 3391 3392 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 3393 { 3394 int i; 3395 uint32_t pipe_count = pool->res_cap->num_dwb; 3396 3397 for (i = 0; i < pipe_count; i++) { 3398 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc), 3399 GFP_KERNEL); 3400 3401 if (!dwbc20) { 3402 dm_error("DC: failed to create dwbc20!\n"); 3403 return false; 3404 } 3405 dcn20_dwbc_construct(dwbc20, ctx, 3406 &dwbc20_regs[i], 3407 &dwbc20_shift, 3408 &dwbc20_mask, 3409 i); 3410 pool->dwbc[i] = &dwbc20->base; 3411 } 3412 return true; 3413 } 3414 3415 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 3416 { 3417 int i; 3418 uint32_t pipe_count = pool->res_cap->num_dwb; 3419 3420 ASSERT(pipe_count > 0); 3421 3422 for (i = 0; i < pipe_count; i++) { 3423 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub), 3424 GFP_KERNEL); 3425 3426 if (!mcif_wb20) { 3427 dm_error("DC: failed to create mcif_wb20!\n"); 3428 return false; 3429 } 3430 3431 dcn20_mmhubbub_construct(mcif_wb20, ctx, 3432 &mcif_wb20_regs[i], 3433 &mcif_wb20_shift, 3434 &mcif_wb20_mask, 3435 i); 3436 3437 pool->mcif_wb[i] = &mcif_wb20->base; 3438 } 3439 return true; 3440 } 3441 3442 static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx) 3443 { 3444 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_ATOMIC); 3445 3446 if (!pp_smu) 3447 return pp_smu; 3448 3449 dm_pp_get_funcs(ctx, pp_smu); 3450 3451 if (pp_smu->ctx.ver != PP_SMU_VER_NV) 3452 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); 3453 3454 return pp_smu; 3455 } 3456 3457 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu) 3458 { 3459 if (pp_smu && *pp_smu) { 3460 kfree(*pp_smu); 3461 *pp_smu = NULL; 3462 } 3463 } 3464 3465 void dcn20_cap_soc_clocks( 3466 struct _vcs_dpi_soc_bounding_box_st *bb, 3467 struct pp_smu_nv_clock_table max_clocks) 3468 { 3469 int i; 3470 3471 // First pass - cap all clocks higher than the reported max 3472 for (i = 0; i < bb->num_states; i++) { 3473 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000)) 3474 && max_clocks.dcfClockInKhz != 0) 3475 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000); 3476 3477 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16) 3478 && max_clocks.uClockInKhz != 0) 3479 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16; 3480 3481 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000)) 3482 && max_clocks.fabricClockInKhz != 0) 3483 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000); 3484 3485 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000)) 3486 && max_clocks.displayClockInKhz != 0) 3487 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000); 3488 3489 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000)) 3490 && max_clocks.dppClockInKhz != 0) 3491 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000); 3492 3493 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000)) 3494 && max_clocks.phyClockInKhz != 0) 3495 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000); 3496 3497 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000)) 3498 && max_clocks.socClockInKhz != 0) 3499 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000); 3500 3501 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000)) 3502 && max_clocks.dscClockInKhz != 0) 3503 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000); 3504 } 3505 3506 // Second pass - remove all duplicate clock states 3507 for (i = bb->num_states - 1; i > 1; i--) { 3508 bool duplicate = true; 3509 3510 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz) 3511 duplicate = false; 3512 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz) 3513 duplicate = false; 3514 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz) 3515 duplicate = false; 3516 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts) 3517 duplicate = false; 3518 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz) 3519 duplicate = false; 3520 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz) 3521 duplicate = false; 3522 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz) 3523 duplicate = false; 3524 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz) 3525 duplicate = false; 3526 3527 if (duplicate) 3528 bb->num_states--; 3529 } 3530 } 3531 3532 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb, 3533 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) 3534 { 3535 struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES]; 3536 int i; 3537 int num_calculated_states = 0; 3538 int min_dcfclk = 0; 3539 3540 if (num_states == 0) 3541 return; 3542 3543 memset(calculated_states, 0, sizeof(calculated_states)); 3544 3545 if (dc->bb_overrides.min_dcfclk_mhz > 0) 3546 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz; 3547 else { 3548 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) 3549 min_dcfclk = 310; 3550 else 3551 // Accounting for SOC/DCF relationship, we can go as high as 3552 // 506Mhz in Vmin. 3553 min_dcfclk = 506; 3554 } 3555 3556 for (i = 0; i < num_states; i++) { 3557 int min_fclk_required_by_uclk; 3558 calculated_states[i].state = i; 3559 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000; 3560 3561 // FCLK:UCLK ratio is 1.08 3562 min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080, 3563 1000000); 3564 3565 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? 3566 min_dcfclk : min_fclk_required_by_uclk; 3567 3568 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ? 3569 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; 3570 3571 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ? 3572 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; 3573 3574 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000; 3575 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000; 3576 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3); 3577 3578 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000; 3579 3580 num_calculated_states++; 3581 } 3582 3583 calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000; 3584 calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000; 3585 calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000; 3586 3587 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits)); 3588 bb->num_states = num_calculated_states; 3589 3590 // Duplicate the last state, DML always an extra state identical to max state to work 3591 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st)); 3592 bb->clock_limits[num_calculated_states].state = bb->num_states; 3593 } 3594 3595 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) 3596 { 3597 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns 3598 && dc->bb_overrides.sr_exit_time_ns) { 3599 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; 3600 } 3601 3602 if ((int)(bb->sr_enter_plus_exit_time_us * 1000) 3603 != dc->bb_overrides.sr_enter_plus_exit_time_ns 3604 && dc->bb_overrides.sr_enter_plus_exit_time_ns) { 3605 bb->sr_enter_plus_exit_time_us = 3606 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 3607 } 3608 3609 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns 3610 && dc->bb_overrides.urgent_latency_ns) { 3611 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 3612 } 3613 3614 if ((int)(bb->dram_clock_change_latency_us * 1000) 3615 != dc->bb_overrides.dram_clock_change_latency_ns 3616 && dc->bb_overrides.dram_clock_change_latency_ns) { 3617 bb->dram_clock_change_latency_us = 3618 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 3619 } 3620 3621 if ((int)(bb->dummy_pstate_latency_us * 1000) 3622 != dc->bb_overrides.dummy_clock_change_latency_ns 3623 && dc->bb_overrides.dummy_clock_change_latency_ns) { 3624 bb->dummy_pstate_latency_us = 3625 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0; 3626 } 3627 } 3628 3629 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb( 3630 uint32_t hw_internal_rev) 3631 { 3632 if (ASICREV_IS_NAVI14_M(hw_internal_rev)) 3633 return &dcn2_0_nv14_soc; 3634 3635 if (ASICREV_IS_NAVI12_P(hw_internal_rev)) 3636 return &dcn2_0_nv12_soc; 3637 3638 return &dcn2_0_soc; 3639 } 3640 3641 static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params( 3642 uint32_t hw_internal_rev) 3643 { 3644 /* NV14 */ 3645 if (ASICREV_IS_NAVI14_M(hw_internal_rev)) 3646 return &dcn2_0_nv14_ip; 3647 3648 /* NV12 and NV10 */ 3649 return &dcn2_0_ip; 3650 } 3651 3652 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev) 3653 { 3654 return DML_PROJECT_NAVI10v2; 3655 } 3656 3657 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16))) 3658 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) 3659 3660 static bool init_soc_bounding_box(struct dc *dc, 3661 struct dcn20_resource_pool *pool) 3662 { 3663 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = 3664 get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev); 3665 struct _vcs_dpi_ip_params_st *loaded_ip = 3666 get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev); 3667 3668 DC_LOGGER_INIT(dc->ctx->logger); 3669 3670 if (pool->base.pp_smu) { 3671 struct pp_smu_nv_clock_table max_clocks = {0}; 3672 unsigned int uclk_states[8] = {0}; 3673 unsigned int num_states = 0; 3674 enum pp_smu_status status; 3675 bool clock_limits_available = false; 3676 bool uclk_states_available = false; 3677 3678 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) { 3679 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) 3680 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); 3681 3682 uclk_states_available = (status == PP_SMU_RESULT_OK); 3683 } 3684 3685 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) { 3686 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) 3687 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks); 3688 /* SMU cannot set DCF clock to anything equal to or higher than SOC clock 3689 */ 3690 if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz) 3691 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000; 3692 clock_limits_available = (status == PP_SMU_RESULT_OK); 3693 } 3694 3695 if (clock_limits_available && uclk_states_available && num_states) 3696 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states); 3697 else if (clock_limits_available) 3698 dcn20_cap_soc_clocks(loaded_bb, max_clocks); 3699 } 3700 3701 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; 3702 loaded_ip->max_num_dpp = pool->base.pipe_count; 3703 dcn20_patch_bounding_box(dc, loaded_bb); 3704 3705 return true; 3706 } 3707 3708 static bool dcn20_resource_construct( 3709 uint8_t num_virtual_links, 3710 struct dc *dc, 3711 struct dcn20_resource_pool *pool) 3712 { 3713 int i; 3714 struct dc_context *ctx = dc->ctx; 3715 struct irq_service_init_data init_data; 3716 struct ddc_service_init_data ddc_init_data = {0}; 3717 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = 3718 get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev); 3719 struct _vcs_dpi_ip_params_st *loaded_ip = 3720 get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev); 3721 enum dml_project dml_project_version = 3722 get_dml_project_version(ctx->asic_id.hw_internal_rev); 3723 3724 DC_FP_START(); 3725 3726 ctx->dc_bios->regs = &bios_regs; 3727 pool->base.funcs = &dcn20_res_pool_funcs; 3728 3729 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) { 3730 pool->base.res_cap = &res_cap_nv14; 3731 pool->base.pipe_count = 5; 3732 pool->base.mpcc_count = 5; 3733 } else { 3734 pool->base.res_cap = &res_cap_nv10; 3735 pool->base.pipe_count = 6; 3736 pool->base.mpcc_count = 6; 3737 } 3738 /************************************************* 3739 * Resource + asic cap harcoding * 3740 *************************************************/ 3741 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 3742 3743 dc->caps.max_downscale_ratio = 200; 3744 dc->caps.i2c_speed_in_khz = 100; 3745 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/ 3746 dc->caps.max_cursor_size = 256; 3747 dc->caps.min_horizontal_blanking_period = 80; 3748 dc->caps.dmdata_alloc_size = 2048; 3749 3750 dc->caps.max_slave_planes = 1; 3751 dc->caps.max_slave_yuv_planes = 1; 3752 dc->caps.max_slave_rgb_planes = 1; 3753 dc->caps.post_blend_color_processing = true; 3754 dc->caps.force_dp_tps4_for_cp2520 = true; 3755 dc->caps.extended_aux_timeout_support = true; 3756 3757 /* Color pipeline capabilities */ 3758 dc->caps.color.dpp.dcn_arch = 1; 3759 dc->caps.color.dpp.input_lut_shared = 0; 3760 dc->caps.color.dpp.icsc = 1; 3761 dc->caps.color.dpp.dgam_ram = 1; 3762 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 3763 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 3764 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0; 3765 dc->caps.color.dpp.dgam_rom_caps.pq = 0; 3766 dc->caps.color.dpp.dgam_rom_caps.hlg = 0; 3767 dc->caps.color.dpp.post_csc = 0; 3768 dc->caps.color.dpp.gamma_corr = 0; 3769 dc->caps.color.dpp.dgam_rom_for_yuv = 1; 3770 3771 dc->caps.color.dpp.hw_3d_lut = 1; 3772 dc->caps.color.dpp.ogam_ram = 1; 3773 // no OGAM ROM on DCN2, only MPC ROM 3774 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 3775 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 3776 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 3777 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 3778 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 3779 dc->caps.color.dpp.ocsc = 0; 3780 3781 dc->caps.color.mpc.gamut_remap = 0; 3782 dc->caps.color.mpc.num_3dluts = 0; 3783 dc->caps.color.mpc.shared_3d_lut = 0; 3784 dc->caps.color.mpc.ogam_ram = 1; 3785 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 3786 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 3787 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 3788 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 3789 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 3790 dc->caps.color.mpc.ocsc = 1; 3791 3792 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) { 3793 dc->debug = debug_defaults_drv; 3794 } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 3795 pool->base.pipe_count = 4; 3796 pool->base.mpcc_count = pool->base.pipe_count; 3797 dc->debug = debug_defaults_diags; 3798 } else { 3799 dc->debug = debug_defaults_diags; 3800 } 3801 //dcn2.0x 3802 dc->work_arounds.dedcn20_305_wa = true; 3803 3804 // Init the vm_helper 3805 if (dc->vm_helper) 3806 vm_helper_init(dc->vm_helper, 16); 3807 3808 /************************************************* 3809 * Create resources * 3810 *************************************************/ 3811 3812 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = 3813 dcn20_clock_source_create(ctx, ctx->dc_bios, 3814 CLOCK_SOURCE_COMBO_PHY_PLL0, 3815 &clk_src_regs[0], false); 3816 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = 3817 dcn20_clock_source_create(ctx, ctx->dc_bios, 3818 CLOCK_SOURCE_COMBO_PHY_PLL1, 3819 &clk_src_regs[1], false); 3820 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = 3821 dcn20_clock_source_create(ctx, ctx->dc_bios, 3822 CLOCK_SOURCE_COMBO_PHY_PLL2, 3823 &clk_src_regs[2], false); 3824 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] = 3825 dcn20_clock_source_create(ctx, ctx->dc_bios, 3826 CLOCK_SOURCE_COMBO_PHY_PLL3, 3827 &clk_src_regs[3], false); 3828 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] = 3829 dcn20_clock_source_create(ctx, ctx->dc_bios, 3830 CLOCK_SOURCE_COMBO_PHY_PLL4, 3831 &clk_src_regs[4], false); 3832 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] = 3833 dcn20_clock_source_create(ctx, ctx->dc_bios, 3834 CLOCK_SOURCE_COMBO_PHY_PLL5, 3835 &clk_src_regs[5], false); 3836 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL; 3837 /* todo: not reuse phy_pll registers */ 3838 pool->base.dp_clock_source = 3839 dcn20_clock_source_create(ctx, ctx->dc_bios, 3840 CLOCK_SOURCE_ID_DP_DTO, 3841 &clk_src_regs[0], true); 3842 3843 for (i = 0; i < pool->base.clk_src_count; i++) { 3844 if (pool->base.clock_sources[i] == NULL) { 3845 dm_error("DC: failed to create clock sources!\n"); 3846 BREAK_TO_DEBUGGER(); 3847 goto create_fail; 3848 } 3849 } 3850 3851 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 3852 if (pool->base.dccg == NULL) { 3853 dm_error("DC: failed to create dccg!\n"); 3854 BREAK_TO_DEBUGGER(); 3855 goto create_fail; 3856 } 3857 3858 pool->base.dmcu = dcn20_dmcu_create(ctx, 3859 &dmcu_regs, 3860 &dmcu_shift, 3861 &dmcu_mask); 3862 if (pool->base.dmcu == NULL) { 3863 dm_error("DC: failed to create dmcu!\n"); 3864 BREAK_TO_DEBUGGER(); 3865 goto create_fail; 3866 } 3867 3868 pool->base.abm = dce_abm_create(ctx, 3869 &abm_regs, 3870 &abm_shift, 3871 &abm_mask); 3872 if (pool->base.abm == NULL) { 3873 dm_error("DC: failed to create abm!\n"); 3874 BREAK_TO_DEBUGGER(); 3875 goto create_fail; 3876 } 3877 3878 pool->base.pp_smu = dcn20_pp_smu_create(ctx); 3879 3880 3881 if (!init_soc_bounding_box(dc, pool)) { 3882 dm_error("DC: failed to initialize soc bounding box!\n"); 3883 BREAK_TO_DEBUGGER(); 3884 goto create_fail; 3885 } 3886 3887 dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version); 3888 3889 if (!dc->debug.disable_pplib_wm_range) { 3890 struct pp_smu_wm_range_sets ranges = {0}; 3891 int i = 0; 3892 3893 ranges.num_reader_wm_sets = 0; 3894 3895 if (loaded_bb->num_states == 1) { 3896 ranges.reader_wm_sets[0].wm_inst = i; 3897 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3898 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3899 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3900 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3901 3902 ranges.num_reader_wm_sets = 1; 3903 } else if (loaded_bb->num_states > 1) { 3904 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { 3905 ranges.reader_wm_sets[i].wm_inst = i; 3906 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3907 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3908 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; 3909 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; 3910 3911 ranges.num_reader_wm_sets = i + 1; 3912 } 3913 3914 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3915 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3916 } 3917 3918 ranges.num_writer_wm_sets = 1; 3919 3920 ranges.writer_wm_sets[0].wm_inst = 0; 3921 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3922 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3923 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3924 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3925 3926 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 3927 if (pool->base.pp_smu->nv_funcs.set_wm_ranges) 3928 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges); 3929 } 3930 3931 init_data.ctx = dc->ctx; 3932 pool->base.irqs = dal_irq_service_dcn20_create(&init_data); 3933 if (!pool->base.irqs) 3934 goto create_fail; 3935 3936 /* mem input -> ipp -> dpp -> opp -> TG */ 3937 for (i = 0; i < pool->base.pipe_count; i++) { 3938 pool->base.hubps[i] = dcn20_hubp_create(ctx, i); 3939 if (pool->base.hubps[i] == NULL) { 3940 BREAK_TO_DEBUGGER(); 3941 dm_error( 3942 "DC: failed to create memory input!\n"); 3943 goto create_fail; 3944 } 3945 3946 pool->base.ipps[i] = dcn20_ipp_create(ctx, i); 3947 if (pool->base.ipps[i] == NULL) { 3948 BREAK_TO_DEBUGGER(); 3949 dm_error( 3950 "DC: failed to create input pixel processor!\n"); 3951 goto create_fail; 3952 } 3953 3954 pool->base.dpps[i] = dcn20_dpp_create(ctx, i); 3955 if (pool->base.dpps[i] == NULL) { 3956 BREAK_TO_DEBUGGER(); 3957 dm_error( 3958 "DC: failed to create dpps!\n"); 3959 goto create_fail; 3960 } 3961 } 3962 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 3963 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i); 3964 if (pool->base.engines[i] == NULL) { 3965 BREAK_TO_DEBUGGER(); 3966 dm_error( 3967 "DC:failed to create aux engine!!\n"); 3968 goto create_fail; 3969 } 3970 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i); 3971 if (pool->base.hw_i2cs[i] == NULL) { 3972 BREAK_TO_DEBUGGER(); 3973 dm_error( 3974 "DC:failed to create hw i2c!!\n"); 3975 goto create_fail; 3976 } 3977 pool->base.sw_i2cs[i] = NULL; 3978 } 3979 3980 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 3981 pool->base.opps[i] = dcn20_opp_create(ctx, i); 3982 if (pool->base.opps[i] == NULL) { 3983 BREAK_TO_DEBUGGER(); 3984 dm_error( 3985 "DC: failed to create output pixel processor!\n"); 3986 goto create_fail; 3987 } 3988 } 3989 3990 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 3991 pool->base.timing_generators[i] = dcn20_timing_generator_create( 3992 ctx, i); 3993 if (pool->base.timing_generators[i] == NULL) { 3994 BREAK_TO_DEBUGGER(); 3995 dm_error("DC: failed to create tg!\n"); 3996 goto create_fail; 3997 } 3998 } 3999 4000 pool->base.timing_generator_count = i; 4001 4002 pool->base.mpc = dcn20_mpc_create(ctx); 4003 if (pool->base.mpc == NULL) { 4004 BREAK_TO_DEBUGGER(); 4005 dm_error("DC: failed to create mpc!\n"); 4006 goto create_fail; 4007 } 4008 4009 pool->base.hubbub = dcn20_hubbub_create(ctx); 4010 if (pool->base.hubbub == NULL) { 4011 BREAK_TO_DEBUGGER(); 4012 dm_error("DC: failed to create hubbub!\n"); 4013 goto create_fail; 4014 } 4015 4016 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 4017 pool->base.dscs[i] = dcn20_dsc_create(ctx, i); 4018 if (pool->base.dscs[i] == NULL) { 4019 BREAK_TO_DEBUGGER(); 4020 dm_error("DC: failed to create display stream compressor %d!\n", i); 4021 goto create_fail; 4022 } 4023 } 4024 4025 if (!dcn20_dwbc_create(ctx, &pool->base)) { 4026 BREAK_TO_DEBUGGER(); 4027 dm_error("DC: failed to create dwbc!\n"); 4028 goto create_fail; 4029 } 4030 if (!dcn20_mmhubbub_create(ctx, &pool->base)) { 4031 BREAK_TO_DEBUGGER(); 4032 dm_error("DC: failed to create mcif_wb!\n"); 4033 goto create_fail; 4034 } 4035 4036 if (!resource_construct(num_virtual_links, dc, &pool->base, 4037 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 4038 &res_create_funcs : &res_create_maximus_funcs))) 4039 goto create_fail; 4040 4041 dcn20_hw_sequencer_construct(dc); 4042 4043 // IF NV12, set PG function pointer to NULL. It's not that 4044 // PG isn't supported for NV12, it's that we don't want to 4045 // program the registers because that will cause more power 4046 // to be consumed. We could have created dcn20_init_hw to get 4047 // the same effect by checking ASIC rev, but there was a 4048 // request at some point to not check ASIC rev on hw sequencer. 4049 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) { 4050 dc->hwseq->funcs.enable_power_gating_plane = NULL; 4051 dc->debug.disable_dpp_power_gate = true; 4052 dc->debug.disable_hubp_power_gate = true; 4053 } 4054 4055 4056 dc->caps.max_planes = pool->base.pipe_count; 4057 4058 for (i = 0; i < dc->caps.max_planes; ++i) 4059 dc->caps.planes[i] = plane_cap; 4060 4061 dc->cap_funcs = cap_funcs; 4062 4063 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 4064 ddc_init_data.ctx = dc->ctx; 4065 ddc_init_data.link = NULL; 4066 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 4067 ddc_init_data.id.enum_id = 0; 4068 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 4069 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); 4070 } else { 4071 pool->base.oem_device = NULL; 4072 } 4073 4074 DC_FP_END(); 4075 return true; 4076 4077 create_fail: 4078 4079 DC_FP_END(); 4080 dcn20_resource_destruct(pool); 4081 4082 return false; 4083 } 4084 4085 struct resource_pool *dcn20_create_resource_pool( 4086 const struct dc_init_data *init_data, 4087 struct dc *dc) 4088 { 4089 struct dcn20_resource_pool *pool = 4090 kzalloc(sizeof(struct dcn20_resource_pool), GFP_ATOMIC); 4091 4092 if (!pool) 4093 return NULL; 4094 4095 if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool)) 4096 return &pool->base; 4097 4098 BREAK_TO_DEBUGGER(); 4099 kfree(pool); 4100 return NULL; 4101 } 4102