1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3  * Copyright 2019 Raptor Engineering, LLC
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 
27 #include <linux/slab.h>
28 
29 #include "dm_services.h"
30 #include "dc.h"
31 
32 #include "dcn20_init.h"
33 
34 #include "resource.h"
35 #include "include/irq_service_interface.h"
36 #include "dcn20/dcn20_resource.h"
37 
38 #include "dml/dcn20/dcn20_fpu.h"
39 
40 #include "dcn10/dcn10_hubp.h"
41 #include "dcn10/dcn10_ipp.h"
42 #include "dcn20_hubbub.h"
43 #include "dcn20_mpc.h"
44 #include "dcn20_hubp.h"
45 #include "irq/dcn20/irq_service_dcn20.h"
46 #include "dcn20_dpp.h"
47 #include "dcn20_optc.h"
48 #include "dcn20_hwseq.h"
49 #include "dce110/dce110_hw_sequencer.h"
50 #include "dcn10/dcn10_resource.h"
51 #include "dcn20_opp.h"
52 
53 #include "dcn20_dsc.h"
54 
55 #include "dcn20_link_encoder.h"
56 #include "dcn20_stream_encoder.h"
57 #include "dce/dce_clock_source.h"
58 #include "dce/dce_audio.h"
59 #include "dce/dce_hwseq.h"
60 #include "virtual/virtual_stream_encoder.h"
61 #include "dce110/dce110_resource.h"
62 #include "dml/display_mode_vba.h"
63 #include "dcn20_dccg.h"
64 #include "dcn20_vmid.h"
65 #include "dc_link_ddc.h"
66 #include "dc_link_dp.h"
67 #include "dce/dce_panel_cntl.h"
68 
69 #include "navi10_ip_offset.h"
70 
71 #include "dcn/dcn_2_0_0_offset.h"
72 #include "dcn/dcn_2_0_0_sh_mask.h"
73 #include "dpcs/dpcs_2_0_0_offset.h"
74 #include "dpcs/dpcs_2_0_0_sh_mask.h"
75 
76 #include "nbio/nbio_2_3_offset.h"
77 
78 #include "dcn20/dcn20_dwb.h"
79 #include "dcn20/dcn20_mmhubbub.h"
80 
81 #include "mmhub/mmhub_2_0_0_offset.h"
82 #include "mmhub/mmhub_2_0_0_sh_mask.h"
83 
84 #include "reg_helper.h"
85 #include "dce/dce_abm.h"
86 #include "dce/dce_dmcu.h"
87 #include "dce/dce_aux.h"
88 #include "dce/dce_i2c.h"
89 #include "vm_helper.h"
90 #include "link_enc_cfg.h"
91 
92 #include "amdgpu_socbb.h"
93 
94 #define DC_LOGGER_INIT(logger)
95 
96 struct _vcs_dpi_ip_params_st dcn2_0_ip = {
97 	.odm_capable = 1,
98 	.gpuvm_enable = 0,
99 	.hostvm_enable = 0,
100 	.gpuvm_max_page_table_levels = 4,
101 	.hostvm_max_page_table_levels = 4,
102 	.hostvm_cached_page_table_levels = 0,
103 	.pte_group_size_bytes = 2048,
104 	.num_dsc = 6,
105 	.rob_buffer_size_kbytes = 168,
106 	.det_buffer_size_kbytes = 164,
107 	.dpte_buffer_size_in_pte_reqs_luma = 84,
108 	.pde_proc_buffer_size_64k_reqs = 48,
109 	.dpp_output_buffer_pixels = 2560,
110 	.opp_output_buffer_lines = 1,
111 	.pixel_chunk_size_kbytes = 8,
112 	.pte_chunk_size_kbytes = 2,
113 	.meta_chunk_size_kbytes = 2,
114 	.writeback_chunk_size_kbytes = 2,
115 	.line_buffer_size_bits = 789504,
116 	.is_line_buffer_bpp_fixed = 0,
117 	.line_buffer_fixed_bpp = 0,
118 	.dcc_supported = true,
119 	.max_line_buffer_lines = 12,
120 	.writeback_luma_buffer_size_kbytes = 12,
121 	.writeback_chroma_buffer_size_kbytes = 8,
122 	.writeback_chroma_line_buffer_width_pixels = 4,
123 	.writeback_max_hscl_ratio = 1,
124 	.writeback_max_vscl_ratio = 1,
125 	.writeback_min_hscl_ratio = 1,
126 	.writeback_min_vscl_ratio = 1,
127 	.writeback_max_hscl_taps = 12,
128 	.writeback_max_vscl_taps = 12,
129 	.writeback_line_buffer_luma_buffer_size = 0,
130 	.writeback_line_buffer_chroma_buffer_size = 14643,
131 	.cursor_buffer_size = 8,
132 	.cursor_chunk_size = 2,
133 	.max_num_otg = 6,
134 	.max_num_dpp = 6,
135 	.max_num_wb = 1,
136 	.max_dchub_pscl_bw_pix_per_clk = 4,
137 	.max_pscl_lb_bw_pix_per_clk = 2,
138 	.max_lb_vscl_bw_pix_per_clk = 4,
139 	.max_vscl_hscl_bw_pix_per_clk = 4,
140 	.max_hscl_ratio = 8,
141 	.max_vscl_ratio = 8,
142 	.hscl_mults = 4,
143 	.vscl_mults = 4,
144 	.max_hscl_taps = 8,
145 	.max_vscl_taps = 8,
146 	.dispclk_ramp_margin_percent = 1,
147 	.underscan_factor = 1.10,
148 	.min_vblank_lines = 32, //
149 	.dppclk_delay_subtotal = 77, //
150 	.dppclk_delay_scl_lb_only = 16,
151 	.dppclk_delay_scl = 50,
152 	.dppclk_delay_cnvc_formatter = 8,
153 	.dppclk_delay_cnvc_cursor = 6,
154 	.dispclk_delay_subtotal = 87, //
155 	.dcfclk_cstate_latency = 10, // SRExitTime
156 	.max_inter_dcn_tile_repeaters = 8,
157 	.xfc_supported = true,
158 	.xfc_fill_bw_overhead_percent = 10.0,
159 	.xfc_fill_constant_bytes = 0,
160 	.number_of_cursors = 1,
161 };
162 
163 static struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
164 	.odm_capable = 1,
165 	.gpuvm_enable = 0,
166 	.hostvm_enable = 0,
167 	.gpuvm_max_page_table_levels = 4,
168 	.hostvm_max_page_table_levels = 4,
169 	.hostvm_cached_page_table_levels = 0,
170 	.num_dsc = 5,
171 	.rob_buffer_size_kbytes = 168,
172 	.det_buffer_size_kbytes = 164,
173 	.dpte_buffer_size_in_pte_reqs_luma = 84,
174 	.dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
175 	.dpp_output_buffer_pixels = 2560,
176 	.opp_output_buffer_lines = 1,
177 	.pixel_chunk_size_kbytes = 8,
178 	.pte_enable = 1,
179 	.max_page_table_levels = 4,
180 	.pte_chunk_size_kbytes = 2,
181 	.meta_chunk_size_kbytes = 2,
182 	.writeback_chunk_size_kbytes = 2,
183 	.line_buffer_size_bits = 789504,
184 	.is_line_buffer_bpp_fixed = 0,
185 	.line_buffer_fixed_bpp = 0,
186 	.dcc_supported = true,
187 	.max_line_buffer_lines = 12,
188 	.writeback_luma_buffer_size_kbytes = 12,
189 	.writeback_chroma_buffer_size_kbytes = 8,
190 	.writeback_chroma_line_buffer_width_pixels = 4,
191 	.writeback_max_hscl_ratio = 1,
192 	.writeback_max_vscl_ratio = 1,
193 	.writeback_min_hscl_ratio = 1,
194 	.writeback_min_vscl_ratio = 1,
195 	.writeback_max_hscl_taps = 12,
196 	.writeback_max_vscl_taps = 12,
197 	.writeback_line_buffer_luma_buffer_size = 0,
198 	.writeback_line_buffer_chroma_buffer_size = 14643,
199 	.cursor_buffer_size = 8,
200 	.cursor_chunk_size = 2,
201 	.max_num_otg = 5,
202 	.max_num_dpp = 5,
203 	.max_num_wb = 1,
204 	.max_dchub_pscl_bw_pix_per_clk = 4,
205 	.max_pscl_lb_bw_pix_per_clk = 2,
206 	.max_lb_vscl_bw_pix_per_clk = 4,
207 	.max_vscl_hscl_bw_pix_per_clk = 4,
208 	.max_hscl_ratio = 8,
209 	.max_vscl_ratio = 8,
210 	.hscl_mults = 4,
211 	.vscl_mults = 4,
212 	.max_hscl_taps = 8,
213 	.max_vscl_taps = 8,
214 	.dispclk_ramp_margin_percent = 1,
215 	.underscan_factor = 1.10,
216 	.min_vblank_lines = 32, //
217 	.dppclk_delay_subtotal = 77, //
218 	.dppclk_delay_scl_lb_only = 16,
219 	.dppclk_delay_scl = 50,
220 	.dppclk_delay_cnvc_formatter = 8,
221 	.dppclk_delay_cnvc_cursor = 6,
222 	.dispclk_delay_subtotal = 87, //
223 	.dcfclk_cstate_latency = 10, // SRExitTime
224 	.max_inter_dcn_tile_repeaters = 8,
225 	.xfc_supported = true,
226 	.xfc_fill_bw_overhead_percent = 10.0,
227 	.xfc_fill_constant_bytes = 0,
228 	.ptoi_supported = 0,
229 	.number_of_cursors = 1,
230 };
231 
232 static struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
233 	/* Defaults that get patched on driver load from firmware. */
234 	.clock_limits = {
235 			{
236 				.state = 0,
237 				.dcfclk_mhz = 560.0,
238 				.fabricclk_mhz = 560.0,
239 				.dispclk_mhz = 513.0,
240 				.dppclk_mhz = 513.0,
241 				.phyclk_mhz = 540.0,
242 				.socclk_mhz = 560.0,
243 				.dscclk_mhz = 171.0,
244 				.dram_speed_mts = 8960.0,
245 			},
246 			{
247 				.state = 1,
248 				.dcfclk_mhz = 694.0,
249 				.fabricclk_mhz = 694.0,
250 				.dispclk_mhz = 642.0,
251 				.dppclk_mhz = 642.0,
252 				.phyclk_mhz = 600.0,
253 				.socclk_mhz = 694.0,
254 				.dscclk_mhz = 214.0,
255 				.dram_speed_mts = 11104.0,
256 			},
257 			{
258 				.state = 2,
259 				.dcfclk_mhz = 875.0,
260 				.fabricclk_mhz = 875.0,
261 				.dispclk_mhz = 734.0,
262 				.dppclk_mhz = 734.0,
263 				.phyclk_mhz = 810.0,
264 				.socclk_mhz = 875.0,
265 				.dscclk_mhz = 245.0,
266 				.dram_speed_mts = 14000.0,
267 			},
268 			{
269 				.state = 3,
270 				.dcfclk_mhz = 1000.0,
271 				.fabricclk_mhz = 1000.0,
272 				.dispclk_mhz = 1100.0,
273 				.dppclk_mhz = 1100.0,
274 				.phyclk_mhz = 810.0,
275 				.socclk_mhz = 1000.0,
276 				.dscclk_mhz = 367.0,
277 				.dram_speed_mts = 16000.0,
278 			},
279 			{
280 				.state = 4,
281 				.dcfclk_mhz = 1200.0,
282 				.fabricclk_mhz = 1200.0,
283 				.dispclk_mhz = 1284.0,
284 				.dppclk_mhz = 1284.0,
285 				.phyclk_mhz = 810.0,
286 				.socclk_mhz = 1200.0,
287 				.dscclk_mhz = 428.0,
288 				.dram_speed_mts = 16000.0,
289 			},
290 			/*Extra state, no dispclk ramping*/
291 			{
292 				.state = 5,
293 				.dcfclk_mhz = 1200.0,
294 				.fabricclk_mhz = 1200.0,
295 				.dispclk_mhz = 1284.0,
296 				.dppclk_mhz = 1284.0,
297 				.phyclk_mhz = 810.0,
298 				.socclk_mhz = 1200.0,
299 				.dscclk_mhz = 428.0,
300 				.dram_speed_mts = 16000.0,
301 			},
302 		},
303 	.num_states = 5,
304 	.sr_exit_time_us = 8.6,
305 	.sr_enter_plus_exit_time_us = 10.9,
306 	.urgent_latency_us = 4.0,
307 	.urgent_latency_pixel_data_only_us = 4.0,
308 	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
309 	.urgent_latency_vm_data_only_us = 4.0,
310 	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
311 	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
312 	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
313 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
314 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
315 	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
316 	.max_avg_sdp_bw_use_normal_percent = 40.0,
317 	.max_avg_dram_bw_use_normal_percent = 40.0,
318 	.writeback_latency_us = 12.0,
319 	.ideal_dram_bw_after_urgent_percent = 40.0,
320 	.max_request_size_bytes = 256,
321 	.dram_channel_width_bytes = 2,
322 	.fabric_datapath_to_dcn_data_return_bytes = 64,
323 	.dcn_downspread_percent = 0.5,
324 	.downspread_percent = 0.38,
325 	.dram_page_open_time_ns = 50.0,
326 	.dram_rw_turnaround_time_ns = 17.5,
327 	.dram_return_buffer_per_channel_bytes = 8192,
328 	.round_trip_ping_latency_dcfclk_cycles = 131,
329 	.urgent_out_of_order_return_per_channel_bytes = 256,
330 	.channel_interleave_bytes = 256,
331 	.num_banks = 8,
332 	.num_chans = 16,
333 	.vmm_page_size_bytes = 4096,
334 	.dram_clock_change_latency_us = 404.0,
335 	.dummy_pstate_latency_us = 5.0,
336 	.writeback_dram_clock_change_latency_us = 23.0,
337 	.return_bus_width_bytes = 64,
338 	.dispclk_dppclk_vco_speed_mhz = 3850,
339 	.xfc_bus_transport_time_us = 20,
340 	.xfc_xbuf_latency_tolerance_us = 4,
341 	.use_urgent_burst_bw = 0
342 };
343 
344 static struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
345 	.clock_limits = {
346 			{
347 				.state = 0,
348 				.dcfclk_mhz = 560.0,
349 				.fabricclk_mhz = 560.0,
350 				.dispclk_mhz = 513.0,
351 				.dppclk_mhz = 513.0,
352 				.phyclk_mhz = 540.0,
353 				.socclk_mhz = 560.0,
354 				.dscclk_mhz = 171.0,
355 				.dram_speed_mts = 8960.0,
356 			},
357 			{
358 				.state = 1,
359 				.dcfclk_mhz = 694.0,
360 				.fabricclk_mhz = 694.0,
361 				.dispclk_mhz = 642.0,
362 				.dppclk_mhz = 642.0,
363 				.phyclk_mhz = 600.0,
364 				.socclk_mhz = 694.0,
365 				.dscclk_mhz = 214.0,
366 				.dram_speed_mts = 11104.0,
367 			},
368 			{
369 				.state = 2,
370 				.dcfclk_mhz = 875.0,
371 				.fabricclk_mhz = 875.0,
372 				.dispclk_mhz = 734.0,
373 				.dppclk_mhz = 734.0,
374 				.phyclk_mhz = 810.0,
375 				.socclk_mhz = 875.0,
376 				.dscclk_mhz = 245.0,
377 				.dram_speed_mts = 14000.0,
378 			},
379 			{
380 				.state = 3,
381 				.dcfclk_mhz = 1000.0,
382 				.fabricclk_mhz = 1000.0,
383 				.dispclk_mhz = 1100.0,
384 				.dppclk_mhz = 1100.0,
385 				.phyclk_mhz = 810.0,
386 				.socclk_mhz = 1000.0,
387 				.dscclk_mhz = 367.0,
388 				.dram_speed_mts = 16000.0,
389 			},
390 			{
391 				.state = 4,
392 				.dcfclk_mhz = 1200.0,
393 				.fabricclk_mhz = 1200.0,
394 				.dispclk_mhz = 1284.0,
395 				.dppclk_mhz = 1284.0,
396 				.phyclk_mhz = 810.0,
397 				.socclk_mhz = 1200.0,
398 				.dscclk_mhz = 428.0,
399 				.dram_speed_mts = 16000.0,
400 			},
401 			/*Extra state, no dispclk ramping*/
402 			{
403 				.state = 5,
404 				.dcfclk_mhz = 1200.0,
405 				.fabricclk_mhz = 1200.0,
406 				.dispclk_mhz = 1284.0,
407 				.dppclk_mhz = 1284.0,
408 				.phyclk_mhz = 810.0,
409 				.socclk_mhz = 1200.0,
410 				.dscclk_mhz = 428.0,
411 				.dram_speed_mts = 16000.0,
412 			},
413 		},
414 	.num_states = 5,
415 	.sr_exit_time_us = 11.6,
416 	.sr_enter_plus_exit_time_us = 13.9,
417 	.urgent_latency_us = 4.0,
418 	.urgent_latency_pixel_data_only_us = 4.0,
419 	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
420 	.urgent_latency_vm_data_only_us = 4.0,
421 	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
422 	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
423 	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
424 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
425 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
426 	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
427 	.max_avg_sdp_bw_use_normal_percent = 40.0,
428 	.max_avg_dram_bw_use_normal_percent = 40.0,
429 	.writeback_latency_us = 12.0,
430 	.ideal_dram_bw_after_urgent_percent = 40.0,
431 	.max_request_size_bytes = 256,
432 	.dram_channel_width_bytes = 2,
433 	.fabric_datapath_to_dcn_data_return_bytes = 64,
434 	.dcn_downspread_percent = 0.5,
435 	.downspread_percent = 0.38,
436 	.dram_page_open_time_ns = 50.0,
437 	.dram_rw_turnaround_time_ns = 17.5,
438 	.dram_return_buffer_per_channel_bytes = 8192,
439 	.round_trip_ping_latency_dcfclk_cycles = 131,
440 	.urgent_out_of_order_return_per_channel_bytes = 256,
441 	.channel_interleave_bytes = 256,
442 	.num_banks = 8,
443 	.num_chans = 8,
444 	.vmm_page_size_bytes = 4096,
445 	.dram_clock_change_latency_us = 404.0,
446 	.dummy_pstate_latency_us = 5.0,
447 	.writeback_dram_clock_change_latency_us = 23.0,
448 	.return_bus_width_bytes = 64,
449 	.dispclk_dppclk_vco_speed_mhz = 3850,
450 	.xfc_bus_transport_time_us = 20,
451 	.xfc_xbuf_latency_tolerance_us = 4,
452 	.use_urgent_burst_bw = 0
453 };
454 
455 static struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
456 
457 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
458 	#define mmDP0_DP_DPHY_INTERNAL_CTRL		0x210f
459 	#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
460 	#define mmDP1_DP_DPHY_INTERNAL_CTRL		0x220f
461 	#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
462 	#define mmDP2_DP_DPHY_INTERNAL_CTRL		0x230f
463 	#define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
464 	#define mmDP3_DP_DPHY_INTERNAL_CTRL		0x240f
465 	#define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
466 	#define mmDP4_DP_DPHY_INTERNAL_CTRL		0x250f
467 	#define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
468 	#define mmDP5_DP_DPHY_INTERNAL_CTRL		0x260f
469 	#define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
470 	#define mmDP6_DP_DPHY_INTERNAL_CTRL		0x270f
471 	#define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
472 #endif
473 
474 
475 enum dcn20_clk_src_array_id {
476 	DCN20_CLK_SRC_PLL0,
477 	DCN20_CLK_SRC_PLL1,
478 	DCN20_CLK_SRC_PLL2,
479 	DCN20_CLK_SRC_PLL3,
480 	DCN20_CLK_SRC_PLL4,
481 	DCN20_CLK_SRC_PLL5,
482 	DCN20_CLK_SRC_TOTAL
483 };
484 
485 /* begin *********************
486  * macros to expend register list macro defined in HW object header file */
487 
488 /* DCN */
489 /* TODO awful hack. fixup dcn20_dwb.h */
490 #undef BASE_INNER
491 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
492 
493 #define BASE(seg) BASE_INNER(seg)
494 
495 #define SR(reg_name)\
496 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
497 					mm ## reg_name
498 
499 #define SRI(reg_name, block, id)\
500 	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
501 					mm ## block ## id ## _ ## reg_name
502 
503 #define SRIR(var_name, reg_name, block, id)\
504 	.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
505 					mm ## block ## id ## _ ## reg_name
506 
507 #define SRII(reg_name, block, id)\
508 	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
509 					mm ## block ## id ## _ ## reg_name
510 
511 #define DCCG_SRII(reg_name, block, id)\
512 	.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
513 					mm ## block ## id ## _ ## reg_name
514 
515 #define VUPDATE_SRII(reg_name, block, id)\
516 	.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
517 					mm ## reg_name ## _ ## block ## id
518 
519 /* NBIO */
520 #define NBIO_BASE_INNER(seg) \
521 	NBIO_BASE__INST0_SEG ## seg
522 
523 #define NBIO_BASE(seg) \
524 	NBIO_BASE_INNER(seg)
525 
526 #define NBIO_SR(reg_name)\
527 		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
528 					mm ## reg_name
529 
530 /* MMHUB */
531 #define MMHUB_BASE_INNER(seg) \
532 	MMHUB_BASE__INST0_SEG ## seg
533 
534 #define MMHUB_BASE(seg) \
535 	MMHUB_BASE_INNER(seg)
536 
537 #define MMHUB_SR(reg_name)\
538 		.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
539 					mmMM ## reg_name
540 
541 static const struct bios_registers bios_regs = {
542 		NBIO_SR(BIOS_SCRATCH_3),
543 		NBIO_SR(BIOS_SCRATCH_6)
544 };
545 
546 #define clk_src_regs(index, pllid)\
547 [index] = {\
548 	CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
549 }
550 
551 static const struct dce110_clk_src_regs clk_src_regs[] = {
552 	clk_src_regs(0, A),
553 	clk_src_regs(1, B),
554 	clk_src_regs(2, C),
555 	clk_src_regs(3, D),
556 	clk_src_regs(4, E),
557 	clk_src_regs(5, F)
558 };
559 
560 static const struct dce110_clk_src_shift cs_shift = {
561 		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
562 };
563 
564 static const struct dce110_clk_src_mask cs_mask = {
565 		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
566 };
567 
568 static const struct dce_dmcu_registers dmcu_regs = {
569 		DMCU_DCN10_REG_LIST()
570 };
571 
572 static const struct dce_dmcu_shift dmcu_shift = {
573 		DMCU_MASK_SH_LIST_DCN10(__SHIFT)
574 };
575 
576 static const struct dce_dmcu_mask dmcu_mask = {
577 		DMCU_MASK_SH_LIST_DCN10(_MASK)
578 };
579 
580 static const struct dce_abm_registers abm_regs = {
581 		ABM_DCN20_REG_LIST()
582 };
583 
584 static const struct dce_abm_shift abm_shift = {
585 		ABM_MASK_SH_LIST_DCN20(__SHIFT)
586 };
587 
588 static const struct dce_abm_mask abm_mask = {
589 		ABM_MASK_SH_LIST_DCN20(_MASK)
590 };
591 
592 #define audio_regs(id)\
593 [id] = {\
594 		AUD_COMMON_REG_LIST(id)\
595 }
596 
597 static const struct dce_audio_registers audio_regs[] = {
598 	audio_regs(0),
599 	audio_regs(1),
600 	audio_regs(2),
601 	audio_regs(3),
602 	audio_regs(4),
603 	audio_regs(5),
604 	audio_regs(6),
605 };
606 
607 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
608 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
609 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
610 		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
611 
612 static const struct dce_audio_shift audio_shift = {
613 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
614 };
615 
616 static const struct dce_audio_mask audio_mask = {
617 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
618 };
619 
620 #define stream_enc_regs(id)\
621 [id] = {\
622 	SE_DCN2_REG_LIST(id)\
623 }
624 
625 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
626 	stream_enc_regs(0),
627 	stream_enc_regs(1),
628 	stream_enc_regs(2),
629 	stream_enc_regs(3),
630 	stream_enc_regs(4),
631 	stream_enc_regs(5),
632 };
633 
634 static const struct dcn10_stream_encoder_shift se_shift = {
635 		SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
636 };
637 
638 static const struct dcn10_stream_encoder_mask se_mask = {
639 		SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
640 };
641 
642 
643 #define aux_regs(id)\
644 [id] = {\
645 	DCN2_AUX_REG_LIST(id)\
646 }
647 
648 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
649 		aux_regs(0),
650 		aux_regs(1),
651 		aux_regs(2),
652 		aux_regs(3),
653 		aux_regs(4),
654 		aux_regs(5)
655 };
656 
657 #define hpd_regs(id)\
658 [id] = {\
659 	HPD_REG_LIST(id)\
660 }
661 
662 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
663 		hpd_regs(0),
664 		hpd_regs(1),
665 		hpd_regs(2),
666 		hpd_regs(3),
667 		hpd_regs(4),
668 		hpd_regs(5)
669 };
670 
671 #define link_regs(id, phyid)\
672 [id] = {\
673 	LE_DCN10_REG_LIST(id), \
674 	UNIPHY_DCN2_REG_LIST(phyid), \
675 	DPCS_DCN2_REG_LIST(id), \
676 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
677 }
678 
679 static const struct dcn10_link_enc_registers link_enc_regs[] = {
680 	link_regs(0, A),
681 	link_regs(1, B),
682 	link_regs(2, C),
683 	link_regs(3, D),
684 	link_regs(4, E),
685 	link_regs(5, F)
686 };
687 
688 static const struct dcn10_link_enc_shift le_shift = {
689 	LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
690 	DPCS_DCN2_MASK_SH_LIST(__SHIFT)
691 };
692 
693 static const struct dcn10_link_enc_mask le_mask = {
694 	LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
695 	DPCS_DCN2_MASK_SH_LIST(_MASK)
696 };
697 
698 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
699 	{ DCN_PANEL_CNTL_REG_LIST() }
700 };
701 
702 static const struct dce_panel_cntl_shift panel_cntl_shift = {
703 	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
704 };
705 
706 static const struct dce_panel_cntl_mask panel_cntl_mask = {
707 	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
708 };
709 
710 #define ipp_regs(id)\
711 [id] = {\
712 	IPP_REG_LIST_DCN20(id),\
713 }
714 
715 static const struct dcn10_ipp_registers ipp_regs[] = {
716 	ipp_regs(0),
717 	ipp_regs(1),
718 	ipp_regs(2),
719 	ipp_regs(3),
720 	ipp_regs(4),
721 	ipp_regs(5),
722 };
723 
724 static const struct dcn10_ipp_shift ipp_shift = {
725 		IPP_MASK_SH_LIST_DCN20(__SHIFT)
726 };
727 
728 static const struct dcn10_ipp_mask ipp_mask = {
729 		IPP_MASK_SH_LIST_DCN20(_MASK),
730 };
731 
732 #define opp_regs(id)\
733 [id] = {\
734 	OPP_REG_LIST_DCN20(id),\
735 }
736 
737 static const struct dcn20_opp_registers opp_regs[] = {
738 	opp_regs(0),
739 	opp_regs(1),
740 	opp_regs(2),
741 	opp_regs(3),
742 	opp_regs(4),
743 	opp_regs(5),
744 };
745 
746 static const struct dcn20_opp_shift opp_shift = {
747 		OPP_MASK_SH_LIST_DCN20(__SHIFT)
748 };
749 
750 static const struct dcn20_opp_mask opp_mask = {
751 		OPP_MASK_SH_LIST_DCN20(_MASK)
752 };
753 
754 #define aux_engine_regs(id)\
755 [id] = {\
756 	AUX_COMMON_REG_LIST0(id), \
757 	.AUXN_IMPCAL = 0, \
758 	.AUXP_IMPCAL = 0, \
759 	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
760 }
761 
762 static const struct dce110_aux_registers aux_engine_regs[] = {
763 		aux_engine_regs(0),
764 		aux_engine_regs(1),
765 		aux_engine_regs(2),
766 		aux_engine_regs(3),
767 		aux_engine_regs(4),
768 		aux_engine_regs(5)
769 };
770 
771 #define tf_regs(id)\
772 [id] = {\
773 	TF_REG_LIST_DCN20(id),\
774 	TF_REG_LIST_DCN20_COMMON_APPEND(id),\
775 }
776 
777 static const struct dcn2_dpp_registers tf_regs[] = {
778 	tf_regs(0),
779 	tf_regs(1),
780 	tf_regs(2),
781 	tf_regs(3),
782 	tf_regs(4),
783 	tf_regs(5),
784 };
785 
786 static const struct dcn2_dpp_shift tf_shift = {
787 		TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
788 		TF_DEBUG_REG_LIST_SH_DCN20
789 };
790 
791 static const struct dcn2_dpp_mask tf_mask = {
792 		TF_REG_LIST_SH_MASK_DCN20(_MASK),
793 		TF_DEBUG_REG_LIST_MASK_DCN20
794 };
795 
796 #define dwbc_regs_dcn2(id)\
797 [id] = {\
798 	DWBC_COMMON_REG_LIST_DCN2_0(id),\
799 		}
800 
801 static const struct dcn20_dwbc_registers dwbc20_regs[] = {
802 	dwbc_regs_dcn2(0),
803 };
804 
805 static const struct dcn20_dwbc_shift dwbc20_shift = {
806 	DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
807 };
808 
809 static const struct dcn20_dwbc_mask dwbc20_mask = {
810 	DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
811 };
812 
813 #define mcif_wb_regs_dcn2(id)\
814 [id] = {\
815 	MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
816 		}
817 
818 static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
819 	mcif_wb_regs_dcn2(0),
820 };
821 
822 static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
823 	MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
824 };
825 
826 static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
827 	MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
828 };
829 
830 static const struct dcn20_mpc_registers mpc_regs = {
831 		MPC_REG_LIST_DCN2_0(0),
832 		MPC_REG_LIST_DCN2_0(1),
833 		MPC_REG_LIST_DCN2_0(2),
834 		MPC_REG_LIST_DCN2_0(3),
835 		MPC_REG_LIST_DCN2_0(4),
836 		MPC_REG_LIST_DCN2_0(5),
837 		MPC_OUT_MUX_REG_LIST_DCN2_0(0),
838 		MPC_OUT_MUX_REG_LIST_DCN2_0(1),
839 		MPC_OUT_MUX_REG_LIST_DCN2_0(2),
840 		MPC_OUT_MUX_REG_LIST_DCN2_0(3),
841 		MPC_OUT_MUX_REG_LIST_DCN2_0(4),
842 		MPC_OUT_MUX_REG_LIST_DCN2_0(5),
843 		MPC_DBG_REG_LIST_DCN2_0()
844 };
845 
846 static const struct dcn20_mpc_shift mpc_shift = {
847 	MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
848 	MPC_DEBUG_REG_LIST_SH_DCN20
849 };
850 
851 static const struct dcn20_mpc_mask mpc_mask = {
852 	MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
853 	MPC_DEBUG_REG_LIST_MASK_DCN20
854 };
855 
856 #define tg_regs(id)\
857 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
858 
859 
860 static const struct dcn_optc_registers tg_regs[] = {
861 	tg_regs(0),
862 	tg_regs(1),
863 	tg_regs(2),
864 	tg_regs(3),
865 	tg_regs(4),
866 	tg_regs(5)
867 };
868 
869 static const struct dcn_optc_shift tg_shift = {
870 	TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
871 };
872 
873 static const struct dcn_optc_mask tg_mask = {
874 	TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
875 };
876 
877 #define hubp_regs(id)\
878 [id] = {\
879 	HUBP_REG_LIST_DCN20(id)\
880 }
881 
882 static const struct dcn_hubp2_registers hubp_regs[] = {
883 		hubp_regs(0),
884 		hubp_regs(1),
885 		hubp_regs(2),
886 		hubp_regs(3),
887 		hubp_regs(4),
888 		hubp_regs(5)
889 };
890 
891 static const struct dcn_hubp2_shift hubp_shift = {
892 		HUBP_MASK_SH_LIST_DCN20(__SHIFT)
893 };
894 
895 static const struct dcn_hubp2_mask hubp_mask = {
896 		HUBP_MASK_SH_LIST_DCN20(_MASK)
897 };
898 
899 static const struct dcn_hubbub_registers hubbub_reg = {
900 		HUBBUB_REG_LIST_DCN20(0)
901 };
902 
903 static const struct dcn_hubbub_shift hubbub_shift = {
904 		HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
905 };
906 
907 static const struct dcn_hubbub_mask hubbub_mask = {
908 		HUBBUB_MASK_SH_LIST_DCN20(_MASK)
909 };
910 
911 #define vmid_regs(id)\
912 [id] = {\
913 		DCN20_VMID_REG_LIST(id)\
914 }
915 
916 static const struct dcn_vmid_registers vmid_regs[] = {
917 	vmid_regs(0),
918 	vmid_regs(1),
919 	vmid_regs(2),
920 	vmid_regs(3),
921 	vmid_regs(4),
922 	vmid_regs(5),
923 	vmid_regs(6),
924 	vmid_regs(7),
925 	vmid_regs(8),
926 	vmid_regs(9),
927 	vmid_regs(10),
928 	vmid_regs(11),
929 	vmid_regs(12),
930 	vmid_regs(13),
931 	vmid_regs(14),
932 	vmid_regs(15)
933 };
934 
935 static const struct dcn20_vmid_shift vmid_shifts = {
936 		DCN20_VMID_MASK_SH_LIST(__SHIFT)
937 };
938 
939 static const struct dcn20_vmid_mask vmid_masks = {
940 		DCN20_VMID_MASK_SH_LIST(_MASK)
941 };
942 
943 static const struct dce110_aux_registers_shift aux_shift = {
944 		DCN_AUX_MASK_SH_LIST(__SHIFT)
945 };
946 
947 static const struct dce110_aux_registers_mask aux_mask = {
948 		DCN_AUX_MASK_SH_LIST(_MASK)
949 };
950 
951 static int map_transmitter_id_to_phy_instance(
952 	enum transmitter transmitter)
953 {
954 	switch (transmitter) {
955 	case TRANSMITTER_UNIPHY_A:
956 		return 0;
957 	break;
958 	case TRANSMITTER_UNIPHY_B:
959 		return 1;
960 	break;
961 	case TRANSMITTER_UNIPHY_C:
962 		return 2;
963 	break;
964 	case TRANSMITTER_UNIPHY_D:
965 		return 3;
966 	break;
967 	case TRANSMITTER_UNIPHY_E:
968 		return 4;
969 	break;
970 	case TRANSMITTER_UNIPHY_F:
971 		return 5;
972 	break;
973 	default:
974 		ASSERT(0);
975 		return 0;
976 	}
977 }
978 
979 #define dsc_regsDCN20(id)\
980 [id] = {\
981 	DSC_REG_LIST_DCN20(id)\
982 }
983 
984 static const struct dcn20_dsc_registers dsc_regs[] = {
985 	dsc_regsDCN20(0),
986 	dsc_regsDCN20(1),
987 	dsc_regsDCN20(2),
988 	dsc_regsDCN20(3),
989 	dsc_regsDCN20(4),
990 	dsc_regsDCN20(5)
991 };
992 
993 static const struct dcn20_dsc_shift dsc_shift = {
994 	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
995 };
996 
997 static const struct dcn20_dsc_mask dsc_mask = {
998 	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
999 };
1000 
1001 static const struct dccg_registers dccg_regs = {
1002 		DCCG_REG_LIST_DCN2()
1003 };
1004 
1005 static const struct dccg_shift dccg_shift = {
1006 		DCCG_MASK_SH_LIST_DCN2(__SHIFT)
1007 };
1008 
1009 static const struct dccg_mask dccg_mask = {
1010 		DCCG_MASK_SH_LIST_DCN2(_MASK)
1011 };
1012 
1013 static const struct resource_caps res_cap_nv10 = {
1014 		.num_timing_generator = 6,
1015 		.num_opp = 6,
1016 		.num_video_plane = 6,
1017 		.num_audio = 7,
1018 		.num_stream_encoder = 6,
1019 		.num_pll = 6,
1020 		.num_dwb = 1,
1021 		.num_ddc = 6,
1022 		.num_vmid = 16,
1023 		.num_dsc = 6,
1024 };
1025 
1026 static const struct dc_plane_cap plane_cap = {
1027 	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
1028 	.blends_with_above = true,
1029 	.blends_with_below = true,
1030 	.per_pixel_alpha = true,
1031 
1032 	.pixel_format_support = {
1033 			.argb8888 = true,
1034 			.nv12 = true,
1035 			.fp16 = true,
1036 			.p010 = true
1037 	},
1038 
1039 	.max_upscale_factor = {
1040 			.argb8888 = 16000,
1041 			.nv12 = 16000,
1042 			.fp16 = 1
1043 	},
1044 
1045 	.max_downscale_factor = {
1046 			.argb8888 = 250,
1047 			.nv12 = 250,
1048 			.fp16 = 1
1049 	},
1050 	16,
1051 	16
1052 };
1053 static const struct resource_caps res_cap_nv14 = {
1054 		.num_timing_generator = 5,
1055 		.num_opp = 5,
1056 		.num_video_plane = 5,
1057 		.num_audio = 6,
1058 		.num_stream_encoder = 5,
1059 		.num_pll = 5,
1060 		.num_dwb = 1,
1061 		.num_ddc = 5,
1062 		.num_vmid = 16,
1063 		.num_dsc = 5,
1064 };
1065 
1066 static const struct dc_debug_options debug_defaults_drv = {
1067 		.disable_dmcu = false,
1068 		.force_abm_enable = false,
1069 		.timing_trace = false,
1070 		.clock_trace = true,
1071 		.disable_pplib_clock_request = true,
1072 		.pipe_split_policy = MPC_SPLIT_DYNAMIC,
1073 		.force_single_disp_pipe_split = false,
1074 		.disable_dcc = DCC_ENABLE,
1075 		.vsr_support = true,
1076 		.performance_trace = false,
1077 		.max_downscale_src_width = 5120,/*upto 5K*/
1078 		.disable_pplib_wm_range = false,
1079 		.scl_reset_length10 = true,
1080 		.sanity_checks = false,
1081 		.underflow_assert_delay_us = 0xFFFFFFFF,
1082 };
1083 
1084 static const struct dc_debug_options debug_defaults_diags = {
1085 		.disable_dmcu = false,
1086 		.force_abm_enable = false,
1087 		.timing_trace = true,
1088 		.clock_trace = true,
1089 		.disable_dpp_power_gate = true,
1090 		.disable_hubp_power_gate = true,
1091 		.disable_clock_gate = true,
1092 		.disable_pplib_clock_request = true,
1093 		.disable_pplib_wm_range = true,
1094 		.disable_stutter = true,
1095 		.scl_reset_length10 = true,
1096 		.underflow_assert_delay_us = 0xFFFFFFFF,
1097 		.enable_tri_buf = true,
1098 };
1099 
1100 void dcn20_dpp_destroy(struct dpp **dpp)
1101 {
1102 	kfree(TO_DCN20_DPP(*dpp));
1103 	*dpp = NULL;
1104 }
1105 
1106 struct dpp *dcn20_dpp_create(
1107 	struct dc_context *ctx,
1108 	uint32_t inst)
1109 {
1110 	struct dcn20_dpp *dpp =
1111 		kzalloc(sizeof(struct dcn20_dpp), GFP_ATOMIC);
1112 
1113 	if (!dpp)
1114 		return NULL;
1115 
1116 	if (dpp2_construct(dpp, ctx, inst,
1117 			&tf_regs[inst], &tf_shift, &tf_mask))
1118 		return &dpp->base;
1119 
1120 	BREAK_TO_DEBUGGER();
1121 	kfree(dpp);
1122 	return NULL;
1123 }
1124 
1125 struct input_pixel_processor *dcn20_ipp_create(
1126 	struct dc_context *ctx, uint32_t inst)
1127 {
1128 	struct dcn10_ipp *ipp =
1129 		kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC);
1130 
1131 	if (!ipp) {
1132 		BREAK_TO_DEBUGGER();
1133 		return NULL;
1134 	}
1135 
1136 	dcn20_ipp_construct(ipp, ctx, inst,
1137 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
1138 	return &ipp->base;
1139 }
1140 
1141 
1142 struct output_pixel_processor *dcn20_opp_create(
1143 	struct dc_context *ctx, uint32_t inst)
1144 {
1145 	struct dcn20_opp *opp =
1146 		kzalloc(sizeof(struct dcn20_opp), GFP_ATOMIC);
1147 
1148 	if (!opp) {
1149 		BREAK_TO_DEBUGGER();
1150 		return NULL;
1151 	}
1152 
1153 	dcn20_opp_construct(opp, ctx, inst,
1154 			&opp_regs[inst], &opp_shift, &opp_mask);
1155 	return &opp->base;
1156 }
1157 
1158 struct dce_aux *dcn20_aux_engine_create(
1159 	struct dc_context *ctx,
1160 	uint32_t inst)
1161 {
1162 	struct aux_engine_dce110 *aux_engine =
1163 		kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC);
1164 
1165 	if (!aux_engine)
1166 		return NULL;
1167 
1168 	dce110_aux_engine_construct(aux_engine, ctx, inst,
1169 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1170 				    &aux_engine_regs[inst],
1171 					&aux_mask,
1172 					&aux_shift,
1173 					ctx->dc->caps.extended_aux_timeout_support);
1174 
1175 	return &aux_engine->base;
1176 }
1177 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
1178 
1179 static const struct dce_i2c_registers i2c_hw_regs[] = {
1180 		i2c_inst_regs(1),
1181 		i2c_inst_regs(2),
1182 		i2c_inst_regs(3),
1183 		i2c_inst_regs(4),
1184 		i2c_inst_regs(5),
1185 		i2c_inst_regs(6),
1186 };
1187 
1188 static const struct dce_i2c_shift i2c_shifts = {
1189 		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
1190 };
1191 
1192 static const struct dce_i2c_mask i2c_masks = {
1193 		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
1194 };
1195 
1196 struct dce_i2c_hw *dcn20_i2c_hw_create(
1197 	struct dc_context *ctx,
1198 	uint32_t inst)
1199 {
1200 	struct dce_i2c_hw *dce_i2c_hw =
1201 		kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC);
1202 
1203 	if (!dce_i2c_hw)
1204 		return NULL;
1205 
1206 	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1207 				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1208 
1209 	return dce_i2c_hw;
1210 }
1211 struct mpc *dcn20_mpc_create(struct dc_context *ctx)
1212 {
1213 	struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1214 					  GFP_ATOMIC);
1215 
1216 	if (!mpc20)
1217 		return NULL;
1218 
1219 	dcn20_mpc_construct(mpc20, ctx,
1220 			&mpc_regs,
1221 			&mpc_shift,
1222 			&mpc_mask,
1223 			6);
1224 
1225 	return &mpc20->base;
1226 }
1227 
1228 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
1229 {
1230 	int i;
1231 	struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1232 					  GFP_ATOMIC);
1233 
1234 	if (!hubbub)
1235 		return NULL;
1236 
1237 	hubbub2_construct(hubbub, ctx,
1238 			&hubbub_reg,
1239 			&hubbub_shift,
1240 			&hubbub_mask);
1241 
1242 	for (i = 0; i < res_cap_nv10.num_vmid; i++) {
1243 		struct dcn20_vmid *vmid = &hubbub->vmid[i];
1244 
1245 		vmid->ctx = ctx;
1246 
1247 		vmid->regs = &vmid_regs[i];
1248 		vmid->shifts = &vmid_shifts;
1249 		vmid->masks = &vmid_masks;
1250 	}
1251 
1252 	return &hubbub->base;
1253 }
1254 
1255 struct timing_generator *dcn20_timing_generator_create(
1256 		struct dc_context *ctx,
1257 		uint32_t instance)
1258 {
1259 	struct optc *tgn10 =
1260 		kzalloc(sizeof(struct optc), GFP_ATOMIC);
1261 
1262 	if (!tgn10)
1263 		return NULL;
1264 
1265 	tgn10->base.inst = instance;
1266 	tgn10->base.ctx = ctx;
1267 
1268 	tgn10->tg_regs = &tg_regs[instance];
1269 	tgn10->tg_shift = &tg_shift;
1270 	tgn10->tg_mask = &tg_mask;
1271 
1272 	dcn20_timing_generator_init(tgn10);
1273 
1274 	return &tgn10->base;
1275 }
1276 
1277 static const struct encoder_feature_support link_enc_feature = {
1278 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
1279 		.max_hdmi_pixel_clock = 600000,
1280 		.hdmi_ycbcr420_supported = true,
1281 		.dp_ycbcr420_supported = true,
1282 		.fec_supported = true,
1283 		.flags.bits.IS_HBR2_CAPABLE = true,
1284 		.flags.bits.IS_HBR3_CAPABLE = true,
1285 		.flags.bits.IS_TPS3_CAPABLE = true,
1286 		.flags.bits.IS_TPS4_CAPABLE = true
1287 };
1288 
1289 struct link_encoder *dcn20_link_encoder_create(
1290 	const struct encoder_init_data *enc_init_data)
1291 {
1292 	struct dcn20_link_encoder *enc20 =
1293 		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1294 	int link_regs_id;
1295 
1296 	if (!enc20)
1297 		return NULL;
1298 
1299 	link_regs_id =
1300 		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1301 
1302 	dcn20_link_encoder_construct(enc20,
1303 				      enc_init_data,
1304 				      &link_enc_feature,
1305 				      &link_enc_regs[link_regs_id],
1306 				      &link_enc_aux_regs[enc_init_data->channel - 1],
1307 				      &link_enc_hpd_regs[enc_init_data->hpd_source],
1308 				      &le_shift,
1309 				      &le_mask);
1310 
1311 	return &enc20->enc10.base;
1312 }
1313 
1314 static struct panel_cntl *dcn20_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1315 {
1316 	struct dce_panel_cntl *panel_cntl =
1317 		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1318 
1319 	if (!panel_cntl)
1320 		return NULL;
1321 
1322 	dce_panel_cntl_construct(panel_cntl,
1323 			init_data,
1324 			&panel_cntl_regs[init_data->inst],
1325 			&panel_cntl_shift,
1326 			&panel_cntl_mask);
1327 
1328 	return &panel_cntl->base;
1329 }
1330 
1331 static struct clock_source *dcn20_clock_source_create(
1332 	struct dc_context *ctx,
1333 	struct dc_bios *bios,
1334 	enum clock_source_id id,
1335 	const struct dce110_clk_src_regs *regs,
1336 	bool dp_clk_src)
1337 {
1338 	struct dce110_clk_src *clk_src =
1339 		kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC);
1340 
1341 	if (!clk_src)
1342 		return NULL;
1343 
1344 	if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1345 			regs, &cs_shift, &cs_mask)) {
1346 		clk_src->base.dp_clk_src = dp_clk_src;
1347 		return &clk_src->base;
1348 	}
1349 
1350 	kfree(clk_src);
1351 	BREAK_TO_DEBUGGER();
1352 	return NULL;
1353 }
1354 
1355 static void read_dce_straps(
1356 	struct dc_context *ctx,
1357 	struct resource_straps *straps)
1358 {
1359 	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1360 		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1361 }
1362 
1363 static struct audio *dcn20_create_audio(
1364 		struct dc_context *ctx, unsigned int inst)
1365 {
1366 	return dce_audio_create(ctx, inst,
1367 			&audio_regs[inst], &audio_shift, &audio_mask);
1368 }
1369 
1370 struct stream_encoder *dcn20_stream_encoder_create(
1371 	enum engine_id eng_id,
1372 	struct dc_context *ctx)
1373 {
1374 	struct dcn10_stream_encoder *enc1 =
1375 		kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1376 
1377 	if (!enc1)
1378 		return NULL;
1379 
1380 	if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
1381 		if (eng_id >= ENGINE_ID_DIGD)
1382 			eng_id++;
1383 	}
1384 
1385 	dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1386 					&stream_enc_regs[eng_id],
1387 					&se_shift, &se_mask);
1388 
1389 	return &enc1->base;
1390 }
1391 
1392 static const struct dce_hwseq_registers hwseq_reg = {
1393 		HWSEQ_DCN2_REG_LIST()
1394 };
1395 
1396 static const struct dce_hwseq_shift hwseq_shift = {
1397 		HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
1398 };
1399 
1400 static const struct dce_hwseq_mask hwseq_mask = {
1401 		HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1402 };
1403 
1404 struct dce_hwseq *dcn20_hwseq_create(
1405 	struct dc_context *ctx)
1406 {
1407 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1408 
1409 	if (hws) {
1410 		hws->ctx = ctx;
1411 		hws->regs = &hwseq_reg;
1412 		hws->shifts = &hwseq_shift;
1413 		hws->masks = &hwseq_mask;
1414 	}
1415 	return hws;
1416 }
1417 
1418 static const struct resource_create_funcs res_create_funcs = {
1419 	.read_dce_straps = read_dce_straps,
1420 	.create_audio = dcn20_create_audio,
1421 	.create_stream_encoder = dcn20_stream_encoder_create,
1422 	.create_hwseq = dcn20_hwseq_create,
1423 };
1424 
1425 static const struct resource_create_funcs res_create_maximus_funcs = {
1426 	.read_dce_straps = NULL,
1427 	.create_audio = NULL,
1428 	.create_stream_encoder = NULL,
1429 	.create_hwseq = dcn20_hwseq_create,
1430 };
1431 
1432 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1433 
1434 void dcn20_clock_source_destroy(struct clock_source **clk_src)
1435 {
1436 	kfree(TO_DCE110_CLK_SRC(*clk_src));
1437 	*clk_src = NULL;
1438 }
1439 
1440 
1441 struct display_stream_compressor *dcn20_dsc_create(
1442 	struct dc_context *ctx, uint32_t inst)
1443 {
1444 	struct dcn20_dsc *dsc =
1445 		kzalloc(sizeof(struct dcn20_dsc), GFP_ATOMIC);
1446 
1447 	if (!dsc) {
1448 		BREAK_TO_DEBUGGER();
1449 		return NULL;
1450 	}
1451 
1452 	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1453 	return &dsc->base;
1454 }
1455 
1456 void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1457 {
1458 	kfree(container_of(*dsc, struct dcn20_dsc, base));
1459 	*dsc = NULL;
1460 }
1461 
1462 
1463 static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
1464 {
1465 	unsigned int i;
1466 
1467 	for (i = 0; i < pool->base.stream_enc_count; i++) {
1468 		if (pool->base.stream_enc[i] != NULL) {
1469 			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1470 			pool->base.stream_enc[i] = NULL;
1471 		}
1472 	}
1473 
1474 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1475 		if (pool->base.dscs[i] != NULL)
1476 			dcn20_dsc_destroy(&pool->base.dscs[i]);
1477 	}
1478 
1479 	if (pool->base.mpc != NULL) {
1480 		kfree(TO_DCN20_MPC(pool->base.mpc));
1481 		pool->base.mpc = NULL;
1482 	}
1483 	if (pool->base.hubbub != NULL) {
1484 		kfree(pool->base.hubbub);
1485 		pool->base.hubbub = NULL;
1486 	}
1487 	for (i = 0; i < pool->base.pipe_count; i++) {
1488 		if (pool->base.dpps[i] != NULL)
1489 			dcn20_dpp_destroy(&pool->base.dpps[i]);
1490 
1491 		if (pool->base.ipps[i] != NULL)
1492 			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1493 
1494 		if (pool->base.hubps[i] != NULL) {
1495 			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1496 			pool->base.hubps[i] = NULL;
1497 		}
1498 
1499 		if (pool->base.irqs != NULL) {
1500 			dal_irq_service_destroy(&pool->base.irqs);
1501 		}
1502 	}
1503 
1504 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1505 		if (pool->base.engines[i] != NULL)
1506 			dce110_engine_destroy(&pool->base.engines[i]);
1507 		if (pool->base.hw_i2cs[i] != NULL) {
1508 			kfree(pool->base.hw_i2cs[i]);
1509 			pool->base.hw_i2cs[i] = NULL;
1510 		}
1511 		if (pool->base.sw_i2cs[i] != NULL) {
1512 			kfree(pool->base.sw_i2cs[i]);
1513 			pool->base.sw_i2cs[i] = NULL;
1514 		}
1515 	}
1516 
1517 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1518 		if (pool->base.opps[i] != NULL)
1519 			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1520 	}
1521 
1522 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1523 		if (pool->base.timing_generators[i] != NULL)	{
1524 			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1525 			pool->base.timing_generators[i] = NULL;
1526 		}
1527 	}
1528 
1529 	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1530 		if (pool->base.dwbc[i] != NULL) {
1531 			kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1532 			pool->base.dwbc[i] = NULL;
1533 		}
1534 		if (pool->base.mcif_wb[i] != NULL) {
1535 			kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1536 			pool->base.mcif_wb[i] = NULL;
1537 		}
1538 	}
1539 
1540 	for (i = 0; i < pool->base.audio_count; i++) {
1541 		if (pool->base.audios[i])
1542 			dce_aud_destroy(&pool->base.audios[i]);
1543 	}
1544 
1545 	for (i = 0; i < pool->base.clk_src_count; i++) {
1546 		if (pool->base.clock_sources[i] != NULL) {
1547 			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1548 			pool->base.clock_sources[i] = NULL;
1549 		}
1550 	}
1551 
1552 	if (pool->base.dp_clock_source != NULL) {
1553 		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1554 		pool->base.dp_clock_source = NULL;
1555 	}
1556 
1557 
1558 	if (pool->base.abm != NULL)
1559 		dce_abm_destroy(&pool->base.abm);
1560 
1561 	if (pool->base.dmcu != NULL)
1562 		dce_dmcu_destroy(&pool->base.dmcu);
1563 
1564 	if (pool->base.dccg != NULL)
1565 		dcn_dccg_destroy(&pool->base.dccg);
1566 
1567 	if (pool->base.pp_smu != NULL)
1568 		dcn20_pp_smu_destroy(&pool->base.pp_smu);
1569 
1570 	if (pool->base.oem_device != NULL)
1571 		dal_ddc_service_destroy(&pool->base.oem_device);
1572 }
1573 
1574 struct hubp *dcn20_hubp_create(
1575 	struct dc_context *ctx,
1576 	uint32_t inst)
1577 {
1578 	struct dcn20_hubp *hubp2 =
1579 		kzalloc(sizeof(struct dcn20_hubp), GFP_ATOMIC);
1580 
1581 	if (!hubp2)
1582 		return NULL;
1583 
1584 	if (hubp2_construct(hubp2, ctx, inst,
1585 			&hubp_regs[inst], &hubp_shift, &hubp_mask))
1586 		return &hubp2->base;
1587 
1588 	BREAK_TO_DEBUGGER();
1589 	kfree(hubp2);
1590 	return NULL;
1591 }
1592 
1593 static void get_pixel_clock_parameters(
1594 	struct pipe_ctx *pipe_ctx,
1595 	struct pixel_clk_params *pixel_clk_params)
1596 {
1597 	const struct dc_stream_state *stream = pipe_ctx->stream;
1598 	struct pipe_ctx *odm_pipe;
1599 	int opp_cnt = 1;
1600 	struct dc_link *link = stream->link;
1601 	struct link_encoder *link_enc = NULL;
1602 
1603 	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1604 		opp_cnt++;
1605 
1606 	pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1607 
1608 	/* Links supporting dynamically assigned link encoder will be assigned next
1609 	 * available encoder if one not already assigned.
1610 	 */
1611 	if (link->is_dig_mapping_flexible &&
1612 			link->dc->res_pool->funcs->link_encs_assign) {
1613 		link_enc = link_enc_cfg_get_link_enc_used_by_stream(stream->ctx->dc, stream);
1614 		if (link_enc == NULL)
1615 			link_enc = link_enc_cfg_get_next_avail_link_enc(stream->ctx->dc);
1616 	} else
1617 		link_enc = stream->link->link_enc;
1618 	ASSERT(link_enc);
1619 
1620 	if (link_enc)
1621 		pixel_clk_params->encoder_object_id = link_enc->id;
1622 	pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1623 	pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1624 	/* TODO: un-hardcode*/
1625 	/* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */
1626 	pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1627 		LINK_RATE_REF_FREQ_IN_KHZ;
1628 	pixel_clk_params->flags.ENABLE_SS = 0;
1629 	pixel_clk_params->color_depth =
1630 		stream->timing.display_color_depth;
1631 	pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1632 	pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1633 
1634 	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1635 		pixel_clk_params->color_depth = COLOR_DEPTH_888;
1636 
1637 	if (opp_cnt == 4)
1638 		pixel_clk_params->requested_pix_clk_100hz /= 4;
1639 	else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
1640 		pixel_clk_params->requested_pix_clk_100hz /= 2;
1641 
1642 	if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1643 		pixel_clk_params->requested_pix_clk_100hz *= 2;
1644 
1645 }
1646 
1647 static void build_clamping_params(struct dc_stream_state *stream)
1648 {
1649 	stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1650 	stream->clamping.c_depth = stream->timing.display_color_depth;
1651 	stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1652 }
1653 
1654 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1655 {
1656 
1657 	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1658 
1659 	pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1660 		pipe_ctx->clock_source,
1661 		&pipe_ctx->stream_res.pix_clk_params,
1662 		&pipe_ctx->pll_settings);
1663 
1664 	pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1665 
1666 	resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1667 					&pipe_ctx->stream->bit_depth_params);
1668 	build_clamping_params(pipe_ctx->stream);
1669 
1670 	return DC_OK;
1671 }
1672 
1673 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1674 {
1675 	enum dc_status status = DC_OK;
1676 	struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1677 
1678 	if (!pipe_ctx)
1679 		return DC_ERROR_UNEXPECTED;
1680 
1681 
1682 	status = build_pipe_hw_param(pipe_ctx);
1683 
1684 	return status;
1685 }
1686 
1687 
1688 void dcn20_acquire_dsc(const struct dc *dc,
1689 			struct resource_context *res_ctx,
1690 			struct display_stream_compressor **dsc,
1691 			int pipe_idx)
1692 {
1693 	int i;
1694 	const struct resource_pool *pool = dc->res_pool;
1695 	struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc;
1696 
1697 	ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */
1698 	*dsc = NULL;
1699 
1700 	/* Always do 1-to-1 mapping when number of DSCs is same as number of pipes */
1701 	if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
1702 		*dsc = pool->dscs[pipe_idx];
1703 		res_ctx->is_dsc_acquired[pipe_idx] = true;
1704 		return;
1705 	}
1706 
1707 	/* Return old DSC to avoid the need for re-programming */
1708 	if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) {
1709 		*dsc = dsc_old;
1710 		res_ctx->is_dsc_acquired[dsc_old->inst] = true;
1711 		return ;
1712 	}
1713 
1714 	/* Find first free DSC */
1715 	for (i = 0; i < pool->res_cap->num_dsc; i++)
1716 		if (!res_ctx->is_dsc_acquired[i]) {
1717 			*dsc = pool->dscs[i];
1718 			res_ctx->is_dsc_acquired[i] = true;
1719 			break;
1720 		}
1721 }
1722 
1723 void dcn20_release_dsc(struct resource_context *res_ctx,
1724 			const struct resource_pool *pool,
1725 			struct display_stream_compressor **dsc)
1726 {
1727 	int i;
1728 
1729 	for (i = 0; i < pool->res_cap->num_dsc; i++)
1730 		if (pool->dscs[i] == *dsc) {
1731 			res_ctx->is_dsc_acquired[i] = false;
1732 			*dsc = NULL;
1733 			break;
1734 		}
1735 }
1736 
1737 
1738 
1739 enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,
1740 		struct dc_state *dc_ctx,
1741 		struct dc_stream_state *dc_stream)
1742 {
1743 	enum dc_status result = DC_OK;
1744 	int i;
1745 
1746 	/* Get a DSC if required and available */
1747 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1748 		struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
1749 
1750 		if (pipe_ctx->stream != dc_stream)
1751 			continue;
1752 
1753 		if (pipe_ctx->stream_res.dsc)
1754 			continue;
1755 
1756 		dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i);
1757 
1758 		/* The number of DSCs can be less than the number of pipes */
1759 		if (!pipe_ctx->stream_res.dsc) {
1760 			result = DC_NO_DSC_RESOURCE;
1761 		}
1762 
1763 		break;
1764 	}
1765 
1766 	return result;
1767 }
1768 
1769 
1770 static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
1771 		struct dc_state *new_ctx,
1772 		struct dc_stream_state *dc_stream)
1773 {
1774 	struct pipe_ctx *pipe_ctx = NULL;
1775 	int i;
1776 
1777 	for (i = 0; i < MAX_PIPES; i++) {
1778 		if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1779 			pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1780 
1781 			if (pipe_ctx->stream_res.dsc)
1782 				dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
1783 		}
1784 	}
1785 
1786 	if (!pipe_ctx)
1787 		return DC_ERROR_UNEXPECTED;
1788 	else
1789 		return DC_OK;
1790 }
1791 
1792 
1793 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1794 {
1795 	enum dc_status result = DC_ERROR_UNEXPECTED;
1796 
1797 	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1798 
1799 	if (result == DC_OK)
1800 		result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1801 
1802 	/* Get a DSC if required and available */
1803 	if (result == DC_OK && dc_stream->timing.flags.DSC)
1804 		result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
1805 
1806 	if (result == DC_OK)
1807 		result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1808 
1809 	return result;
1810 }
1811 
1812 
1813 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1814 {
1815 	enum dc_status result = DC_OK;
1816 
1817 	result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
1818 
1819 	return result;
1820 }
1821 
1822 
1823 static void swizzle_to_dml_params(
1824 		enum swizzle_mode_values swizzle,
1825 		unsigned int *sw_mode)
1826 {
1827 	switch (swizzle) {
1828 	case DC_SW_LINEAR:
1829 		*sw_mode = dm_sw_linear;
1830 		break;
1831 	case DC_SW_4KB_S:
1832 		*sw_mode = dm_sw_4kb_s;
1833 		break;
1834 	case DC_SW_4KB_S_X:
1835 		*sw_mode = dm_sw_4kb_s_x;
1836 		break;
1837 	case DC_SW_4KB_D:
1838 		*sw_mode = dm_sw_4kb_d;
1839 		break;
1840 	case DC_SW_4KB_D_X:
1841 		*sw_mode = dm_sw_4kb_d_x;
1842 		break;
1843 	case DC_SW_64KB_S:
1844 		*sw_mode = dm_sw_64kb_s;
1845 		break;
1846 	case DC_SW_64KB_S_X:
1847 		*sw_mode = dm_sw_64kb_s_x;
1848 		break;
1849 	case DC_SW_64KB_S_T:
1850 		*sw_mode = dm_sw_64kb_s_t;
1851 		break;
1852 	case DC_SW_64KB_D:
1853 		*sw_mode = dm_sw_64kb_d;
1854 		break;
1855 	case DC_SW_64KB_D_X:
1856 		*sw_mode = dm_sw_64kb_d_x;
1857 		break;
1858 	case DC_SW_64KB_D_T:
1859 		*sw_mode = dm_sw_64kb_d_t;
1860 		break;
1861 	case DC_SW_64KB_R_X:
1862 		*sw_mode = dm_sw_64kb_r_x;
1863 		break;
1864 	case DC_SW_VAR_S:
1865 		*sw_mode = dm_sw_var_s;
1866 		break;
1867 	case DC_SW_VAR_S_X:
1868 		*sw_mode = dm_sw_var_s_x;
1869 		break;
1870 	case DC_SW_VAR_D:
1871 		*sw_mode = dm_sw_var_d;
1872 		break;
1873 	case DC_SW_VAR_D_X:
1874 		*sw_mode = dm_sw_var_d_x;
1875 		break;
1876 	case DC_SW_VAR_R_X:
1877 		*sw_mode = dm_sw_var_r_x;
1878 		break;
1879 	default:
1880 		ASSERT(0); /* Not supported */
1881 		break;
1882 	}
1883 }
1884 
1885 bool dcn20_split_stream_for_odm(
1886 		const struct dc *dc,
1887 		struct resource_context *res_ctx,
1888 		struct pipe_ctx *prev_odm_pipe,
1889 		struct pipe_ctx *next_odm_pipe)
1890 {
1891 	int pipe_idx = next_odm_pipe->pipe_idx;
1892 	const struct resource_pool *pool = dc->res_pool;
1893 
1894 	*next_odm_pipe = *prev_odm_pipe;
1895 
1896 	next_odm_pipe->pipe_idx = pipe_idx;
1897 	next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1898 	next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1899 	next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1900 	next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
1901 	next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
1902 	next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
1903 	next_odm_pipe->stream_res.dsc = NULL;
1904 	if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
1905 		next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
1906 		next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
1907 	}
1908 	if (prev_odm_pipe->top_pipe && prev_odm_pipe->top_pipe->next_odm_pipe) {
1909 		prev_odm_pipe->top_pipe->next_odm_pipe->bottom_pipe = next_odm_pipe;
1910 		next_odm_pipe->top_pipe = prev_odm_pipe->top_pipe->next_odm_pipe;
1911 	}
1912 	if (prev_odm_pipe->bottom_pipe && prev_odm_pipe->bottom_pipe->next_odm_pipe) {
1913 		prev_odm_pipe->bottom_pipe->next_odm_pipe->top_pipe = next_odm_pipe;
1914 		next_odm_pipe->bottom_pipe = prev_odm_pipe->bottom_pipe->next_odm_pipe;
1915 	}
1916 	prev_odm_pipe->next_odm_pipe = next_odm_pipe;
1917 	next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
1918 
1919 	if (prev_odm_pipe->plane_state) {
1920 		struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
1921 		int new_width;
1922 
1923 		/* HACTIVE halved for odm combine */
1924 		sd->h_active /= 2;
1925 		/* Calculate new vp and recout for left pipe */
1926 		/* Need at least 16 pixels width per side */
1927 		if (sd->recout.x + 16 >= sd->h_active)
1928 			return false;
1929 		new_width = sd->h_active - sd->recout.x;
1930 		sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1931 				sd->ratios.horz, sd->recout.width - new_width));
1932 		sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1933 				sd->ratios.horz_c, sd->recout.width - new_width));
1934 		sd->recout.width = new_width;
1935 
1936 		/* Calculate new vp and recout for right pipe */
1937 		sd = &next_odm_pipe->plane_res.scl_data;
1938 		/* HACTIVE halved for odm combine */
1939 		sd->h_active /= 2;
1940 		/* Need at least 16 pixels width per side */
1941 		if (new_width <= 16)
1942 			return false;
1943 		new_width = sd->recout.width + sd->recout.x - sd->h_active;
1944 		sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1945 				sd->ratios.horz, sd->recout.width - new_width));
1946 		sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1947 				sd->ratios.horz_c, sd->recout.width - new_width));
1948 		sd->recout.width = new_width;
1949 		sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1950 				sd->ratios.horz, sd->h_active - sd->recout.x));
1951 		sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1952 				sd->ratios.horz_c, sd->h_active - sd->recout.x));
1953 		sd->recout.x = 0;
1954 	}
1955 	if (!next_odm_pipe->top_pipe)
1956 		next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
1957 	else
1958 		next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp;
1959 	if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) {
1960 		dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
1961 		ASSERT(next_odm_pipe->stream_res.dsc);
1962 		if (next_odm_pipe->stream_res.dsc == NULL)
1963 			return false;
1964 	}
1965 
1966 	return true;
1967 }
1968 
1969 void dcn20_split_stream_for_mpc(
1970 		struct resource_context *res_ctx,
1971 		const struct resource_pool *pool,
1972 		struct pipe_ctx *primary_pipe,
1973 		struct pipe_ctx *secondary_pipe)
1974 {
1975 	int pipe_idx = secondary_pipe->pipe_idx;
1976 	struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
1977 
1978 	*secondary_pipe = *primary_pipe;
1979 	secondary_pipe->bottom_pipe = sec_bot_pipe;
1980 
1981 	secondary_pipe->pipe_idx = pipe_idx;
1982 	secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1983 	secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1984 	secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1985 	secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1986 	secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1987 	secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
1988 	secondary_pipe->stream_res.dsc = NULL;
1989 	if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1990 		ASSERT(!secondary_pipe->bottom_pipe);
1991 		secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1992 		secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1993 	}
1994 	primary_pipe->bottom_pipe = secondary_pipe;
1995 	secondary_pipe->top_pipe = primary_pipe;
1996 
1997 	ASSERT(primary_pipe->plane_state);
1998 }
1999 
2000 int dcn20_populate_dml_pipes_from_context(
2001 		struct dc *dc,
2002 		struct dc_state *context,
2003 		display_e2e_pipe_params_st *pipes,
2004 		bool fast_validate)
2005 {
2006 	int pipe_cnt, i;
2007 	bool synchronized_vblank = true;
2008 	struct resource_context *res_ctx = &context->res_ctx;
2009 
2010 	for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
2011 		if (!res_ctx->pipe_ctx[i].stream)
2012 			continue;
2013 
2014 		if (pipe_cnt < 0) {
2015 			pipe_cnt = i;
2016 			continue;
2017 		}
2018 
2019 		if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream)
2020 			continue;
2021 
2022 		if (dc->debug.disable_timing_sync ||
2023 			(!resource_are_streams_timing_synchronizable(
2024 				res_ctx->pipe_ctx[pipe_cnt].stream,
2025 				res_ctx->pipe_ctx[i].stream) &&
2026 			!resource_are_vblanks_synchronizable(
2027 				res_ctx->pipe_ctx[pipe_cnt].stream,
2028 				res_ctx->pipe_ctx[i].stream))) {
2029 			synchronized_vblank = false;
2030 			break;
2031 		}
2032 	}
2033 
2034 	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2035 		struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
2036 		unsigned int v_total;
2037 		unsigned int front_porch;
2038 		int output_bpc;
2039 		struct audio_check aud_check = {0};
2040 
2041 		if (!res_ctx->pipe_ctx[i].stream)
2042 			continue;
2043 
2044 		v_total = timing->v_total;
2045 		front_porch = timing->v_front_porch;
2046 
2047 		/* todo:
2048 		pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
2049 		pipes[pipe_cnt].pipe.src.dcc = 0;
2050 		pipes[pipe_cnt].pipe.src.vm = 0;*/
2051 
2052 		pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2053 
2054 		pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
2055 		/* todo: rotation?*/
2056 		pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
2057 		if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
2058 			pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
2059 			/* 1/2 vblank */
2060 			pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
2061 				(v_total - timing->v_addressable
2062 					- timing->v_border_top - timing->v_border_bottom) / 2;
2063 			/* 36 bytes dp, 32 hdmi */
2064 			pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
2065 				dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
2066 		}
2067 		pipes[pipe_cnt].pipe.src.dcc = false;
2068 		pipes[pipe_cnt].pipe.src.dcc_rate = 1;
2069 		pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
2070 		pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
2071 		pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
2072 				- timing->h_addressable
2073 				- timing->h_border_left
2074 				- timing->h_border_right;
2075 		pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch;
2076 		pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
2077 				- timing->v_addressable
2078 				- timing->v_border_top
2079 				- timing->v_border_bottom;
2080 		pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
2081 		pipes[pipe_cnt].pipe.dest.vtotal = v_total;
2082 		pipes[pipe_cnt].pipe.dest.hactive =
2083 			timing->h_addressable + timing->h_border_left + timing->h_border_right;
2084 		pipes[pipe_cnt].pipe.dest.vactive =
2085 			timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
2086 		pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
2087 		pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
2088 		if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2089 			pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
2090 		pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
2091 		pipes[pipe_cnt].dout.dp_lanes = 4;
2092 		pipes[pipe_cnt].dout.is_virtual = 0;
2093 		pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
2094 		pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
2095 		switch (get_num_odm_splits(&res_ctx->pipe_ctx[i])) {
2096 		case 1:
2097 			pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;
2098 			break;
2099 		case 3:
2100 			pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1;
2101 			break;
2102 		default:
2103 			pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled;
2104 		}
2105 		pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
2106 		if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
2107 				== res_ctx->pipe_ctx[i].plane_state) {
2108 			struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe;
2109 			int split_idx = 0;
2110 
2111 			while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state
2112 					== res_ctx->pipe_ctx[i].plane_state) {
2113 				first_pipe = first_pipe->top_pipe;
2114 				split_idx++;
2115 			}
2116 			/* Treat 4to1 mpc combine as an mpo of 2 2-to-1 combines */
2117 			if (split_idx == 0)
2118 				pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
2119 			else if (split_idx == 1)
2120 				pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
2121 			else if (split_idx == 2)
2122 				pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
2123 		} else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
2124 			struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
2125 
2126 			while (first_pipe->prev_odm_pipe)
2127 				first_pipe = first_pipe->prev_odm_pipe;
2128 			pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
2129 		}
2130 
2131 		switch (res_ctx->pipe_ctx[i].stream->signal) {
2132 		case SIGNAL_TYPE_DISPLAY_PORT_MST:
2133 		case SIGNAL_TYPE_DISPLAY_PORT:
2134 			pipes[pipe_cnt].dout.output_type = dm_dp;
2135 			break;
2136 		case SIGNAL_TYPE_EDP:
2137 			pipes[pipe_cnt].dout.output_type = dm_edp;
2138 			break;
2139 		case SIGNAL_TYPE_HDMI_TYPE_A:
2140 		case SIGNAL_TYPE_DVI_SINGLE_LINK:
2141 		case SIGNAL_TYPE_DVI_DUAL_LINK:
2142 			pipes[pipe_cnt].dout.output_type = dm_hdmi;
2143 			break;
2144 		default:
2145 			/* In case there is no signal, set dp with 4 lanes to allow max config */
2146 			pipes[pipe_cnt].dout.is_virtual = 1;
2147 			pipes[pipe_cnt].dout.output_type = dm_dp;
2148 			pipes[pipe_cnt].dout.dp_lanes = 4;
2149 		}
2150 
2151 		switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
2152 		case COLOR_DEPTH_666:
2153 			output_bpc = 6;
2154 			break;
2155 		case COLOR_DEPTH_888:
2156 			output_bpc = 8;
2157 			break;
2158 		case COLOR_DEPTH_101010:
2159 			output_bpc = 10;
2160 			break;
2161 		case COLOR_DEPTH_121212:
2162 			output_bpc = 12;
2163 			break;
2164 		case COLOR_DEPTH_141414:
2165 			output_bpc = 14;
2166 			break;
2167 		case COLOR_DEPTH_161616:
2168 			output_bpc = 16;
2169 			break;
2170 		case COLOR_DEPTH_999:
2171 			output_bpc = 9;
2172 			break;
2173 		case COLOR_DEPTH_111111:
2174 			output_bpc = 11;
2175 			break;
2176 		default:
2177 			output_bpc = 8;
2178 			break;
2179 		}
2180 
2181 		switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
2182 		case PIXEL_ENCODING_RGB:
2183 		case PIXEL_ENCODING_YCBCR444:
2184 			pipes[pipe_cnt].dout.output_format = dm_444;
2185 			pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
2186 			break;
2187 		case PIXEL_ENCODING_YCBCR420:
2188 			pipes[pipe_cnt].dout.output_format = dm_420;
2189 			pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2;
2190 			break;
2191 		case PIXEL_ENCODING_YCBCR422:
2192 			if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC &&
2193 			    !res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.ycbcr422_simple)
2194 				pipes[pipe_cnt].dout.output_format = dm_n422;
2195 			else
2196 				pipes[pipe_cnt].dout.output_format = dm_s422;
2197 			pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
2198 			break;
2199 		default:
2200 			pipes[pipe_cnt].dout.output_format = dm_444;
2201 			pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
2202 		}
2203 
2204 		if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
2205 			pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
2206 
2207 		/* todo: default max for now, until there is logic reflecting this in dc*/
2208 		pipes[pipe_cnt].dout.dsc_input_bpc = 12;
2209 		/*fill up the audio sample rate (unit in kHz)*/
2210 		get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check);
2211 		pipes[pipe_cnt].dout.max_audio_sample_rate = aud_check.max_audiosample_rate / 1000;
2212 		/*
2213 		 * For graphic plane, cursor number is 1, nv12 is 0
2214 		 * bw calculations due to cursor on/off
2215 		 */
2216 		if (res_ctx->pipe_ctx[i].plane_state &&
2217 				res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2218 			pipes[pipe_cnt].pipe.src.num_cursors = 0;
2219 		else
2220 			pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors;
2221 
2222 		pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
2223 		pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
2224 
2225 		if (!res_ctx->pipe_ctx[i].plane_state) {
2226 			pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
2227 			pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
2228 			pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_4kb_s;
2229 			pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
2230 			pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
2231 			if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
2232 				pipes[pipe_cnt].pipe.src.viewport_width = 1920;
2233 			pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
2234 			if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
2235 				pipes[pipe_cnt].pipe.src.viewport_height = 1080;
2236 			pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
2237 			pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width;
2238 			pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height;
2239 			pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width;
2240 			pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 255) / 256) * 256;
2241 			pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2242 			pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
2243 			pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
2244 			pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width;  /*when is_hsplit != 1*/
2245 			pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
2246 			pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2247 			pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
2248 			pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
2249 			pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
2250 			pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
2251 			pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
2252 			pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
2253 			pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
2254 
2255 			if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {
2256 				pipes[pipe_cnt].pipe.src.viewport_width /= 2;
2257 				pipes[pipe_cnt].pipe.dest.recout_width /= 2;
2258 			} else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) {
2259 				pipes[pipe_cnt].pipe.src.viewport_width /= 4;
2260 				pipes[pipe_cnt].pipe.dest.recout_width /= 4;
2261 			}
2262 		} else {
2263 			struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
2264 			struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
2265 
2266 			pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
2267 			pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
2268 					|| (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)
2269 					|| pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
2270 
2271 			/* stereo is not split */
2272 			if (pln->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE ||
2273 			    pln->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) {
2274 				pipes[pipe_cnt].pipe.src.is_hsplit = false;
2275 				pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
2276 			}
2277 
2278 			pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
2279 					|| pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
2280 			pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
2281 			pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
2282 			pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
2283 			pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
2284 			pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
2285 			pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
2286 			pipes[pipe_cnt].pipe.src.viewport_width_max = pln->src_rect.width;
2287 			pipes[pipe_cnt].pipe.src.viewport_height_max = pln->src_rect.height;
2288 			pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width;
2289 			pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
2290 			pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width;
2291 			pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height;
2292 			if (pln->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA
2293 					|| pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2294 				pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2295 				pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
2296 				pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2297 				pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
2298 			} else {
2299 				pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2300 				pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2301 			}
2302 			pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
2303 			pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
2304 			pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
2305 			pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
2306 			pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
2307 			if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1)
2308 				pipes[pipe_cnt].pipe.dest.full_recout_width *= 2;
2309 			else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1)
2310 				pipes[pipe_cnt].pipe.dest.full_recout_width *= 4;
2311 			else {
2312 				struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe;
2313 
2314 				while (split_pipe && split_pipe->plane_state == pln) {
2315 					pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
2316 					split_pipe = split_pipe->bottom_pipe;
2317 				}
2318 				split_pipe = res_ctx->pipe_ctx[i].top_pipe;
2319 				while (split_pipe && split_pipe->plane_state == pln) {
2320 					pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
2321 					split_pipe = split_pipe->top_pipe;
2322 				}
2323 			}
2324 
2325 			pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2326 			pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
2327 			pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
2328 			pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
2329 			pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
2330 			pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
2331 					scl->ratios.vert.value != dc_fixpt_one.value
2332 					|| scl->ratios.horz.value != dc_fixpt_one.value
2333 					|| scl->ratios.vert_c.value != dc_fixpt_one.value
2334 					|| scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
2335 					|| dc->debug.always_scale; /*support always scale*/
2336 			pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
2337 			pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
2338 			pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
2339 			pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
2340 
2341 			pipes[pipe_cnt].pipe.src.macro_tile_size =
2342 					swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
2343 			swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
2344 					&pipes[pipe_cnt].pipe.src.sw_mode);
2345 
2346 			switch (pln->format) {
2347 			case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2348 			case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2349 				pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
2350 				break;
2351 			case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2352 			case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2353 				pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
2354 				break;
2355 			case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2356 			case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
2357 			case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2358 			case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2359 				pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
2360 				break;
2361 			case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2362 			case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2363 				pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
2364 				break;
2365 			case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2366 				pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
2367 				break;
2368 			case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
2369 				pipes[pipe_cnt].pipe.src.source_format = dm_rgbe_alpha;
2370 				break;
2371 			default:
2372 				pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2373 				break;
2374 			}
2375 		}
2376 
2377 		pipe_cnt++;
2378 	}
2379 
2380 	/* populate writeback information */
2381 	DC_FP_START();
2382 	dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
2383 	DC_FP_END();
2384 
2385 	return pipe_cnt;
2386 }
2387 
2388 unsigned int dcn20_calc_max_scaled_time(
2389 		unsigned int time_per_pixel,
2390 		enum mmhubbub_wbif_mode mode,
2391 		unsigned int urgent_watermark)
2392 {
2393 	unsigned int time_per_byte = 0;
2394 	unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
2395 	unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
2396 	unsigned int small_free_entry, max_free_entry;
2397 	unsigned int buf_lh_capability;
2398 	unsigned int max_scaled_time;
2399 
2400 	if (mode == PACKED_444) /* packed mode */
2401 		time_per_byte = time_per_pixel/4;
2402 	else if (mode == PLANAR_420_8BPC)
2403 		time_per_byte  = time_per_pixel;
2404 	else if (mode == PLANAR_420_10BPC) /* p010 */
2405 		time_per_byte  = time_per_pixel * 819/1024;
2406 
2407 	if (time_per_byte == 0)
2408 		time_per_byte = 1;
2409 
2410 	small_free_entry  = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
2411 	max_free_entry    = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
2412 	buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
2413 	max_scaled_time   = buf_lh_capability - urgent_watermark;
2414 	return max_scaled_time;
2415 }
2416 
2417 void dcn20_set_mcif_arb_params(
2418 		struct dc *dc,
2419 		struct dc_state *context,
2420 		display_e2e_pipe_params_st *pipes,
2421 		int pipe_cnt)
2422 {
2423 	enum mmhubbub_wbif_mode wbif_mode;
2424 	struct mcif_arb_params *wb_arb_params;
2425 	int i, j, k, dwb_pipe;
2426 
2427 	/* Writeback MCIF_WB arbitration parameters */
2428 	dwb_pipe = 0;
2429 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
2430 
2431 		if (!context->res_ctx.pipe_ctx[i].stream)
2432 			continue;
2433 
2434 		for (j = 0; j < MAX_DWB_PIPES; j++) {
2435 			if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
2436 				continue;
2437 
2438 			//wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
2439 			wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
2440 
2441 			if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
2442 				if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2443 					wbif_mode = PLANAR_420_8BPC;
2444 				else
2445 					wbif_mode = PLANAR_420_10BPC;
2446 			} else
2447 				wbif_mode = PACKED_444;
2448 
2449 			for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
2450 				wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2451 				wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2452 			}
2453 			wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction, ms */
2454 			wb_arb_params->slice_lines = 32;
2455 			wb_arb_params->arbitration_slice = 2;
2456 			wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
2457 				wbif_mode,
2458 				wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
2459 
2460 			dwb_pipe++;
2461 
2462 			if (dwb_pipe >= MAX_DWB_PIPES)
2463 				return;
2464 		}
2465 		if (dwb_pipe >= MAX_DWB_PIPES)
2466 			return;
2467 	}
2468 }
2469 
2470 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
2471 {
2472 	int i;
2473 
2474 	/* Validate DSC config, dsc count validation is already done */
2475 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
2476 		struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
2477 		struct dc_stream_state *stream = pipe_ctx->stream;
2478 		struct dsc_config dsc_cfg;
2479 		struct pipe_ctx *odm_pipe;
2480 		int opp_cnt = 1;
2481 
2482 		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
2483 			opp_cnt++;
2484 
2485 		/* Only need to validate top pipe */
2486 		if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
2487 			continue;
2488 
2489 		dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
2490 				+ stream->timing.h_border_right) / opp_cnt;
2491 		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
2492 				+ stream->timing.v_border_bottom;
2493 		dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
2494 		dsc_cfg.color_depth = stream->timing.display_color_depth;
2495 		dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
2496 		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
2497 		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
2498 
2499 		if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
2500 			return false;
2501 	}
2502 	return true;
2503 }
2504 
2505 struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
2506 		struct resource_context *res_ctx,
2507 		const struct resource_pool *pool,
2508 		const struct pipe_ctx *primary_pipe)
2509 {
2510 	struct pipe_ctx *secondary_pipe = NULL;
2511 
2512 	if (dc && primary_pipe) {
2513 		int j;
2514 		int preferred_pipe_idx = 0;
2515 
2516 		/* first check the prev dc state:
2517 		 * if this primary pipe has a bottom pipe in prev. state
2518 		 * and if the bottom pipe is still available (which it should be),
2519 		 * pick that pipe as secondary
2520 		 * Same logic applies for ODM pipes
2521 		 */
2522 		if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
2523 			preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
2524 			if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2525 				secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2526 				secondary_pipe->pipe_idx = preferred_pipe_idx;
2527 			}
2528 		}
2529 		if (secondary_pipe == NULL &&
2530 				dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
2531 			preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
2532 			if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2533 				secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2534 				secondary_pipe->pipe_idx = preferred_pipe_idx;
2535 			}
2536 		}
2537 
2538 		/*
2539 		 * if this primary pipe does not have a bottom pipe in prev. state
2540 		 * start backward and find a pipe that did not used to be a bottom pipe in
2541 		 * prev. dc state. This way we make sure we keep the same assignment as
2542 		 * last state and will not have to reprogram every pipe
2543 		 */
2544 		if (secondary_pipe == NULL) {
2545 			for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2546 				if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL
2547 						&& dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {
2548 					preferred_pipe_idx = j;
2549 
2550 					if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2551 						secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2552 						secondary_pipe->pipe_idx = preferred_pipe_idx;
2553 						break;
2554 					}
2555 				}
2556 			}
2557 		}
2558 		/*
2559 		 * We should never hit this assert unless assignments are shuffled around
2560 		 * if this happens we will prob. hit a vsync tdr
2561 		 */
2562 		ASSERT(secondary_pipe);
2563 		/*
2564 		 * search backwards for the second pipe to keep pipe
2565 		 * assignment more consistent
2566 		 */
2567 		if (secondary_pipe == NULL) {
2568 			for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2569 				preferred_pipe_idx = j;
2570 
2571 				if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2572 					secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2573 					secondary_pipe->pipe_idx = preferred_pipe_idx;
2574 					break;
2575 				}
2576 			}
2577 		}
2578 	}
2579 
2580 	return secondary_pipe;
2581 }
2582 
2583 void dcn20_merge_pipes_for_validate(
2584 		struct dc *dc,
2585 		struct dc_state *context)
2586 {
2587 	int i;
2588 
2589 	/* merge previously split odm pipes since mode support needs to make the decision */
2590 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
2591 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2592 		struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
2593 
2594 		if (pipe->prev_odm_pipe)
2595 			continue;
2596 
2597 		pipe->next_odm_pipe = NULL;
2598 		while (odm_pipe) {
2599 			struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
2600 
2601 			odm_pipe->plane_state = NULL;
2602 			odm_pipe->stream = NULL;
2603 			odm_pipe->top_pipe = NULL;
2604 			odm_pipe->bottom_pipe = NULL;
2605 			odm_pipe->prev_odm_pipe = NULL;
2606 			odm_pipe->next_odm_pipe = NULL;
2607 			if (odm_pipe->stream_res.dsc)
2608 				dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
2609 			/* Clear plane_res and stream_res */
2610 			memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
2611 			memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
2612 			odm_pipe = next_odm_pipe;
2613 		}
2614 		if (pipe->plane_state)
2615 			resource_build_scaling_params(pipe);
2616 	}
2617 
2618 	/* merge previously mpc split pipes since mode support needs to make the decision */
2619 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
2620 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2621 		struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2622 
2623 		if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
2624 			continue;
2625 
2626 		pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
2627 		if (hsplit_pipe->bottom_pipe)
2628 			hsplit_pipe->bottom_pipe->top_pipe = pipe;
2629 		hsplit_pipe->plane_state = NULL;
2630 		hsplit_pipe->stream = NULL;
2631 		hsplit_pipe->top_pipe = NULL;
2632 		hsplit_pipe->bottom_pipe = NULL;
2633 
2634 		/* Clear plane_res and stream_res */
2635 		memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
2636 		memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
2637 		if (pipe->plane_state)
2638 			resource_build_scaling_params(pipe);
2639 	}
2640 }
2641 
2642 int dcn20_validate_apply_pipe_split_flags(
2643 		struct dc *dc,
2644 		struct dc_state *context,
2645 		int vlevel,
2646 		int *split,
2647 		bool *merge)
2648 {
2649 	int i, pipe_idx, vlevel_split;
2650 	int plane_count = 0;
2651 	bool force_split = false;
2652 	bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID;
2653 	struct vba_vars_st *v = &context->bw_ctx.dml.vba;
2654 	int max_mpc_comb = v->maxMpcComb;
2655 
2656 	if (context->stream_count > 1) {
2657 		if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP)
2658 			avoid_split = true;
2659 	} else if (dc->debug.force_single_disp_pipe_split)
2660 			force_split = true;
2661 
2662 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
2663 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2664 
2665 		/**
2666 		 * Workaround for avoiding pipe-split in cases where we'd split
2667 		 * planes that are too small, resulting in splits that aren't
2668 		 * valid for the scaler.
2669 		 */
2670 		if (pipe->plane_state &&
2671 		    (pipe->plane_state->dst_rect.width <= 16 ||
2672 		     pipe->plane_state->dst_rect.height <= 16 ||
2673 		     pipe->plane_state->src_rect.width <= 16 ||
2674 		     pipe->plane_state->src_rect.height <= 16))
2675 			avoid_split = true;
2676 
2677 		/* TODO: fix dc bugs and remove this split threshold thing */
2678 		if (pipe->stream && !pipe->prev_odm_pipe &&
2679 				(!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state))
2680 			++plane_count;
2681 	}
2682 	if (plane_count > dc->res_pool->pipe_count / 2)
2683 		avoid_split = true;
2684 
2685 	/* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */
2686 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
2687 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2688 		struct dc_crtc_timing timing;
2689 
2690 		if (!pipe->stream)
2691 			continue;
2692 		else {
2693 			timing = pipe->stream->timing;
2694 			if (timing.h_border_left + timing.h_border_right
2695 					+ timing.v_border_top + timing.v_border_bottom > 0) {
2696 				avoid_split = true;
2697 				break;
2698 			}
2699 		}
2700 	}
2701 
2702 	/* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */
2703 	if (avoid_split) {
2704 		for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2705 			if (!context->res_ctx.pipe_ctx[i].stream)
2706 				continue;
2707 
2708 			for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
2709 				if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 &&
2710 						v->ModeSupport[vlevel][0])
2711 					break;
2712 			/* Impossible to not split this pipe */
2713 			if (vlevel > context->bw_ctx.dml.soc.num_states)
2714 				vlevel = vlevel_split;
2715 			else
2716 				max_mpc_comb = 0;
2717 			pipe_idx++;
2718 		}
2719 		v->maxMpcComb = max_mpc_comb;
2720 	}
2721 
2722 	/* Split loop sets which pipe should be split based on dml outputs and dc flags */
2723 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2724 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2725 		int pipe_plane = v->pipe_plane[pipe_idx];
2726 		bool split4mpc = context->stream_count == 1 && plane_count == 1
2727 				&& dc->config.enable_4to1MPC && dc->res_pool->pipe_count >= 4;
2728 
2729 		if (!context->res_ctx.pipe_ctx[i].stream)
2730 			continue;
2731 
2732 		if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4)
2733 			split[i] = 4;
2734 		else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2)
2735 				split[i] = 2;
2736 
2737 		if ((pipe->stream->view_format ==
2738 				VIEW_3D_FORMAT_SIDE_BY_SIDE ||
2739 				pipe->stream->view_format ==
2740 				VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
2741 				(pipe->stream->timing.timing_3d_format ==
2742 				TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
2743 				 pipe->stream->timing.timing_3d_format ==
2744 				TIMING_3D_FORMAT_SIDE_BY_SIDE))
2745 			split[i] = 2;
2746 		if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
2747 			split[i] = 2;
2748 			v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1;
2749 		}
2750 		if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) {
2751 			split[i] = 4;
2752 			v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1;
2753 		}
2754 		/*420 format workaround*/
2755 		if (pipe->stream->timing.h_addressable > 7680 &&
2756 				pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
2757 			split[i] = 4;
2758 		}
2759 		v->ODMCombineEnabled[pipe_plane] =
2760 			v->ODMCombineEnablePerState[vlevel][pipe_plane];
2761 
2762 		if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) {
2763 			if (get_num_mpc_splits(pipe) == 1) {
2764 				/*If need split for mpc but 2 way split already*/
2765 				if (split[i] == 4)
2766 					split[i] = 2; /* 2 -> 4 MPC */
2767 				else if (split[i] == 2)
2768 					split[i] = 0; /* 2 -> 2 MPC */
2769 				else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
2770 					merge[i] = true; /* 2 -> 1 MPC */
2771 			} else if (get_num_mpc_splits(pipe) == 3) {
2772 				/*If need split for mpc but 4 way split already*/
2773 				if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe)
2774 						|| !pipe->bottom_pipe)) {
2775 					merge[i] = true; /* 4 -> 2 MPC */
2776 				} else if (split[i] == 0 && pipe->top_pipe &&
2777 						pipe->top_pipe->plane_state == pipe->plane_state)
2778 					merge[i] = true; /* 4 -> 1 MPC */
2779 				split[i] = 0;
2780 			} else if (get_num_odm_splits(pipe)) {
2781 				/* ODM -> MPC transition */
2782 				if (pipe->prev_odm_pipe) {
2783 					split[i] = 0;
2784 					merge[i] = true;
2785 				}
2786 			}
2787 		} else {
2788 			if (get_num_odm_splits(pipe) == 1) {
2789 				/*If need split for odm but 2 way split already*/
2790 				if (split[i] == 4)
2791 					split[i] = 2; /* 2 -> 4 ODM */
2792 				else if (split[i] == 2)
2793 					split[i] = 0; /* 2 -> 2 ODM */
2794 				else if (pipe->prev_odm_pipe) {
2795 					ASSERT(0); /* NOT expected yet */
2796 					merge[i] = true; /* exit ODM */
2797 				}
2798 			} else if (get_num_odm_splits(pipe) == 3) {
2799 				/*If need split for odm but 4 way split already*/
2800 				if (split[i] == 2 && ((pipe->prev_odm_pipe && !pipe->prev_odm_pipe->prev_odm_pipe)
2801 						|| !pipe->next_odm_pipe)) {
2802 					ASSERT(0); /* NOT expected yet */
2803 					merge[i] = true; /* 4 -> 2 ODM */
2804 				} else if (split[i] == 0 && pipe->prev_odm_pipe) {
2805 					ASSERT(0); /* NOT expected yet */
2806 					merge[i] = true; /* exit ODM */
2807 				}
2808 				split[i] = 0;
2809 			} else if (get_num_mpc_splits(pipe)) {
2810 				/* MPC -> ODM transition */
2811 				ASSERT(0); /* NOT expected yet */
2812 				if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
2813 					split[i] = 0;
2814 					merge[i] = true;
2815 				}
2816 			}
2817 		}
2818 
2819 		/* Adjust dppclk when split is forced, do not bother with dispclk */
2820 		if (split[i] != 0 && v->NoOfDPP[vlevel][max_mpc_comb][pipe_idx] == 1)
2821 			v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2;
2822 		pipe_idx++;
2823 	}
2824 
2825 	return vlevel;
2826 }
2827 
2828 bool dcn20_fast_validate_bw(
2829 		struct dc *dc,
2830 		struct dc_state *context,
2831 		display_e2e_pipe_params_st *pipes,
2832 		int *pipe_cnt_out,
2833 		int *pipe_split_from,
2834 		int *vlevel_out,
2835 		bool fast_validate)
2836 {
2837 	bool out = false;
2838 	int split[MAX_PIPES] = { 0 };
2839 	int pipe_cnt, i, pipe_idx, vlevel;
2840 
2841 	ASSERT(pipes);
2842 	if (!pipes)
2843 		return false;
2844 
2845 	dcn20_merge_pipes_for_validate(dc, context);
2846 
2847 	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2848 
2849 	*pipe_cnt_out = pipe_cnt;
2850 
2851 	if (!pipe_cnt) {
2852 		out = true;
2853 		goto validate_out;
2854 	}
2855 
2856 	vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2857 
2858 	if (vlevel > context->bw_ctx.dml.soc.num_states)
2859 		goto validate_fail;
2860 
2861 	vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
2862 
2863 	/*initialize pipe_just_split_from to invalid idx*/
2864 	for (i = 0; i < MAX_PIPES; i++)
2865 		pipe_split_from[i] = -1;
2866 
2867 	for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2868 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2869 		struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2870 
2871 		if (!pipe->stream || pipe_split_from[i] >= 0)
2872 			continue;
2873 
2874 		pipe_idx++;
2875 
2876 		if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2877 			hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2878 			ASSERT(hsplit_pipe);
2879 			if (!dcn20_split_stream_for_odm(
2880 					dc, &context->res_ctx,
2881 					pipe, hsplit_pipe))
2882 				goto validate_fail;
2883 			pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2884 			dcn20_build_mapped_resource(dc, context, pipe->stream);
2885 		}
2886 
2887 		if (!pipe->plane_state)
2888 			continue;
2889 		/* Skip 2nd half of already split pipe */
2890 		if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2891 			continue;
2892 
2893 		/* We do not support mpo + odm at the moment */
2894 		if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2895 				&& context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2896 			goto validate_fail;
2897 
2898 		if (split[i] == 2) {
2899 			if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2900 				/* pipe not split previously needs split */
2901 				hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2902 				ASSERT(hsplit_pipe);
2903 				if (!hsplit_pipe) {
2904 					context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
2905 					continue;
2906 				}
2907 				if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2908 					if (!dcn20_split_stream_for_odm(
2909 							dc, &context->res_ctx,
2910 							pipe, hsplit_pipe))
2911 						goto validate_fail;
2912 					dcn20_build_mapped_resource(dc, context, pipe->stream);
2913 				} else {
2914 					dcn20_split_stream_for_mpc(
2915 							&context->res_ctx, dc->res_pool,
2916 							pipe, hsplit_pipe);
2917 					resource_build_scaling_params(pipe);
2918 					resource_build_scaling_params(hsplit_pipe);
2919 				}
2920 				pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2921 			}
2922 		} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
2923 			/* merge should already have been done */
2924 			ASSERT(0);
2925 		}
2926 	}
2927 	/* Actual dsc count per stream dsc validation*/
2928 	if (!dcn20_validate_dsc(dc, context)) {
2929 		context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2930 				DML_FAIL_DSC_VALIDATION_FAILURE;
2931 		goto validate_fail;
2932 	}
2933 
2934 	*vlevel_out = vlevel;
2935 
2936 	out = true;
2937 	goto validate_out;
2938 
2939 validate_fail:
2940 	out = false;
2941 
2942 validate_out:
2943 	return out;
2944 }
2945 
2946 static void dcn20_calculate_wm(
2947 		struct dc *dc, struct dc_state *context,
2948 		display_e2e_pipe_params_st *pipes,
2949 		int *out_pipe_cnt,
2950 		int *pipe_split_from,
2951 		int vlevel,
2952 		bool fast_validate)
2953 {
2954 	int pipe_cnt, i, pipe_idx;
2955 
2956 	for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2957 		if (!context->res_ctx.pipe_ctx[i].stream)
2958 			continue;
2959 
2960 		pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2961 		pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2962 
2963 		if (pipe_split_from[i] < 0) {
2964 			pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2965 					context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2966 			if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2967 				pipes[pipe_cnt].pipe.dest.odm_combine =
2968 						context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx];
2969 			else
2970 				pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2971 			pipe_idx++;
2972 		} else {
2973 			pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2974 					context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2975 			if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2976 				pipes[pipe_cnt].pipe.dest.odm_combine =
2977 						context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]];
2978 			else
2979 				pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2980 		}
2981 
2982 		if (dc->config.forced_clocks) {
2983 			pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2984 			pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2985 		}
2986 		if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
2987 			pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2988 		if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
2989 			pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2990 
2991 		pipe_cnt++;
2992 	}
2993 
2994 	if (pipe_cnt != pipe_idx) {
2995 		if (dc->res_pool->funcs->populate_dml_pipes)
2996 			pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2997 				context, pipes, fast_validate);
2998 		else
2999 			pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
3000 				context, pipes, fast_validate);
3001 	}
3002 
3003 	*out_pipe_cnt = pipe_cnt;
3004 
3005 	pipes[0].clks_cfg.voltage = vlevel;
3006 	pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
3007 	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
3008 
3009 	/* only pipe 0 is read for voltage and dcf/soc clocks */
3010 	if (vlevel < 1) {
3011 		pipes[0].clks_cfg.voltage = 1;
3012 		pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
3013 		pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
3014 	}
3015 	context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3016 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3017 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3018 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3019 	context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3020 	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3021 	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3022 	context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3023 
3024 	if (vlevel < 2) {
3025 		pipes[0].clks_cfg.voltage = 2;
3026 		pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
3027 		pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
3028 	}
3029 	context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3030 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3031 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3032 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3033 	context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3034 	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3035 	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3036 
3037 	if (vlevel < 3) {
3038 		pipes[0].clks_cfg.voltage = 3;
3039 		pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
3040 		pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
3041 	}
3042 	context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3043 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3044 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3045 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3046 	context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3047 	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3048 	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3049 
3050 	pipes[0].clks_cfg.voltage = vlevel;
3051 	pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
3052 	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
3053 	context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3054 	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3055 	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3056 	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3057 	context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3058 	context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3059 	context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3060 }
3061 
3062 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
3063 {
3064 	int i;
3065 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
3066 		if (!context->res_ctx.pipe_ctx[i].stream)
3067 			continue;
3068 		if (is_dp_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))
3069 			return true;
3070 	}
3071 	return false;
3072 }
3073 
3074 static enum dcn_zstate_support_state  decide_zstate_support(struct dc *dc, struct dc_state *context)
3075 {
3076 	int plane_count;
3077 	int i;
3078 
3079 	plane_count = 0;
3080 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
3081 		if (context->res_ctx.pipe_ctx[i].plane_state)
3082 			plane_count++;
3083 	}
3084 
3085 	/*
3086 	 * Zstate is allowed in following scenarios:
3087 	 * 	1. Single eDP with PSR enabled
3088 	 * 	2. 0 planes (No memory requests)
3089 	 * 	3. Single eDP without PSR but > 5ms stutter period
3090 	 */
3091 	if (plane_count == 0)
3092 		return DCN_ZSTATE_SUPPORT_ALLOW;
3093 	else if (context->stream_count == 1 &&  context->streams[0]->signal == SIGNAL_TYPE_EDP) {
3094 		struct dc_link *link = context->streams[0]->sink->link;
3095 
3096 		if (link->link_index == 0 && context->bw_ctx.dml.vba.StutterPeriod > 5000.0)
3097 			return DCN_ZSTATE_SUPPORT_ALLOW;
3098 		else
3099 			return DCN_ZSTATE_SUPPORT_DISALLOW;
3100 	} else
3101 		return DCN_ZSTATE_SUPPORT_DISALLOW;
3102 }
3103 
3104 void dcn20_calculate_dlg_params(
3105 		struct dc *dc, struct dc_state *context,
3106 		display_e2e_pipe_params_st *pipes,
3107 		int pipe_cnt,
3108 		int vlevel)
3109 {
3110 	int i, pipe_idx;
3111 
3112 	/* Writeback MCIF_WB arbitration parameters */
3113 	dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
3114 
3115 	context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
3116 	context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
3117 	context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
3118 	context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
3119 
3120 	if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz)
3121 		context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz;
3122 
3123 	context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
3124 	context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
3125 	context->bw_ctx.bw.dcn.clk.p_state_change_support =
3126 		context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
3127 							!= dm_dram_clock_change_unsupported;
3128 	context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
3129 
3130 	context->bw_ctx.bw.dcn.clk.zstate_support = decide_zstate_support(dc, context);
3131 
3132 	context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
3133 
3134 	if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
3135 		context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
3136 
3137 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3138 		if (!context->res_ctx.pipe_ctx[i].stream)
3139 			continue;
3140 		pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3141 		pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3142 		pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3143 		pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3144 		context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;
3145 		context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
3146 
3147 		if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
3148 			context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
3149 		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
3150 						pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
3151 		context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
3152 		pipe_idx++;
3153 	}
3154 	/*save a original dppclock copy*/
3155 	context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
3156 	context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
3157 	context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
3158 	context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
3159 
3160 	context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes
3161 						- context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx;
3162 
3163 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3164 		bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
3165 
3166 		if (!context->res_ctx.pipe_ctx[i].stream)
3167 			continue;
3168 
3169 		if (dc->ctx->dce_version == DCN_VERSION_2_01)
3170 			cstate_en = false;
3171 
3172 		context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
3173 				&context->res_ctx.pipe_ctx[i].dlg_regs,
3174 				&context->res_ctx.pipe_ctx[i].ttu_regs,
3175 				pipes,
3176 				pipe_cnt,
3177 				pipe_idx,
3178 				cstate_en,
3179 				context->bw_ctx.bw.dcn.clk.p_state_change_support,
3180 				false, false, true);
3181 
3182 		context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
3183 				&context->res_ctx.pipe_ctx[i].rq_regs,
3184 				&pipes[pipe_idx].pipe);
3185 		pipe_idx++;
3186 	}
3187 }
3188 
3189 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
3190 		bool fast_validate)
3191 {
3192 	bool out = false;
3193 
3194 	BW_VAL_TRACE_SETUP();
3195 
3196 	int vlevel = 0;
3197 	int pipe_split_from[MAX_PIPES];
3198 	int pipe_cnt = 0;
3199 	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
3200 	DC_LOGGER_INIT(dc->ctx->logger);
3201 
3202 	BW_VAL_TRACE_COUNT();
3203 
3204 	out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
3205 
3206 	if (pipe_cnt == 0)
3207 		goto validate_out;
3208 
3209 	if (!out)
3210 		goto validate_fail;
3211 
3212 	BW_VAL_TRACE_END_VOLTAGE_LEVEL();
3213 
3214 	if (fast_validate) {
3215 		BW_VAL_TRACE_SKIP(fast);
3216 		goto validate_out;
3217 	}
3218 
3219 	dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
3220 	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
3221 
3222 	BW_VAL_TRACE_END_WATERMARKS();
3223 
3224 	goto validate_out;
3225 
3226 validate_fail:
3227 	DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
3228 		dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
3229 
3230 	BW_VAL_TRACE_SKIP(fail);
3231 	out = false;
3232 
3233 validate_out:
3234 	kfree(pipes);
3235 
3236 	BW_VAL_TRACE_FINISH();
3237 
3238 	return out;
3239 }
3240 
3241 /*
3242  * This must be noinline to ensure anything that deals with FP registers
3243  * is contained within this call; previously our compiling with hard-float
3244  * would result in fp instructions being emitted outside of the boundaries
3245  * of the DC_FP_START/END macros, which makes sense as the compiler has no
3246  * idea about what is wrapped and what is not
3247  *
3248  * This is largely just a workaround to avoid breakage introduced with 5.6,
3249  * ideally all fp-using code should be moved into its own file, only that
3250  * should be compiled with hard-float, and all code exported from there
3251  * should be strictly wrapped with DC_FP_START/END
3252  */
3253 static noinline bool dcn20_validate_bandwidth_fp(struct dc *dc,
3254 		struct dc_state *context, bool fast_validate)
3255 {
3256 	bool voltage_supported = false;
3257 	bool full_pstate_supported = false;
3258 	bool dummy_pstate_supported = false;
3259 	double p_state_latency_us;
3260 
3261 	p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
3262 	context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =
3263 		dc->debug.disable_dram_clock_change_vactive_support;
3264 	context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive =
3265 		dc->debug.enable_dram_clock_change_one_display_vactive;
3266 
3267 	/*Unsafe due to current pipe merge and split logic*/
3268 	ASSERT(context != dc->current_state);
3269 
3270 	if (fast_validate) {
3271 		return dcn20_validate_bandwidth_internal(dc, context, true);
3272 	}
3273 
3274 	// Best case, we support full UCLK switch latency
3275 	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
3276 	full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
3277 
3278 	if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
3279 		(voltage_supported && full_pstate_supported)) {
3280 		context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported;
3281 		goto restore_dml_state;
3282 	}
3283 
3284 	// Fallback: Try to only support G6 temperature read latency
3285 	context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
3286 
3287 	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
3288 	dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
3289 
3290 	if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) {
3291 		context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
3292 		goto restore_dml_state;
3293 	}
3294 
3295 	// ERROR: fallback is supposed to always work.
3296 	ASSERT(false);
3297 
3298 restore_dml_state:
3299 	context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
3300 	return voltage_supported;
3301 }
3302 
3303 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
3304 		bool fast_validate)
3305 {
3306 	bool voltage_supported;
3307 	DC_FP_START();
3308 	voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate);
3309 	DC_FP_END();
3310 	return voltage_supported;
3311 }
3312 
3313 struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
3314 		struct dc_state *state,
3315 		const struct resource_pool *pool,
3316 		struct dc_stream_state *stream)
3317 {
3318 	struct resource_context *res_ctx = &state->res_ctx;
3319 	struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
3320 	struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
3321 
3322 	if (!head_pipe)
3323 		ASSERT(0);
3324 
3325 	if (!idle_pipe)
3326 		return NULL;
3327 
3328 	idle_pipe->stream = head_pipe->stream;
3329 	idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
3330 	idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
3331 
3332 	idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
3333 	idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
3334 	idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
3335 	idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
3336 
3337 	return idle_pipe;
3338 }
3339 
3340 bool dcn20_get_dcc_compression_cap(const struct dc *dc,
3341 		const struct dc_dcc_surface_param *input,
3342 		struct dc_surface_dcc_cap *output)
3343 {
3344 	return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
3345 			dc->res_pool->hubbub,
3346 			input,
3347 			output);
3348 }
3349 
3350 static void dcn20_destroy_resource_pool(struct resource_pool **pool)
3351 {
3352 	struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
3353 
3354 	dcn20_resource_destruct(dcn20_pool);
3355 	kfree(dcn20_pool);
3356 	*pool = NULL;
3357 }
3358 
3359 
3360 static struct dc_cap_funcs cap_funcs = {
3361 	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
3362 };
3363 
3364 
3365 enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state)
3366 {
3367 	enum surface_pixel_format surf_pix_format = plane_state->format;
3368 	unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
3369 
3370 	enum swizzle_mode_values swizzle = DC_SW_LINEAR;
3371 
3372 	if (bpp == 64)
3373 		swizzle = DC_SW_64KB_D;
3374 	else
3375 		swizzle = DC_SW_64KB_S;
3376 
3377 	plane_state->tiling_info.gfx9.swizzle = swizzle;
3378 	return DC_OK;
3379 }
3380 
3381 static const struct resource_funcs dcn20_res_pool_funcs = {
3382 	.destroy = dcn20_destroy_resource_pool,
3383 	.link_enc_create = dcn20_link_encoder_create,
3384 	.panel_cntl_create = dcn20_panel_cntl_create,
3385 	.validate_bandwidth = dcn20_validate_bandwidth,
3386 	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
3387 	.add_stream_to_ctx = dcn20_add_stream_to_ctx,
3388 	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
3389 	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
3390 	.populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
3391 	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
3392 	.set_mcif_arb_params = dcn20_set_mcif_arb_params,
3393 	.populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
3394 	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
3395 };
3396 
3397 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
3398 {
3399 	int i;
3400 	uint32_t pipe_count = pool->res_cap->num_dwb;
3401 
3402 	for (i = 0; i < pipe_count; i++) {
3403 		struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
3404 						    GFP_KERNEL);
3405 
3406 		if (!dwbc20) {
3407 			dm_error("DC: failed to create dwbc20!\n");
3408 			return false;
3409 		}
3410 		dcn20_dwbc_construct(dwbc20, ctx,
3411 				&dwbc20_regs[i],
3412 				&dwbc20_shift,
3413 				&dwbc20_mask,
3414 				i);
3415 		pool->dwbc[i] = &dwbc20->base;
3416 	}
3417 	return true;
3418 }
3419 
3420 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
3421 {
3422 	int i;
3423 	uint32_t pipe_count = pool->res_cap->num_dwb;
3424 
3425 	ASSERT(pipe_count > 0);
3426 
3427 	for (i = 0; i < pipe_count; i++) {
3428 		struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
3429 						    GFP_KERNEL);
3430 
3431 		if (!mcif_wb20) {
3432 			dm_error("DC: failed to create mcif_wb20!\n");
3433 			return false;
3434 		}
3435 
3436 		dcn20_mmhubbub_construct(mcif_wb20, ctx,
3437 				&mcif_wb20_regs[i],
3438 				&mcif_wb20_shift,
3439 				&mcif_wb20_mask,
3440 				i);
3441 
3442 		pool->mcif_wb[i] = &mcif_wb20->base;
3443 	}
3444 	return true;
3445 }
3446 
3447 static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
3448 {
3449 	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_ATOMIC);
3450 
3451 	if (!pp_smu)
3452 		return pp_smu;
3453 
3454 	dm_pp_get_funcs(ctx, pp_smu);
3455 
3456 	if (pp_smu->ctx.ver != PP_SMU_VER_NV)
3457 		pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
3458 
3459 	return pp_smu;
3460 }
3461 
3462 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
3463 {
3464 	if (pp_smu && *pp_smu) {
3465 		kfree(*pp_smu);
3466 		*pp_smu = NULL;
3467 	}
3468 }
3469 
3470 void dcn20_cap_soc_clocks(
3471 		struct _vcs_dpi_soc_bounding_box_st *bb,
3472 		struct pp_smu_nv_clock_table max_clocks)
3473 {
3474 	int i;
3475 
3476 	// First pass - cap all clocks higher than the reported max
3477 	for (i = 0; i < bb->num_states; i++) {
3478 		if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
3479 				&& max_clocks.dcfClockInKhz != 0)
3480 			bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
3481 
3482 		if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
3483 						&& max_clocks.uClockInKhz != 0)
3484 			bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
3485 
3486 		if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
3487 						&& max_clocks.fabricClockInKhz != 0)
3488 			bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
3489 
3490 		if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
3491 						&& max_clocks.displayClockInKhz != 0)
3492 			bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
3493 
3494 		if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
3495 						&& max_clocks.dppClockInKhz != 0)
3496 			bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
3497 
3498 		if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
3499 						&& max_clocks.phyClockInKhz != 0)
3500 			bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
3501 
3502 		if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
3503 						&& max_clocks.socClockInKhz != 0)
3504 			bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
3505 
3506 		if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
3507 						&& max_clocks.dscClockInKhz != 0)
3508 			bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
3509 	}
3510 
3511 	// Second pass - remove all duplicate clock states
3512 	for (i = bb->num_states - 1; i > 1; i--) {
3513 		bool duplicate = true;
3514 
3515 		if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
3516 			duplicate = false;
3517 		if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
3518 			duplicate = false;
3519 		if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
3520 			duplicate = false;
3521 		if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
3522 			duplicate = false;
3523 		if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
3524 			duplicate = false;
3525 		if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
3526 			duplicate = false;
3527 		if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
3528 			duplicate = false;
3529 		if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
3530 			duplicate = false;
3531 
3532 		if (duplicate)
3533 			bb->num_states--;
3534 	}
3535 }
3536 
3537 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
3538 		struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
3539 {
3540 	struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES];
3541 	int i;
3542 	int num_calculated_states = 0;
3543 	int min_dcfclk = 0;
3544 
3545 	if (num_states == 0)
3546 		return;
3547 
3548 	memset(calculated_states, 0, sizeof(calculated_states));
3549 
3550 	if (dc->bb_overrides.min_dcfclk_mhz > 0)
3551 		min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
3552 	else {
3553 		if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
3554 			min_dcfclk = 310;
3555 		else
3556 			// Accounting for SOC/DCF relationship, we can go as high as
3557 			// 506Mhz in Vmin.
3558 			min_dcfclk = 506;
3559 	}
3560 
3561 	for (i = 0; i < num_states; i++) {
3562 		int min_fclk_required_by_uclk;
3563 		calculated_states[i].state = i;
3564 		calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
3565 
3566 		// FCLK:UCLK ratio is 1.08
3567 		min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080,
3568 			1000000);
3569 
3570 		calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
3571 				min_dcfclk : min_fclk_required_by_uclk;
3572 
3573 		calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
3574 				max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
3575 
3576 		calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
3577 				max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
3578 
3579 		calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
3580 		calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
3581 		calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
3582 
3583 		calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
3584 
3585 		num_calculated_states++;
3586 	}
3587 
3588 	calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
3589 	calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
3590 	calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
3591 
3592 	memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
3593 	bb->num_states = num_calculated_states;
3594 
3595 	// Duplicate the last state, DML always an extra state identical to max state to work
3596 	memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
3597 	bb->clock_limits[num_calculated_states].state = bb->num_states;
3598 }
3599 
3600 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
3601 {
3602 	if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
3603 			&& dc->bb_overrides.sr_exit_time_ns) {
3604 		bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
3605 	}
3606 
3607 	if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
3608 				!= dc->bb_overrides.sr_enter_plus_exit_time_ns
3609 			&& dc->bb_overrides.sr_enter_plus_exit_time_ns) {
3610 		bb->sr_enter_plus_exit_time_us =
3611 				dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
3612 	}
3613 
3614 	if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
3615 			&& dc->bb_overrides.urgent_latency_ns) {
3616 		bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
3617 	}
3618 
3619 	if ((int)(bb->dram_clock_change_latency_us * 1000)
3620 				!= dc->bb_overrides.dram_clock_change_latency_ns
3621 			&& dc->bb_overrides.dram_clock_change_latency_ns) {
3622 		bb->dram_clock_change_latency_us =
3623 				dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
3624 	}
3625 
3626 	if ((int)(bb->dummy_pstate_latency_us * 1000)
3627 				!= dc->bb_overrides.dummy_clock_change_latency_ns
3628 			&& dc->bb_overrides.dummy_clock_change_latency_ns) {
3629 		bb->dummy_pstate_latency_us =
3630 				dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
3631 	}
3632 }
3633 
3634 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
3635 	uint32_t hw_internal_rev)
3636 {
3637 	if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3638 		return &dcn2_0_nv14_soc;
3639 
3640 	if (ASICREV_IS_NAVI12_P(hw_internal_rev))
3641 		return &dcn2_0_nv12_soc;
3642 
3643 	return &dcn2_0_soc;
3644 }
3645 
3646 static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
3647 	uint32_t hw_internal_rev)
3648 {
3649 	/* NV14 */
3650 	if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3651 		return &dcn2_0_nv14_ip;
3652 
3653 	/* NV12 and NV10 */
3654 	return &dcn2_0_ip;
3655 }
3656 
3657 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
3658 {
3659 	return DML_PROJECT_NAVI10v2;
3660 }
3661 
3662 static bool init_soc_bounding_box(struct dc *dc,
3663 				  struct dcn20_resource_pool *pool)
3664 {
3665 	struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3666 			get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
3667 	struct _vcs_dpi_ip_params_st *loaded_ip =
3668 			get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
3669 
3670 	DC_LOGGER_INIT(dc->ctx->logger);
3671 
3672 	if (pool->base.pp_smu) {
3673 		struct pp_smu_nv_clock_table max_clocks = {0};
3674 		unsigned int uclk_states[8] = {0};
3675 		unsigned int num_states = 0;
3676 		enum pp_smu_status status;
3677 		bool clock_limits_available = false;
3678 		bool uclk_states_available = false;
3679 
3680 		if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
3681 			status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
3682 				(&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
3683 
3684 			uclk_states_available = (status == PP_SMU_RESULT_OK);
3685 		}
3686 
3687 		if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
3688 			status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
3689 					(&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
3690 			/* SMU cannot set DCF clock to anything equal to or higher than SOC clock
3691 			 */
3692 			if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
3693 				max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
3694 			clock_limits_available = (status == PP_SMU_RESULT_OK);
3695 		}
3696 
3697 		if (clock_limits_available && uclk_states_available && num_states) {
3698 			DC_FP_START();
3699 			dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
3700 			DC_FP_END();
3701 		} else if (clock_limits_available) {
3702 			DC_FP_START();
3703 			dcn20_cap_soc_clocks(loaded_bb, max_clocks);
3704 			DC_FP_END();
3705 		}
3706 	}
3707 
3708 	loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
3709 	loaded_ip->max_num_dpp = pool->base.pipe_count;
3710 	DC_FP_START();
3711 	dcn20_patch_bounding_box(dc, loaded_bb);
3712 	DC_FP_END();
3713 	return true;
3714 }
3715 
3716 static bool dcn20_resource_construct(
3717 	uint8_t num_virtual_links,
3718 	struct dc *dc,
3719 	struct dcn20_resource_pool *pool)
3720 {
3721 	int i;
3722 	struct dc_context *ctx = dc->ctx;
3723 	struct irq_service_init_data init_data;
3724 	struct ddc_service_init_data ddc_init_data = {0};
3725 	struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3726 			get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
3727 	struct _vcs_dpi_ip_params_st *loaded_ip =
3728 			get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);
3729 	enum dml_project dml_project_version =
3730 			get_dml_project_version(ctx->asic_id.hw_internal_rev);
3731 
3732 	ctx->dc_bios->regs = &bios_regs;
3733 	pool->base.funcs = &dcn20_res_pool_funcs;
3734 
3735 	if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
3736 		pool->base.res_cap = &res_cap_nv14;
3737 		pool->base.pipe_count = 5;
3738 		pool->base.mpcc_count = 5;
3739 	} else {
3740 		pool->base.res_cap = &res_cap_nv10;
3741 		pool->base.pipe_count = 6;
3742 		pool->base.mpcc_count = 6;
3743 	}
3744 	/*************************************************
3745 	 *  Resource + asic cap harcoding                *
3746 	 *************************************************/
3747 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
3748 
3749 	dc->caps.max_downscale_ratio = 200;
3750 	dc->caps.i2c_speed_in_khz = 100;
3751 	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
3752 	dc->caps.max_cursor_size = 256;
3753 	dc->caps.min_horizontal_blanking_period = 80;
3754 	dc->caps.dmdata_alloc_size = 2048;
3755 
3756 	dc->caps.max_slave_planes = 1;
3757 	dc->caps.max_slave_yuv_planes = 1;
3758 	dc->caps.max_slave_rgb_planes = 1;
3759 	dc->caps.post_blend_color_processing = true;
3760 	dc->caps.force_dp_tps4_for_cp2520 = true;
3761 	dc->caps.extended_aux_timeout_support = true;
3762 
3763 	/* Color pipeline capabilities */
3764 	dc->caps.color.dpp.dcn_arch = 1;
3765 	dc->caps.color.dpp.input_lut_shared = 0;
3766 	dc->caps.color.dpp.icsc = 1;
3767 	dc->caps.color.dpp.dgam_ram = 1;
3768 	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
3769 	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
3770 	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
3771 	dc->caps.color.dpp.dgam_rom_caps.pq = 0;
3772 	dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
3773 	dc->caps.color.dpp.post_csc = 0;
3774 	dc->caps.color.dpp.gamma_corr = 0;
3775 	dc->caps.color.dpp.dgam_rom_for_yuv = 1;
3776 
3777 	dc->caps.color.dpp.hw_3d_lut = 1;
3778 	dc->caps.color.dpp.ogam_ram = 1;
3779 	// no OGAM ROM on DCN2, only MPC ROM
3780 	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
3781 	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
3782 	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
3783 	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
3784 	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
3785 	dc->caps.color.dpp.ocsc = 0;
3786 
3787 	dc->caps.color.mpc.gamut_remap = 0;
3788 	dc->caps.color.mpc.num_3dluts = 0;
3789 	dc->caps.color.mpc.shared_3d_lut = 0;
3790 	dc->caps.color.mpc.ogam_ram = 1;
3791 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
3792 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
3793 	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
3794 	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
3795 	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
3796 	dc->caps.color.mpc.ocsc = 1;
3797 
3798 	dc->caps.hdmi_frl_pcon_support = true;
3799 
3800 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
3801 		dc->debug = debug_defaults_drv;
3802 	} else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
3803 		pool->base.pipe_count = 4;
3804 		pool->base.mpcc_count = pool->base.pipe_count;
3805 		dc->debug = debug_defaults_diags;
3806 	} else {
3807 		dc->debug = debug_defaults_diags;
3808 	}
3809 	//dcn2.0x
3810 	dc->work_arounds.dedcn20_305_wa = true;
3811 
3812 	// Init the vm_helper
3813 	if (dc->vm_helper)
3814 		vm_helper_init(dc->vm_helper, 16);
3815 
3816 	/*************************************************
3817 	 *  Create resources                             *
3818 	 *************************************************/
3819 
3820 	pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
3821 			dcn20_clock_source_create(ctx, ctx->dc_bios,
3822 				CLOCK_SOURCE_COMBO_PHY_PLL0,
3823 				&clk_src_regs[0], false);
3824 	pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
3825 			dcn20_clock_source_create(ctx, ctx->dc_bios,
3826 				CLOCK_SOURCE_COMBO_PHY_PLL1,
3827 				&clk_src_regs[1], false);
3828 	pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
3829 			dcn20_clock_source_create(ctx, ctx->dc_bios,
3830 				CLOCK_SOURCE_COMBO_PHY_PLL2,
3831 				&clk_src_regs[2], false);
3832 	pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
3833 			dcn20_clock_source_create(ctx, ctx->dc_bios,
3834 				CLOCK_SOURCE_COMBO_PHY_PLL3,
3835 				&clk_src_regs[3], false);
3836 	pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
3837 			dcn20_clock_source_create(ctx, ctx->dc_bios,
3838 				CLOCK_SOURCE_COMBO_PHY_PLL4,
3839 				&clk_src_regs[4], false);
3840 	pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
3841 			dcn20_clock_source_create(ctx, ctx->dc_bios,
3842 				CLOCK_SOURCE_COMBO_PHY_PLL5,
3843 				&clk_src_regs[5], false);
3844 	pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
3845 	/* todo: not reuse phy_pll registers */
3846 	pool->base.dp_clock_source =
3847 			dcn20_clock_source_create(ctx, ctx->dc_bios,
3848 				CLOCK_SOURCE_ID_DP_DTO,
3849 				&clk_src_regs[0], true);
3850 
3851 	for (i = 0; i < pool->base.clk_src_count; i++) {
3852 		if (pool->base.clock_sources[i] == NULL) {
3853 			dm_error("DC: failed to create clock sources!\n");
3854 			BREAK_TO_DEBUGGER();
3855 			goto create_fail;
3856 		}
3857 	}
3858 
3859 	pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
3860 	if (pool->base.dccg == NULL) {
3861 		dm_error("DC: failed to create dccg!\n");
3862 		BREAK_TO_DEBUGGER();
3863 		goto create_fail;
3864 	}
3865 
3866 	pool->base.dmcu = dcn20_dmcu_create(ctx,
3867 			&dmcu_regs,
3868 			&dmcu_shift,
3869 			&dmcu_mask);
3870 	if (pool->base.dmcu == NULL) {
3871 		dm_error("DC: failed to create dmcu!\n");
3872 		BREAK_TO_DEBUGGER();
3873 		goto create_fail;
3874 	}
3875 
3876 	pool->base.abm = dce_abm_create(ctx,
3877 			&abm_regs,
3878 			&abm_shift,
3879 			&abm_mask);
3880 	if (pool->base.abm == NULL) {
3881 		dm_error("DC: failed to create abm!\n");
3882 		BREAK_TO_DEBUGGER();
3883 		goto create_fail;
3884 	}
3885 
3886 	pool->base.pp_smu = dcn20_pp_smu_create(ctx);
3887 
3888 
3889 	if (!init_soc_bounding_box(dc, pool)) {
3890 		dm_error("DC: failed to initialize soc bounding box!\n");
3891 		BREAK_TO_DEBUGGER();
3892 		goto create_fail;
3893 	}
3894 
3895 	dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
3896 
3897 	if (!dc->debug.disable_pplib_wm_range) {
3898 		struct pp_smu_wm_range_sets ranges = {0};
3899 		int i = 0;
3900 
3901 		ranges.num_reader_wm_sets = 0;
3902 
3903 		if (loaded_bb->num_states == 1) {
3904 			ranges.reader_wm_sets[0].wm_inst = i;
3905 			ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3906 			ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3907 			ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3908 			ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3909 
3910 			ranges.num_reader_wm_sets = 1;
3911 		} else if (loaded_bb->num_states > 1) {
3912 			for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
3913 				ranges.reader_wm_sets[i].wm_inst = i;
3914 				ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3915 				ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3916 				ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
3917 				ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
3918 
3919 				ranges.num_reader_wm_sets = i + 1;
3920 			}
3921 
3922 			ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3923 			ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3924 		}
3925 
3926 		ranges.num_writer_wm_sets = 1;
3927 
3928 		ranges.writer_wm_sets[0].wm_inst = 0;
3929 		ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3930 		ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3931 		ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3932 		ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3933 
3934 		/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
3935 		if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
3936 			pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
3937 	}
3938 
3939 	init_data.ctx = dc->ctx;
3940 	pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
3941 	if (!pool->base.irqs)
3942 		goto create_fail;
3943 
3944 	/* mem input -> ipp -> dpp -> opp -> TG */
3945 	for (i = 0; i < pool->base.pipe_count; i++) {
3946 		pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
3947 		if (pool->base.hubps[i] == NULL) {
3948 			BREAK_TO_DEBUGGER();
3949 			dm_error(
3950 				"DC: failed to create memory input!\n");
3951 			goto create_fail;
3952 		}
3953 
3954 		pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
3955 		if (pool->base.ipps[i] == NULL) {
3956 			BREAK_TO_DEBUGGER();
3957 			dm_error(
3958 				"DC: failed to create input pixel processor!\n");
3959 			goto create_fail;
3960 		}
3961 
3962 		pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
3963 		if (pool->base.dpps[i] == NULL) {
3964 			BREAK_TO_DEBUGGER();
3965 			dm_error(
3966 				"DC: failed to create dpps!\n");
3967 			goto create_fail;
3968 		}
3969 	}
3970 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
3971 		pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
3972 		if (pool->base.engines[i] == NULL) {
3973 			BREAK_TO_DEBUGGER();
3974 			dm_error(
3975 				"DC:failed to create aux engine!!\n");
3976 			goto create_fail;
3977 		}
3978 		pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
3979 		if (pool->base.hw_i2cs[i] == NULL) {
3980 			BREAK_TO_DEBUGGER();
3981 			dm_error(
3982 				"DC:failed to create hw i2c!!\n");
3983 			goto create_fail;
3984 		}
3985 		pool->base.sw_i2cs[i] = NULL;
3986 	}
3987 
3988 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
3989 		pool->base.opps[i] = dcn20_opp_create(ctx, i);
3990 		if (pool->base.opps[i] == NULL) {
3991 			BREAK_TO_DEBUGGER();
3992 			dm_error(
3993 				"DC: failed to create output pixel processor!\n");
3994 			goto create_fail;
3995 		}
3996 	}
3997 
3998 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
3999 		pool->base.timing_generators[i] = dcn20_timing_generator_create(
4000 				ctx, i);
4001 		if (pool->base.timing_generators[i] == NULL) {
4002 			BREAK_TO_DEBUGGER();
4003 			dm_error("DC: failed to create tg!\n");
4004 			goto create_fail;
4005 		}
4006 	}
4007 
4008 	pool->base.timing_generator_count = i;
4009 
4010 	pool->base.mpc = dcn20_mpc_create(ctx);
4011 	if (pool->base.mpc == NULL) {
4012 		BREAK_TO_DEBUGGER();
4013 		dm_error("DC: failed to create mpc!\n");
4014 		goto create_fail;
4015 	}
4016 
4017 	pool->base.hubbub = dcn20_hubbub_create(ctx);
4018 	if (pool->base.hubbub == NULL) {
4019 		BREAK_TO_DEBUGGER();
4020 		dm_error("DC: failed to create hubbub!\n");
4021 		goto create_fail;
4022 	}
4023 
4024 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
4025 		pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
4026 		if (pool->base.dscs[i] == NULL) {
4027 			BREAK_TO_DEBUGGER();
4028 			dm_error("DC: failed to create display stream compressor %d!\n", i);
4029 			goto create_fail;
4030 		}
4031 	}
4032 
4033 	if (!dcn20_dwbc_create(ctx, &pool->base)) {
4034 		BREAK_TO_DEBUGGER();
4035 		dm_error("DC: failed to create dwbc!\n");
4036 		goto create_fail;
4037 	}
4038 	if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
4039 		BREAK_TO_DEBUGGER();
4040 		dm_error("DC: failed to create mcif_wb!\n");
4041 		goto create_fail;
4042 	}
4043 
4044 	if (!resource_construct(num_virtual_links, dc, &pool->base,
4045 			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
4046 			&res_create_funcs : &res_create_maximus_funcs)))
4047 			goto create_fail;
4048 
4049 	dcn20_hw_sequencer_construct(dc);
4050 
4051 	// IF NV12, set PG function pointer to NULL. It's not that
4052 	// PG isn't supported for NV12, it's that we don't want to
4053 	// program the registers because that will cause more power
4054 	// to be consumed. We could have created dcn20_init_hw to get
4055 	// the same effect by checking ASIC rev, but there was a
4056 	// request at some point to not check ASIC rev on hw sequencer.
4057 	if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
4058 		dc->hwseq->funcs.enable_power_gating_plane = NULL;
4059 		dc->debug.disable_dpp_power_gate = true;
4060 		dc->debug.disable_hubp_power_gate = true;
4061 	}
4062 
4063 
4064 	dc->caps.max_planes =  pool->base.pipe_count;
4065 
4066 	for (i = 0; i < dc->caps.max_planes; ++i)
4067 		dc->caps.planes[i] = plane_cap;
4068 
4069 	dc->cap_funcs = cap_funcs;
4070 
4071 	if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
4072 		ddc_init_data.ctx = dc->ctx;
4073 		ddc_init_data.link = NULL;
4074 		ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
4075 		ddc_init_data.id.enum_id = 0;
4076 		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
4077 		pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
4078 	} else {
4079 		pool->base.oem_device = NULL;
4080 	}
4081 
4082 	return true;
4083 
4084 create_fail:
4085 
4086 	dcn20_resource_destruct(pool);
4087 
4088 	return false;
4089 }
4090 
4091 struct resource_pool *dcn20_create_resource_pool(
4092 		const struct dc_init_data *init_data,
4093 		struct dc *dc)
4094 {
4095 	struct dcn20_resource_pool *pool =
4096 		kzalloc(sizeof(struct dcn20_resource_pool), GFP_ATOMIC);
4097 
4098 	if (!pool)
4099 		return NULL;
4100 
4101 	if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))
4102 		return &pool->base;
4103 
4104 	BREAK_TO_DEBUGGER();
4105 	kfree(pool);
4106 	return NULL;
4107 }
4108