1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * Copyright 2019 Raptor Engineering, LLC 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 #include "dc.h" 31 32 #include "dcn20_init.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dcn20/dcn20_resource.h" 37 38 #include "dcn10/dcn10_hubp.h" 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn20_hubbub.h" 41 #include "dcn20_mpc.h" 42 #include "dcn20_hubp.h" 43 #include "irq/dcn20/irq_service_dcn20.h" 44 #include "dcn20_dpp.h" 45 #include "dcn20_optc.h" 46 #include "dcn20_hwseq.h" 47 #include "dce110/dce110_hw_sequencer.h" 48 #include "dcn10/dcn10_resource.h" 49 #include "dcn20_opp.h" 50 51 #include "dcn20_dsc.h" 52 53 #include "dcn20_link_encoder.h" 54 #include "dcn20_stream_encoder.h" 55 #include "dce/dce_clock_source.h" 56 #include "dce/dce_audio.h" 57 #include "dce/dce_hwseq.h" 58 #include "virtual/virtual_stream_encoder.h" 59 #include "dce110/dce110_resource.h" 60 #include "dml/display_mode_vba.h" 61 #include "dcn20_dccg.h" 62 #include "dcn20_vmid.h" 63 #include "dc_link_ddc.h" 64 #include "dce/dce_panel_cntl.h" 65 66 #include "navi10_ip_offset.h" 67 68 #include "dcn/dcn_2_0_0_offset.h" 69 #include "dcn/dcn_2_0_0_sh_mask.h" 70 #include "dpcs/dpcs_2_0_0_offset.h" 71 #include "dpcs/dpcs_2_0_0_sh_mask.h" 72 73 #include "nbio/nbio_2_3_offset.h" 74 75 #include "dcn20/dcn20_dwb.h" 76 #include "dcn20/dcn20_mmhubbub.h" 77 78 #include "mmhub/mmhub_2_0_0_offset.h" 79 #include "mmhub/mmhub_2_0_0_sh_mask.h" 80 81 #include "reg_helper.h" 82 #include "dce/dce_abm.h" 83 #include "dce/dce_dmcu.h" 84 #include "dce/dce_aux.h" 85 #include "dce/dce_i2c.h" 86 #include "vm_helper.h" 87 88 #include "amdgpu_socbb.h" 89 90 #define DC_LOGGER_INIT(logger) 91 92 struct _vcs_dpi_ip_params_st dcn2_0_ip = { 93 .odm_capable = 1, 94 .gpuvm_enable = 0, 95 .hostvm_enable = 0, 96 .gpuvm_max_page_table_levels = 4, 97 .hostvm_max_page_table_levels = 4, 98 .hostvm_cached_page_table_levels = 0, 99 .pte_group_size_bytes = 2048, 100 .num_dsc = 6, 101 .rob_buffer_size_kbytes = 168, 102 .det_buffer_size_kbytes = 164, 103 .dpte_buffer_size_in_pte_reqs_luma = 84, 104 .pde_proc_buffer_size_64k_reqs = 48, 105 .dpp_output_buffer_pixels = 2560, 106 .opp_output_buffer_lines = 1, 107 .pixel_chunk_size_kbytes = 8, 108 .pte_chunk_size_kbytes = 2, 109 .meta_chunk_size_kbytes = 2, 110 .writeback_chunk_size_kbytes = 2, 111 .line_buffer_size_bits = 789504, 112 .is_line_buffer_bpp_fixed = 0, 113 .line_buffer_fixed_bpp = 0, 114 .dcc_supported = true, 115 .max_line_buffer_lines = 12, 116 .writeback_luma_buffer_size_kbytes = 12, 117 .writeback_chroma_buffer_size_kbytes = 8, 118 .writeback_chroma_line_buffer_width_pixels = 4, 119 .writeback_max_hscl_ratio = 1, 120 .writeback_max_vscl_ratio = 1, 121 .writeback_min_hscl_ratio = 1, 122 .writeback_min_vscl_ratio = 1, 123 .writeback_max_hscl_taps = 12, 124 .writeback_max_vscl_taps = 12, 125 .writeback_line_buffer_luma_buffer_size = 0, 126 .writeback_line_buffer_chroma_buffer_size = 14643, 127 .cursor_buffer_size = 8, 128 .cursor_chunk_size = 2, 129 .max_num_otg = 6, 130 .max_num_dpp = 6, 131 .max_num_wb = 1, 132 .max_dchub_pscl_bw_pix_per_clk = 4, 133 .max_pscl_lb_bw_pix_per_clk = 2, 134 .max_lb_vscl_bw_pix_per_clk = 4, 135 .max_vscl_hscl_bw_pix_per_clk = 4, 136 .max_hscl_ratio = 8, 137 .max_vscl_ratio = 8, 138 .hscl_mults = 4, 139 .vscl_mults = 4, 140 .max_hscl_taps = 8, 141 .max_vscl_taps = 8, 142 .dispclk_ramp_margin_percent = 1, 143 .underscan_factor = 1.10, 144 .min_vblank_lines = 32, // 145 .dppclk_delay_subtotal = 77, // 146 .dppclk_delay_scl_lb_only = 16, 147 .dppclk_delay_scl = 50, 148 .dppclk_delay_cnvc_formatter = 8, 149 .dppclk_delay_cnvc_cursor = 6, 150 .dispclk_delay_subtotal = 87, // 151 .dcfclk_cstate_latency = 10, // SRExitTime 152 .max_inter_dcn_tile_repeaters = 8, 153 154 .xfc_supported = true, 155 .xfc_fill_bw_overhead_percent = 10.0, 156 .xfc_fill_constant_bytes = 0, 157 .number_of_cursors = 1, 158 }; 159 160 static struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = { 161 .odm_capable = 1, 162 .gpuvm_enable = 0, 163 .hostvm_enable = 0, 164 .gpuvm_max_page_table_levels = 4, 165 .hostvm_max_page_table_levels = 4, 166 .hostvm_cached_page_table_levels = 0, 167 .num_dsc = 5, 168 .rob_buffer_size_kbytes = 168, 169 .det_buffer_size_kbytes = 164, 170 .dpte_buffer_size_in_pte_reqs_luma = 84, 171 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo 172 .dpp_output_buffer_pixels = 2560, 173 .opp_output_buffer_lines = 1, 174 .pixel_chunk_size_kbytes = 8, 175 .pte_enable = 1, 176 .max_page_table_levels = 4, 177 .pte_chunk_size_kbytes = 2, 178 .meta_chunk_size_kbytes = 2, 179 .writeback_chunk_size_kbytes = 2, 180 .line_buffer_size_bits = 789504, 181 .is_line_buffer_bpp_fixed = 0, 182 .line_buffer_fixed_bpp = 0, 183 .dcc_supported = true, 184 .max_line_buffer_lines = 12, 185 .writeback_luma_buffer_size_kbytes = 12, 186 .writeback_chroma_buffer_size_kbytes = 8, 187 .writeback_chroma_line_buffer_width_pixels = 4, 188 .writeback_max_hscl_ratio = 1, 189 .writeback_max_vscl_ratio = 1, 190 .writeback_min_hscl_ratio = 1, 191 .writeback_min_vscl_ratio = 1, 192 .writeback_max_hscl_taps = 12, 193 .writeback_max_vscl_taps = 12, 194 .writeback_line_buffer_luma_buffer_size = 0, 195 .writeback_line_buffer_chroma_buffer_size = 14643, 196 .cursor_buffer_size = 8, 197 .cursor_chunk_size = 2, 198 .max_num_otg = 5, 199 .max_num_dpp = 5, 200 .max_num_wb = 1, 201 .max_dchub_pscl_bw_pix_per_clk = 4, 202 .max_pscl_lb_bw_pix_per_clk = 2, 203 .max_lb_vscl_bw_pix_per_clk = 4, 204 .max_vscl_hscl_bw_pix_per_clk = 4, 205 .max_hscl_ratio = 8, 206 .max_vscl_ratio = 8, 207 .hscl_mults = 4, 208 .vscl_mults = 4, 209 .max_hscl_taps = 8, 210 .max_vscl_taps = 8, 211 .dispclk_ramp_margin_percent = 1, 212 .underscan_factor = 1.10, 213 .min_vblank_lines = 32, // 214 .dppclk_delay_subtotal = 77, // 215 .dppclk_delay_scl_lb_only = 16, 216 .dppclk_delay_scl = 50, 217 .dppclk_delay_cnvc_formatter = 8, 218 .dppclk_delay_cnvc_cursor = 6, 219 .dispclk_delay_subtotal = 87, // 220 .dcfclk_cstate_latency = 10, // SRExitTime 221 .max_inter_dcn_tile_repeaters = 8, 222 .xfc_supported = true, 223 .xfc_fill_bw_overhead_percent = 10.0, 224 .xfc_fill_constant_bytes = 0, 225 .ptoi_supported = 0, 226 .number_of_cursors = 1, 227 }; 228 229 static struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { 230 /* Defaults that get patched on driver load from firmware. */ 231 .clock_limits = { 232 { 233 .state = 0, 234 .dcfclk_mhz = 560.0, 235 .fabricclk_mhz = 560.0, 236 .dispclk_mhz = 513.0, 237 .dppclk_mhz = 513.0, 238 .phyclk_mhz = 540.0, 239 .socclk_mhz = 560.0, 240 .dscclk_mhz = 171.0, 241 .dram_speed_mts = 8960.0, 242 }, 243 { 244 .state = 1, 245 .dcfclk_mhz = 694.0, 246 .fabricclk_mhz = 694.0, 247 .dispclk_mhz = 642.0, 248 .dppclk_mhz = 642.0, 249 .phyclk_mhz = 600.0, 250 .socclk_mhz = 694.0, 251 .dscclk_mhz = 214.0, 252 .dram_speed_mts = 11104.0, 253 }, 254 { 255 .state = 2, 256 .dcfclk_mhz = 875.0, 257 .fabricclk_mhz = 875.0, 258 .dispclk_mhz = 734.0, 259 .dppclk_mhz = 734.0, 260 .phyclk_mhz = 810.0, 261 .socclk_mhz = 875.0, 262 .dscclk_mhz = 245.0, 263 .dram_speed_mts = 14000.0, 264 }, 265 { 266 .state = 3, 267 .dcfclk_mhz = 1000.0, 268 .fabricclk_mhz = 1000.0, 269 .dispclk_mhz = 1100.0, 270 .dppclk_mhz = 1100.0, 271 .phyclk_mhz = 810.0, 272 .socclk_mhz = 1000.0, 273 .dscclk_mhz = 367.0, 274 .dram_speed_mts = 16000.0, 275 }, 276 { 277 .state = 4, 278 .dcfclk_mhz = 1200.0, 279 .fabricclk_mhz = 1200.0, 280 .dispclk_mhz = 1284.0, 281 .dppclk_mhz = 1284.0, 282 .phyclk_mhz = 810.0, 283 .socclk_mhz = 1200.0, 284 .dscclk_mhz = 428.0, 285 .dram_speed_mts = 16000.0, 286 }, 287 /*Extra state, no dispclk ramping*/ 288 { 289 .state = 5, 290 .dcfclk_mhz = 1200.0, 291 .fabricclk_mhz = 1200.0, 292 .dispclk_mhz = 1284.0, 293 .dppclk_mhz = 1284.0, 294 .phyclk_mhz = 810.0, 295 .socclk_mhz = 1200.0, 296 .dscclk_mhz = 428.0, 297 .dram_speed_mts = 16000.0, 298 }, 299 }, 300 .num_states = 5, 301 .sr_exit_time_us = 8.6, 302 .sr_enter_plus_exit_time_us = 10.9, 303 .urgent_latency_us = 4.0, 304 .urgent_latency_pixel_data_only_us = 4.0, 305 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 306 .urgent_latency_vm_data_only_us = 4.0, 307 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 308 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 309 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 310 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0, 311 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0, 312 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 313 .max_avg_sdp_bw_use_normal_percent = 40.0, 314 .max_avg_dram_bw_use_normal_percent = 40.0, 315 .writeback_latency_us = 12.0, 316 .ideal_dram_bw_after_urgent_percent = 40.0, 317 .max_request_size_bytes = 256, 318 .dram_channel_width_bytes = 2, 319 .fabric_datapath_to_dcn_data_return_bytes = 64, 320 .dcn_downspread_percent = 0.5, 321 .downspread_percent = 0.38, 322 .dram_page_open_time_ns = 50.0, 323 .dram_rw_turnaround_time_ns = 17.5, 324 .dram_return_buffer_per_channel_bytes = 8192, 325 .round_trip_ping_latency_dcfclk_cycles = 131, 326 .urgent_out_of_order_return_per_channel_bytes = 256, 327 .channel_interleave_bytes = 256, 328 .num_banks = 8, 329 .num_chans = 16, 330 .vmm_page_size_bytes = 4096, 331 .dram_clock_change_latency_us = 404.0, 332 .dummy_pstate_latency_us = 5.0, 333 .writeback_dram_clock_change_latency_us = 23.0, 334 .return_bus_width_bytes = 64, 335 .dispclk_dppclk_vco_speed_mhz = 3850, 336 .xfc_bus_transport_time_us = 20, 337 .xfc_xbuf_latency_tolerance_us = 4, 338 .use_urgent_burst_bw = 0 339 }; 340 341 static struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = { 342 .clock_limits = { 343 { 344 .state = 0, 345 .dcfclk_mhz = 560.0, 346 .fabricclk_mhz = 560.0, 347 .dispclk_mhz = 513.0, 348 .dppclk_mhz = 513.0, 349 .phyclk_mhz = 540.0, 350 .socclk_mhz = 560.0, 351 .dscclk_mhz = 171.0, 352 .dram_speed_mts = 8960.0, 353 }, 354 { 355 .state = 1, 356 .dcfclk_mhz = 694.0, 357 .fabricclk_mhz = 694.0, 358 .dispclk_mhz = 642.0, 359 .dppclk_mhz = 642.0, 360 .phyclk_mhz = 600.0, 361 .socclk_mhz = 694.0, 362 .dscclk_mhz = 214.0, 363 .dram_speed_mts = 11104.0, 364 }, 365 { 366 .state = 2, 367 .dcfclk_mhz = 875.0, 368 .fabricclk_mhz = 875.0, 369 .dispclk_mhz = 734.0, 370 .dppclk_mhz = 734.0, 371 .phyclk_mhz = 810.0, 372 .socclk_mhz = 875.0, 373 .dscclk_mhz = 245.0, 374 .dram_speed_mts = 14000.0, 375 }, 376 { 377 .state = 3, 378 .dcfclk_mhz = 1000.0, 379 .fabricclk_mhz = 1000.0, 380 .dispclk_mhz = 1100.0, 381 .dppclk_mhz = 1100.0, 382 .phyclk_mhz = 810.0, 383 .socclk_mhz = 1000.0, 384 .dscclk_mhz = 367.0, 385 .dram_speed_mts = 16000.0, 386 }, 387 { 388 .state = 4, 389 .dcfclk_mhz = 1200.0, 390 .fabricclk_mhz = 1200.0, 391 .dispclk_mhz = 1284.0, 392 .dppclk_mhz = 1284.0, 393 .phyclk_mhz = 810.0, 394 .socclk_mhz = 1200.0, 395 .dscclk_mhz = 428.0, 396 .dram_speed_mts = 16000.0, 397 }, 398 /*Extra state, no dispclk ramping*/ 399 { 400 .state = 5, 401 .dcfclk_mhz = 1200.0, 402 .fabricclk_mhz = 1200.0, 403 .dispclk_mhz = 1284.0, 404 .dppclk_mhz = 1284.0, 405 .phyclk_mhz = 810.0, 406 .socclk_mhz = 1200.0, 407 .dscclk_mhz = 428.0, 408 .dram_speed_mts = 16000.0, 409 }, 410 }, 411 .num_states = 5, 412 .sr_exit_time_us = 8.6, 413 .sr_enter_plus_exit_time_us = 10.9, 414 .urgent_latency_us = 4.0, 415 .urgent_latency_pixel_data_only_us = 4.0, 416 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 417 .urgent_latency_vm_data_only_us = 4.0, 418 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 419 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 420 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 421 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0, 422 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0, 423 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 424 .max_avg_sdp_bw_use_normal_percent = 40.0, 425 .max_avg_dram_bw_use_normal_percent = 40.0, 426 .writeback_latency_us = 12.0, 427 .ideal_dram_bw_after_urgent_percent = 40.0, 428 .max_request_size_bytes = 256, 429 .dram_channel_width_bytes = 2, 430 .fabric_datapath_to_dcn_data_return_bytes = 64, 431 .dcn_downspread_percent = 0.5, 432 .downspread_percent = 0.38, 433 .dram_page_open_time_ns = 50.0, 434 .dram_rw_turnaround_time_ns = 17.5, 435 .dram_return_buffer_per_channel_bytes = 8192, 436 .round_trip_ping_latency_dcfclk_cycles = 131, 437 .urgent_out_of_order_return_per_channel_bytes = 256, 438 .channel_interleave_bytes = 256, 439 .num_banks = 8, 440 .num_chans = 8, 441 .vmm_page_size_bytes = 4096, 442 .dram_clock_change_latency_us = 404.0, 443 .dummy_pstate_latency_us = 5.0, 444 .writeback_dram_clock_change_latency_us = 23.0, 445 .return_bus_width_bytes = 64, 446 .dispclk_dppclk_vco_speed_mhz = 3850, 447 .xfc_bus_transport_time_us = 20, 448 .xfc_xbuf_latency_tolerance_us = 4, 449 .use_urgent_burst_bw = 0 450 }; 451 452 static struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 }; 453 454 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 455 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 456 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 457 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 458 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 459 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 460 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 461 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 462 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 463 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 464 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 465 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 466 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 467 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 468 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 469 #endif 470 471 472 enum dcn20_clk_src_array_id { 473 DCN20_CLK_SRC_PLL0, 474 DCN20_CLK_SRC_PLL1, 475 DCN20_CLK_SRC_PLL2, 476 DCN20_CLK_SRC_PLL3, 477 DCN20_CLK_SRC_PLL4, 478 DCN20_CLK_SRC_PLL5, 479 DCN20_CLK_SRC_TOTAL 480 }; 481 482 /* begin ********************* 483 * macros to expend register list macro defined in HW object header file */ 484 485 /* DCN */ 486 /* TODO awful hack. fixup dcn20_dwb.h */ 487 #undef BASE_INNER 488 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 489 490 #define BASE(seg) BASE_INNER(seg) 491 492 #define SR(reg_name)\ 493 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 494 mm ## reg_name 495 496 #define SRI(reg_name, block, id)\ 497 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 498 mm ## block ## id ## _ ## reg_name 499 500 #define SRIR(var_name, reg_name, block, id)\ 501 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 502 mm ## block ## id ## _ ## reg_name 503 504 #define SRII(reg_name, block, id)\ 505 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 506 mm ## block ## id ## _ ## reg_name 507 508 #define DCCG_SRII(reg_name, block, id)\ 509 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 510 mm ## block ## id ## _ ## reg_name 511 512 #define VUPDATE_SRII(reg_name, block, id)\ 513 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 514 mm ## reg_name ## _ ## block ## id 515 516 /* NBIO */ 517 #define NBIO_BASE_INNER(seg) \ 518 NBIO_BASE__INST0_SEG ## seg 519 520 #define NBIO_BASE(seg) \ 521 NBIO_BASE_INNER(seg) 522 523 #define NBIO_SR(reg_name)\ 524 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 525 mm ## reg_name 526 527 /* MMHUB */ 528 #define MMHUB_BASE_INNER(seg) \ 529 MMHUB_BASE__INST0_SEG ## seg 530 531 #define MMHUB_BASE(seg) \ 532 MMHUB_BASE_INNER(seg) 533 534 #define MMHUB_SR(reg_name)\ 535 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 536 mmMM ## reg_name 537 538 static const struct bios_registers bios_regs = { 539 NBIO_SR(BIOS_SCRATCH_3), 540 NBIO_SR(BIOS_SCRATCH_6) 541 }; 542 543 #define clk_src_regs(index, pllid)\ 544 [index] = {\ 545 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\ 546 } 547 548 static const struct dce110_clk_src_regs clk_src_regs[] = { 549 clk_src_regs(0, A), 550 clk_src_regs(1, B), 551 clk_src_regs(2, C), 552 clk_src_regs(3, D), 553 clk_src_regs(4, E), 554 clk_src_regs(5, F) 555 }; 556 557 static const struct dce110_clk_src_shift cs_shift = { 558 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 559 }; 560 561 static const struct dce110_clk_src_mask cs_mask = { 562 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 563 }; 564 565 static const struct dce_dmcu_registers dmcu_regs = { 566 DMCU_DCN10_REG_LIST() 567 }; 568 569 static const struct dce_dmcu_shift dmcu_shift = { 570 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 571 }; 572 573 static const struct dce_dmcu_mask dmcu_mask = { 574 DMCU_MASK_SH_LIST_DCN10(_MASK) 575 }; 576 577 static const struct dce_abm_registers abm_regs = { 578 ABM_DCN20_REG_LIST() 579 }; 580 581 static const struct dce_abm_shift abm_shift = { 582 ABM_MASK_SH_LIST_DCN20(__SHIFT) 583 }; 584 585 static const struct dce_abm_mask abm_mask = { 586 ABM_MASK_SH_LIST_DCN20(_MASK) 587 }; 588 589 #define audio_regs(id)\ 590 [id] = {\ 591 AUD_COMMON_REG_LIST(id)\ 592 } 593 594 static const struct dce_audio_registers audio_regs[] = { 595 audio_regs(0), 596 audio_regs(1), 597 audio_regs(2), 598 audio_regs(3), 599 audio_regs(4), 600 audio_regs(5), 601 audio_regs(6), 602 }; 603 604 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 605 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 606 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 607 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 608 609 static const struct dce_audio_shift audio_shift = { 610 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 611 }; 612 613 static const struct dce_audio_mask audio_mask = { 614 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 615 }; 616 617 #define stream_enc_regs(id)\ 618 [id] = {\ 619 SE_DCN2_REG_LIST(id)\ 620 } 621 622 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 623 stream_enc_regs(0), 624 stream_enc_regs(1), 625 stream_enc_regs(2), 626 stream_enc_regs(3), 627 stream_enc_regs(4), 628 stream_enc_regs(5), 629 }; 630 631 static const struct dcn10_stream_encoder_shift se_shift = { 632 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) 633 }; 634 635 static const struct dcn10_stream_encoder_mask se_mask = { 636 SE_COMMON_MASK_SH_LIST_DCN20(_MASK) 637 }; 638 639 640 #define aux_regs(id)\ 641 [id] = {\ 642 DCN2_AUX_REG_LIST(id)\ 643 } 644 645 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 646 aux_regs(0), 647 aux_regs(1), 648 aux_regs(2), 649 aux_regs(3), 650 aux_regs(4), 651 aux_regs(5) 652 }; 653 654 #define hpd_regs(id)\ 655 [id] = {\ 656 HPD_REG_LIST(id)\ 657 } 658 659 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 660 hpd_regs(0), 661 hpd_regs(1), 662 hpd_regs(2), 663 hpd_regs(3), 664 hpd_regs(4), 665 hpd_regs(5) 666 }; 667 668 #define link_regs(id, phyid)\ 669 [id] = {\ 670 LE_DCN10_REG_LIST(id), \ 671 UNIPHY_DCN2_REG_LIST(phyid), \ 672 DPCS_DCN2_REG_LIST(id), \ 673 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 674 } 675 676 static const struct dcn10_link_enc_registers link_enc_regs[] = { 677 link_regs(0, A), 678 link_regs(1, B), 679 link_regs(2, C), 680 link_regs(3, D), 681 link_regs(4, E), 682 link_regs(5, F) 683 }; 684 685 static const struct dcn10_link_enc_shift le_shift = { 686 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\ 687 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 688 }; 689 690 static const struct dcn10_link_enc_mask le_mask = { 691 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\ 692 DPCS_DCN2_MASK_SH_LIST(_MASK) 693 }; 694 695 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 696 { DCN_PANEL_CNTL_REG_LIST() } 697 }; 698 699 static const struct dce_panel_cntl_shift panel_cntl_shift = { 700 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 701 }; 702 703 static const struct dce_panel_cntl_mask panel_cntl_mask = { 704 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 705 }; 706 707 #define ipp_regs(id)\ 708 [id] = {\ 709 IPP_REG_LIST_DCN20(id),\ 710 } 711 712 static const struct dcn10_ipp_registers ipp_regs[] = { 713 ipp_regs(0), 714 ipp_regs(1), 715 ipp_regs(2), 716 ipp_regs(3), 717 ipp_regs(4), 718 ipp_regs(5), 719 }; 720 721 static const struct dcn10_ipp_shift ipp_shift = { 722 IPP_MASK_SH_LIST_DCN20(__SHIFT) 723 }; 724 725 static const struct dcn10_ipp_mask ipp_mask = { 726 IPP_MASK_SH_LIST_DCN20(_MASK), 727 }; 728 729 #define opp_regs(id)\ 730 [id] = {\ 731 OPP_REG_LIST_DCN20(id),\ 732 } 733 734 static const struct dcn20_opp_registers opp_regs[] = { 735 opp_regs(0), 736 opp_regs(1), 737 opp_regs(2), 738 opp_regs(3), 739 opp_regs(4), 740 opp_regs(5), 741 }; 742 743 static const struct dcn20_opp_shift opp_shift = { 744 OPP_MASK_SH_LIST_DCN20(__SHIFT) 745 }; 746 747 static const struct dcn20_opp_mask opp_mask = { 748 OPP_MASK_SH_LIST_DCN20(_MASK) 749 }; 750 751 #define aux_engine_regs(id)\ 752 [id] = {\ 753 AUX_COMMON_REG_LIST0(id), \ 754 .AUXN_IMPCAL = 0, \ 755 .AUXP_IMPCAL = 0, \ 756 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 757 } 758 759 static const struct dce110_aux_registers aux_engine_regs[] = { 760 aux_engine_regs(0), 761 aux_engine_regs(1), 762 aux_engine_regs(2), 763 aux_engine_regs(3), 764 aux_engine_regs(4), 765 aux_engine_regs(5) 766 }; 767 768 #define tf_regs(id)\ 769 [id] = {\ 770 TF_REG_LIST_DCN20(id),\ 771 TF_REG_LIST_DCN20_COMMON_APPEND(id),\ 772 } 773 774 static const struct dcn2_dpp_registers tf_regs[] = { 775 tf_regs(0), 776 tf_regs(1), 777 tf_regs(2), 778 tf_regs(3), 779 tf_regs(4), 780 tf_regs(5), 781 }; 782 783 static const struct dcn2_dpp_shift tf_shift = { 784 TF_REG_LIST_SH_MASK_DCN20(__SHIFT), 785 TF_DEBUG_REG_LIST_SH_DCN20 786 }; 787 788 static const struct dcn2_dpp_mask tf_mask = { 789 TF_REG_LIST_SH_MASK_DCN20(_MASK), 790 TF_DEBUG_REG_LIST_MASK_DCN20 791 }; 792 793 #define dwbc_regs_dcn2(id)\ 794 [id] = {\ 795 DWBC_COMMON_REG_LIST_DCN2_0(id),\ 796 } 797 798 static const struct dcn20_dwbc_registers dwbc20_regs[] = { 799 dwbc_regs_dcn2(0), 800 }; 801 802 static const struct dcn20_dwbc_shift dwbc20_shift = { 803 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 804 }; 805 806 static const struct dcn20_dwbc_mask dwbc20_mask = { 807 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 808 }; 809 810 #define mcif_wb_regs_dcn2(id)\ 811 [id] = {\ 812 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\ 813 } 814 815 static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = { 816 mcif_wb_regs_dcn2(0), 817 }; 818 819 static const struct dcn20_mmhubbub_shift mcif_wb20_shift = { 820 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 821 }; 822 823 static const struct dcn20_mmhubbub_mask mcif_wb20_mask = { 824 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 825 }; 826 827 static const struct dcn20_mpc_registers mpc_regs = { 828 MPC_REG_LIST_DCN2_0(0), 829 MPC_REG_LIST_DCN2_0(1), 830 MPC_REG_LIST_DCN2_0(2), 831 MPC_REG_LIST_DCN2_0(3), 832 MPC_REG_LIST_DCN2_0(4), 833 MPC_REG_LIST_DCN2_0(5), 834 MPC_OUT_MUX_REG_LIST_DCN2_0(0), 835 MPC_OUT_MUX_REG_LIST_DCN2_0(1), 836 MPC_OUT_MUX_REG_LIST_DCN2_0(2), 837 MPC_OUT_MUX_REG_LIST_DCN2_0(3), 838 MPC_OUT_MUX_REG_LIST_DCN2_0(4), 839 MPC_OUT_MUX_REG_LIST_DCN2_0(5), 840 MPC_DBG_REG_LIST_DCN2_0() 841 }; 842 843 static const struct dcn20_mpc_shift mpc_shift = { 844 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT), 845 MPC_DEBUG_REG_LIST_SH_DCN20 846 }; 847 848 static const struct dcn20_mpc_mask mpc_mask = { 849 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK), 850 MPC_DEBUG_REG_LIST_MASK_DCN20 851 }; 852 853 #define tg_regs(id)\ 854 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)} 855 856 857 static const struct dcn_optc_registers tg_regs[] = { 858 tg_regs(0), 859 tg_regs(1), 860 tg_regs(2), 861 tg_regs(3), 862 tg_regs(4), 863 tg_regs(5) 864 }; 865 866 static const struct dcn_optc_shift tg_shift = { 867 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 868 }; 869 870 static const struct dcn_optc_mask tg_mask = { 871 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 872 }; 873 874 #define hubp_regs(id)\ 875 [id] = {\ 876 HUBP_REG_LIST_DCN20(id)\ 877 } 878 879 static const struct dcn_hubp2_registers hubp_regs[] = { 880 hubp_regs(0), 881 hubp_regs(1), 882 hubp_regs(2), 883 hubp_regs(3), 884 hubp_regs(4), 885 hubp_regs(5) 886 }; 887 888 static const struct dcn_hubp2_shift hubp_shift = { 889 HUBP_MASK_SH_LIST_DCN20(__SHIFT) 890 }; 891 892 static const struct dcn_hubp2_mask hubp_mask = { 893 HUBP_MASK_SH_LIST_DCN20(_MASK) 894 }; 895 896 static const struct dcn_hubbub_registers hubbub_reg = { 897 HUBBUB_REG_LIST_DCN20(0) 898 }; 899 900 static const struct dcn_hubbub_shift hubbub_shift = { 901 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT) 902 }; 903 904 static const struct dcn_hubbub_mask hubbub_mask = { 905 HUBBUB_MASK_SH_LIST_DCN20(_MASK) 906 }; 907 908 #define vmid_regs(id)\ 909 [id] = {\ 910 DCN20_VMID_REG_LIST(id)\ 911 } 912 913 static const struct dcn_vmid_registers vmid_regs[] = { 914 vmid_regs(0), 915 vmid_regs(1), 916 vmid_regs(2), 917 vmid_regs(3), 918 vmid_regs(4), 919 vmid_regs(5), 920 vmid_regs(6), 921 vmid_regs(7), 922 vmid_regs(8), 923 vmid_regs(9), 924 vmid_regs(10), 925 vmid_regs(11), 926 vmid_regs(12), 927 vmid_regs(13), 928 vmid_regs(14), 929 vmid_regs(15) 930 }; 931 932 static const struct dcn20_vmid_shift vmid_shifts = { 933 DCN20_VMID_MASK_SH_LIST(__SHIFT) 934 }; 935 936 static const struct dcn20_vmid_mask vmid_masks = { 937 DCN20_VMID_MASK_SH_LIST(_MASK) 938 }; 939 940 static const struct dce110_aux_registers_shift aux_shift = { 941 DCN_AUX_MASK_SH_LIST(__SHIFT) 942 }; 943 944 static const struct dce110_aux_registers_mask aux_mask = { 945 DCN_AUX_MASK_SH_LIST(_MASK) 946 }; 947 948 static int map_transmitter_id_to_phy_instance( 949 enum transmitter transmitter) 950 { 951 switch (transmitter) { 952 case TRANSMITTER_UNIPHY_A: 953 return 0; 954 break; 955 case TRANSMITTER_UNIPHY_B: 956 return 1; 957 break; 958 case TRANSMITTER_UNIPHY_C: 959 return 2; 960 break; 961 case TRANSMITTER_UNIPHY_D: 962 return 3; 963 break; 964 case TRANSMITTER_UNIPHY_E: 965 return 4; 966 break; 967 case TRANSMITTER_UNIPHY_F: 968 return 5; 969 break; 970 default: 971 ASSERT(0); 972 return 0; 973 } 974 } 975 976 #define dsc_regsDCN20(id)\ 977 [id] = {\ 978 DSC_REG_LIST_DCN20(id)\ 979 } 980 981 static const struct dcn20_dsc_registers dsc_regs[] = { 982 dsc_regsDCN20(0), 983 dsc_regsDCN20(1), 984 dsc_regsDCN20(2), 985 dsc_regsDCN20(3), 986 dsc_regsDCN20(4), 987 dsc_regsDCN20(5) 988 }; 989 990 static const struct dcn20_dsc_shift dsc_shift = { 991 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 992 }; 993 994 static const struct dcn20_dsc_mask dsc_mask = { 995 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 996 }; 997 998 static const struct dccg_registers dccg_regs = { 999 DCCG_REG_LIST_DCN2() 1000 }; 1001 1002 static const struct dccg_shift dccg_shift = { 1003 DCCG_MASK_SH_LIST_DCN2(__SHIFT) 1004 }; 1005 1006 static const struct dccg_mask dccg_mask = { 1007 DCCG_MASK_SH_LIST_DCN2(_MASK) 1008 }; 1009 1010 static const struct resource_caps res_cap_nv10 = { 1011 .num_timing_generator = 6, 1012 .num_opp = 6, 1013 .num_video_plane = 6, 1014 .num_audio = 7, 1015 .num_stream_encoder = 6, 1016 .num_pll = 6, 1017 .num_dwb = 1, 1018 .num_ddc = 6, 1019 .num_vmid = 16, 1020 .num_dsc = 6, 1021 }; 1022 1023 static const struct dc_plane_cap plane_cap = { 1024 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 1025 .blends_with_above = true, 1026 .blends_with_below = true, 1027 .per_pixel_alpha = true, 1028 1029 .pixel_format_support = { 1030 .argb8888 = true, 1031 .nv12 = true, 1032 .fp16 = true, 1033 .p010 = true 1034 }, 1035 1036 .max_upscale_factor = { 1037 .argb8888 = 16000, 1038 .nv12 = 16000, 1039 .fp16 = 1 1040 }, 1041 1042 .max_downscale_factor = { 1043 .argb8888 = 250, 1044 .nv12 = 250, 1045 .fp16 = 1 1046 }, 1047 16, 1048 16 1049 }; 1050 static const struct resource_caps res_cap_nv14 = { 1051 .num_timing_generator = 5, 1052 .num_opp = 5, 1053 .num_video_plane = 5, 1054 .num_audio = 6, 1055 .num_stream_encoder = 5, 1056 .num_pll = 5, 1057 .num_dwb = 1, 1058 .num_ddc = 5, 1059 .num_vmid = 16, 1060 .num_dsc = 5, 1061 }; 1062 1063 static const struct dc_debug_options debug_defaults_drv = { 1064 .disable_dmcu = false, 1065 .force_abm_enable = false, 1066 .timing_trace = false, 1067 .clock_trace = true, 1068 .disable_pplib_clock_request = true, 1069 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 1070 .force_single_disp_pipe_split = false, 1071 .disable_dcc = DCC_ENABLE, 1072 .vsr_support = true, 1073 .performance_trace = false, 1074 .max_downscale_src_width = 5120,/*upto 5K*/ 1075 .disable_pplib_wm_range = false, 1076 .scl_reset_length10 = true, 1077 .sanity_checks = false, 1078 .disable_tri_buf = true, 1079 .underflow_assert_delay_us = 0xFFFFFFFF, 1080 }; 1081 1082 static const struct dc_debug_options debug_defaults_diags = { 1083 .disable_dmcu = false, 1084 .force_abm_enable = false, 1085 .timing_trace = true, 1086 .clock_trace = true, 1087 .disable_dpp_power_gate = true, 1088 .disable_hubp_power_gate = true, 1089 .disable_clock_gate = true, 1090 .disable_pplib_clock_request = true, 1091 .disable_pplib_wm_range = true, 1092 .disable_stutter = true, 1093 .scl_reset_length10 = true, 1094 .underflow_assert_delay_us = 0xFFFFFFFF, 1095 }; 1096 1097 void dcn20_dpp_destroy(struct dpp **dpp) 1098 { 1099 kfree(TO_DCN20_DPP(*dpp)); 1100 *dpp = NULL; 1101 } 1102 1103 struct dpp *dcn20_dpp_create( 1104 struct dc_context *ctx, 1105 uint32_t inst) 1106 { 1107 struct dcn20_dpp *dpp = 1108 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL); 1109 1110 if (!dpp) 1111 return NULL; 1112 1113 if (dpp2_construct(dpp, ctx, inst, 1114 &tf_regs[inst], &tf_shift, &tf_mask)) 1115 return &dpp->base; 1116 1117 BREAK_TO_DEBUGGER(); 1118 kfree(dpp); 1119 return NULL; 1120 } 1121 1122 struct input_pixel_processor *dcn20_ipp_create( 1123 struct dc_context *ctx, uint32_t inst) 1124 { 1125 struct dcn10_ipp *ipp = 1126 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 1127 1128 if (!ipp) { 1129 BREAK_TO_DEBUGGER(); 1130 return NULL; 1131 } 1132 1133 dcn20_ipp_construct(ipp, ctx, inst, 1134 &ipp_regs[inst], &ipp_shift, &ipp_mask); 1135 return &ipp->base; 1136 } 1137 1138 1139 struct output_pixel_processor *dcn20_opp_create( 1140 struct dc_context *ctx, uint32_t inst) 1141 { 1142 struct dcn20_opp *opp = 1143 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1144 1145 if (!opp) { 1146 BREAK_TO_DEBUGGER(); 1147 return NULL; 1148 } 1149 1150 dcn20_opp_construct(opp, ctx, inst, 1151 &opp_regs[inst], &opp_shift, &opp_mask); 1152 return &opp->base; 1153 } 1154 1155 struct dce_aux *dcn20_aux_engine_create( 1156 struct dc_context *ctx, 1157 uint32_t inst) 1158 { 1159 struct aux_engine_dce110 *aux_engine = 1160 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 1161 1162 if (!aux_engine) 1163 return NULL; 1164 1165 dce110_aux_engine_construct(aux_engine, ctx, inst, 1166 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1167 &aux_engine_regs[inst], 1168 &aux_mask, 1169 &aux_shift, 1170 ctx->dc->caps.extended_aux_timeout_support); 1171 1172 return &aux_engine->base; 1173 } 1174 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 1175 1176 static const struct dce_i2c_registers i2c_hw_regs[] = { 1177 i2c_inst_regs(1), 1178 i2c_inst_regs(2), 1179 i2c_inst_regs(3), 1180 i2c_inst_regs(4), 1181 i2c_inst_regs(5), 1182 i2c_inst_regs(6), 1183 }; 1184 1185 static const struct dce_i2c_shift i2c_shifts = { 1186 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 1187 }; 1188 1189 static const struct dce_i2c_mask i2c_masks = { 1190 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 1191 }; 1192 1193 struct dce_i2c_hw *dcn20_i2c_hw_create( 1194 struct dc_context *ctx, 1195 uint32_t inst) 1196 { 1197 struct dce_i2c_hw *dce_i2c_hw = 1198 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1199 1200 if (!dce_i2c_hw) 1201 return NULL; 1202 1203 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1204 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1205 1206 return dce_i2c_hw; 1207 } 1208 struct mpc *dcn20_mpc_create(struct dc_context *ctx) 1209 { 1210 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), 1211 GFP_KERNEL); 1212 1213 if (!mpc20) 1214 return NULL; 1215 1216 dcn20_mpc_construct(mpc20, ctx, 1217 &mpc_regs, 1218 &mpc_shift, 1219 &mpc_mask, 1220 6); 1221 1222 return &mpc20->base; 1223 } 1224 1225 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx) 1226 { 1227 int i; 1228 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), 1229 GFP_KERNEL); 1230 1231 if (!hubbub) 1232 return NULL; 1233 1234 hubbub2_construct(hubbub, ctx, 1235 &hubbub_reg, 1236 &hubbub_shift, 1237 &hubbub_mask); 1238 1239 for (i = 0; i < res_cap_nv10.num_vmid; i++) { 1240 struct dcn20_vmid *vmid = &hubbub->vmid[i]; 1241 1242 vmid->ctx = ctx; 1243 1244 vmid->regs = &vmid_regs[i]; 1245 vmid->shifts = &vmid_shifts; 1246 vmid->masks = &vmid_masks; 1247 } 1248 1249 return &hubbub->base; 1250 } 1251 1252 struct timing_generator *dcn20_timing_generator_create( 1253 struct dc_context *ctx, 1254 uint32_t instance) 1255 { 1256 struct optc *tgn10 = 1257 kzalloc(sizeof(struct optc), GFP_KERNEL); 1258 1259 if (!tgn10) 1260 return NULL; 1261 1262 tgn10->base.inst = instance; 1263 tgn10->base.ctx = ctx; 1264 1265 tgn10->tg_regs = &tg_regs[instance]; 1266 tgn10->tg_shift = &tg_shift; 1267 tgn10->tg_mask = &tg_mask; 1268 1269 dcn20_timing_generator_init(tgn10); 1270 1271 return &tgn10->base; 1272 } 1273 1274 static const struct encoder_feature_support link_enc_feature = { 1275 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1276 .max_hdmi_pixel_clock = 600000, 1277 .hdmi_ycbcr420_supported = true, 1278 .dp_ycbcr420_supported = true, 1279 .fec_supported = true, 1280 .flags.bits.IS_HBR2_CAPABLE = true, 1281 .flags.bits.IS_HBR3_CAPABLE = true, 1282 .flags.bits.IS_TPS3_CAPABLE = true, 1283 .flags.bits.IS_TPS4_CAPABLE = true 1284 }; 1285 1286 struct link_encoder *dcn20_link_encoder_create( 1287 const struct encoder_init_data *enc_init_data) 1288 { 1289 struct dcn20_link_encoder *enc20 = 1290 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1291 int link_regs_id; 1292 1293 if (!enc20) 1294 return NULL; 1295 1296 link_regs_id = 1297 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 1298 1299 dcn20_link_encoder_construct(enc20, 1300 enc_init_data, 1301 &link_enc_feature, 1302 &link_enc_regs[link_regs_id], 1303 &link_enc_aux_regs[enc_init_data->channel - 1], 1304 &link_enc_hpd_regs[enc_init_data->hpd_source], 1305 &le_shift, 1306 &le_mask); 1307 1308 return &enc20->enc10.base; 1309 } 1310 1311 static struct panel_cntl *dcn20_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1312 { 1313 struct dce_panel_cntl *panel_cntl = 1314 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 1315 1316 if (!panel_cntl) 1317 return NULL; 1318 1319 dce_panel_cntl_construct(panel_cntl, 1320 init_data, 1321 &panel_cntl_regs[init_data->inst], 1322 &panel_cntl_shift, 1323 &panel_cntl_mask); 1324 1325 return &panel_cntl->base; 1326 } 1327 1328 static struct clock_source *dcn20_clock_source_create( 1329 struct dc_context *ctx, 1330 struct dc_bios *bios, 1331 enum clock_source_id id, 1332 const struct dce110_clk_src_regs *regs, 1333 bool dp_clk_src) 1334 { 1335 struct dce110_clk_src *clk_src = 1336 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1337 1338 if (!clk_src) 1339 return NULL; 1340 1341 if (dcn20_clk_src_construct(clk_src, ctx, bios, id, 1342 regs, &cs_shift, &cs_mask)) { 1343 clk_src->base.dp_clk_src = dp_clk_src; 1344 return &clk_src->base; 1345 } 1346 1347 kfree(clk_src); 1348 BREAK_TO_DEBUGGER(); 1349 return NULL; 1350 } 1351 1352 static void read_dce_straps( 1353 struct dc_context *ctx, 1354 struct resource_straps *straps) 1355 { 1356 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1357 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1358 } 1359 1360 static struct audio *dcn20_create_audio( 1361 struct dc_context *ctx, unsigned int inst) 1362 { 1363 return dce_audio_create(ctx, inst, 1364 &audio_regs[inst], &audio_shift, &audio_mask); 1365 } 1366 1367 struct stream_encoder *dcn20_stream_encoder_create( 1368 enum engine_id eng_id, 1369 struct dc_context *ctx) 1370 { 1371 struct dcn10_stream_encoder *enc1 = 1372 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1373 1374 if (!enc1) 1375 return NULL; 1376 1377 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) { 1378 if (eng_id >= ENGINE_ID_DIGD) 1379 eng_id++; 1380 } 1381 1382 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1383 &stream_enc_regs[eng_id], 1384 &se_shift, &se_mask); 1385 1386 return &enc1->base; 1387 } 1388 1389 static const struct dce_hwseq_registers hwseq_reg = { 1390 HWSEQ_DCN2_REG_LIST() 1391 }; 1392 1393 static const struct dce_hwseq_shift hwseq_shift = { 1394 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT) 1395 }; 1396 1397 static const struct dce_hwseq_mask hwseq_mask = { 1398 HWSEQ_DCN2_MASK_SH_LIST(_MASK) 1399 }; 1400 1401 struct dce_hwseq *dcn20_hwseq_create( 1402 struct dc_context *ctx) 1403 { 1404 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1405 1406 if (hws) { 1407 hws->ctx = ctx; 1408 hws->regs = &hwseq_reg; 1409 hws->shifts = &hwseq_shift; 1410 hws->masks = &hwseq_mask; 1411 } 1412 return hws; 1413 } 1414 1415 static const struct resource_create_funcs res_create_funcs = { 1416 .read_dce_straps = read_dce_straps, 1417 .create_audio = dcn20_create_audio, 1418 .create_stream_encoder = dcn20_stream_encoder_create, 1419 .create_hwseq = dcn20_hwseq_create, 1420 }; 1421 1422 static const struct resource_create_funcs res_create_maximus_funcs = { 1423 .read_dce_straps = NULL, 1424 .create_audio = NULL, 1425 .create_stream_encoder = NULL, 1426 .create_hwseq = dcn20_hwseq_create, 1427 }; 1428 1429 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu); 1430 1431 void dcn20_clock_source_destroy(struct clock_source **clk_src) 1432 { 1433 kfree(TO_DCE110_CLK_SRC(*clk_src)); 1434 *clk_src = NULL; 1435 } 1436 1437 1438 struct display_stream_compressor *dcn20_dsc_create( 1439 struct dc_context *ctx, uint32_t inst) 1440 { 1441 struct dcn20_dsc *dsc = 1442 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1443 1444 if (!dsc) { 1445 BREAK_TO_DEBUGGER(); 1446 return NULL; 1447 } 1448 1449 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1450 return &dsc->base; 1451 } 1452 1453 void dcn20_dsc_destroy(struct display_stream_compressor **dsc) 1454 { 1455 kfree(container_of(*dsc, struct dcn20_dsc, base)); 1456 *dsc = NULL; 1457 } 1458 1459 1460 static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) 1461 { 1462 unsigned int i; 1463 1464 for (i = 0; i < pool->base.stream_enc_count; i++) { 1465 if (pool->base.stream_enc[i] != NULL) { 1466 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1467 pool->base.stream_enc[i] = NULL; 1468 } 1469 } 1470 1471 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1472 if (pool->base.dscs[i] != NULL) 1473 dcn20_dsc_destroy(&pool->base.dscs[i]); 1474 } 1475 1476 if (pool->base.mpc != NULL) { 1477 kfree(TO_DCN20_MPC(pool->base.mpc)); 1478 pool->base.mpc = NULL; 1479 } 1480 if (pool->base.hubbub != NULL) { 1481 kfree(pool->base.hubbub); 1482 pool->base.hubbub = NULL; 1483 } 1484 for (i = 0; i < pool->base.pipe_count; i++) { 1485 if (pool->base.dpps[i] != NULL) 1486 dcn20_dpp_destroy(&pool->base.dpps[i]); 1487 1488 if (pool->base.ipps[i] != NULL) 1489 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1490 1491 if (pool->base.hubps[i] != NULL) { 1492 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1493 pool->base.hubps[i] = NULL; 1494 } 1495 1496 if (pool->base.irqs != NULL) { 1497 dal_irq_service_destroy(&pool->base.irqs); 1498 } 1499 } 1500 1501 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1502 if (pool->base.engines[i] != NULL) 1503 dce110_engine_destroy(&pool->base.engines[i]); 1504 if (pool->base.hw_i2cs[i] != NULL) { 1505 kfree(pool->base.hw_i2cs[i]); 1506 pool->base.hw_i2cs[i] = NULL; 1507 } 1508 if (pool->base.sw_i2cs[i] != NULL) { 1509 kfree(pool->base.sw_i2cs[i]); 1510 pool->base.sw_i2cs[i] = NULL; 1511 } 1512 } 1513 1514 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1515 if (pool->base.opps[i] != NULL) 1516 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1517 } 1518 1519 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1520 if (pool->base.timing_generators[i] != NULL) { 1521 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1522 pool->base.timing_generators[i] = NULL; 1523 } 1524 } 1525 1526 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1527 if (pool->base.dwbc[i] != NULL) { 1528 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); 1529 pool->base.dwbc[i] = NULL; 1530 } 1531 if (pool->base.mcif_wb[i] != NULL) { 1532 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); 1533 pool->base.mcif_wb[i] = NULL; 1534 } 1535 } 1536 1537 for (i = 0; i < pool->base.audio_count; i++) { 1538 if (pool->base.audios[i]) 1539 dce_aud_destroy(&pool->base.audios[i]); 1540 } 1541 1542 for (i = 0; i < pool->base.clk_src_count; i++) { 1543 if (pool->base.clock_sources[i] != NULL) { 1544 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1545 pool->base.clock_sources[i] = NULL; 1546 } 1547 } 1548 1549 if (pool->base.dp_clock_source != NULL) { 1550 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1551 pool->base.dp_clock_source = NULL; 1552 } 1553 1554 1555 if (pool->base.abm != NULL) 1556 dce_abm_destroy(&pool->base.abm); 1557 1558 if (pool->base.dmcu != NULL) 1559 dce_dmcu_destroy(&pool->base.dmcu); 1560 1561 if (pool->base.dccg != NULL) 1562 dcn_dccg_destroy(&pool->base.dccg); 1563 1564 if (pool->base.pp_smu != NULL) 1565 dcn20_pp_smu_destroy(&pool->base.pp_smu); 1566 1567 if (pool->base.oem_device != NULL) 1568 dal_ddc_service_destroy(&pool->base.oem_device); 1569 } 1570 1571 struct hubp *dcn20_hubp_create( 1572 struct dc_context *ctx, 1573 uint32_t inst) 1574 { 1575 struct dcn20_hubp *hubp2 = 1576 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1577 1578 if (!hubp2) 1579 return NULL; 1580 1581 if (hubp2_construct(hubp2, ctx, inst, 1582 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1583 return &hubp2->base; 1584 1585 BREAK_TO_DEBUGGER(); 1586 kfree(hubp2); 1587 return NULL; 1588 } 1589 1590 static void get_pixel_clock_parameters( 1591 struct pipe_ctx *pipe_ctx, 1592 struct pixel_clk_params *pixel_clk_params) 1593 { 1594 const struct dc_stream_state *stream = pipe_ctx->stream; 1595 struct pipe_ctx *odm_pipe; 1596 int opp_cnt = 1; 1597 1598 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1599 opp_cnt++; 1600 1601 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 1602 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 1603 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 1604 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 1605 /* TODO: un-hardcode*/ 1606 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 1607 LINK_RATE_REF_FREQ_IN_KHZ; 1608 pixel_clk_params->flags.ENABLE_SS = 0; 1609 pixel_clk_params->color_depth = 1610 stream->timing.display_color_depth; 1611 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 1612 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 1613 1614 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1615 pixel_clk_params->color_depth = COLOR_DEPTH_888; 1616 1617 if (opp_cnt == 4) 1618 pixel_clk_params->requested_pix_clk_100hz /= 4; 1619 else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2) 1620 pixel_clk_params->requested_pix_clk_100hz /= 2; 1621 1622 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1623 pixel_clk_params->requested_pix_clk_100hz *= 2; 1624 1625 } 1626 1627 static void build_clamping_params(struct dc_stream_state *stream) 1628 { 1629 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1630 stream->clamping.c_depth = stream->timing.display_color_depth; 1631 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1632 } 1633 1634 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1635 { 1636 1637 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1638 1639 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1640 pipe_ctx->clock_source, 1641 &pipe_ctx->stream_res.pix_clk_params, 1642 &pipe_ctx->pll_settings); 1643 1644 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1645 1646 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1647 &pipe_ctx->stream->bit_depth_params); 1648 build_clamping_params(pipe_ctx->stream); 1649 1650 return DC_OK; 1651 } 1652 1653 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream) 1654 { 1655 enum dc_status status = DC_OK; 1656 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1657 1658 if (!pipe_ctx) 1659 return DC_ERROR_UNEXPECTED; 1660 1661 1662 status = build_pipe_hw_param(pipe_ctx); 1663 1664 return status; 1665 } 1666 1667 1668 void dcn20_acquire_dsc(const struct dc *dc, 1669 struct resource_context *res_ctx, 1670 struct display_stream_compressor **dsc, 1671 int pipe_idx) 1672 { 1673 int i; 1674 const struct resource_pool *pool = dc->res_pool; 1675 struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc; 1676 1677 ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */ 1678 *dsc = NULL; 1679 1680 /* Always do 1-to-1 mapping when number of DSCs is same as number of pipes */ 1681 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { 1682 *dsc = pool->dscs[pipe_idx]; 1683 res_ctx->is_dsc_acquired[pipe_idx] = true; 1684 return; 1685 } 1686 1687 /* Return old DSC to avoid the need for re-programming */ 1688 if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) { 1689 *dsc = dsc_old; 1690 res_ctx->is_dsc_acquired[dsc_old->inst] = true; 1691 return ; 1692 } 1693 1694 /* Find first free DSC */ 1695 for (i = 0; i < pool->res_cap->num_dsc; i++) 1696 if (!res_ctx->is_dsc_acquired[i]) { 1697 *dsc = pool->dscs[i]; 1698 res_ctx->is_dsc_acquired[i] = true; 1699 break; 1700 } 1701 } 1702 1703 void dcn20_release_dsc(struct resource_context *res_ctx, 1704 const struct resource_pool *pool, 1705 struct display_stream_compressor **dsc) 1706 { 1707 int i; 1708 1709 for (i = 0; i < pool->res_cap->num_dsc; i++) 1710 if (pool->dscs[i] == *dsc) { 1711 res_ctx->is_dsc_acquired[i] = false; 1712 *dsc = NULL; 1713 break; 1714 } 1715 } 1716 1717 1718 1719 enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, 1720 struct dc_state *dc_ctx, 1721 struct dc_stream_state *dc_stream) 1722 { 1723 enum dc_status result = DC_OK; 1724 int i; 1725 1726 /* Get a DSC if required and available */ 1727 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1728 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i]; 1729 1730 if (pipe_ctx->stream != dc_stream) 1731 continue; 1732 1733 if (pipe_ctx->stream_res.dsc) 1734 continue; 1735 1736 dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i); 1737 1738 /* The number of DSCs can be less than the number of pipes */ 1739 if (!pipe_ctx->stream_res.dsc) { 1740 result = DC_NO_DSC_RESOURCE; 1741 } 1742 1743 break; 1744 } 1745 1746 return result; 1747 } 1748 1749 1750 static enum dc_status remove_dsc_from_stream_resource(struct dc *dc, 1751 struct dc_state *new_ctx, 1752 struct dc_stream_state *dc_stream) 1753 { 1754 struct pipe_ctx *pipe_ctx = NULL; 1755 int i; 1756 1757 for (i = 0; i < MAX_PIPES; i++) { 1758 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { 1759 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; 1760 1761 if (pipe_ctx->stream_res.dsc) 1762 dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); 1763 } 1764 } 1765 1766 if (!pipe_ctx) 1767 return DC_ERROR_UNEXPECTED; 1768 else 1769 return DC_OK; 1770 } 1771 1772 1773 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) 1774 { 1775 enum dc_status result = DC_ERROR_UNEXPECTED; 1776 1777 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1778 1779 if (result == DC_OK) 1780 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1781 1782 /* Get a DSC if required and available */ 1783 if (result == DC_OK && dc_stream->timing.flags.DSC) 1784 result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream); 1785 1786 if (result == DC_OK) 1787 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream); 1788 1789 return result; 1790 } 1791 1792 1793 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) 1794 { 1795 enum dc_status result = DC_OK; 1796 1797 result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream); 1798 1799 return result; 1800 } 1801 1802 1803 static void swizzle_to_dml_params( 1804 enum swizzle_mode_values swizzle, 1805 unsigned int *sw_mode) 1806 { 1807 switch (swizzle) { 1808 case DC_SW_LINEAR: 1809 *sw_mode = dm_sw_linear; 1810 break; 1811 case DC_SW_4KB_S: 1812 *sw_mode = dm_sw_4kb_s; 1813 break; 1814 case DC_SW_4KB_S_X: 1815 *sw_mode = dm_sw_4kb_s_x; 1816 break; 1817 case DC_SW_4KB_D: 1818 *sw_mode = dm_sw_4kb_d; 1819 break; 1820 case DC_SW_4KB_D_X: 1821 *sw_mode = dm_sw_4kb_d_x; 1822 break; 1823 case DC_SW_64KB_S: 1824 *sw_mode = dm_sw_64kb_s; 1825 break; 1826 case DC_SW_64KB_S_X: 1827 *sw_mode = dm_sw_64kb_s_x; 1828 break; 1829 case DC_SW_64KB_S_T: 1830 *sw_mode = dm_sw_64kb_s_t; 1831 break; 1832 case DC_SW_64KB_D: 1833 *sw_mode = dm_sw_64kb_d; 1834 break; 1835 case DC_SW_64KB_D_X: 1836 *sw_mode = dm_sw_64kb_d_x; 1837 break; 1838 case DC_SW_64KB_D_T: 1839 *sw_mode = dm_sw_64kb_d_t; 1840 break; 1841 case DC_SW_64KB_R_X: 1842 *sw_mode = dm_sw_64kb_r_x; 1843 break; 1844 case DC_SW_VAR_S: 1845 *sw_mode = dm_sw_var_s; 1846 break; 1847 case DC_SW_VAR_S_X: 1848 *sw_mode = dm_sw_var_s_x; 1849 break; 1850 case DC_SW_VAR_D: 1851 *sw_mode = dm_sw_var_d; 1852 break; 1853 case DC_SW_VAR_D_X: 1854 *sw_mode = dm_sw_var_d_x; 1855 break; 1856 1857 default: 1858 ASSERT(0); /* Not supported */ 1859 break; 1860 } 1861 } 1862 1863 bool dcn20_split_stream_for_odm( 1864 const struct dc *dc, 1865 struct resource_context *res_ctx, 1866 struct pipe_ctx *prev_odm_pipe, 1867 struct pipe_ctx *next_odm_pipe) 1868 { 1869 int pipe_idx = next_odm_pipe->pipe_idx; 1870 const struct resource_pool *pool = dc->res_pool; 1871 1872 *next_odm_pipe = *prev_odm_pipe; 1873 1874 next_odm_pipe->pipe_idx = pipe_idx; 1875 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; 1876 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; 1877 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; 1878 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; 1879 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; 1880 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; 1881 next_odm_pipe->stream_res.dsc = NULL; 1882 if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) { 1883 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe; 1884 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe; 1885 } 1886 prev_odm_pipe->next_odm_pipe = next_odm_pipe; 1887 next_odm_pipe->prev_odm_pipe = prev_odm_pipe; 1888 ASSERT(next_odm_pipe->top_pipe == NULL); 1889 1890 if (prev_odm_pipe->plane_state) { 1891 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; 1892 int new_width; 1893 1894 /* HACTIVE halved for odm combine */ 1895 sd->h_active /= 2; 1896 /* Calculate new vp and recout for left pipe */ 1897 /* Need at least 16 pixels width per side */ 1898 if (sd->recout.x + 16 >= sd->h_active) 1899 return false; 1900 new_width = sd->h_active - sd->recout.x; 1901 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1902 sd->ratios.horz, sd->recout.width - new_width)); 1903 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1904 sd->ratios.horz_c, sd->recout.width - new_width)); 1905 sd->recout.width = new_width; 1906 1907 /* Calculate new vp and recout for right pipe */ 1908 sd = &next_odm_pipe->plane_res.scl_data; 1909 /* HACTIVE halved for odm combine */ 1910 sd->h_active /= 2; 1911 /* Need at least 16 pixels width per side */ 1912 if (new_width <= 16) 1913 return false; 1914 new_width = sd->recout.width + sd->recout.x - sd->h_active; 1915 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1916 sd->ratios.horz, sd->recout.width - new_width)); 1917 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1918 sd->ratios.horz_c, sd->recout.width - new_width)); 1919 sd->recout.width = new_width; 1920 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int( 1921 sd->ratios.horz, sd->h_active - sd->recout.x)); 1922 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int( 1923 sd->ratios.horz_c, sd->h_active - sd->recout.x)); 1924 sd->recout.x = 0; 1925 } 1926 next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; 1927 if (next_odm_pipe->stream->timing.flags.DSC == 1) { 1928 dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx); 1929 ASSERT(next_odm_pipe->stream_res.dsc); 1930 if (next_odm_pipe->stream_res.dsc == NULL) 1931 return false; 1932 } 1933 1934 return true; 1935 } 1936 1937 void dcn20_split_stream_for_mpc( 1938 struct resource_context *res_ctx, 1939 const struct resource_pool *pool, 1940 struct pipe_ctx *primary_pipe, 1941 struct pipe_ctx *secondary_pipe) 1942 { 1943 int pipe_idx = secondary_pipe->pipe_idx; 1944 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe; 1945 1946 *secondary_pipe = *primary_pipe; 1947 secondary_pipe->bottom_pipe = sec_bot_pipe; 1948 1949 secondary_pipe->pipe_idx = pipe_idx; 1950 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; 1951 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; 1952 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; 1953 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; 1954 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; 1955 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; 1956 secondary_pipe->stream_res.dsc = NULL; 1957 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { 1958 ASSERT(!secondary_pipe->bottom_pipe); 1959 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; 1960 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe; 1961 } 1962 primary_pipe->bottom_pipe = secondary_pipe; 1963 secondary_pipe->top_pipe = primary_pipe; 1964 1965 ASSERT(primary_pipe->plane_state); 1966 } 1967 1968 void dcn20_populate_dml_writeback_from_context( 1969 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) 1970 { 1971 int pipe_cnt, i; 1972 1973 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1974 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; 1975 1976 if (!res_ctx->pipe_ctx[i].stream) 1977 continue; 1978 1979 /* Set writeback information */ 1980 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; 1981 pipes[pipe_cnt].dout.num_active_wb++; 1982 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; 1983 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; 1984 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; 1985 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; 1986 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1; 1987 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1; 1988 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c; 1989 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c; 1990 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0; 1991 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0; 1992 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) { 1993 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) 1994 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8; 1995 else 1996 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10; 1997 } else 1998 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32; 1999 2000 pipe_cnt++; 2001 } 2002 2003 } 2004 2005 int dcn20_populate_dml_pipes_from_context( 2006 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes) 2007 { 2008 int pipe_cnt, i; 2009 bool synchronized_vblank = true; 2010 struct resource_context *res_ctx = &context->res_ctx; 2011 2012 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) { 2013 if (!res_ctx->pipe_ctx[i].stream) 2014 continue; 2015 2016 if (pipe_cnt < 0) { 2017 pipe_cnt = i; 2018 continue; 2019 } 2020 2021 if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream) 2022 continue; 2023 2024 if (dc->debug.disable_timing_sync || !resource_are_streams_timing_synchronizable( 2025 res_ctx->pipe_ctx[pipe_cnt].stream, 2026 res_ctx->pipe_ctx[i].stream)) { 2027 synchronized_vblank = false; 2028 break; 2029 } 2030 } 2031 2032 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 2033 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing; 2034 unsigned int v_total; 2035 unsigned int front_porch; 2036 int output_bpc; 2037 2038 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 2039 struct audio_check aud_check = {0}; 2040 #endif 2041 if (!res_ctx->pipe_ctx[i].stream) 2042 continue; 2043 2044 v_total = timing->v_total; 2045 front_porch = timing->v_front_porch; 2046 /* todo: 2047 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0; 2048 pipes[pipe_cnt].pipe.src.dcc = 0; 2049 pipes[pipe_cnt].pipe.src.vm = 0;*/ 2050 2051 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 2052 2053 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC; 2054 /* todo: rotation?*/ 2055 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; 2056 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) { 2057 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true; 2058 /* 1/2 vblank */ 2059 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active = 2060 (v_total - timing->v_addressable 2061 - timing->v_border_top - timing->v_border_bottom) / 2; 2062 /* 36 bytes dp, 32 hdmi */ 2063 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes = 2064 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32; 2065 } 2066 pipes[pipe_cnt].pipe.src.dcc = false; 2067 pipes[pipe_cnt].pipe.src.dcc_rate = 1; 2068 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank; 2069 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch; 2070 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start 2071 - timing->h_addressable 2072 - timing->h_border_left 2073 - timing->h_border_right; 2074 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch; 2075 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start 2076 - timing->v_addressable 2077 - timing->v_border_top 2078 - timing->v_border_bottom; 2079 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total; 2080 pipes[pipe_cnt].pipe.dest.vtotal = v_total; 2081 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable; 2082 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable; 2083 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE; 2084 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0; 2085 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 2086 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2; 2087 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst; 2088 pipes[pipe_cnt].dout.dp_lanes = 4; 2089 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min; 2090 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max; 2091 switch (get_num_odm_splits(&res_ctx->pipe_ctx[i])) { 2092 case 1: 2093 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1; 2094 break; 2095 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 2096 case 3: 2097 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1; 2098 break; 2099 #endif 2100 default: 2101 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled; 2102 } 2103 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; 2104 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state 2105 == res_ctx->pipe_ctx[i].plane_state) { 2106 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe; 2107 int split_idx = 0; 2108 2109 while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state 2110 == res_ctx->pipe_ctx[i].plane_state) { 2111 first_pipe = first_pipe->top_pipe; 2112 split_idx++; 2113 } 2114 /* Treat 4to1 mpc combine as an mpo of 2 2-to-1 combines */ 2115 if (split_idx == 0) 2116 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx; 2117 else if (split_idx == 1) 2118 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; 2119 else if (split_idx == 2) 2120 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx; 2121 } else if (res_ctx->pipe_ctx[i].prev_odm_pipe) { 2122 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe; 2123 2124 while (first_pipe->prev_odm_pipe) 2125 first_pipe = first_pipe->prev_odm_pipe; 2126 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx; 2127 } 2128 2129 switch (res_ctx->pipe_ctx[i].stream->signal) { 2130 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2131 case SIGNAL_TYPE_DISPLAY_PORT: 2132 pipes[pipe_cnt].dout.output_type = dm_dp; 2133 break; 2134 case SIGNAL_TYPE_EDP: 2135 pipes[pipe_cnt].dout.output_type = dm_edp; 2136 break; 2137 case SIGNAL_TYPE_HDMI_TYPE_A: 2138 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2139 case SIGNAL_TYPE_DVI_DUAL_LINK: 2140 pipes[pipe_cnt].dout.output_type = dm_hdmi; 2141 break; 2142 default: 2143 /* In case there is no signal, set dp with 4 lanes to allow max config */ 2144 pipes[pipe_cnt].dout.output_type = dm_dp; 2145 pipes[pipe_cnt].dout.dp_lanes = 4; 2146 } 2147 2148 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) { 2149 case COLOR_DEPTH_666: 2150 output_bpc = 6; 2151 break; 2152 case COLOR_DEPTH_888: 2153 output_bpc = 8; 2154 break; 2155 case COLOR_DEPTH_101010: 2156 output_bpc = 10; 2157 break; 2158 case COLOR_DEPTH_121212: 2159 output_bpc = 12; 2160 break; 2161 case COLOR_DEPTH_141414: 2162 output_bpc = 14; 2163 break; 2164 case COLOR_DEPTH_161616: 2165 output_bpc = 16; 2166 break; 2167 case COLOR_DEPTH_999: 2168 output_bpc = 9; 2169 break; 2170 case COLOR_DEPTH_111111: 2171 output_bpc = 11; 2172 break; 2173 default: 2174 output_bpc = 8; 2175 break; 2176 } 2177 2178 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) { 2179 case PIXEL_ENCODING_RGB: 2180 case PIXEL_ENCODING_YCBCR444: 2181 pipes[pipe_cnt].dout.output_format = dm_444; 2182 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3; 2183 break; 2184 case PIXEL_ENCODING_YCBCR420: 2185 pipes[pipe_cnt].dout.output_format = dm_420; 2186 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2; 2187 break; 2188 case PIXEL_ENCODING_YCBCR422: 2189 if (true) /* todo */ 2190 pipes[pipe_cnt].dout.output_format = dm_s422; 2191 else 2192 pipes[pipe_cnt].dout.output_format = dm_n422; 2193 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2; 2194 break; 2195 default: 2196 pipes[pipe_cnt].dout.output_format = dm_444; 2197 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3; 2198 } 2199 2200 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC) 2201 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0; 2202 2203 /* todo: default max for now, until there is logic reflecting this in dc*/ 2204 pipes[pipe_cnt].dout.output_bpc = 12; 2205 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 2206 /*fill up the audio sample rate*/ 2207 get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check); 2208 pipes[pipe_cnt].dout.max_audio_sample_rate = aud_check.max_audiosample_rate; 2209 #endif 2210 /* 2211 * For graphic plane, cursor number is 1, nv12 is 0 2212 * bw calculations due to cursor on/off 2213 */ 2214 if (res_ctx->pipe_ctx[i].plane_state && 2215 res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 2216 pipes[pipe_cnt].pipe.src.num_cursors = 0; 2217 else 2218 pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors; 2219 2220 pipes[pipe_cnt].pipe.src.cur0_src_width = 256; 2221 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit; 2222 2223 if (!res_ctx->pipe_ctx[i].plane_state) { 2224 pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled; 2225 pipes[pipe_cnt].pipe.src.source_scan = dm_horz; 2226 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear; 2227 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile; 2228 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable; 2229 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920) 2230 pipes[pipe_cnt].pipe.src.viewport_width = 1920; 2231 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable; 2232 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080) 2233 pipes[pipe_cnt].pipe.src.viewport_height = 1080; 2234 pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height; 2235 pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width; 2236 pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height; 2237 pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width; 2238 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */ 2239 pipes[pipe_cnt].pipe.src.source_format = dm_444_32; 2240 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/ 2241 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/ 2242 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/ 2243 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/ 2244 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16; 2245 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0; 2246 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0; 2247 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/ 2248 pipes[pipe_cnt].pipe.scale_taps.htaps = 1; 2249 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1; 2250 pipes[pipe_cnt].pipe.dest.vtotal_min = v_total; 2251 pipes[pipe_cnt].pipe.dest.vtotal_max = v_total; 2252 2253 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) { 2254 pipes[pipe_cnt].pipe.src.viewport_width /= 2; 2255 pipes[pipe_cnt].pipe.dest.recout_width /= 2; 2256 } 2257 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 2258 else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) { 2259 pipes[pipe_cnt].pipe.src.viewport_width /= 4; 2260 pipes[pipe_cnt].pipe.dest.recout_width /= 4; 2261 } 2262 #endif 2263 } else { 2264 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state; 2265 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data; 2266 2267 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate; 2268 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) 2269 || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) 2270 || pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled; 2271 2272 /* stereo is not split */ 2273 if (pln->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE || 2274 pln->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) { 2275 pipes[pipe_cnt].pipe.src.is_hsplit = false; 2276 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; 2277 } 2278 2279 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90 2280 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz; 2281 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport_unadjusted.y; 2282 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c_unadjusted.y; 2283 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport_unadjusted.width; 2284 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c_unadjusted.width; 2285 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport_unadjusted.height; 2286 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c_unadjusted.height; 2287 pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width; 2288 pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height; 2289 pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width; 2290 pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height; 2291 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 2292 if (pln->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA 2293 || pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 2294 #else 2295 if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 2296 #endif 2297 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch; 2298 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch; 2299 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; 2300 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c; 2301 } else { 2302 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch; 2303 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; 2304 } 2305 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable; 2306 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width; 2307 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height; 2308 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height; 2309 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width; 2310 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) 2311 pipes[pipe_cnt].pipe.dest.full_recout_width *= 2; 2312 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 2313 else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) 2314 pipes[pipe_cnt].pipe.dest.full_recout_width *= 4; 2315 #endif 2316 else { 2317 struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe; 2318 2319 while (split_pipe && split_pipe->plane_state == pln) { 2320 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; 2321 split_pipe = split_pipe->bottom_pipe; 2322 } 2323 split_pipe = res_ctx->pipe_ctx[i].top_pipe; 2324 while (split_pipe && split_pipe->plane_state == pln) { 2325 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; 2326 split_pipe = split_pipe->top_pipe; 2327 } 2328 } 2329 2330 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16; 2331 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32); 2332 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32); 2333 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32); 2334 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32); 2335 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 2336 scl->ratios.vert.value != dc_fixpt_one.value 2337 || scl->ratios.horz.value != dc_fixpt_one.value 2338 || scl->ratios.vert_c.value != dc_fixpt_one.value 2339 || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/ 2340 || dc->debug.always_scale; /*support always scale*/ 2341 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps; 2342 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c; 2343 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps; 2344 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c; 2345 2346 pipes[pipe_cnt].pipe.src.macro_tile_size = 2347 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); 2348 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, 2349 &pipes[pipe_cnt].pipe.src.sw_mode); 2350 2351 switch (pln->format) { 2352 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 2353 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 2354 pipes[pipe_cnt].pipe.src.source_format = dm_420_8; 2355 break; 2356 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 2357 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 2358 pipes[pipe_cnt].pipe.src.source_format = dm_420_10; 2359 break; 2360 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 2361 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 2362 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2363 pipes[pipe_cnt].pipe.src.source_format = dm_444_64; 2364 break; 2365 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 2366 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 2367 pipes[pipe_cnt].pipe.src.source_format = dm_444_16; 2368 break; 2369 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 2370 pipes[pipe_cnt].pipe.src.source_format = dm_444_8; 2371 break; 2372 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 2373 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 2374 pipes[pipe_cnt].pipe.src.source_format = dm_rgbe_alpha; 2375 break; 2376 #endif 2377 default: 2378 pipes[pipe_cnt].pipe.src.source_format = dm_444_32; 2379 break; 2380 } 2381 } 2382 2383 pipe_cnt++; 2384 } 2385 2386 /* populate writeback information */ 2387 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes); 2388 2389 return pipe_cnt; 2390 } 2391 2392 unsigned int dcn20_calc_max_scaled_time( 2393 unsigned int time_per_pixel, 2394 enum mmhubbub_wbif_mode mode, 2395 unsigned int urgent_watermark) 2396 { 2397 unsigned int time_per_byte = 0; 2398 unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */ 2399 unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */ 2400 unsigned int small_free_entry, max_free_entry; 2401 unsigned int buf_lh_capability; 2402 unsigned int max_scaled_time; 2403 2404 if (mode == PACKED_444) /* packed mode */ 2405 time_per_byte = time_per_pixel/4; 2406 else if (mode == PLANAR_420_8BPC) 2407 time_per_byte = time_per_pixel; 2408 else if (mode == PLANAR_420_10BPC) /* p010 */ 2409 time_per_byte = time_per_pixel * 819/1024; 2410 2411 if (time_per_byte == 0) 2412 time_per_byte = 1; 2413 2414 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry; 2415 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry; 2416 buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */ 2417 max_scaled_time = buf_lh_capability - urgent_watermark; 2418 return max_scaled_time; 2419 } 2420 2421 void dcn20_set_mcif_arb_params( 2422 struct dc *dc, 2423 struct dc_state *context, 2424 display_e2e_pipe_params_st *pipes, 2425 int pipe_cnt) 2426 { 2427 enum mmhubbub_wbif_mode wbif_mode; 2428 struct mcif_arb_params *wb_arb_params; 2429 int i, j, k, dwb_pipe; 2430 2431 /* Writeback MCIF_WB arbitration parameters */ 2432 dwb_pipe = 0; 2433 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2434 2435 if (!context->res_ctx.pipe_ctx[i].stream) 2436 continue; 2437 2438 for (j = 0; j < MAX_DWB_PIPES; j++) { 2439 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false) 2440 continue; 2441 2442 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params; 2443 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe]; 2444 2445 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) { 2446 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) 2447 wbif_mode = PLANAR_420_8BPC; 2448 else 2449 wbif_mode = PLANAR_420_10BPC; 2450 } else 2451 wbif_mode = PACKED_444; 2452 2453 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) { 2454 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2455 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2456 } 2457 wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */ 2458 wb_arb_params->slice_lines = 32; 2459 wb_arb_params->arbitration_slice = 2; 2460 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel, 2461 wbif_mode, 2462 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */ 2463 2464 dwb_pipe++; 2465 2466 if (dwb_pipe >= MAX_DWB_PIPES) 2467 return; 2468 } 2469 if (dwb_pipe >= MAX_DWB_PIPES) 2470 return; 2471 } 2472 } 2473 2474 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) 2475 { 2476 int i; 2477 2478 /* Validate DSC config, dsc count validation is already done */ 2479 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2480 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; 2481 struct dc_stream_state *stream = pipe_ctx->stream; 2482 struct dsc_config dsc_cfg; 2483 struct pipe_ctx *odm_pipe; 2484 int opp_cnt = 1; 2485 2486 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 2487 opp_cnt++; 2488 2489 /* Only need to validate top pipe */ 2490 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC) 2491 continue; 2492 2493 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left 2494 + stream->timing.h_border_right) / opp_cnt; 2495 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top 2496 + stream->timing.v_border_bottom; 2497 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 2498 dsc_cfg.color_depth = stream->timing.display_color_depth; 2499 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 2500 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 2501 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 2502 2503 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg)) 2504 return false; 2505 } 2506 return true; 2507 } 2508 2509 struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, 2510 struct resource_context *res_ctx, 2511 const struct resource_pool *pool, 2512 const struct pipe_ctx *primary_pipe) 2513 { 2514 struct pipe_ctx *secondary_pipe = NULL; 2515 2516 if (dc && primary_pipe) { 2517 int j; 2518 int preferred_pipe_idx = 0; 2519 2520 /* first check the prev dc state: 2521 * if this primary pipe has a bottom pipe in prev. state 2522 * and if the bottom pipe is still available (which it should be), 2523 * pick that pipe as secondary 2524 * Same logic applies for ODM pipes. Since mpo is not allowed with odm 2525 * check in else case. 2526 */ 2527 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) { 2528 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx; 2529 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2530 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2531 secondary_pipe->pipe_idx = preferred_pipe_idx; 2532 } 2533 } else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) { 2534 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx; 2535 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2536 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2537 secondary_pipe->pipe_idx = preferred_pipe_idx; 2538 } 2539 } 2540 2541 /* 2542 * if this primary pipe does not have a bottom pipe in prev. state 2543 * start backward and find a pipe that did not used to be a bottom pipe in 2544 * prev. dc state. This way we make sure we keep the same assignment as 2545 * last state and will not have to reprogram every pipe 2546 */ 2547 if (secondary_pipe == NULL) { 2548 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { 2549 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL 2550 && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) { 2551 preferred_pipe_idx = j; 2552 2553 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2554 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2555 secondary_pipe->pipe_idx = preferred_pipe_idx; 2556 break; 2557 } 2558 } 2559 } 2560 } 2561 /* 2562 * We should never hit this assert unless assignments are shuffled around 2563 * if this happens we will prob. hit a vsync tdr 2564 */ 2565 ASSERT(secondary_pipe); 2566 /* 2567 * search backwards for the second pipe to keep pipe 2568 * assignment more consistent 2569 */ 2570 if (secondary_pipe == NULL) { 2571 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { 2572 preferred_pipe_idx = j; 2573 2574 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2575 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2576 secondary_pipe->pipe_idx = preferred_pipe_idx; 2577 break; 2578 } 2579 } 2580 } 2581 } 2582 2583 return secondary_pipe; 2584 } 2585 2586 static void dcn20_merge_pipes_for_validate( 2587 struct dc *dc, 2588 struct dc_state *context) 2589 { 2590 int i; 2591 2592 /* merge previously split odm pipes since mode support needs to make the decision */ 2593 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2594 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2595 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe; 2596 2597 if (pipe->prev_odm_pipe) 2598 continue; 2599 2600 pipe->next_odm_pipe = NULL; 2601 while (odm_pipe) { 2602 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe; 2603 2604 odm_pipe->plane_state = NULL; 2605 odm_pipe->stream = NULL; 2606 odm_pipe->top_pipe = NULL; 2607 odm_pipe->bottom_pipe = NULL; 2608 odm_pipe->prev_odm_pipe = NULL; 2609 odm_pipe->next_odm_pipe = NULL; 2610 if (odm_pipe->stream_res.dsc) 2611 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); 2612 /* Clear plane_res and stream_res */ 2613 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res)); 2614 memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res)); 2615 odm_pipe = next_odm_pipe; 2616 } 2617 if (pipe->plane_state) 2618 resource_build_scaling_params(pipe); 2619 } 2620 2621 /* merge previously mpc split pipes since mode support needs to make the decision */ 2622 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2623 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2624 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 2625 2626 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) 2627 continue; 2628 2629 pipe->bottom_pipe = hsplit_pipe->bottom_pipe; 2630 if (hsplit_pipe->bottom_pipe) 2631 hsplit_pipe->bottom_pipe->top_pipe = pipe; 2632 hsplit_pipe->plane_state = NULL; 2633 hsplit_pipe->stream = NULL; 2634 hsplit_pipe->top_pipe = NULL; 2635 hsplit_pipe->bottom_pipe = NULL; 2636 2637 /* Clear plane_res and stream_res */ 2638 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res)); 2639 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res)); 2640 if (pipe->plane_state) 2641 resource_build_scaling_params(pipe); 2642 } 2643 } 2644 2645 int dcn20_validate_apply_pipe_split_flags( 2646 struct dc *dc, 2647 struct dc_state *context, 2648 int vlevel, 2649 int *split, 2650 bool *merge) 2651 { 2652 int i, pipe_idx, vlevel_split; 2653 int plane_count = 0; 2654 bool force_split = false; 2655 bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID; 2656 struct vba_vars_st *v = &context->bw_ctx.dml.vba; 2657 int max_mpc_comb = v->maxMpcComb; 2658 2659 if (context->stream_count > 1) { 2660 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) 2661 avoid_split = true; 2662 } else if (dc->debug.force_single_disp_pipe_split) 2663 force_split = true; 2664 2665 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2666 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2667 2668 /** 2669 * Workaround for avoiding pipe-split in cases where we'd split 2670 * planes that are too small, resulting in splits that aren't 2671 * valid for the scaler. 2672 */ 2673 if (pipe->plane_state && 2674 (pipe->plane_state->dst_rect.width <= 16 || 2675 pipe->plane_state->dst_rect.height <= 16 || 2676 pipe->plane_state->src_rect.width <= 16 || 2677 pipe->plane_state->src_rect.height <= 16)) 2678 avoid_split = true; 2679 2680 /* TODO: fix dc bugs and remove this split threshold thing */ 2681 if (pipe->stream && !pipe->prev_odm_pipe && 2682 (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state)) 2683 ++plane_count; 2684 } 2685 if (plane_count > dc->res_pool->pipe_count / 2) 2686 avoid_split = true; 2687 2688 /* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */ 2689 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2690 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2691 struct dc_crtc_timing timing; 2692 2693 if (!pipe->stream) 2694 continue; 2695 else { 2696 timing = pipe->stream->timing; 2697 if (timing.h_border_left + timing.h_border_right 2698 + timing.v_border_top + timing.v_border_bottom > 0) { 2699 avoid_split = true; 2700 break; 2701 } 2702 } 2703 } 2704 2705 /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */ 2706 if (avoid_split) { 2707 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2708 if (!context->res_ctx.pipe_ctx[i].stream) 2709 continue; 2710 2711 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) 2712 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 && 2713 v->ModeSupport[vlevel][0]) 2714 break; 2715 /* Impossible to not split this pipe */ 2716 if (vlevel > context->bw_ctx.dml.soc.num_states) 2717 vlevel = vlevel_split; 2718 else 2719 max_mpc_comb = 0; 2720 pipe_idx++; 2721 } 2722 v->maxMpcComb = max_mpc_comb; 2723 } 2724 2725 /* Split loop sets which pipe should be split based on dml outputs and dc flags */ 2726 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2727 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2728 int pipe_plane = v->pipe_plane[pipe_idx]; 2729 bool split4mpc = context->stream_count == 1 && plane_count == 1 2730 && dc->config.enable_4to1MPC && dc->res_pool->pipe_count >= 4; 2731 2732 if (!context->res_ctx.pipe_ctx[i].stream) 2733 continue; 2734 2735 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4) 2736 split[i] = 4; 2737 else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2) 2738 split[i] = 2; 2739 2740 if ((pipe->stream->view_format == 2741 VIEW_3D_FORMAT_SIDE_BY_SIDE || 2742 pipe->stream->view_format == 2743 VIEW_3D_FORMAT_TOP_AND_BOTTOM) && 2744 (pipe->stream->timing.timing_3d_format == 2745 TIMING_3D_FORMAT_TOP_AND_BOTTOM || 2746 pipe->stream->timing.timing_3d_format == 2747 TIMING_3D_FORMAT_SIDE_BY_SIDE)) 2748 split[i] = 2; 2749 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) { 2750 split[i] = 2; 2751 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1; 2752 } 2753 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 2754 if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) { 2755 split[i] = 4; 2756 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1; 2757 } 2758 /*420 format workaround*/ 2759 if (pipe->stream->timing.h_addressable > 7680 && 2760 pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 2761 split[i] = 4; 2762 } 2763 #endif 2764 v->ODMCombineEnabled[pipe_plane] = 2765 v->ODMCombineEnablePerState[vlevel][pipe_plane]; 2766 2767 if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) { 2768 if (get_num_mpc_splits(pipe) == 1) { 2769 /*If need split for mpc but 2 way split already*/ 2770 if (split[i] == 4) 2771 split[i] = 2; /* 2 -> 4 MPC */ 2772 else if (split[i] == 2) 2773 split[i] = 0; /* 2 -> 2 MPC */ 2774 else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) 2775 merge[i] = true; /* 2 -> 1 MPC */ 2776 } else if (get_num_mpc_splits(pipe) == 3) { 2777 /*If need split for mpc but 4 way split already*/ 2778 if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe) 2779 || !pipe->bottom_pipe)) { 2780 merge[i] = true; /* 4 -> 2 MPC */ 2781 } else if (split[i] == 0 && pipe->top_pipe && 2782 pipe->top_pipe->plane_state == pipe->plane_state) 2783 merge[i] = true; /* 4 -> 1 MPC */ 2784 split[i] = 0; 2785 } else if (get_num_odm_splits(pipe)) { 2786 /* ODM -> MPC transition */ 2787 ASSERT(0); /* NOT expected yet */ 2788 if (pipe->prev_odm_pipe) { 2789 split[i] = 0; 2790 merge[i] = true; 2791 } 2792 } 2793 } else { 2794 if (get_num_odm_splits(pipe) == 1) { 2795 /*If need split for odm but 2 way split already*/ 2796 if (split[i] == 4) 2797 split[i] = 2; /* 2 -> 4 ODM */ 2798 else if (split[i] == 2) 2799 split[i] = 0; /* 2 -> 2 ODM */ 2800 else if (pipe->prev_odm_pipe) { 2801 ASSERT(0); /* NOT expected yet */ 2802 merge[i] = true; /* exit ODM */ 2803 } 2804 } else if (get_num_odm_splits(pipe) == 3) { 2805 /*If need split for odm but 4 way split already*/ 2806 if (split[i] == 2 && ((pipe->prev_odm_pipe && !pipe->prev_odm_pipe->prev_odm_pipe) 2807 || !pipe->next_odm_pipe)) { 2808 ASSERT(0); /* NOT expected yet */ 2809 merge[i] = true; /* 4 -> 2 ODM */ 2810 } else if (split[i] == 0 && pipe->prev_odm_pipe) { 2811 ASSERT(0); /* NOT expected yet */ 2812 merge[i] = true; /* exit ODM */ 2813 } 2814 split[i] = 0; 2815 } else if (get_num_mpc_splits(pipe)) { 2816 /* MPC -> ODM transition */ 2817 ASSERT(0); /* NOT expected yet */ 2818 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { 2819 split[i] = 0; 2820 merge[i] = true; 2821 } 2822 } 2823 } 2824 2825 /* Adjust dppclk when split is forced, do not bother with dispclk */ 2826 if (split[i] != 0 && v->NoOfDPP[vlevel][max_mpc_comb][pipe_idx] == 1) 2827 v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2; 2828 pipe_idx++; 2829 } 2830 2831 return vlevel; 2832 } 2833 2834 bool dcn20_fast_validate_bw( 2835 struct dc *dc, 2836 struct dc_state *context, 2837 display_e2e_pipe_params_st *pipes, 2838 int *pipe_cnt_out, 2839 int *pipe_split_from, 2840 int *vlevel_out) 2841 { 2842 bool out = false; 2843 int split[MAX_PIPES] = { 0 }; 2844 int pipe_cnt, i, pipe_idx, vlevel; 2845 2846 ASSERT(pipes); 2847 if (!pipes) 2848 return false; 2849 2850 dcn20_merge_pipes_for_validate(dc, context); 2851 2852 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes); 2853 2854 *pipe_cnt_out = pipe_cnt; 2855 2856 if (!pipe_cnt) { 2857 out = true; 2858 goto validate_out; 2859 } 2860 2861 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 2862 2863 if (vlevel > context->bw_ctx.dml.soc.num_states) 2864 goto validate_fail; 2865 2866 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL); 2867 2868 /*initialize pipe_just_split_from to invalid idx*/ 2869 for (i = 0; i < MAX_PIPES; i++) 2870 pipe_split_from[i] = -1; 2871 2872 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { 2873 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2874 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 2875 2876 if (!pipe->stream || pipe_split_from[i] >= 0) 2877 continue; 2878 2879 pipe_idx++; 2880 2881 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 2882 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 2883 ASSERT(hsplit_pipe); 2884 if (!dcn20_split_stream_for_odm( 2885 dc, &context->res_ctx, 2886 pipe, hsplit_pipe)) 2887 goto validate_fail; 2888 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 2889 dcn20_build_mapped_resource(dc, context, pipe->stream); 2890 } 2891 2892 if (!pipe->plane_state) 2893 continue; 2894 /* Skip 2nd half of already split pipe */ 2895 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state) 2896 continue; 2897 2898 /* We do not support mpo + odm at the moment */ 2899 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state 2900 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) 2901 goto validate_fail; 2902 2903 if (split[i] == 2) { 2904 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) { 2905 /* pipe not split previously needs split */ 2906 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 2907 ASSERT(hsplit_pipe); 2908 if (!hsplit_pipe) { 2909 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2; 2910 continue; 2911 } 2912 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 2913 if (!dcn20_split_stream_for_odm( 2914 dc, &context->res_ctx, 2915 pipe, hsplit_pipe)) 2916 goto validate_fail; 2917 dcn20_build_mapped_resource(dc, context, pipe->stream); 2918 } else { 2919 dcn20_split_stream_for_mpc( 2920 &context->res_ctx, dc->res_pool, 2921 pipe, hsplit_pipe); 2922 resource_build_scaling_params(pipe); 2923 resource_build_scaling_params(hsplit_pipe); 2924 } 2925 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 2926 } 2927 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { 2928 /* merge should already have been done */ 2929 ASSERT(0); 2930 } 2931 } 2932 /* Actual dsc count per stream dsc validation*/ 2933 if (!dcn20_validate_dsc(dc, context)) { 2934 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = 2935 DML_FAIL_DSC_VALIDATION_FAILURE; 2936 goto validate_fail; 2937 } 2938 2939 *vlevel_out = vlevel; 2940 2941 out = true; 2942 goto validate_out; 2943 2944 validate_fail: 2945 out = false; 2946 2947 validate_out: 2948 return out; 2949 } 2950 2951 static void dcn20_calculate_wm( 2952 struct dc *dc, struct dc_state *context, 2953 display_e2e_pipe_params_st *pipes, 2954 int *out_pipe_cnt, 2955 int *pipe_split_from, 2956 int vlevel) 2957 { 2958 int pipe_cnt, i, pipe_idx; 2959 2960 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 2961 if (!context->res_ctx.pipe_ctx[i].stream) 2962 continue; 2963 2964 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 2965 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 2966 2967 if (pipe_split_from[i] < 0) { 2968 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 2969 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; 2970 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) 2971 pipes[pipe_cnt].pipe.dest.odm_combine = 2972 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]; 2973 else 2974 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 2975 pipe_idx++; 2976 } else { 2977 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 2978 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; 2979 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) 2980 pipes[pipe_cnt].pipe.dest.odm_combine = 2981 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]]; 2982 else 2983 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 2984 } 2985 2986 if (dc->config.forced_clocks) { 2987 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 2988 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 2989 } 2990 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000) 2991 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 2992 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000) 2993 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 2994 2995 pipe_cnt++; 2996 } 2997 2998 if (pipe_cnt != pipe_idx) { 2999 if (dc->res_pool->funcs->populate_dml_pipes) 3000 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, 3001 context, pipes); 3002 else 3003 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, 3004 context, pipes); 3005 } 3006 3007 *out_pipe_cnt = pipe_cnt; 3008 3009 pipes[0].clks_cfg.voltage = vlevel; 3010 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; 3011 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 3012 3013 /* only pipe 0 is read for voltage and dcf/soc clocks */ 3014 if (vlevel < 1) { 3015 pipes[0].clks_cfg.voltage = 1; 3016 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz; 3017 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz; 3018 } 3019 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3020 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3021 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3022 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3023 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3024 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3025 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3026 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3027 3028 if (vlevel < 2) { 3029 pipes[0].clks_cfg.voltage = 2; 3030 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; 3031 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; 3032 } 3033 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3034 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3035 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3036 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3037 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3038 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3039 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3040 3041 if (vlevel < 3) { 3042 pipes[0].clks_cfg.voltage = 3; 3043 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; 3044 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; 3045 } 3046 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3047 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3048 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3049 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3050 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3051 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3052 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3053 3054 pipes[0].clks_cfg.voltage = vlevel; 3055 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; 3056 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 3057 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3058 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3059 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3060 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3061 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3062 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3063 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3064 } 3065 3066 void dcn20_calculate_dlg_params( 3067 struct dc *dc, struct dc_state *context, 3068 display_e2e_pipe_params_st *pipes, 3069 int pipe_cnt, 3070 int vlevel) 3071 { 3072 int i, pipe_idx; 3073 3074 /* Writeback MCIF_WB arbitration parameters */ 3075 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); 3076 3077 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; 3078 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; 3079 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; 3080 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; 3081 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; 3082 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; 3083 context->bw_ctx.bw.dcn.clk.p_state_change_support = 3084 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] 3085 != dm_dram_clock_change_unsupported; 3086 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 3087 3088 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) 3089 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; 3090 3091 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 3092 if (!context->res_ctx.pipe_ctx[i].stream) 3093 continue; 3094 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 3095 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 3096 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 3097 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 3098 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 3099 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 3100 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 3101 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 3102 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; 3103 pipe_idx++; 3104 } 3105 /*save a original dppclock copy*/ 3106 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; 3107 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; 3108 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000; 3109 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000; 3110 3111 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 3112 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2; 3113 3114 if (!context->res_ctx.pipe_ctx[i].stream) 3115 continue; 3116 3117 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml, 3118 &context->res_ctx.pipe_ctx[i].dlg_regs, 3119 &context->res_ctx.pipe_ctx[i].ttu_regs, 3120 pipes, 3121 pipe_cnt, 3122 pipe_idx, 3123 cstate_en, 3124 context->bw_ctx.bw.dcn.clk.p_state_change_support, 3125 false, false, true); 3126 3127 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml, 3128 &context->res_ctx.pipe_ctx[i].rq_regs, 3129 pipes[pipe_idx].pipe); 3130 pipe_idx++; 3131 } 3132 } 3133 3134 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context, 3135 bool fast_validate) 3136 { 3137 bool out = false; 3138 3139 BW_VAL_TRACE_SETUP(); 3140 3141 int vlevel = 0; 3142 int pipe_split_from[MAX_PIPES]; 3143 int pipe_cnt = 0; 3144 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 3145 DC_LOGGER_INIT(dc->ctx->logger); 3146 3147 BW_VAL_TRACE_COUNT(); 3148 3149 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel); 3150 3151 if (pipe_cnt == 0) 3152 goto validate_out; 3153 3154 if (!out) 3155 goto validate_fail; 3156 3157 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 3158 3159 if (fast_validate) { 3160 BW_VAL_TRACE_SKIP(fast); 3161 goto validate_out; 3162 } 3163 3164 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel); 3165 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 3166 3167 BW_VAL_TRACE_END_WATERMARKS(); 3168 3169 goto validate_out; 3170 3171 validate_fail: 3172 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 3173 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 3174 3175 BW_VAL_TRACE_SKIP(fail); 3176 out = false; 3177 3178 validate_out: 3179 kfree(pipes); 3180 3181 BW_VAL_TRACE_FINISH(); 3182 3183 return out; 3184 } 3185 3186 /* 3187 * This must be noinline to ensure anything that deals with FP registers 3188 * is contained within this call; previously our compiling with hard-float 3189 * would result in fp instructions being emitted outside of the boundaries 3190 * of the DC_FP_START/END macros, which makes sense as the compiler has no 3191 * idea about what is wrapped and what is not 3192 * 3193 * This is largely just a workaround to avoid breakage introduced with 5.6, 3194 * ideally all fp-using code should be moved into its own file, only that 3195 * should be compiled with hard-float, and all code exported from there 3196 * should be strictly wrapped with DC_FP_START/END 3197 */ 3198 static noinline bool dcn20_validate_bandwidth_fp(struct dc *dc, 3199 struct dc_state *context, bool fast_validate) 3200 { 3201 bool voltage_supported = false; 3202 bool full_pstate_supported = false; 3203 bool dummy_pstate_supported = false; 3204 double p_state_latency_us; 3205 3206 p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us; 3207 context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support = 3208 dc->debug.disable_dram_clock_change_vactive_support; 3209 context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive = 3210 dc->debug.enable_dram_clock_change_one_display_vactive; 3211 3212 if (fast_validate) { 3213 return dcn20_validate_bandwidth_internal(dc, context, true); 3214 } 3215 3216 // Best case, we support full UCLK switch latency 3217 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); 3218 full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; 3219 3220 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 || 3221 (voltage_supported && full_pstate_supported)) { 3222 context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported; 3223 goto restore_dml_state; 3224 } 3225 3226 // Fallback: Try to only support G6 temperature read latency 3227 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us; 3228 3229 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); 3230 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; 3231 3232 if (voltage_supported && dummy_pstate_supported) { 3233 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; 3234 goto restore_dml_state; 3235 } 3236 3237 // ERROR: fallback is supposed to always work. 3238 ASSERT(false); 3239 3240 restore_dml_state: 3241 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us; 3242 return voltage_supported; 3243 } 3244 3245 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, 3246 bool fast_validate) 3247 { 3248 bool voltage_supported = false; 3249 DC_FP_START(); 3250 voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate); 3251 DC_FP_END(); 3252 return voltage_supported; 3253 } 3254 3255 struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer( 3256 struct dc_state *state, 3257 const struct resource_pool *pool, 3258 struct dc_stream_state *stream) 3259 { 3260 struct resource_context *res_ctx = &state->res_ctx; 3261 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 3262 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe); 3263 3264 if (!head_pipe) 3265 ASSERT(0); 3266 3267 if (!idle_pipe) 3268 return NULL; 3269 3270 idle_pipe->stream = head_pipe->stream; 3271 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 3272 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 3273 3274 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 3275 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 3276 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 3277 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 3278 3279 return idle_pipe; 3280 } 3281 3282 bool dcn20_get_dcc_compression_cap(const struct dc *dc, 3283 const struct dc_dcc_surface_param *input, 3284 struct dc_surface_dcc_cap *output) 3285 { 3286 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 3287 dc->res_pool->hubbub, 3288 input, 3289 output); 3290 } 3291 3292 static void dcn20_destroy_resource_pool(struct resource_pool **pool) 3293 { 3294 struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool); 3295 3296 dcn20_resource_destruct(dcn20_pool); 3297 kfree(dcn20_pool); 3298 *pool = NULL; 3299 } 3300 3301 3302 static struct dc_cap_funcs cap_funcs = { 3303 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 3304 }; 3305 3306 3307 enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state) 3308 { 3309 enum surface_pixel_format surf_pix_format = plane_state->format; 3310 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 3311 3312 enum swizzle_mode_values swizzle = DC_SW_LINEAR; 3313 3314 if (bpp == 64) 3315 swizzle = DC_SW_64KB_D; 3316 else 3317 swizzle = DC_SW_64KB_S; 3318 3319 plane_state->tiling_info.gfx9.swizzle = swizzle; 3320 return DC_OK; 3321 } 3322 3323 static struct resource_funcs dcn20_res_pool_funcs = { 3324 .destroy = dcn20_destroy_resource_pool, 3325 .link_enc_create = dcn20_link_encoder_create, 3326 .panel_cntl_create = dcn20_panel_cntl_create, 3327 .validate_bandwidth = dcn20_validate_bandwidth, 3328 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 3329 .add_stream_to_ctx = dcn20_add_stream_to_ctx, 3330 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 3331 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 3332 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, 3333 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 3334 .set_mcif_arb_params = dcn20_set_mcif_arb_params, 3335 .populate_dml_pipes = dcn20_populate_dml_pipes_from_context, 3336 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link 3337 }; 3338 3339 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 3340 { 3341 int i; 3342 uint32_t pipe_count = pool->res_cap->num_dwb; 3343 3344 for (i = 0; i < pipe_count; i++) { 3345 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc), 3346 GFP_KERNEL); 3347 3348 if (!dwbc20) { 3349 dm_error("DC: failed to create dwbc20!\n"); 3350 return false; 3351 } 3352 dcn20_dwbc_construct(dwbc20, ctx, 3353 &dwbc20_regs[i], 3354 &dwbc20_shift, 3355 &dwbc20_mask, 3356 i); 3357 pool->dwbc[i] = &dwbc20->base; 3358 } 3359 return true; 3360 } 3361 3362 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 3363 { 3364 int i; 3365 uint32_t pipe_count = pool->res_cap->num_dwb; 3366 3367 ASSERT(pipe_count > 0); 3368 3369 for (i = 0; i < pipe_count; i++) { 3370 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub), 3371 GFP_KERNEL); 3372 3373 if (!mcif_wb20) { 3374 dm_error("DC: failed to create mcif_wb20!\n"); 3375 return false; 3376 } 3377 3378 dcn20_mmhubbub_construct(mcif_wb20, ctx, 3379 &mcif_wb20_regs[i], 3380 &mcif_wb20_shift, 3381 &mcif_wb20_mask, 3382 i); 3383 3384 pool->mcif_wb[i] = &mcif_wb20->base; 3385 } 3386 return true; 3387 } 3388 3389 static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx) 3390 { 3391 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 3392 3393 if (!pp_smu) 3394 return pp_smu; 3395 3396 dm_pp_get_funcs(ctx, pp_smu); 3397 3398 if (pp_smu->ctx.ver != PP_SMU_VER_NV) 3399 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); 3400 3401 return pp_smu; 3402 } 3403 3404 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu) 3405 { 3406 if (pp_smu && *pp_smu) { 3407 kfree(*pp_smu); 3408 *pp_smu = NULL; 3409 } 3410 } 3411 3412 void dcn20_cap_soc_clocks( 3413 struct _vcs_dpi_soc_bounding_box_st *bb, 3414 struct pp_smu_nv_clock_table max_clocks) 3415 { 3416 int i; 3417 3418 // First pass - cap all clocks higher than the reported max 3419 for (i = 0; i < bb->num_states; i++) { 3420 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000)) 3421 && max_clocks.dcfClockInKhz != 0) 3422 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000); 3423 3424 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16) 3425 && max_clocks.uClockInKhz != 0) 3426 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16; 3427 3428 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000)) 3429 && max_clocks.fabricClockInKhz != 0) 3430 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000); 3431 3432 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000)) 3433 && max_clocks.displayClockInKhz != 0) 3434 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000); 3435 3436 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000)) 3437 && max_clocks.dppClockInKhz != 0) 3438 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000); 3439 3440 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000)) 3441 && max_clocks.phyClockInKhz != 0) 3442 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000); 3443 3444 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000)) 3445 && max_clocks.socClockInKhz != 0) 3446 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000); 3447 3448 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000)) 3449 && max_clocks.dscClockInKhz != 0) 3450 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000); 3451 } 3452 3453 // Second pass - remove all duplicate clock states 3454 for (i = bb->num_states - 1; i > 1; i--) { 3455 bool duplicate = true; 3456 3457 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz) 3458 duplicate = false; 3459 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz) 3460 duplicate = false; 3461 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz) 3462 duplicate = false; 3463 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts) 3464 duplicate = false; 3465 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz) 3466 duplicate = false; 3467 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz) 3468 duplicate = false; 3469 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz) 3470 duplicate = false; 3471 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz) 3472 duplicate = false; 3473 3474 if (duplicate) 3475 bb->num_states--; 3476 } 3477 } 3478 3479 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb, 3480 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) 3481 { 3482 struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES]; 3483 int i; 3484 int num_calculated_states = 0; 3485 int min_dcfclk = 0; 3486 3487 if (num_states == 0) 3488 return; 3489 3490 memset(calculated_states, 0, sizeof(calculated_states)); 3491 3492 if (dc->bb_overrides.min_dcfclk_mhz > 0) 3493 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz; 3494 else { 3495 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) 3496 min_dcfclk = 310; 3497 else 3498 // Accounting for SOC/DCF relationship, we can go as high as 3499 // 506Mhz in Vmin. 3500 min_dcfclk = 506; 3501 } 3502 3503 for (i = 0; i < num_states; i++) { 3504 int min_fclk_required_by_uclk; 3505 calculated_states[i].state = i; 3506 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000; 3507 3508 // FCLK:UCLK ratio is 1.08 3509 min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32); 3510 3511 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? 3512 min_dcfclk : min_fclk_required_by_uclk; 3513 3514 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ? 3515 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; 3516 3517 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ? 3518 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; 3519 3520 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000; 3521 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000; 3522 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3); 3523 3524 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000; 3525 3526 num_calculated_states++; 3527 } 3528 3529 calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000; 3530 calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000; 3531 calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000; 3532 3533 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits)); 3534 bb->num_states = num_calculated_states; 3535 3536 // Duplicate the last state, DML always an extra state identical to max state to work 3537 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st)); 3538 bb->clock_limits[num_calculated_states].state = bb->num_states; 3539 } 3540 3541 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) 3542 { 3543 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns 3544 && dc->bb_overrides.sr_exit_time_ns) { 3545 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; 3546 } 3547 3548 if ((int)(bb->sr_enter_plus_exit_time_us * 1000) 3549 != dc->bb_overrides.sr_enter_plus_exit_time_ns 3550 && dc->bb_overrides.sr_enter_plus_exit_time_ns) { 3551 bb->sr_enter_plus_exit_time_us = 3552 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 3553 } 3554 3555 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns 3556 && dc->bb_overrides.urgent_latency_ns) { 3557 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 3558 } 3559 3560 if ((int)(bb->dram_clock_change_latency_us * 1000) 3561 != dc->bb_overrides.dram_clock_change_latency_ns 3562 && dc->bb_overrides.dram_clock_change_latency_ns) { 3563 bb->dram_clock_change_latency_us = 3564 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 3565 } 3566 3567 if ((int)(bb->dummy_pstate_latency_us * 1000) 3568 != dc->bb_overrides.dummy_clock_change_latency_ns 3569 && dc->bb_overrides.dummy_clock_change_latency_ns) { 3570 bb->dummy_pstate_latency_us = 3571 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0; 3572 } 3573 } 3574 3575 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb( 3576 uint32_t hw_internal_rev) 3577 { 3578 if (ASICREV_IS_NAVI14_M(hw_internal_rev)) 3579 return &dcn2_0_nv14_soc; 3580 3581 if (ASICREV_IS_NAVI12_P(hw_internal_rev)) 3582 return &dcn2_0_nv12_soc; 3583 3584 return &dcn2_0_soc; 3585 } 3586 3587 static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params( 3588 uint32_t hw_internal_rev) 3589 { 3590 /* NV14 */ 3591 if (ASICREV_IS_NAVI14_M(hw_internal_rev)) 3592 return &dcn2_0_nv14_ip; 3593 3594 /* NV12 and NV10 */ 3595 return &dcn2_0_ip; 3596 } 3597 3598 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev) 3599 { 3600 return DML_PROJECT_NAVI10v2; 3601 } 3602 3603 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16))) 3604 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) 3605 3606 static bool init_soc_bounding_box(struct dc *dc, 3607 struct dcn20_resource_pool *pool) 3608 { 3609 const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box; 3610 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = 3611 get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev); 3612 struct _vcs_dpi_ip_params_st *loaded_ip = 3613 get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev); 3614 3615 DC_LOGGER_INIT(dc->ctx->logger); 3616 3617 /* TODO: upstream NV12 bounding box when its launched */ 3618 if (!bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) { 3619 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); 3620 return false; 3621 } 3622 3623 if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) { 3624 int i; 3625 3626 dcn2_0_nv12_soc.sr_exit_time_us = 3627 fixed16_to_double_to_cpu(bb->sr_exit_time_us); 3628 dcn2_0_nv12_soc.sr_enter_plus_exit_time_us = 3629 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us); 3630 dcn2_0_nv12_soc.urgent_latency_us = 3631 fixed16_to_double_to_cpu(bb->urgent_latency_us); 3632 dcn2_0_nv12_soc.urgent_latency_pixel_data_only_us = 3633 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us); 3634 dcn2_0_nv12_soc.urgent_latency_pixel_mixed_with_vm_data_us = 3635 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us); 3636 dcn2_0_nv12_soc.urgent_latency_vm_data_only_us = 3637 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us); 3638 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes = 3639 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes); 3640 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 3641 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes); 3642 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_vm_only_bytes = 3643 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes); 3644 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 3645 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only); 3646 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 3647 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm); 3648 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 3649 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only); 3650 dcn2_0_nv12_soc.max_avg_sdp_bw_use_normal_percent = 3651 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent); 3652 dcn2_0_nv12_soc.max_avg_dram_bw_use_normal_percent = 3653 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent); 3654 dcn2_0_nv12_soc.writeback_latency_us = 3655 fixed16_to_double_to_cpu(bb->writeback_latency_us); 3656 dcn2_0_nv12_soc.ideal_dram_bw_after_urgent_percent = 3657 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent); 3658 dcn2_0_nv12_soc.max_request_size_bytes = 3659 le32_to_cpu(bb->max_request_size_bytes); 3660 dcn2_0_nv12_soc.dram_channel_width_bytes = 3661 le32_to_cpu(bb->dram_channel_width_bytes); 3662 dcn2_0_nv12_soc.fabric_datapath_to_dcn_data_return_bytes = 3663 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes); 3664 dcn2_0_nv12_soc.dcn_downspread_percent = 3665 fixed16_to_double_to_cpu(bb->dcn_downspread_percent); 3666 dcn2_0_nv12_soc.downspread_percent = 3667 fixed16_to_double_to_cpu(bb->downspread_percent); 3668 dcn2_0_nv12_soc.dram_page_open_time_ns = 3669 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns); 3670 dcn2_0_nv12_soc.dram_rw_turnaround_time_ns = 3671 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns); 3672 dcn2_0_nv12_soc.dram_return_buffer_per_channel_bytes = 3673 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes); 3674 dcn2_0_nv12_soc.round_trip_ping_latency_dcfclk_cycles = 3675 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles); 3676 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_bytes = 3677 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes); 3678 dcn2_0_nv12_soc.channel_interleave_bytes = 3679 le32_to_cpu(bb->channel_interleave_bytes); 3680 dcn2_0_nv12_soc.num_banks = 3681 le32_to_cpu(bb->num_banks); 3682 dcn2_0_nv12_soc.num_chans = 3683 le32_to_cpu(bb->num_chans); 3684 dcn2_0_nv12_soc.vmm_page_size_bytes = 3685 le32_to_cpu(bb->vmm_page_size_bytes); 3686 dcn2_0_nv12_soc.dram_clock_change_latency_us = 3687 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us); 3688 // HACK!! Lower uclock latency switch time so we don't switch 3689 dcn2_0_nv12_soc.dram_clock_change_latency_us = 10; 3690 dcn2_0_nv12_soc.writeback_dram_clock_change_latency_us = 3691 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us); 3692 dcn2_0_nv12_soc.return_bus_width_bytes = 3693 le32_to_cpu(bb->return_bus_width_bytes); 3694 dcn2_0_nv12_soc.dispclk_dppclk_vco_speed_mhz = 3695 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz); 3696 dcn2_0_nv12_soc.xfc_bus_transport_time_us = 3697 le32_to_cpu(bb->xfc_bus_transport_time_us); 3698 dcn2_0_nv12_soc.xfc_xbuf_latency_tolerance_us = 3699 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us); 3700 dcn2_0_nv12_soc.use_urgent_burst_bw = 3701 le32_to_cpu(bb->use_urgent_burst_bw); 3702 dcn2_0_nv12_soc.num_states = 3703 le32_to_cpu(bb->num_states); 3704 3705 for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) { 3706 dcn2_0_nv12_soc.clock_limits[i].state = 3707 le32_to_cpu(bb->clock_limits[i].state); 3708 dcn2_0_nv12_soc.clock_limits[i].dcfclk_mhz = 3709 fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz); 3710 dcn2_0_nv12_soc.clock_limits[i].fabricclk_mhz = 3711 fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz); 3712 dcn2_0_nv12_soc.clock_limits[i].dispclk_mhz = 3713 fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz); 3714 dcn2_0_nv12_soc.clock_limits[i].dppclk_mhz = 3715 fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz); 3716 dcn2_0_nv12_soc.clock_limits[i].phyclk_mhz = 3717 fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz); 3718 dcn2_0_nv12_soc.clock_limits[i].socclk_mhz = 3719 fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz); 3720 dcn2_0_nv12_soc.clock_limits[i].dscclk_mhz = 3721 fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz); 3722 dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts = 3723 fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts); 3724 } 3725 } 3726 3727 if (pool->base.pp_smu) { 3728 struct pp_smu_nv_clock_table max_clocks = {0}; 3729 unsigned int uclk_states[8] = {0}; 3730 unsigned int num_states = 0; 3731 enum pp_smu_status status; 3732 bool clock_limits_available = false; 3733 bool uclk_states_available = false; 3734 3735 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) { 3736 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) 3737 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); 3738 3739 uclk_states_available = (status == PP_SMU_RESULT_OK); 3740 } 3741 3742 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) { 3743 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) 3744 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks); 3745 /* SMU cannot set DCF clock to anything equal to or higher than SOC clock 3746 */ 3747 if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz) 3748 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000; 3749 clock_limits_available = (status == PP_SMU_RESULT_OK); 3750 } 3751 3752 if (clock_limits_available && uclk_states_available && num_states) 3753 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states); 3754 else if (clock_limits_available) 3755 dcn20_cap_soc_clocks(loaded_bb, max_clocks); 3756 } 3757 3758 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; 3759 loaded_ip->max_num_dpp = pool->base.pipe_count; 3760 dcn20_patch_bounding_box(dc, loaded_bb); 3761 3762 return true; 3763 } 3764 3765 static bool dcn20_resource_construct( 3766 uint8_t num_virtual_links, 3767 struct dc *dc, 3768 struct dcn20_resource_pool *pool) 3769 { 3770 int i; 3771 struct dc_context *ctx = dc->ctx; 3772 struct irq_service_init_data init_data; 3773 struct ddc_service_init_data ddc_init_data; 3774 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = 3775 get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev); 3776 struct _vcs_dpi_ip_params_st *loaded_ip = 3777 get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev); 3778 enum dml_project dml_project_version = 3779 get_dml_project_version(ctx->asic_id.hw_internal_rev); 3780 3781 DC_FP_START(); 3782 3783 ctx->dc_bios->regs = &bios_regs; 3784 pool->base.funcs = &dcn20_res_pool_funcs; 3785 3786 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) { 3787 pool->base.res_cap = &res_cap_nv14; 3788 pool->base.pipe_count = 5; 3789 pool->base.mpcc_count = 5; 3790 } else { 3791 pool->base.res_cap = &res_cap_nv10; 3792 pool->base.pipe_count = 6; 3793 pool->base.mpcc_count = 6; 3794 } 3795 /************************************************* 3796 * Resource + asic cap harcoding * 3797 *************************************************/ 3798 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 3799 3800 dc->caps.max_downscale_ratio = 200; 3801 dc->caps.i2c_speed_in_khz = 100; 3802 dc->caps.max_cursor_size = 256; 3803 dc->caps.dmdata_alloc_size = 2048; 3804 3805 dc->caps.max_slave_planes = 1; 3806 dc->caps.post_blend_color_processing = true; 3807 dc->caps.force_dp_tps4_for_cp2520 = true; 3808 dc->caps.extended_aux_timeout_support = true; 3809 3810 /* Color pipeline capabilities */ 3811 dc->caps.color.dpp.dcn_arch = 1; 3812 dc->caps.color.dpp.input_lut_shared = 0; 3813 dc->caps.color.dpp.icsc = 1; 3814 dc->caps.color.dpp.dgam_ram = 1; 3815 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 3816 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 3817 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0; 3818 dc->caps.color.dpp.dgam_rom_caps.pq = 0; 3819 dc->caps.color.dpp.dgam_rom_caps.hlg = 0; 3820 dc->caps.color.dpp.post_csc = 0; 3821 dc->caps.color.dpp.gamma_corr = 0; 3822 3823 dc->caps.color.dpp.hw_3d_lut = 1; 3824 dc->caps.color.dpp.ogam_ram = 1; 3825 // no OGAM ROM on DCN2, only MPC ROM 3826 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 3827 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 3828 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 3829 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 3830 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 3831 dc->caps.color.dpp.ocsc = 0; 3832 3833 dc->caps.color.mpc.gamut_remap = 0; 3834 dc->caps.color.mpc.num_3dluts = 0; 3835 dc->caps.color.mpc.shared_3d_lut = 0; 3836 dc->caps.color.mpc.ogam_ram = 1; 3837 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 3838 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 3839 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 3840 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 3841 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 3842 dc->caps.color.mpc.ocsc = 1; 3843 3844 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) { 3845 dc->debug = debug_defaults_drv; 3846 } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 3847 pool->base.pipe_count = 4; 3848 pool->base.mpcc_count = pool->base.pipe_count; 3849 dc->debug = debug_defaults_diags; 3850 } else { 3851 dc->debug = debug_defaults_diags; 3852 } 3853 //dcn2.0x 3854 dc->work_arounds.dedcn20_305_wa = true; 3855 3856 // Init the vm_helper 3857 if (dc->vm_helper) 3858 vm_helper_init(dc->vm_helper, 16); 3859 3860 /************************************************* 3861 * Create resources * 3862 *************************************************/ 3863 3864 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = 3865 dcn20_clock_source_create(ctx, ctx->dc_bios, 3866 CLOCK_SOURCE_COMBO_PHY_PLL0, 3867 &clk_src_regs[0], false); 3868 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = 3869 dcn20_clock_source_create(ctx, ctx->dc_bios, 3870 CLOCK_SOURCE_COMBO_PHY_PLL1, 3871 &clk_src_regs[1], false); 3872 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = 3873 dcn20_clock_source_create(ctx, ctx->dc_bios, 3874 CLOCK_SOURCE_COMBO_PHY_PLL2, 3875 &clk_src_regs[2], false); 3876 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] = 3877 dcn20_clock_source_create(ctx, ctx->dc_bios, 3878 CLOCK_SOURCE_COMBO_PHY_PLL3, 3879 &clk_src_regs[3], false); 3880 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] = 3881 dcn20_clock_source_create(ctx, ctx->dc_bios, 3882 CLOCK_SOURCE_COMBO_PHY_PLL4, 3883 &clk_src_regs[4], false); 3884 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] = 3885 dcn20_clock_source_create(ctx, ctx->dc_bios, 3886 CLOCK_SOURCE_COMBO_PHY_PLL5, 3887 &clk_src_regs[5], false); 3888 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL; 3889 /* todo: not reuse phy_pll registers */ 3890 pool->base.dp_clock_source = 3891 dcn20_clock_source_create(ctx, ctx->dc_bios, 3892 CLOCK_SOURCE_ID_DP_DTO, 3893 &clk_src_regs[0], true); 3894 3895 for (i = 0; i < pool->base.clk_src_count; i++) { 3896 if (pool->base.clock_sources[i] == NULL) { 3897 dm_error("DC: failed to create clock sources!\n"); 3898 BREAK_TO_DEBUGGER(); 3899 goto create_fail; 3900 } 3901 } 3902 3903 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 3904 if (pool->base.dccg == NULL) { 3905 dm_error("DC: failed to create dccg!\n"); 3906 BREAK_TO_DEBUGGER(); 3907 goto create_fail; 3908 } 3909 3910 pool->base.dmcu = dcn20_dmcu_create(ctx, 3911 &dmcu_regs, 3912 &dmcu_shift, 3913 &dmcu_mask); 3914 if (pool->base.dmcu == NULL) { 3915 dm_error("DC: failed to create dmcu!\n"); 3916 BREAK_TO_DEBUGGER(); 3917 goto create_fail; 3918 } 3919 3920 pool->base.abm = dce_abm_create(ctx, 3921 &abm_regs, 3922 &abm_shift, 3923 &abm_mask); 3924 if (pool->base.abm == NULL) { 3925 dm_error("DC: failed to create abm!\n"); 3926 BREAK_TO_DEBUGGER(); 3927 goto create_fail; 3928 } 3929 3930 pool->base.pp_smu = dcn20_pp_smu_create(ctx); 3931 3932 3933 if (!init_soc_bounding_box(dc, pool)) { 3934 dm_error("DC: failed to initialize soc bounding box!\n"); 3935 BREAK_TO_DEBUGGER(); 3936 goto create_fail; 3937 } 3938 3939 dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version); 3940 3941 if (!dc->debug.disable_pplib_wm_range) { 3942 struct pp_smu_wm_range_sets ranges = {0}; 3943 int i = 0; 3944 3945 ranges.num_reader_wm_sets = 0; 3946 3947 if (loaded_bb->num_states == 1) { 3948 ranges.reader_wm_sets[0].wm_inst = i; 3949 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3950 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3951 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3952 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3953 3954 ranges.num_reader_wm_sets = 1; 3955 } else if (loaded_bb->num_states > 1) { 3956 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { 3957 ranges.reader_wm_sets[i].wm_inst = i; 3958 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3959 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3960 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; 3961 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; 3962 3963 ranges.num_reader_wm_sets = i + 1; 3964 } 3965 3966 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3967 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3968 } 3969 3970 ranges.num_writer_wm_sets = 1; 3971 3972 ranges.writer_wm_sets[0].wm_inst = 0; 3973 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3974 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3975 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3976 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3977 3978 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 3979 if (pool->base.pp_smu->nv_funcs.set_wm_ranges) 3980 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges); 3981 } 3982 3983 init_data.ctx = dc->ctx; 3984 pool->base.irqs = dal_irq_service_dcn20_create(&init_data); 3985 if (!pool->base.irqs) 3986 goto create_fail; 3987 3988 /* mem input -> ipp -> dpp -> opp -> TG */ 3989 for (i = 0; i < pool->base.pipe_count; i++) { 3990 pool->base.hubps[i] = dcn20_hubp_create(ctx, i); 3991 if (pool->base.hubps[i] == NULL) { 3992 BREAK_TO_DEBUGGER(); 3993 dm_error( 3994 "DC: failed to create memory input!\n"); 3995 goto create_fail; 3996 } 3997 3998 pool->base.ipps[i] = dcn20_ipp_create(ctx, i); 3999 if (pool->base.ipps[i] == NULL) { 4000 BREAK_TO_DEBUGGER(); 4001 dm_error( 4002 "DC: failed to create input pixel processor!\n"); 4003 goto create_fail; 4004 } 4005 4006 pool->base.dpps[i] = dcn20_dpp_create(ctx, i); 4007 if (pool->base.dpps[i] == NULL) { 4008 BREAK_TO_DEBUGGER(); 4009 dm_error( 4010 "DC: failed to create dpps!\n"); 4011 goto create_fail; 4012 } 4013 } 4014 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 4015 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i); 4016 if (pool->base.engines[i] == NULL) { 4017 BREAK_TO_DEBUGGER(); 4018 dm_error( 4019 "DC:failed to create aux engine!!\n"); 4020 goto create_fail; 4021 } 4022 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i); 4023 if (pool->base.hw_i2cs[i] == NULL) { 4024 BREAK_TO_DEBUGGER(); 4025 dm_error( 4026 "DC:failed to create hw i2c!!\n"); 4027 goto create_fail; 4028 } 4029 pool->base.sw_i2cs[i] = NULL; 4030 } 4031 4032 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 4033 pool->base.opps[i] = dcn20_opp_create(ctx, i); 4034 if (pool->base.opps[i] == NULL) { 4035 BREAK_TO_DEBUGGER(); 4036 dm_error( 4037 "DC: failed to create output pixel processor!\n"); 4038 goto create_fail; 4039 } 4040 } 4041 4042 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 4043 pool->base.timing_generators[i] = dcn20_timing_generator_create( 4044 ctx, i); 4045 if (pool->base.timing_generators[i] == NULL) { 4046 BREAK_TO_DEBUGGER(); 4047 dm_error("DC: failed to create tg!\n"); 4048 goto create_fail; 4049 } 4050 } 4051 4052 pool->base.timing_generator_count = i; 4053 4054 pool->base.mpc = dcn20_mpc_create(ctx); 4055 if (pool->base.mpc == NULL) { 4056 BREAK_TO_DEBUGGER(); 4057 dm_error("DC: failed to create mpc!\n"); 4058 goto create_fail; 4059 } 4060 4061 pool->base.hubbub = dcn20_hubbub_create(ctx); 4062 if (pool->base.hubbub == NULL) { 4063 BREAK_TO_DEBUGGER(); 4064 dm_error("DC: failed to create hubbub!\n"); 4065 goto create_fail; 4066 } 4067 4068 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 4069 pool->base.dscs[i] = dcn20_dsc_create(ctx, i); 4070 if (pool->base.dscs[i] == NULL) { 4071 BREAK_TO_DEBUGGER(); 4072 dm_error("DC: failed to create display stream compressor %d!\n", i); 4073 goto create_fail; 4074 } 4075 } 4076 4077 if (!dcn20_dwbc_create(ctx, &pool->base)) { 4078 BREAK_TO_DEBUGGER(); 4079 dm_error("DC: failed to create dwbc!\n"); 4080 goto create_fail; 4081 } 4082 if (!dcn20_mmhubbub_create(ctx, &pool->base)) { 4083 BREAK_TO_DEBUGGER(); 4084 dm_error("DC: failed to create mcif_wb!\n"); 4085 goto create_fail; 4086 } 4087 4088 if (!resource_construct(num_virtual_links, dc, &pool->base, 4089 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 4090 &res_create_funcs : &res_create_maximus_funcs))) 4091 goto create_fail; 4092 4093 dcn20_hw_sequencer_construct(dc); 4094 4095 // IF NV12, set PG function pointer to NULL. It's not that 4096 // PG isn't supported for NV12, it's that we don't want to 4097 // program the registers because that will cause more power 4098 // to be consumed. We could have created dcn20_init_hw to get 4099 // the same effect by checking ASIC rev, but there was a 4100 // request at some point to not check ASIC rev on hw sequencer. 4101 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) { 4102 dc->hwseq->funcs.enable_power_gating_plane = NULL; 4103 dc->debug.disable_dpp_power_gate = true; 4104 dc->debug.disable_hubp_power_gate = true; 4105 } 4106 4107 4108 dc->caps.max_planes = pool->base.pipe_count; 4109 4110 for (i = 0; i < dc->caps.max_planes; ++i) 4111 dc->caps.planes[i] = plane_cap; 4112 4113 dc->cap_funcs = cap_funcs; 4114 4115 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 4116 ddc_init_data.ctx = dc->ctx; 4117 ddc_init_data.link = NULL; 4118 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 4119 ddc_init_data.id.enum_id = 0; 4120 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 4121 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); 4122 } else { 4123 pool->base.oem_device = NULL; 4124 } 4125 4126 DC_FP_END(); 4127 return true; 4128 4129 create_fail: 4130 4131 DC_FP_END(); 4132 dcn20_resource_destruct(pool); 4133 4134 return false; 4135 } 4136 4137 struct resource_pool *dcn20_create_resource_pool( 4138 const struct dc_init_data *init_data, 4139 struct dc *dc) 4140 { 4141 struct dcn20_resource_pool *pool = 4142 kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL); 4143 4144 if (!pool) 4145 return NULL; 4146 4147 if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool)) 4148 return &pool->base; 4149 4150 BREAK_TO_DEBUGGER(); 4151 kfree(pool); 4152 return NULL; 4153 } 4154