1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * Copyright 2019 Raptor Engineering, LLC 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 #include "dc.h" 31 32 #include "dcn20_init.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dcn20/dcn20_resource.h" 37 38 #include "dml/dcn2x/dcn2x.h" 39 40 #include "dcn10/dcn10_hubp.h" 41 #include "dcn10/dcn10_ipp.h" 42 #include "dcn20_hubbub.h" 43 #include "dcn20_mpc.h" 44 #include "dcn20_hubp.h" 45 #include "irq/dcn20/irq_service_dcn20.h" 46 #include "dcn20_dpp.h" 47 #include "dcn20_optc.h" 48 #include "dcn20_hwseq.h" 49 #include "dce110/dce110_hw_sequencer.h" 50 #include "dcn10/dcn10_resource.h" 51 #include "dcn20_opp.h" 52 53 #include "dcn20_dsc.h" 54 55 #include "dcn20_link_encoder.h" 56 #include "dcn20_stream_encoder.h" 57 #include "dce/dce_clock_source.h" 58 #include "dce/dce_audio.h" 59 #include "dce/dce_hwseq.h" 60 #include "virtual/virtual_stream_encoder.h" 61 #include "dce110/dce110_resource.h" 62 #include "dml/display_mode_vba.h" 63 #include "dcn20_dccg.h" 64 #include "dcn20_vmid.h" 65 #include "dc_link_ddc.h" 66 #include "dce/dce_panel_cntl.h" 67 68 #include "navi10_ip_offset.h" 69 70 #include "dcn/dcn_2_0_0_offset.h" 71 #include "dcn/dcn_2_0_0_sh_mask.h" 72 #include "dpcs/dpcs_2_0_0_offset.h" 73 #include "dpcs/dpcs_2_0_0_sh_mask.h" 74 75 #include "nbio/nbio_2_3_offset.h" 76 77 #include "dcn20/dcn20_dwb.h" 78 #include "dcn20/dcn20_mmhubbub.h" 79 80 #include "mmhub/mmhub_2_0_0_offset.h" 81 #include "mmhub/mmhub_2_0_0_sh_mask.h" 82 83 #include "reg_helper.h" 84 #include "dce/dce_abm.h" 85 #include "dce/dce_dmcu.h" 86 #include "dce/dce_aux.h" 87 #include "dce/dce_i2c.h" 88 #include "vm_helper.h" 89 90 #include "amdgpu_socbb.h" 91 92 #define DC_LOGGER_INIT(logger) 93 94 struct _vcs_dpi_ip_params_st dcn2_0_ip = { 95 .odm_capable = 1, 96 .gpuvm_enable = 0, 97 .hostvm_enable = 0, 98 .gpuvm_max_page_table_levels = 4, 99 .hostvm_max_page_table_levels = 4, 100 .hostvm_cached_page_table_levels = 0, 101 .pte_group_size_bytes = 2048, 102 .num_dsc = 6, 103 .rob_buffer_size_kbytes = 168, 104 .det_buffer_size_kbytes = 164, 105 .dpte_buffer_size_in_pte_reqs_luma = 84, 106 .pde_proc_buffer_size_64k_reqs = 48, 107 .dpp_output_buffer_pixels = 2560, 108 .opp_output_buffer_lines = 1, 109 .pixel_chunk_size_kbytes = 8, 110 .pte_chunk_size_kbytes = 2, 111 .meta_chunk_size_kbytes = 2, 112 .writeback_chunk_size_kbytes = 2, 113 .line_buffer_size_bits = 789504, 114 .is_line_buffer_bpp_fixed = 0, 115 .line_buffer_fixed_bpp = 0, 116 .dcc_supported = true, 117 .max_line_buffer_lines = 12, 118 .writeback_luma_buffer_size_kbytes = 12, 119 .writeback_chroma_buffer_size_kbytes = 8, 120 .writeback_chroma_line_buffer_width_pixels = 4, 121 .writeback_max_hscl_ratio = 1, 122 .writeback_max_vscl_ratio = 1, 123 .writeback_min_hscl_ratio = 1, 124 .writeback_min_vscl_ratio = 1, 125 .writeback_max_hscl_taps = 12, 126 .writeback_max_vscl_taps = 12, 127 .writeback_line_buffer_luma_buffer_size = 0, 128 .writeback_line_buffer_chroma_buffer_size = 14643, 129 .cursor_buffer_size = 8, 130 .cursor_chunk_size = 2, 131 .max_num_otg = 6, 132 .max_num_dpp = 6, 133 .max_num_wb = 1, 134 .max_dchub_pscl_bw_pix_per_clk = 4, 135 .max_pscl_lb_bw_pix_per_clk = 2, 136 .max_lb_vscl_bw_pix_per_clk = 4, 137 .max_vscl_hscl_bw_pix_per_clk = 4, 138 .max_hscl_ratio = 8, 139 .max_vscl_ratio = 8, 140 .hscl_mults = 4, 141 .vscl_mults = 4, 142 .max_hscl_taps = 8, 143 .max_vscl_taps = 8, 144 .dispclk_ramp_margin_percent = 1, 145 .underscan_factor = 1.10, 146 .min_vblank_lines = 32, // 147 .dppclk_delay_subtotal = 77, // 148 .dppclk_delay_scl_lb_only = 16, 149 .dppclk_delay_scl = 50, 150 .dppclk_delay_cnvc_formatter = 8, 151 .dppclk_delay_cnvc_cursor = 6, 152 .dispclk_delay_subtotal = 87, // 153 .dcfclk_cstate_latency = 10, // SRExitTime 154 .max_inter_dcn_tile_repeaters = 8, 155 .xfc_supported = true, 156 .xfc_fill_bw_overhead_percent = 10.0, 157 .xfc_fill_constant_bytes = 0, 158 .number_of_cursors = 1, 159 }; 160 161 static struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = { 162 .odm_capable = 1, 163 .gpuvm_enable = 0, 164 .hostvm_enable = 0, 165 .gpuvm_max_page_table_levels = 4, 166 .hostvm_max_page_table_levels = 4, 167 .hostvm_cached_page_table_levels = 0, 168 .num_dsc = 5, 169 .rob_buffer_size_kbytes = 168, 170 .det_buffer_size_kbytes = 164, 171 .dpte_buffer_size_in_pte_reqs_luma = 84, 172 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo 173 .dpp_output_buffer_pixels = 2560, 174 .opp_output_buffer_lines = 1, 175 .pixel_chunk_size_kbytes = 8, 176 .pte_enable = 1, 177 .max_page_table_levels = 4, 178 .pte_chunk_size_kbytes = 2, 179 .meta_chunk_size_kbytes = 2, 180 .writeback_chunk_size_kbytes = 2, 181 .line_buffer_size_bits = 789504, 182 .is_line_buffer_bpp_fixed = 0, 183 .line_buffer_fixed_bpp = 0, 184 .dcc_supported = true, 185 .max_line_buffer_lines = 12, 186 .writeback_luma_buffer_size_kbytes = 12, 187 .writeback_chroma_buffer_size_kbytes = 8, 188 .writeback_chroma_line_buffer_width_pixels = 4, 189 .writeback_max_hscl_ratio = 1, 190 .writeback_max_vscl_ratio = 1, 191 .writeback_min_hscl_ratio = 1, 192 .writeback_min_vscl_ratio = 1, 193 .writeback_max_hscl_taps = 12, 194 .writeback_max_vscl_taps = 12, 195 .writeback_line_buffer_luma_buffer_size = 0, 196 .writeback_line_buffer_chroma_buffer_size = 14643, 197 .cursor_buffer_size = 8, 198 .cursor_chunk_size = 2, 199 .max_num_otg = 5, 200 .max_num_dpp = 5, 201 .max_num_wb = 1, 202 .max_dchub_pscl_bw_pix_per_clk = 4, 203 .max_pscl_lb_bw_pix_per_clk = 2, 204 .max_lb_vscl_bw_pix_per_clk = 4, 205 .max_vscl_hscl_bw_pix_per_clk = 4, 206 .max_hscl_ratio = 8, 207 .max_vscl_ratio = 8, 208 .hscl_mults = 4, 209 .vscl_mults = 4, 210 .max_hscl_taps = 8, 211 .max_vscl_taps = 8, 212 .dispclk_ramp_margin_percent = 1, 213 .underscan_factor = 1.10, 214 .min_vblank_lines = 32, // 215 .dppclk_delay_subtotal = 77, // 216 .dppclk_delay_scl_lb_only = 16, 217 .dppclk_delay_scl = 50, 218 .dppclk_delay_cnvc_formatter = 8, 219 .dppclk_delay_cnvc_cursor = 6, 220 .dispclk_delay_subtotal = 87, // 221 .dcfclk_cstate_latency = 10, // SRExitTime 222 .max_inter_dcn_tile_repeaters = 8, 223 .xfc_supported = true, 224 .xfc_fill_bw_overhead_percent = 10.0, 225 .xfc_fill_constant_bytes = 0, 226 .ptoi_supported = 0, 227 .number_of_cursors = 1, 228 }; 229 230 static struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { 231 /* Defaults that get patched on driver load from firmware. */ 232 .clock_limits = { 233 { 234 .state = 0, 235 .dcfclk_mhz = 560.0, 236 .fabricclk_mhz = 560.0, 237 .dispclk_mhz = 513.0, 238 .dppclk_mhz = 513.0, 239 .phyclk_mhz = 540.0, 240 .socclk_mhz = 560.0, 241 .dscclk_mhz = 171.0, 242 .dram_speed_mts = 8960.0, 243 }, 244 { 245 .state = 1, 246 .dcfclk_mhz = 694.0, 247 .fabricclk_mhz = 694.0, 248 .dispclk_mhz = 642.0, 249 .dppclk_mhz = 642.0, 250 .phyclk_mhz = 600.0, 251 .socclk_mhz = 694.0, 252 .dscclk_mhz = 214.0, 253 .dram_speed_mts = 11104.0, 254 }, 255 { 256 .state = 2, 257 .dcfclk_mhz = 875.0, 258 .fabricclk_mhz = 875.0, 259 .dispclk_mhz = 734.0, 260 .dppclk_mhz = 734.0, 261 .phyclk_mhz = 810.0, 262 .socclk_mhz = 875.0, 263 .dscclk_mhz = 245.0, 264 .dram_speed_mts = 14000.0, 265 }, 266 { 267 .state = 3, 268 .dcfclk_mhz = 1000.0, 269 .fabricclk_mhz = 1000.0, 270 .dispclk_mhz = 1100.0, 271 .dppclk_mhz = 1100.0, 272 .phyclk_mhz = 810.0, 273 .socclk_mhz = 1000.0, 274 .dscclk_mhz = 367.0, 275 .dram_speed_mts = 16000.0, 276 }, 277 { 278 .state = 4, 279 .dcfclk_mhz = 1200.0, 280 .fabricclk_mhz = 1200.0, 281 .dispclk_mhz = 1284.0, 282 .dppclk_mhz = 1284.0, 283 .phyclk_mhz = 810.0, 284 .socclk_mhz = 1200.0, 285 .dscclk_mhz = 428.0, 286 .dram_speed_mts = 16000.0, 287 }, 288 /*Extra state, no dispclk ramping*/ 289 { 290 .state = 5, 291 .dcfclk_mhz = 1200.0, 292 .fabricclk_mhz = 1200.0, 293 .dispclk_mhz = 1284.0, 294 .dppclk_mhz = 1284.0, 295 .phyclk_mhz = 810.0, 296 .socclk_mhz = 1200.0, 297 .dscclk_mhz = 428.0, 298 .dram_speed_mts = 16000.0, 299 }, 300 }, 301 .num_states = 5, 302 .sr_exit_time_us = 8.6, 303 .sr_enter_plus_exit_time_us = 10.9, 304 .urgent_latency_us = 4.0, 305 .urgent_latency_pixel_data_only_us = 4.0, 306 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 307 .urgent_latency_vm_data_only_us = 4.0, 308 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 309 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 310 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 311 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0, 312 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0, 313 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 314 .max_avg_sdp_bw_use_normal_percent = 40.0, 315 .max_avg_dram_bw_use_normal_percent = 40.0, 316 .writeback_latency_us = 12.0, 317 .ideal_dram_bw_after_urgent_percent = 40.0, 318 .max_request_size_bytes = 256, 319 .dram_channel_width_bytes = 2, 320 .fabric_datapath_to_dcn_data_return_bytes = 64, 321 .dcn_downspread_percent = 0.5, 322 .downspread_percent = 0.38, 323 .dram_page_open_time_ns = 50.0, 324 .dram_rw_turnaround_time_ns = 17.5, 325 .dram_return_buffer_per_channel_bytes = 8192, 326 .round_trip_ping_latency_dcfclk_cycles = 131, 327 .urgent_out_of_order_return_per_channel_bytes = 256, 328 .channel_interleave_bytes = 256, 329 .num_banks = 8, 330 .num_chans = 16, 331 .vmm_page_size_bytes = 4096, 332 .dram_clock_change_latency_us = 404.0, 333 .dummy_pstate_latency_us = 5.0, 334 .writeback_dram_clock_change_latency_us = 23.0, 335 .return_bus_width_bytes = 64, 336 .dispclk_dppclk_vco_speed_mhz = 3850, 337 .xfc_bus_transport_time_us = 20, 338 .xfc_xbuf_latency_tolerance_us = 4, 339 .use_urgent_burst_bw = 0 340 }; 341 342 static struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = { 343 .clock_limits = { 344 { 345 .state = 0, 346 .dcfclk_mhz = 560.0, 347 .fabricclk_mhz = 560.0, 348 .dispclk_mhz = 513.0, 349 .dppclk_mhz = 513.0, 350 .phyclk_mhz = 540.0, 351 .socclk_mhz = 560.0, 352 .dscclk_mhz = 171.0, 353 .dram_speed_mts = 8960.0, 354 }, 355 { 356 .state = 1, 357 .dcfclk_mhz = 694.0, 358 .fabricclk_mhz = 694.0, 359 .dispclk_mhz = 642.0, 360 .dppclk_mhz = 642.0, 361 .phyclk_mhz = 600.0, 362 .socclk_mhz = 694.0, 363 .dscclk_mhz = 214.0, 364 .dram_speed_mts = 11104.0, 365 }, 366 { 367 .state = 2, 368 .dcfclk_mhz = 875.0, 369 .fabricclk_mhz = 875.0, 370 .dispclk_mhz = 734.0, 371 .dppclk_mhz = 734.0, 372 .phyclk_mhz = 810.0, 373 .socclk_mhz = 875.0, 374 .dscclk_mhz = 245.0, 375 .dram_speed_mts = 14000.0, 376 }, 377 { 378 .state = 3, 379 .dcfclk_mhz = 1000.0, 380 .fabricclk_mhz = 1000.0, 381 .dispclk_mhz = 1100.0, 382 .dppclk_mhz = 1100.0, 383 .phyclk_mhz = 810.0, 384 .socclk_mhz = 1000.0, 385 .dscclk_mhz = 367.0, 386 .dram_speed_mts = 16000.0, 387 }, 388 { 389 .state = 4, 390 .dcfclk_mhz = 1200.0, 391 .fabricclk_mhz = 1200.0, 392 .dispclk_mhz = 1284.0, 393 .dppclk_mhz = 1284.0, 394 .phyclk_mhz = 810.0, 395 .socclk_mhz = 1200.0, 396 .dscclk_mhz = 428.0, 397 .dram_speed_mts = 16000.0, 398 }, 399 /*Extra state, no dispclk ramping*/ 400 { 401 .state = 5, 402 .dcfclk_mhz = 1200.0, 403 .fabricclk_mhz = 1200.0, 404 .dispclk_mhz = 1284.0, 405 .dppclk_mhz = 1284.0, 406 .phyclk_mhz = 810.0, 407 .socclk_mhz = 1200.0, 408 .dscclk_mhz = 428.0, 409 .dram_speed_mts = 16000.0, 410 }, 411 }, 412 .num_states = 5, 413 .sr_exit_time_us = 11.6, 414 .sr_enter_plus_exit_time_us = 13.9, 415 .urgent_latency_us = 4.0, 416 .urgent_latency_pixel_data_only_us = 4.0, 417 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 418 .urgent_latency_vm_data_only_us = 4.0, 419 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 420 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 421 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 422 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0, 423 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0, 424 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 425 .max_avg_sdp_bw_use_normal_percent = 40.0, 426 .max_avg_dram_bw_use_normal_percent = 40.0, 427 .writeback_latency_us = 12.0, 428 .ideal_dram_bw_after_urgent_percent = 40.0, 429 .max_request_size_bytes = 256, 430 .dram_channel_width_bytes = 2, 431 .fabric_datapath_to_dcn_data_return_bytes = 64, 432 .dcn_downspread_percent = 0.5, 433 .downspread_percent = 0.38, 434 .dram_page_open_time_ns = 50.0, 435 .dram_rw_turnaround_time_ns = 17.5, 436 .dram_return_buffer_per_channel_bytes = 8192, 437 .round_trip_ping_latency_dcfclk_cycles = 131, 438 .urgent_out_of_order_return_per_channel_bytes = 256, 439 .channel_interleave_bytes = 256, 440 .num_banks = 8, 441 .num_chans = 8, 442 .vmm_page_size_bytes = 4096, 443 .dram_clock_change_latency_us = 404.0, 444 .dummy_pstate_latency_us = 5.0, 445 .writeback_dram_clock_change_latency_us = 23.0, 446 .return_bus_width_bytes = 64, 447 .dispclk_dppclk_vco_speed_mhz = 3850, 448 .xfc_bus_transport_time_us = 20, 449 .xfc_xbuf_latency_tolerance_us = 4, 450 .use_urgent_burst_bw = 0 451 }; 452 453 static struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 }; 454 455 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 456 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 457 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 458 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 459 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 460 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 461 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 462 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 463 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 464 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 465 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 466 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 467 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 468 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 469 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 470 #endif 471 472 473 enum dcn20_clk_src_array_id { 474 DCN20_CLK_SRC_PLL0, 475 DCN20_CLK_SRC_PLL1, 476 DCN20_CLK_SRC_PLL2, 477 DCN20_CLK_SRC_PLL3, 478 DCN20_CLK_SRC_PLL4, 479 DCN20_CLK_SRC_PLL5, 480 DCN20_CLK_SRC_TOTAL 481 }; 482 483 /* begin ********************* 484 * macros to expend register list macro defined in HW object header file */ 485 486 /* DCN */ 487 /* TODO awful hack. fixup dcn20_dwb.h */ 488 #undef BASE_INNER 489 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 490 491 #define BASE(seg) BASE_INNER(seg) 492 493 #define SR(reg_name)\ 494 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 495 mm ## reg_name 496 497 #define SRI(reg_name, block, id)\ 498 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 499 mm ## block ## id ## _ ## reg_name 500 501 #define SRIR(var_name, reg_name, block, id)\ 502 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 503 mm ## block ## id ## _ ## reg_name 504 505 #define SRII(reg_name, block, id)\ 506 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 507 mm ## block ## id ## _ ## reg_name 508 509 #define DCCG_SRII(reg_name, block, id)\ 510 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 511 mm ## block ## id ## _ ## reg_name 512 513 #define VUPDATE_SRII(reg_name, block, id)\ 514 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 515 mm ## reg_name ## _ ## block ## id 516 517 /* NBIO */ 518 #define NBIO_BASE_INNER(seg) \ 519 NBIO_BASE__INST0_SEG ## seg 520 521 #define NBIO_BASE(seg) \ 522 NBIO_BASE_INNER(seg) 523 524 #define NBIO_SR(reg_name)\ 525 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 526 mm ## reg_name 527 528 /* MMHUB */ 529 #define MMHUB_BASE_INNER(seg) \ 530 MMHUB_BASE__INST0_SEG ## seg 531 532 #define MMHUB_BASE(seg) \ 533 MMHUB_BASE_INNER(seg) 534 535 #define MMHUB_SR(reg_name)\ 536 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 537 mmMM ## reg_name 538 539 static const struct bios_registers bios_regs = { 540 NBIO_SR(BIOS_SCRATCH_3), 541 NBIO_SR(BIOS_SCRATCH_6) 542 }; 543 544 #define clk_src_regs(index, pllid)\ 545 [index] = {\ 546 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\ 547 } 548 549 static const struct dce110_clk_src_regs clk_src_regs[] = { 550 clk_src_regs(0, A), 551 clk_src_regs(1, B), 552 clk_src_regs(2, C), 553 clk_src_regs(3, D), 554 clk_src_regs(4, E), 555 clk_src_regs(5, F) 556 }; 557 558 static const struct dce110_clk_src_shift cs_shift = { 559 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 560 }; 561 562 static const struct dce110_clk_src_mask cs_mask = { 563 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 564 }; 565 566 static const struct dce_dmcu_registers dmcu_regs = { 567 DMCU_DCN10_REG_LIST() 568 }; 569 570 static const struct dce_dmcu_shift dmcu_shift = { 571 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 572 }; 573 574 static const struct dce_dmcu_mask dmcu_mask = { 575 DMCU_MASK_SH_LIST_DCN10(_MASK) 576 }; 577 578 static const struct dce_abm_registers abm_regs = { 579 ABM_DCN20_REG_LIST() 580 }; 581 582 static const struct dce_abm_shift abm_shift = { 583 ABM_MASK_SH_LIST_DCN20(__SHIFT) 584 }; 585 586 static const struct dce_abm_mask abm_mask = { 587 ABM_MASK_SH_LIST_DCN20(_MASK) 588 }; 589 590 #define audio_regs(id)\ 591 [id] = {\ 592 AUD_COMMON_REG_LIST(id)\ 593 } 594 595 static const struct dce_audio_registers audio_regs[] = { 596 audio_regs(0), 597 audio_regs(1), 598 audio_regs(2), 599 audio_regs(3), 600 audio_regs(4), 601 audio_regs(5), 602 audio_regs(6), 603 }; 604 605 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 606 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 607 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 608 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 609 610 static const struct dce_audio_shift audio_shift = { 611 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 612 }; 613 614 static const struct dce_audio_mask audio_mask = { 615 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 616 }; 617 618 #define stream_enc_regs(id)\ 619 [id] = {\ 620 SE_DCN2_REG_LIST(id)\ 621 } 622 623 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 624 stream_enc_regs(0), 625 stream_enc_regs(1), 626 stream_enc_regs(2), 627 stream_enc_regs(3), 628 stream_enc_regs(4), 629 stream_enc_regs(5), 630 }; 631 632 static const struct dcn10_stream_encoder_shift se_shift = { 633 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) 634 }; 635 636 static const struct dcn10_stream_encoder_mask se_mask = { 637 SE_COMMON_MASK_SH_LIST_DCN20(_MASK) 638 }; 639 640 641 #define aux_regs(id)\ 642 [id] = {\ 643 DCN2_AUX_REG_LIST(id)\ 644 } 645 646 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 647 aux_regs(0), 648 aux_regs(1), 649 aux_regs(2), 650 aux_regs(3), 651 aux_regs(4), 652 aux_regs(5) 653 }; 654 655 #define hpd_regs(id)\ 656 [id] = {\ 657 HPD_REG_LIST(id)\ 658 } 659 660 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 661 hpd_regs(0), 662 hpd_regs(1), 663 hpd_regs(2), 664 hpd_regs(3), 665 hpd_regs(4), 666 hpd_regs(5) 667 }; 668 669 #define link_regs(id, phyid)\ 670 [id] = {\ 671 LE_DCN10_REG_LIST(id), \ 672 UNIPHY_DCN2_REG_LIST(phyid), \ 673 DPCS_DCN2_REG_LIST(id), \ 674 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 675 } 676 677 static const struct dcn10_link_enc_registers link_enc_regs[] = { 678 link_regs(0, A), 679 link_regs(1, B), 680 link_regs(2, C), 681 link_regs(3, D), 682 link_regs(4, E), 683 link_regs(5, F) 684 }; 685 686 static const struct dcn10_link_enc_shift le_shift = { 687 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\ 688 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 689 }; 690 691 static const struct dcn10_link_enc_mask le_mask = { 692 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\ 693 DPCS_DCN2_MASK_SH_LIST(_MASK) 694 }; 695 696 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 697 { DCN_PANEL_CNTL_REG_LIST() } 698 }; 699 700 static const struct dce_panel_cntl_shift panel_cntl_shift = { 701 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 702 }; 703 704 static const struct dce_panel_cntl_mask panel_cntl_mask = { 705 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 706 }; 707 708 #define ipp_regs(id)\ 709 [id] = {\ 710 IPP_REG_LIST_DCN20(id),\ 711 } 712 713 static const struct dcn10_ipp_registers ipp_regs[] = { 714 ipp_regs(0), 715 ipp_regs(1), 716 ipp_regs(2), 717 ipp_regs(3), 718 ipp_regs(4), 719 ipp_regs(5), 720 }; 721 722 static const struct dcn10_ipp_shift ipp_shift = { 723 IPP_MASK_SH_LIST_DCN20(__SHIFT) 724 }; 725 726 static const struct dcn10_ipp_mask ipp_mask = { 727 IPP_MASK_SH_LIST_DCN20(_MASK), 728 }; 729 730 #define opp_regs(id)\ 731 [id] = {\ 732 OPP_REG_LIST_DCN20(id),\ 733 } 734 735 static const struct dcn20_opp_registers opp_regs[] = { 736 opp_regs(0), 737 opp_regs(1), 738 opp_regs(2), 739 opp_regs(3), 740 opp_regs(4), 741 opp_regs(5), 742 }; 743 744 static const struct dcn20_opp_shift opp_shift = { 745 OPP_MASK_SH_LIST_DCN20(__SHIFT) 746 }; 747 748 static const struct dcn20_opp_mask opp_mask = { 749 OPP_MASK_SH_LIST_DCN20(_MASK) 750 }; 751 752 #define aux_engine_regs(id)\ 753 [id] = {\ 754 AUX_COMMON_REG_LIST0(id), \ 755 .AUXN_IMPCAL = 0, \ 756 .AUXP_IMPCAL = 0, \ 757 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 758 } 759 760 static const struct dce110_aux_registers aux_engine_regs[] = { 761 aux_engine_regs(0), 762 aux_engine_regs(1), 763 aux_engine_regs(2), 764 aux_engine_regs(3), 765 aux_engine_regs(4), 766 aux_engine_regs(5) 767 }; 768 769 #define tf_regs(id)\ 770 [id] = {\ 771 TF_REG_LIST_DCN20(id),\ 772 TF_REG_LIST_DCN20_COMMON_APPEND(id),\ 773 } 774 775 static const struct dcn2_dpp_registers tf_regs[] = { 776 tf_regs(0), 777 tf_regs(1), 778 tf_regs(2), 779 tf_regs(3), 780 tf_regs(4), 781 tf_regs(5), 782 }; 783 784 static const struct dcn2_dpp_shift tf_shift = { 785 TF_REG_LIST_SH_MASK_DCN20(__SHIFT), 786 TF_DEBUG_REG_LIST_SH_DCN20 787 }; 788 789 static const struct dcn2_dpp_mask tf_mask = { 790 TF_REG_LIST_SH_MASK_DCN20(_MASK), 791 TF_DEBUG_REG_LIST_MASK_DCN20 792 }; 793 794 #define dwbc_regs_dcn2(id)\ 795 [id] = {\ 796 DWBC_COMMON_REG_LIST_DCN2_0(id),\ 797 } 798 799 static const struct dcn20_dwbc_registers dwbc20_regs[] = { 800 dwbc_regs_dcn2(0), 801 }; 802 803 static const struct dcn20_dwbc_shift dwbc20_shift = { 804 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 805 }; 806 807 static const struct dcn20_dwbc_mask dwbc20_mask = { 808 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 809 }; 810 811 #define mcif_wb_regs_dcn2(id)\ 812 [id] = {\ 813 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\ 814 } 815 816 static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = { 817 mcif_wb_regs_dcn2(0), 818 }; 819 820 static const struct dcn20_mmhubbub_shift mcif_wb20_shift = { 821 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 822 }; 823 824 static const struct dcn20_mmhubbub_mask mcif_wb20_mask = { 825 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 826 }; 827 828 static const struct dcn20_mpc_registers mpc_regs = { 829 MPC_REG_LIST_DCN2_0(0), 830 MPC_REG_LIST_DCN2_0(1), 831 MPC_REG_LIST_DCN2_0(2), 832 MPC_REG_LIST_DCN2_0(3), 833 MPC_REG_LIST_DCN2_0(4), 834 MPC_REG_LIST_DCN2_0(5), 835 MPC_OUT_MUX_REG_LIST_DCN2_0(0), 836 MPC_OUT_MUX_REG_LIST_DCN2_0(1), 837 MPC_OUT_MUX_REG_LIST_DCN2_0(2), 838 MPC_OUT_MUX_REG_LIST_DCN2_0(3), 839 MPC_OUT_MUX_REG_LIST_DCN2_0(4), 840 MPC_OUT_MUX_REG_LIST_DCN2_0(5), 841 MPC_DBG_REG_LIST_DCN2_0() 842 }; 843 844 static const struct dcn20_mpc_shift mpc_shift = { 845 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT), 846 MPC_DEBUG_REG_LIST_SH_DCN20 847 }; 848 849 static const struct dcn20_mpc_mask mpc_mask = { 850 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK), 851 MPC_DEBUG_REG_LIST_MASK_DCN20 852 }; 853 854 #define tg_regs(id)\ 855 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)} 856 857 858 static const struct dcn_optc_registers tg_regs[] = { 859 tg_regs(0), 860 tg_regs(1), 861 tg_regs(2), 862 tg_regs(3), 863 tg_regs(4), 864 tg_regs(5) 865 }; 866 867 static const struct dcn_optc_shift tg_shift = { 868 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 869 }; 870 871 static const struct dcn_optc_mask tg_mask = { 872 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 873 }; 874 875 #define hubp_regs(id)\ 876 [id] = {\ 877 HUBP_REG_LIST_DCN20(id)\ 878 } 879 880 static const struct dcn_hubp2_registers hubp_regs[] = { 881 hubp_regs(0), 882 hubp_regs(1), 883 hubp_regs(2), 884 hubp_regs(3), 885 hubp_regs(4), 886 hubp_regs(5) 887 }; 888 889 static const struct dcn_hubp2_shift hubp_shift = { 890 HUBP_MASK_SH_LIST_DCN20(__SHIFT) 891 }; 892 893 static const struct dcn_hubp2_mask hubp_mask = { 894 HUBP_MASK_SH_LIST_DCN20(_MASK) 895 }; 896 897 static const struct dcn_hubbub_registers hubbub_reg = { 898 HUBBUB_REG_LIST_DCN20(0) 899 }; 900 901 static const struct dcn_hubbub_shift hubbub_shift = { 902 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT) 903 }; 904 905 static const struct dcn_hubbub_mask hubbub_mask = { 906 HUBBUB_MASK_SH_LIST_DCN20(_MASK) 907 }; 908 909 #define vmid_regs(id)\ 910 [id] = {\ 911 DCN20_VMID_REG_LIST(id)\ 912 } 913 914 static const struct dcn_vmid_registers vmid_regs[] = { 915 vmid_regs(0), 916 vmid_regs(1), 917 vmid_regs(2), 918 vmid_regs(3), 919 vmid_regs(4), 920 vmid_regs(5), 921 vmid_regs(6), 922 vmid_regs(7), 923 vmid_regs(8), 924 vmid_regs(9), 925 vmid_regs(10), 926 vmid_regs(11), 927 vmid_regs(12), 928 vmid_regs(13), 929 vmid_regs(14), 930 vmid_regs(15) 931 }; 932 933 static const struct dcn20_vmid_shift vmid_shifts = { 934 DCN20_VMID_MASK_SH_LIST(__SHIFT) 935 }; 936 937 static const struct dcn20_vmid_mask vmid_masks = { 938 DCN20_VMID_MASK_SH_LIST(_MASK) 939 }; 940 941 static const struct dce110_aux_registers_shift aux_shift = { 942 DCN_AUX_MASK_SH_LIST(__SHIFT) 943 }; 944 945 static const struct dce110_aux_registers_mask aux_mask = { 946 DCN_AUX_MASK_SH_LIST(_MASK) 947 }; 948 949 static int map_transmitter_id_to_phy_instance( 950 enum transmitter transmitter) 951 { 952 switch (transmitter) { 953 case TRANSMITTER_UNIPHY_A: 954 return 0; 955 break; 956 case TRANSMITTER_UNIPHY_B: 957 return 1; 958 break; 959 case TRANSMITTER_UNIPHY_C: 960 return 2; 961 break; 962 case TRANSMITTER_UNIPHY_D: 963 return 3; 964 break; 965 case TRANSMITTER_UNIPHY_E: 966 return 4; 967 break; 968 case TRANSMITTER_UNIPHY_F: 969 return 5; 970 break; 971 default: 972 ASSERT(0); 973 return 0; 974 } 975 } 976 977 #define dsc_regsDCN20(id)\ 978 [id] = {\ 979 DSC_REG_LIST_DCN20(id)\ 980 } 981 982 static const struct dcn20_dsc_registers dsc_regs[] = { 983 dsc_regsDCN20(0), 984 dsc_regsDCN20(1), 985 dsc_regsDCN20(2), 986 dsc_regsDCN20(3), 987 dsc_regsDCN20(4), 988 dsc_regsDCN20(5) 989 }; 990 991 static const struct dcn20_dsc_shift dsc_shift = { 992 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 993 }; 994 995 static const struct dcn20_dsc_mask dsc_mask = { 996 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 997 }; 998 999 static const struct dccg_registers dccg_regs = { 1000 DCCG_REG_LIST_DCN2() 1001 }; 1002 1003 static const struct dccg_shift dccg_shift = { 1004 DCCG_MASK_SH_LIST_DCN2(__SHIFT) 1005 }; 1006 1007 static const struct dccg_mask dccg_mask = { 1008 DCCG_MASK_SH_LIST_DCN2(_MASK) 1009 }; 1010 1011 static const struct resource_caps res_cap_nv10 = { 1012 .num_timing_generator = 6, 1013 .num_opp = 6, 1014 .num_video_plane = 6, 1015 .num_audio = 7, 1016 .num_stream_encoder = 6, 1017 .num_pll = 6, 1018 .num_dwb = 1, 1019 .num_ddc = 6, 1020 .num_vmid = 16, 1021 .num_dsc = 6, 1022 }; 1023 1024 static const struct dc_plane_cap plane_cap = { 1025 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 1026 .blends_with_above = true, 1027 .blends_with_below = true, 1028 .per_pixel_alpha = true, 1029 1030 .pixel_format_support = { 1031 .argb8888 = true, 1032 .nv12 = true, 1033 .fp16 = true, 1034 .p010 = true 1035 }, 1036 1037 .max_upscale_factor = { 1038 .argb8888 = 16000, 1039 .nv12 = 16000, 1040 .fp16 = 1 1041 }, 1042 1043 .max_downscale_factor = { 1044 .argb8888 = 250, 1045 .nv12 = 250, 1046 .fp16 = 1 1047 }, 1048 16, 1049 16 1050 }; 1051 static const struct resource_caps res_cap_nv14 = { 1052 .num_timing_generator = 5, 1053 .num_opp = 5, 1054 .num_video_plane = 5, 1055 .num_audio = 6, 1056 .num_stream_encoder = 5, 1057 .num_pll = 5, 1058 .num_dwb = 1, 1059 .num_ddc = 5, 1060 .num_vmid = 16, 1061 .num_dsc = 5, 1062 }; 1063 1064 static const struct dc_debug_options debug_defaults_drv = { 1065 .disable_dmcu = false, 1066 .force_abm_enable = false, 1067 .timing_trace = false, 1068 .clock_trace = true, 1069 .disable_pplib_clock_request = true, 1070 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 1071 .force_single_disp_pipe_split = false, 1072 .disable_dcc = DCC_ENABLE, 1073 .vsr_support = true, 1074 .performance_trace = false, 1075 .max_downscale_src_width = 5120,/*upto 5K*/ 1076 .disable_pplib_wm_range = false, 1077 .scl_reset_length10 = true, 1078 .sanity_checks = false, 1079 .underflow_assert_delay_us = 0xFFFFFFFF, 1080 }; 1081 1082 static const struct dc_debug_options debug_defaults_diags = { 1083 .disable_dmcu = false, 1084 .force_abm_enable = false, 1085 .timing_trace = true, 1086 .clock_trace = true, 1087 .disable_dpp_power_gate = true, 1088 .disable_hubp_power_gate = true, 1089 .disable_clock_gate = true, 1090 .disable_pplib_clock_request = true, 1091 .disable_pplib_wm_range = true, 1092 .disable_stutter = true, 1093 .scl_reset_length10 = true, 1094 .underflow_assert_delay_us = 0xFFFFFFFF, 1095 .enable_tri_buf = true, 1096 }; 1097 1098 void dcn20_dpp_destroy(struct dpp **dpp) 1099 { 1100 kfree(TO_DCN20_DPP(*dpp)); 1101 *dpp = NULL; 1102 } 1103 1104 struct dpp *dcn20_dpp_create( 1105 struct dc_context *ctx, 1106 uint32_t inst) 1107 { 1108 struct dcn20_dpp *dpp = 1109 kzalloc(sizeof(struct dcn20_dpp), GFP_ATOMIC); 1110 1111 if (!dpp) 1112 return NULL; 1113 1114 if (dpp2_construct(dpp, ctx, inst, 1115 &tf_regs[inst], &tf_shift, &tf_mask)) 1116 return &dpp->base; 1117 1118 BREAK_TO_DEBUGGER(); 1119 kfree(dpp); 1120 return NULL; 1121 } 1122 1123 struct input_pixel_processor *dcn20_ipp_create( 1124 struct dc_context *ctx, uint32_t inst) 1125 { 1126 struct dcn10_ipp *ipp = 1127 kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC); 1128 1129 if (!ipp) { 1130 BREAK_TO_DEBUGGER(); 1131 return NULL; 1132 } 1133 1134 dcn20_ipp_construct(ipp, ctx, inst, 1135 &ipp_regs[inst], &ipp_shift, &ipp_mask); 1136 return &ipp->base; 1137 } 1138 1139 1140 struct output_pixel_processor *dcn20_opp_create( 1141 struct dc_context *ctx, uint32_t inst) 1142 { 1143 struct dcn20_opp *opp = 1144 kzalloc(sizeof(struct dcn20_opp), GFP_ATOMIC); 1145 1146 if (!opp) { 1147 BREAK_TO_DEBUGGER(); 1148 return NULL; 1149 } 1150 1151 dcn20_opp_construct(opp, ctx, inst, 1152 &opp_regs[inst], &opp_shift, &opp_mask); 1153 return &opp->base; 1154 } 1155 1156 struct dce_aux *dcn20_aux_engine_create( 1157 struct dc_context *ctx, 1158 uint32_t inst) 1159 { 1160 struct aux_engine_dce110 *aux_engine = 1161 kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC); 1162 1163 if (!aux_engine) 1164 return NULL; 1165 1166 dce110_aux_engine_construct(aux_engine, ctx, inst, 1167 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1168 &aux_engine_regs[inst], 1169 &aux_mask, 1170 &aux_shift, 1171 ctx->dc->caps.extended_aux_timeout_support); 1172 1173 return &aux_engine->base; 1174 } 1175 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 1176 1177 static const struct dce_i2c_registers i2c_hw_regs[] = { 1178 i2c_inst_regs(1), 1179 i2c_inst_regs(2), 1180 i2c_inst_regs(3), 1181 i2c_inst_regs(4), 1182 i2c_inst_regs(5), 1183 i2c_inst_regs(6), 1184 }; 1185 1186 static const struct dce_i2c_shift i2c_shifts = { 1187 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 1188 }; 1189 1190 static const struct dce_i2c_mask i2c_masks = { 1191 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 1192 }; 1193 1194 struct dce_i2c_hw *dcn20_i2c_hw_create( 1195 struct dc_context *ctx, 1196 uint32_t inst) 1197 { 1198 struct dce_i2c_hw *dce_i2c_hw = 1199 kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC); 1200 1201 if (!dce_i2c_hw) 1202 return NULL; 1203 1204 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1205 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1206 1207 return dce_i2c_hw; 1208 } 1209 struct mpc *dcn20_mpc_create(struct dc_context *ctx) 1210 { 1211 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), 1212 GFP_ATOMIC); 1213 1214 if (!mpc20) 1215 return NULL; 1216 1217 dcn20_mpc_construct(mpc20, ctx, 1218 &mpc_regs, 1219 &mpc_shift, 1220 &mpc_mask, 1221 6); 1222 1223 return &mpc20->base; 1224 } 1225 1226 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx) 1227 { 1228 int i; 1229 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), 1230 GFP_ATOMIC); 1231 1232 if (!hubbub) 1233 return NULL; 1234 1235 hubbub2_construct(hubbub, ctx, 1236 &hubbub_reg, 1237 &hubbub_shift, 1238 &hubbub_mask); 1239 1240 for (i = 0; i < res_cap_nv10.num_vmid; i++) { 1241 struct dcn20_vmid *vmid = &hubbub->vmid[i]; 1242 1243 vmid->ctx = ctx; 1244 1245 vmid->regs = &vmid_regs[i]; 1246 vmid->shifts = &vmid_shifts; 1247 vmid->masks = &vmid_masks; 1248 } 1249 1250 return &hubbub->base; 1251 } 1252 1253 struct timing_generator *dcn20_timing_generator_create( 1254 struct dc_context *ctx, 1255 uint32_t instance) 1256 { 1257 struct optc *tgn10 = 1258 kzalloc(sizeof(struct optc), GFP_ATOMIC); 1259 1260 if (!tgn10) 1261 return NULL; 1262 1263 tgn10->base.inst = instance; 1264 tgn10->base.ctx = ctx; 1265 1266 tgn10->tg_regs = &tg_regs[instance]; 1267 tgn10->tg_shift = &tg_shift; 1268 tgn10->tg_mask = &tg_mask; 1269 1270 dcn20_timing_generator_init(tgn10); 1271 1272 return &tgn10->base; 1273 } 1274 1275 static const struct encoder_feature_support link_enc_feature = { 1276 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1277 .max_hdmi_pixel_clock = 600000, 1278 .hdmi_ycbcr420_supported = true, 1279 .dp_ycbcr420_supported = true, 1280 .fec_supported = true, 1281 .flags.bits.IS_HBR2_CAPABLE = true, 1282 .flags.bits.IS_HBR3_CAPABLE = true, 1283 .flags.bits.IS_TPS3_CAPABLE = true, 1284 .flags.bits.IS_TPS4_CAPABLE = true 1285 }; 1286 1287 struct link_encoder *dcn20_link_encoder_create( 1288 const struct encoder_init_data *enc_init_data) 1289 { 1290 struct dcn20_link_encoder *enc20 = 1291 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1292 int link_regs_id; 1293 1294 if (!enc20) 1295 return NULL; 1296 1297 link_regs_id = 1298 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 1299 1300 dcn20_link_encoder_construct(enc20, 1301 enc_init_data, 1302 &link_enc_feature, 1303 &link_enc_regs[link_regs_id], 1304 &link_enc_aux_regs[enc_init_data->channel - 1], 1305 &link_enc_hpd_regs[enc_init_data->hpd_source], 1306 &le_shift, 1307 &le_mask); 1308 1309 return &enc20->enc10.base; 1310 } 1311 1312 static struct panel_cntl *dcn20_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1313 { 1314 struct dce_panel_cntl *panel_cntl = 1315 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 1316 1317 if (!panel_cntl) 1318 return NULL; 1319 1320 dce_panel_cntl_construct(panel_cntl, 1321 init_data, 1322 &panel_cntl_regs[init_data->inst], 1323 &panel_cntl_shift, 1324 &panel_cntl_mask); 1325 1326 return &panel_cntl->base; 1327 } 1328 1329 static struct clock_source *dcn20_clock_source_create( 1330 struct dc_context *ctx, 1331 struct dc_bios *bios, 1332 enum clock_source_id id, 1333 const struct dce110_clk_src_regs *regs, 1334 bool dp_clk_src) 1335 { 1336 struct dce110_clk_src *clk_src = 1337 kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC); 1338 1339 if (!clk_src) 1340 return NULL; 1341 1342 if (dcn20_clk_src_construct(clk_src, ctx, bios, id, 1343 regs, &cs_shift, &cs_mask)) { 1344 clk_src->base.dp_clk_src = dp_clk_src; 1345 return &clk_src->base; 1346 } 1347 1348 kfree(clk_src); 1349 BREAK_TO_DEBUGGER(); 1350 return NULL; 1351 } 1352 1353 static void read_dce_straps( 1354 struct dc_context *ctx, 1355 struct resource_straps *straps) 1356 { 1357 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1358 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1359 } 1360 1361 static struct audio *dcn20_create_audio( 1362 struct dc_context *ctx, unsigned int inst) 1363 { 1364 return dce_audio_create(ctx, inst, 1365 &audio_regs[inst], &audio_shift, &audio_mask); 1366 } 1367 1368 struct stream_encoder *dcn20_stream_encoder_create( 1369 enum engine_id eng_id, 1370 struct dc_context *ctx) 1371 { 1372 struct dcn10_stream_encoder *enc1 = 1373 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1374 1375 if (!enc1) 1376 return NULL; 1377 1378 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) { 1379 if (eng_id >= ENGINE_ID_DIGD) 1380 eng_id++; 1381 } 1382 1383 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1384 &stream_enc_regs[eng_id], 1385 &se_shift, &se_mask); 1386 1387 return &enc1->base; 1388 } 1389 1390 static const struct dce_hwseq_registers hwseq_reg = { 1391 HWSEQ_DCN2_REG_LIST() 1392 }; 1393 1394 static const struct dce_hwseq_shift hwseq_shift = { 1395 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT) 1396 }; 1397 1398 static const struct dce_hwseq_mask hwseq_mask = { 1399 HWSEQ_DCN2_MASK_SH_LIST(_MASK) 1400 }; 1401 1402 struct dce_hwseq *dcn20_hwseq_create( 1403 struct dc_context *ctx) 1404 { 1405 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1406 1407 if (hws) { 1408 hws->ctx = ctx; 1409 hws->regs = &hwseq_reg; 1410 hws->shifts = &hwseq_shift; 1411 hws->masks = &hwseq_mask; 1412 } 1413 return hws; 1414 } 1415 1416 static const struct resource_create_funcs res_create_funcs = { 1417 .read_dce_straps = read_dce_straps, 1418 .create_audio = dcn20_create_audio, 1419 .create_stream_encoder = dcn20_stream_encoder_create, 1420 .create_hwseq = dcn20_hwseq_create, 1421 }; 1422 1423 static const struct resource_create_funcs res_create_maximus_funcs = { 1424 .read_dce_straps = NULL, 1425 .create_audio = NULL, 1426 .create_stream_encoder = NULL, 1427 .create_hwseq = dcn20_hwseq_create, 1428 }; 1429 1430 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu); 1431 1432 void dcn20_clock_source_destroy(struct clock_source **clk_src) 1433 { 1434 kfree(TO_DCE110_CLK_SRC(*clk_src)); 1435 *clk_src = NULL; 1436 } 1437 1438 1439 struct display_stream_compressor *dcn20_dsc_create( 1440 struct dc_context *ctx, uint32_t inst) 1441 { 1442 struct dcn20_dsc *dsc = 1443 kzalloc(sizeof(struct dcn20_dsc), GFP_ATOMIC); 1444 1445 if (!dsc) { 1446 BREAK_TO_DEBUGGER(); 1447 return NULL; 1448 } 1449 1450 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1451 return &dsc->base; 1452 } 1453 1454 void dcn20_dsc_destroy(struct display_stream_compressor **dsc) 1455 { 1456 kfree(container_of(*dsc, struct dcn20_dsc, base)); 1457 *dsc = NULL; 1458 } 1459 1460 1461 static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) 1462 { 1463 unsigned int i; 1464 1465 for (i = 0; i < pool->base.stream_enc_count; i++) { 1466 if (pool->base.stream_enc[i] != NULL) { 1467 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1468 pool->base.stream_enc[i] = NULL; 1469 } 1470 } 1471 1472 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1473 if (pool->base.dscs[i] != NULL) 1474 dcn20_dsc_destroy(&pool->base.dscs[i]); 1475 } 1476 1477 if (pool->base.mpc != NULL) { 1478 kfree(TO_DCN20_MPC(pool->base.mpc)); 1479 pool->base.mpc = NULL; 1480 } 1481 if (pool->base.hubbub != NULL) { 1482 kfree(pool->base.hubbub); 1483 pool->base.hubbub = NULL; 1484 } 1485 for (i = 0; i < pool->base.pipe_count; i++) { 1486 if (pool->base.dpps[i] != NULL) 1487 dcn20_dpp_destroy(&pool->base.dpps[i]); 1488 1489 if (pool->base.ipps[i] != NULL) 1490 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1491 1492 if (pool->base.hubps[i] != NULL) { 1493 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1494 pool->base.hubps[i] = NULL; 1495 } 1496 1497 if (pool->base.irqs != NULL) { 1498 dal_irq_service_destroy(&pool->base.irqs); 1499 } 1500 } 1501 1502 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1503 if (pool->base.engines[i] != NULL) 1504 dce110_engine_destroy(&pool->base.engines[i]); 1505 if (pool->base.hw_i2cs[i] != NULL) { 1506 kfree(pool->base.hw_i2cs[i]); 1507 pool->base.hw_i2cs[i] = NULL; 1508 } 1509 if (pool->base.sw_i2cs[i] != NULL) { 1510 kfree(pool->base.sw_i2cs[i]); 1511 pool->base.sw_i2cs[i] = NULL; 1512 } 1513 } 1514 1515 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1516 if (pool->base.opps[i] != NULL) 1517 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1518 } 1519 1520 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1521 if (pool->base.timing_generators[i] != NULL) { 1522 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1523 pool->base.timing_generators[i] = NULL; 1524 } 1525 } 1526 1527 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1528 if (pool->base.dwbc[i] != NULL) { 1529 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); 1530 pool->base.dwbc[i] = NULL; 1531 } 1532 if (pool->base.mcif_wb[i] != NULL) { 1533 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); 1534 pool->base.mcif_wb[i] = NULL; 1535 } 1536 } 1537 1538 for (i = 0; i < pool->base.audio_count; i++) { 1539 if (pool->base.audios[i]) 1540 dce_aud_destroy(&pool->base.audios[i]); 1541 } 1542 1543 for (i = 0; i < pool->base.clk_src_count; i++) { 1544 if (pool->base.clock_sources[i] != NULL) { 1545 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1546 pool->base.clock_sources[i] = NULL; 1547 } 1548 } 1549 1550 if (pool->base.dp_clock_source != NULL) { 1551 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1552 pool->base.dp_clock_source = NULL; 1553 } 1554 1555 1556 if (pool->base.abm != NULL) 1557 dce_abm_destroy(&pool->base.abm); 1558 1559 if (pool->base.dmcu != NULL) 1560 dce_dmcu_destroy(&pool->base.dmcu); 1561 1562 if (pool->base.dccg != NULL) 1563 dcn_dccg_destroy(&pool->base.dccg); 1564 1565 if (pool->base.pp_smu != NULL) 1566 dcn20_pp_smu_destroy(&pool->base.pp_smu); 1567 1568 if (pool->base.oem_device != NULL) 1569 dal_ddc_service_destroy(&pool->base.oem_device); 1570 } 1571 1572 struct hubp *dcn20_hubp_create( 1573 struct dc_context *ctx, 1574 uint32_t inst) 1575 { 1576 struct dcn20_hubp *hubp2 = 1577 kzalloc(sizeof(struct dcn20_hubp), GFP_ATOMIC); 1578 1579 if (!hubp2) 1580 return NULL; 1581 1582 if (hubp2_construct(hubp2, ctx, inst, 1583 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1584 return &hubp2->base; 1585 1586 BREAK_TO_DEBUGGER(); 1587 kfree(hubp2); 1588 return NULL; 1589 } 1590 1591 static void get_pixel_clock_parameters( 1592 struct pipe_ctx *pipe_ctx, 1593 struct pixel_clk_params *pixel_clk_params) 1594 { 1595 const struct dc_stream_state *stream = pipe_ctx->stream; 1596 struct pipe_ctx *odm_pipe; 1597 int opp_cnt = 1; 1598 1599 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1600 opp_cnt++; 1601 1602 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 1603 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 1604 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 1605 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 1606 /* TODO: un-hardcode*/ 1607 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 1608 LINK_RATE_REF_FREQ_IN_KHZ; 1609 pixel_clk_params->flags.ENABLE_SS = 0; 1610 pixel_clk_params->color_depth = 1611 stream->timing.display_color_depth; 1612 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 1613 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 1614 1615 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1616 pixel_clk_params->color_depth = COLOR_DEPTH_888; 1617 1618 if (opp_cnt == 4) 1619 pixel_clk_params->requested_pix_clk_100hz /= 4; 1620 else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2) 1621 pixel_clk_params->requested_pix_clk_100hz /= 2; 1622 1623 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1624 pixel_clk_params->requested_pix_clk_100hz *= 2; 1625 1626 } 1627 1628 static void build_clamping_params(struct dc_stream_state *stream) 1629 { 1630 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1631 stream->clamping.c_depth = stream->timing.display_color_depth; 1632 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1633 } 1634 1635 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1636 { 1637 1638 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1639 1640 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1641 pipe_ctx->clock_source, 1642 &pipe_ctx->stream_res.pix_clk_params, 1643 &pipe_ctx->pll_settings); 1644 1645 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1646 1647 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1648 &pipe_ctx->stream->bit_depth_params); 1649 build_clamping_params(pipe_ctx->stream); 1650 1651 return DC_OK; 1652 } 1653 1654 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream) 1655 { 1656 enum dc_status status = DC_OK; 1657 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1658 1659 if (!pipe_ctx) 1660 return DC_ERROR_UNEXPECTED; 1661 1662 1663 status = build_pipe_hw_param(pipe_ctx); 1664 1665 return status; 1666 } 1667 1668 1669 void dcn20_acquire_dsc(const struct dc *dc, 1670 struct resource_context *res_ctx, 1671 struct display_stream_compressor **dsc, 1672 int pipe_idx) 1673 { 1674 int i; 1675 const struct resource_pool *pool = dc->res_pool; 1676 struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc; 1677 1678 ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */ 1679 *dsc = NULL; 1680 1681 /* Always do 1-to-1 mapping when number of DSCs is same as number of pipes */ 1682 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { 1683 *dsc = pool->dscs[pipe_idx]; 1684 res_ctx->is_dsc_acquired[pipe_idx] = true; 1685 return; 1686 } 1687 1688 /* Return old DSC to avoid the need for re-programming */ 1689 if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) { 1690 *dsc = dsc_old; 1691 res_ctx->is_dsc_acquired[dsc_old->inst] = true; 1692 return ; 1693 } 1694 1695 /* Find first free DSC */ 1696 for (i = 0; i < pool->res_cap->num_dsc; i++) 1697 if (!res_ctx->is_dsc_acquired[i]) { 1698 *dsc = pool->dscs[i]; 1699 res_ctx->is_dsc_acquired[i] = true; 1700 break; 1701 } 1702 } 1703 1704 void dcn20_release_dsc(struct resource_context *res_ctx, 1705 const struct resource_pool *pool, 1706 struct display_stream_compressor **dsc) 1707 { 1708 int i; 1709 1710 for (i = 0; i < pool->res_cap->num_dsc; i++) 1711 if (pool->dscs[i] == *dsc) { 1712 res_ctx->is_dsc_acquired[i] = false; 1713 *dsc = NULL; 1714 break; 1715 } 1716 } 1717 1718 1719 1720 enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, 1721 struct dc_state *dc_ctx, 1722 struct dc_stream_state *dc_stream) 1723 { 1724 enum dc_status result = DC_OK; 1725 int i; 1726 1727 /* Get a DSC if required and available */ 1728 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1729 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i]; 1730 1731 if (pipe_ctx->stream != dc_stream) 1732 continue; 1733 1734 if (pipe_ctx->stream_res.dsc) 1735 continue; 1736 1737 dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i); 1738 1739 /* The number of DSCs can be less than the number of pipes */ 1740 if (!pipe_ctx->stream_res.dsc) { 1741 result = DC_NO_DSC_RESOURCE; 1742 } 1743 1744 break; 1745 } 1746 1747 return result; 1748 } 1749 1750 1751 static enum dc_status remove_dsc_from_stream_resource(struct dc *dc, 1752 struct dc_state *new_ctx, 1753 struct dc_stream_state *dc_stream) 1754 { 1755 struct pipe_ctx *pipe_ctx = NULL; 1756 int i; 1757 1758 for (i = 0; i < MAX_PIPES; i++) { 1759 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { 1760 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; 1761 1762 if (pipe_ctx->stream_res.dsc) 1763 dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); 1764 } 1765 } 1766 1767 if (!pipe_ctx) 1768 return DC_ERROR_UNEXPECTED; 1769 else 1770 return DC_OK; 1771 } 1772 1773 1774 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) 1775 { 1776 enum dc_status result = DC_ERROR_UNEXPECTED; 1777 1778 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1779 1780 if (result == DC_OK) 1781 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1782 1783 /* Get a DSC if required and available */ 1784 if (result == DC_OK && dc_stream->timing.flags.DSC) 1785 result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream); 1786 1787 if (result == DC_OK) 1788 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream); 1789 1790 return result; 1791 } 1792 1793 1794 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) 1795 { 1796 enum dc_status result = DC_OK; 1797 1798 result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream); 1799 1800 return result; 1801 } 1802 1803 1804 static void swizzle_to_dml_params( 1805 enum swizzle_mode_values swizzle, 1806 unsigned int *sw_mode) 1807 { 1808 switch (swizzle) { 1809 case DC_SW_LINEAR: 1810 *sw_mode = dm_sw_linear; 1811 break; 1812 case DC_SW_4KB_S: 1813 *sw_mode = dm_sw_4kb_s; 1814 break; 1815 case DC_SW_4KB_S_X: 1816 *sw_mode = dm_sw_4kb_s_x; 1817 break; 1818 case DC_SW_4KB_D: 1819 *sw_mode = dm_sw_4kb_d; 1820 break; 1821 case DC_SW_4KB_D_X: 1822 *sw_mode = dm_sw_4kb_d_x; 1823 break; 1824 case DC_SW_64KB_S: 1825 *sw_mode = dm_sw_64kb_s; 1826 break; 1827 case DC_SW_64KB_S_X: 1828 *sw_mode = dm_sw_64kb_s_x; 1829 break; 1830 case DC_SW_64KB_S_T: 1831 *sw_mode = dm_sw_64kb_s_t; 1832 break; 1833 case DC_SW_64KB_D: 1834 *sw_mode = dm_sw_64kb_d; 1835 break; 1836 case DC_SW_64KB_D_X: 1837 *sw_mode = dm_sw_64kb_d_x; 1838 break; 1839 case DC_SW_64KB_D_T: 1840 *sw_mode = dm_sw_64kb_d_t; 1841 break; 1842 case DC_SW_64KB_R_X: 1843 *sw_mode = dm_sw_64kb_r_x; 1844 break; 1845 case DC_SW_VAR_S: 1846 *sw_mode = dm_sw_var_s; 1847 break; 1848 case DC_SW_VAR_S_X: 1849 *sw_mode = dm_sw_var_s_x; 1850 break; 1851 case DC_SW_VAR_D: 1852 *sw_mode = dm_sw_var_d; 1853 break; 1854 case DC_SW_VAR_D_X: 1855 *sw_mode = dm_sw_var_d_x; 1856 break; 1857 1858 default: 1859 ASSERT(0); /* Not supported */ 1860 break; 1861 } 1862 } 1863 1864 bool dcn20_split_stream_for_odm( 1865 const struct dc *dc, 1866 struct resource_context *res_ctx, 1867 struct pipe_ctx *prev_odm_pipe, 1868 struct pipe_ctx *next_odm_pipe) 1869 { 1870 int pipe_idx = next_odm_pipe->pipe_idx; 1871 const struct resource_pool *pool = dc->res_pool; 1872 1873 *next_odm_pipe = *prev_odm_pipe; 1874 1875 next_odm_pipe->pipe_idx = pipe_idx; 1876 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; 1877 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; 1878 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; 1879 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; 1880 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; 1881 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; 1882 next_odm_pipe->stream_res.dsc = NULL; 1883 if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) { 1884 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe; 1885 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe; 1886 } 1887 if (prev_odm_pipe->top_pipe && prev_odm_pipe->top_pipe->next_odm_pipe) { 1888 prev_odm_pipe->top_pipe->next_odm_pipe->bottom_pipe = next_odm_pipe; 1889 next_odm_pipe->top_pipe = prev_odm_pipe->top_pipe->next_odm_pipe; 1890 } 1891 if (prev_odm_pipe->bottom_pipe && prev_odm_pipe->bottom_pipe->next_odm_pipe) { 1892 prev_odm_pipe->bottom_pipe->next_odm_pipe->top_pipe = next_odm_pipe; 1893 next_odm_pipe->bottom_pipe = prev_odm_pipe->bottom_pipe->next_odm_pipe; 1894 } 1895 prev_odm_pipe->next_odm_pipe = next_odm_pipe; 1896 next_odm_pipe->prev_odm_pipe = prev_odm_pipe; 1897 1898 if (prev_odm_pipe->plane_state) { 1899 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; 1900 int new_width; 1901 1902 /* HACTIVE halved for odm combine */ 1903 sd->h_active /= 2; 1904 /* Calculate new vp and recout for left pipe */ 1905 /* Need at least 16 pixels width per side */ 1906 if (sd->recout.x + 16 >= sd->h_active) 1907 return false; 1908 new_width = sd->h_active - sd->recout.x; 1909 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1910 sd->ratios.horz, sd->recout.width - new_width)); 1911 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1912 sd->ratios.horz_c, sd->recout.width - new_width)); 1913 sd->recout.width = new_width; 1914 1915 /* Calculate new vp and recout for right pipe */ 1916 sd = &next_odm_pipe->plane_res.scl_data; 1917 /* HACTIVE halved for odm combine */ 1918 sd->h_active /= 2; 1919 /* Need at least 16 pixels width per side */ 1920 if (new_width <= 16) 1921 return false; 1922 new_width = sd->recout.width + sd->recout.x - sd->h_active; 1923 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1924 sd->ratios.horz, sd->recout.width - new_width)); 1925 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1926 sd->ratios.horz_c, sd->recout.width - new_width)); 1927 sd->recout.width = new_width; 1928 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int( 1929 sd->ratios.horz, sd->h_active - sd->recout.x)); 1930 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int( 1931 sd->ratios.horz_c, sd->h_active - sd->recout.x)); 1932 sd->recout.x = 0; 1933 } 1934 if (!next_odm_pipe->top_pipe) 1935 next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; 1936 else 1937 next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp; 1938 if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) { 1939 dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx); 1940 ASSERT(next_odm_pipe->stream_res.dsc); 1941 if (next_odm_pipe->stream_res.dsc == NULL) 1942 return false; 1943 } 1944 1945 return true; 1946 } 1947 1948 void dcn20_split_stream_for_mpc( 1949 struct resource_context *res_ctx, 1950 const struct resource_pool *pool, 1951 struct pipe_ctx *primary_pipe, 1952 struct pipe_ctx *secondary_pipe) 1953 { 1954 int pipe_idx = secondary_pipe->pipe_idx; 1955 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe; 1956 1957 *secondary_pipe = *primary_pipe; 1958 secondary_pipe->bottom_pipe = sec_bot_pipe; 1959 1960 secondary_pipe->pipe_idx = pipe_idx; 1961 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; 1962 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; 1963 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; 1964 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; 1965 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; 1966 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; 1967 secondary_pipe->stream_res.dsc = NULL; 1968 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { 1969 ASSERT(!secondary_pipe->bottom_pipe); 1970 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; 1971 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe; 1972 } 1973 primary_pipe->bottom_pipe = secondary_pipe; 1974 secondary_pipe->top_pipe = primary_pipe; 1975 1976 ASSERT(primary_pipe->plane_state); 1977 } 1978 1979 int dcn20_populate_dml_pipes_from_context( 1980 struct dc *dc, 1981 struct dc_state *context, 1982 display_e2e_pipe_params_st *pipes, 1983 bool fast_validate) 1984 { 1985 int pipe_cnt, i; 1986 bool synchronized_vblank = true; 1987 struct resource_context *res_ctx = &context->res_ctx; 1988 1989 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) { 1990 if (!res_ctx->pipe_ctx[i].stream) 1991 continue; 1992 1993 if (pipe_cnt < 0) { 1994 pipe_cnt = i; 1995 continue; 1996 } 1997 1998 if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream) 1999 continue; 2000 2001 if (dc->debug.disable_timing_sync || 2002 (!resource_are_streams_timing_synchronizable( 2003 res_ctx->pipe_ctx[pipe_cnt].stream, 2004 res_ctx->pipe_ctx[i].stream) && 2005 !resource_are_vblanks_synchronizable( 2006 res_ctx->pipe_ctx[pipe_cnt].stream, 2007 res_ctx->pipe_ctx[i].stream))) { 2008 synchronized_vblank = false; 2009 break; 2010 } 2011 } 2012 2013 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 2014 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing; 2015 unsigned int v_total; 2016 unsigned int front_porch; 2017 int output_bpc; 2018 struct audio_check aud_check = {0}; 2019 2020 if (!res_ctx->pipe_ctx[i].stream) 2021 continue; 2022 2023 v_total = timing->v_total; 2024 front_porch = timing->v_front_porch; 2025 2026 /* todo: 2027 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0; 2028 pipes[pipe_cnt].pipe.src.dcc = 0; 2029 pipes[pipe_cnt].pipe.src.vm = 0;*/ 2030 2031 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 2032 2033 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC; 2034 /* todo: rotation?*/ 2035 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; 2036 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) { 2037 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true; 2038 /* 1/2 vblank */ 2039 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active = 2040 (v_total - timing->v_addressable 2041 - timing->v_border_top - timing->v_border_bottom) / 2; 2042 /* 36 bytes dp, 32 hdmi */ 2043 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes = 2044 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32; 2045 } 2046 pipes[pipe_cnt].pipe.src.dcc = false; 2047 pipes[pipe_cnt].pipe.src.dcc_rate = 1; 2048 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank; 2049 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch; 2050 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start 2051 - timing->h_addressable 2052 - timing->h_border_left 2053 - timing->h_border_right; 2054 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch; 2055 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start 2056 - timing->v_addressable 2057 - timing->v_border_top 2058 - timing->v_border_bottom; 2059 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total; 2060 pipes[pipe_cnt].pipe.dest.vtotal = v_total; 2061 pipes[pipe_cnt].pipe.dest.hactive = 2062 timing->h_addressable + timing->h_border_left + timing->h_border_right; 2063 pipes[pipe_cnt].pipe.dest.vactive = 2064 timing->v_addressable + timing->v_border_top + timing->v_border_bottom; 2065 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE; 2066 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0; 2067 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 2068 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2; 2069 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst; 2070 pipes[pipe_cnt].dout.dp_lanes = 4; 2071 pipes[pipe_cnt].dout.is_virtual = 0; 2072 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min; 2073 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max; 2074 switch (get_num_odm_splits(&res_ctx->pipe_ctx[i])) { 2075 case 1: 2076 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1; 2077 break; 2078 case 3: 2079 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1; 2080 break; 2081 default: 2082 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled; 2083 } 2084 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; 2085 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state 2086 == res_ctx->pipe_ctx[i].plane_state) { 2087 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe; 2088 int split_idx = 0; 2089 2090 while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state 2091 == res_ctx->pipe_ctx[i].plane_state) { 2092 first_pipe = first_pipe->top_pipe; 2093 split_idx++; 2094 } 2095 /* Treat 4to1 mpc combine as an mpo of 2 2-to-1 combines */ 2096 if (split_idx == 0) 2097 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx; 2098 else if (split_idx == 1) 2099 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; 2100 else if (split_idx == 2) 2101 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx; 2102 } else if (res_ctx->pipe_ctx[i].prev_odm_pipe) { 2103 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe; 2104 2105 while (first_pipe->prev_odm_pipe) 2106 first_pipe = first_pipe->prev_odm_pipe; 2107 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx; 2108 } 2109 2110 switch (res_ctx->pipe_ctx[i].stream->signal) { 2111 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2112 case SIGNAL_TYPE_DISPLAY_PORT: 2113 pipes[pipe_cnt].dout.output_type = dm_dp; 2114 break; 2115 case SIGNAL_TYPE_EDP: 2116 pipes[pipe_cnt].dout.output_type = dm_edp; 2117 break; 2118 case SIGNAL_TYPE_HDMI_TYPE_A: 2119 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2120 case SIGNAL_TYPE_DVI_DUAL_LINK: 2121 pipes[pipe_cnt].dout.output_type = dm_hdmi; 2122 break; 2123 default: 2124 /* In case there is no signal, set dp with 4 lanes to allow max config */ 2125 pipes[pipe_cnt].dout.is_virtual = 1; 2126 pipes[pipe_cnt].dout.output_type = dm_dp; 2127 pipes[pipe_cnt].dout.dp_lanes = 4; 2128 } 2129 2130 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) { 2131 case COLOR_DEPTH_666: 2132 output_bpc = 6; 2133 break; 2134 case COLOR_DEPTH_888: 2135 output_bpc = 8; 2136 break; 2137 case COLOR_DEPTH_101010: 2138 output_bpc = 10; 2139 break; 2140 case COLOR_DEPTH_121212: 2141 output_bpc = 12; 2142 break; 2143 case COLOR_DEPTH_141414: 2144 output_bpc = 14; 2145 break; 2146 case COLOR_DEPTH_161616: 2147 output_bpc = 16; 2148 break; 2149 case COLOR_DEPTH_999: 2150 output_bpc = 9; 2151 break; 2152 case COLOR_DEPTH_111111: 2153 output_bpc = 11; 2154 break; 2155 default: 2156 output_bpc = 8; 2157 break; 2158 } 2159 2160 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) { 2161 case PIXEL_ENCODING_RGB: 2162 case PIXEL_ENCODING_YCBCR444: 2163 pipes[pipe_cnt].dout.output_format = dm_444; 2164 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3; 2165 break; 2166 case PIXEL_ENCODING_YCBCR420: 2167 pipes[pipe_cnt].dout.output_format = dm_420; 2168 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2; 2169 break; 2170 case PIXEL_ENCODING_YCBCR422: 2171 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC && 2172 !res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.ycbcr422_simple) 2173 pipes[pipe_cnt].dout.output_format = dm_n422; 2174 else 2175 pipes[pipe_cnt].dout.output_format = dm_s422; 2176 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2; 2177 break; 2178 default: 2179 pipes[pipe_cnt].dout.output_format = dm_444; 2180 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3; 2181 } 2182 2183 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC) 2184 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0; 2185 2186 /* todo: default max for now, until there is logic reflecting this in dc*/ 2187 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 2188 /*fill up the audio sample rate (unit in kHz)*/ 2189 get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check); 2190 pipes[pipe_cnt].dout.max_audio_sample_rate = aud_check.max_audiosample_rate / 1000; 2191 /* 2192 * For graphic plane, cursor number is 1, nv12 is 0 2193 * bw calculations due to cursor on/off 2194 */ 2195 if (res_ctx->pipe_ctx[i].plane_state && 2196 res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 2197 pipes[pipe_cnt].pipe.src.num_cursors = 0; 2198 else 2199 pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors; 2200 2201 pipes[pipe_cnt].pipe.src.cur0_src_width = 256; 2202 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit; 2203 2204 if (!res_ctx->pipe_ctx[i].plane_state) { 2205 pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled; 2206 pipes[pipe_cnt].pipe.src.source_scan = dm_horz; 2207 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_4kb_s; 2208 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile; 2209 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable; 2210 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920) 2211 pipes[pipe_cnt].pipe.src.viewport_width = 1920; 2212 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable; 2213 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080) 2214 pipes[pipe_cnt].pipe.src.viewport_height = 1080; 2215 pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height; 2216 pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width; 2217 pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height; 2218 pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width; 2219 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 255) / 256) * 256; 2220 pipes[pipe_cnt].pipe.src.source_format = dm_444_32; 2221 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/ 2222 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/ 2223 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/ 2224 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/ 2225 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16; 2226 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0; 2227 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0; 2228 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/ 2229 pipes[pipe_cnt].pipe.scale_taps.htaps = 1; 2230 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1; 2231 pipes[pipe_cnt].pipe.dest.vtotal_min = v_total; 2232 pipes[pipe_cnt].pipe.dest.vtotal_max = v_total; 2233 2234 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) { 2235 pipes[pipe_cnt].pipe.src.viewport_width /= 2; 2236 pipes[pipe_cnt].pipe.dest.recout_width /= 2; 2237 } else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) { 2238 pipes[pipe_cnt].pipe.src.viewport_width /= 4; 2239 pipes[pipe_cnt].pipe.dest.recout_width /= 4; 2240 } 2241 } else { 2242 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state; 2243 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data; 2244 2245 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate; 2246 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) 2247 || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) 2248 || pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled; 2249 2250 /* stereo is not split */ 2251 if (pln->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE || 2252 pln->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) { 2253 pipes[pipe_cnt].pipe.src.is_hsplit = false; 2254 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; 2255 } 2256 2257 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90 2258 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz; 2259 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y; 2260 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y; 2261 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width; 2262 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width; 2263 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height; 2264 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height; 2265 pipes[pipe_cnt].pipe.src.viewport_width_max = pln->src_rect.width; 2266 pipes[pipe_cnt].pipe.src.viewport_height_max = pln->src_rect.height; 2267 pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width; 2268 pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height; 2269 pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width; 2270 pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height; 2271 if (pln->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA 2272 || pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 2273 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch; 2274 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch; 2275 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; 2276 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c; 2277 } else { 2278 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch; 2279 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; 2280 } 2281 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable; 2282 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width; 2283 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height; 2284 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height; 2285 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width; 2286 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) 2287 pipes[pipe_cnt].pipe.dest.full_recout_width *= 2; 2288 else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) 2289 pipes[pipe_cnt].pipe.dest.full_recout_width *= 4; 2290 else { 2291 struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe; 2292 2293 while (split_pipe && split_pipe->plane_state == pln) { 2294 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; 2295 split_pipe = split_pipe->bottom_pipe; 2296 } 2297 split_pipe = res_ctx->pipe_ctx[i].top_pipe; 2298 while (split_pipe && split_pipe->plane_state == pln) { 2299 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; 2300 split_pipe = split_pipe->top_pipe; 2301 } 2302 } 2303 2304 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16; 2305 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32); 2306 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32); 2307 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32); 2308 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32); 2309 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 2310 scl->ratios.vert.value != dc_fixpt_one.value 2311 || scl->ratios.horz.value != dc_fixpt_one.value 2312 || scl->ratios.vert_c.value != dc_fixpt_one.value 2313 || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/ 2314 || dc->debug.always_scale; /*support always scale*/ 2315 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps; 2316 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c; 2317 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps; 2318 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c; 2319 2320 pipes[pipe_cnt].pipe.src.macro_tile_size = 2321 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); 2322 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, 2323 &pipes[pipe_cnt].pipe.src.sw_mode); 2324 2325 switch (pln->format) { 2326 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 2327 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 2328 pipes[pipe_cnt].pipe.src.source_format = dm_420_8; 2329 break; 2330 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 2331 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 2332 pipes[pipe_cnt].pipe.src.source_format = dm_420_10; 2333 break; 2334 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 2335 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 2336 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 2337 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2338 pipes[pipe_cnt].pipe.src.source_format = dm_444_64; 2339 break; 2340 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 2341 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 2342 pipes[pipe_cnt].pipe.src.source_format = dm_444_16; 2343 break; 2344 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 2345 pipes[pipe_cnt].pipe.src.source_format = dm_444_8; 2346 break; 2347 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 2348 pipes[pipe_cnt].pipe.src.source_format = dm_rgbe_alpha; 2349 break; 2350 default: 2351 pipes[pipe_cnt].pipe.src.source_format = dm_444_32; 2352 break; 2353 } 2354 } 2355 2356 pipe_cnt++; 2357 } 2358 2359 /* populate writeback information */ 2360 DC_FP_START(); 2361 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes); 2362 DC_FP_END(); 2363 2364 return pipe_cnt; 2365 } 2366 2367 unsigned int dcn20_calc_max_scaled_time( 2368 unsigned int time_per_pixel, 2369 enum mmhubbub_wbif_mode mode, 2370 unsigned int urgent_watermark) 2371 { 2372 unsigned int time_per_byte = 0; 2373 unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */ 2374 unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */ 2375 unsigned int small_free_entry, max_free_entry; 2376 unsigned int buf_lh_capability; 2377 unsigned int max_scaled_time; 2378 2379 if (mode == PACKED_444) /* packed mode */ 2380 time_per_byte = time_per_pixel/4; 2381 else if (mode == PLANAR_420_8BPC) 2382 time_per_byte = time_per_pixel; 2383 else if (mode == PLANAR_420_10BPC) /* p010 */ 2384 time_per_byte = time_per_pixel * 819/1024; 2385 2386 if (time_per_byte == 0) 2387 time_per_byte = 1; 2388 2389 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry; 2390 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry; 2391 buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */ 2392 max_scaled_time = buf_lh_capability - urgent_watermark; 2393 return max_scaled_time; 2394 } 2395 2396 void dcn20_set_mcif_arb_params( 2397 struct dc *dc, 2398 struct dc_state *context, 2399 display_e2e_pipe_params_st *pipes, 2400 int pipe_cnt) 2401 { 2402 enum mmhubbub_wbif_mode wbif_mode; 2403 struct mcif_arb_params *wb_arb_params; 2404 int i, j, k, dwb_pipe; 2405 2406 /* Writeback MCIF_WB arbitration parameters */ 2407 dwb_pipe = 0; 2408 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2409 2410 if (!context->res_ctx.pipe_ctx[i].stream) 2411 continue; 2412 2413 for (j = 0; j < MAX_DWB_PIPES; j++) { 2414 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false) 2415 continue; 2416 2417 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params; 2418 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe]; 2419 2420 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) { 2421 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) 2422 wbif_mode = PLANAR_420_8BPC; 2423 else 2424 wbif_mode = PLANAR_420_10BPC; 2425 } else 2426 wbif_mode = PACKED_444; 2427 2428 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) { 2429 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2430 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2431 } 2432 wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction, ms */ 2433 wb_arb_params->slice_lines = 32; 2434 wb_arb_params->arbitration_slice = 2; 2435 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel, 2436 wbif_mode, 2437 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */ 2438 2439 dwb_pipe++; 2440 2441 if (dwb_pipe >= MAX_DWB_PIPES) 2442 return; 2443 } 2444 if (dwb_pipe >= MAX_DWB_PIPES) 2445 return; 2446 } 2447 } 2448 2449 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) 2450 { 2451 int i; 2452 2453 /* Validate DSC config, dsc count validation is already done */ 2454 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2455 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; 2456 struct dc_stream_state *stream = pipe_ctx->stream; 2457 struct dsc_config dsc_cfg; 2458 struct pipe_ctx *odm_pipe; 2459 int opp_cnt = 1; 2460 2461 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 2462 opp_cnt++; 2463 2464 /* Only need to validate top pipe */ 2465 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC) 2466 continue; 2467 2468 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left 2469 + stream->timing.h_border_right) / opp_cnt; 2470 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top 2471 + stream->timing.v_border_bottom; 2472 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 2473 dsc_cfg.color_depth = stream->timing.display_color_depth; 2474 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 2475 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 2476 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 2477 2478 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg)) 2479 return false; 2480 } 2481 return true; 2482 } 2483 2484 struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, 2485 struct resource_context *res_ctx, 2486 const struct resource_pool *pool, 2487 const struct pipe_ctx *primary_pipe) 2488 { 2489 struct pipe_ctx *secondary_pipe = NULL; 2490 2491 if (dc && primary_pipe) { 2492 int j; 2493 int preferred_pipe_idx = 0; 2494 2495 /* first check the prev dc state: 2496 * if this primary pipe has a bottom pipe in prev. state 2497 * and if the bottom pipe is still available (which it should be), 2498 * pick that pipe as secondary 2499 * Same logic applies for ODM pipes 2500 */ 2501 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) { 2502 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx; 2503 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2504 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2505 secondary_pipe->pipe_idx = preferred_pipe_idx; 2506 } 2507 } 2508 if (secondary_pipe == NULL && 2509 dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) { 2510 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx; 2511 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2512 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2513 secondary_pipe->pipe_idx = preferred_pipe_idx; 2514 } 2515 } 2516 2517 /* 2518 * if this primary pipe does not have a bottom pipe in prev. state 2519 * start backward and find a pipe that did not used to be a bottom pipe in 2520 * prev. dc state. This way we make sure we keep the same assignment as 2521 * last state and will not have to reprogram every pipe 2522 */ 2523 if (secondary_pipe == NULL) { 2524 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { 2525 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL 2526 && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) { 2527 preferred_pipe_idx = j; 2528 2529 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2530 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2531 secondary_pipe->pipe_idx = preferred_pipe_idx; 2532 break; 2533 } 2534 } 2535 } 2536 } 2537 /* 2538 * We should never hit this assert unless assignments are shuffled around 2539 * if this happens we will prob. hit a vsync tdr 2540 */ 2541 ASSERT(secondary_pipe); 2542 /* 2543 * search backwards for the second pipe to keep pipe 2544 * assignment more consistent 2545 */ 2546 if (secondary_pipe == NULL) { 2547 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { 2548 preferred_pipe_idx = j; 2549 2550 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2551 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2552 secondary_pipe->pipe_idx = preferred_pipe_idx; 2553 break; 2554 } 2555 } 2556 } 2557 } 2558 2559 return secondary_pipe; 2560 } 2561 2562 void dcn20_merge_pipes_for_validate( 2563 struct dc *dc, 2564 struct dc_state *context) 2565 { 2566 int i; 2567 2568 /* merge previously split odm pipes since mode support needs to make the decision */ 2569 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2570 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2571 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe; 2572 2573 if (pipe->prev_odm_pipe) 2574 continue; 2575 2576 pipe->next_odm_pipe = NULL; 2577 while (odm_pipe) { 2578 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe; 2579 2580 odm_pipe->plane_state = NULL; 2581 odm_pipe->stream = NULL; 2582 odm_pipe->top_pipe = NULL; 2583 odm_pipe->bottom_pipe = NULL; 2584 odm_pipe->prev_odm_pipe = NULL; 2585 odm_pipe->next_odm_pipe = NULL; 2586 if (odm_pipe->stream_res.dsc) 2587 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); 2588 /* Clear plane_res and stream_res */ 2589 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res)); 2590 memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res)); 2591 odm_pipe = next_odm_pipe; 2592 } 2593 if (pipe->plane_state) 2594 resource_build_scaling_params(pipe); 2595 } 2596 2597 /* merge previously mpc split pipes since mode support needs to make the decision */ 2598 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2599 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2600 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 2601 2602 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) 2603 continue; 2604 2605 pipe->bottom_pipe = hsplit_pipe->bottom_pipe; 2606 if (hsplit_pipe->bottom_pipe) 2607 hsplit_pipe->bottom_pipe->top_pipe = pipe; 2608 hsplit_pipe->plane_state = NULL; 2609 hsplit_pipe->stream = NULL; 2610 hsplit_pipe->top_pipe = NULL; 2611 hsplit_pipe->bottom_pipe = NULL; 2612 2613 /* Clear plane_res and stream_res */ 2614 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res)); 2615 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res)); 2616 if (pipe->plane_state) 2617 resource_build_scaling_params(pipe); 2618 } 2619 } 2620 2621 int dcn20_validate_apply_pipe_split_flags( 2622 struct dc *dc, 2623 struct dc_state *context, 2624 int vlevel, 2625 int *split, 2626 bool *merge) 2627 { 2628 int i, pipe_idx, vlevel_split; 2629 int plane_count = 0; 2630 bool force_split = false; 2631 bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID; 2632 struct vba_vars_st *v = &context->bw_ctx.dml.vba; 2633 int max_mpc_comb = v->maxMpcComb; 2634 2635 if (context->stream_count > 1) { 2636 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) 2637 avoid_split = true; 2638 } else if (dc->debug.force_single_disp_pipe_split) 2639 force_split = true; 2640 2641 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2642 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2643 2644 /** 2645 * Workaround for avoiding pipe-split in cases where we'd split 2646 * planes that are too small, resulting in splits that aren't 2647 * valid for the scaler. 2648 */ 2649 if (pipe->plane_state && 2650 (pipe->plane_state->dst_rect.width <= 16 || 2651 pipe->plane_state->dst_rect.height <= 16 || 2652 pipe->plane_state->src_rect.width <= 16 || 2653 pipe->plane_state->src_rect.height <= 16)) 2654 avoid_split = true; 2655 2656 /* TODO: fix dc bugs and remove this split threshold thing */ 2657 if (pipe->stream && !pipe->prev_odm_pipe && 2658 (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state)) 2659 ++plane_count; 2660 } 2661 if (plane_count > dc->res_pool->pipe_count / 2) 2662 avoid_split = true; 2663 2664 /* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */ 2665 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2666 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2667 struct dc_crtc_timing timing; 2668 2669 if (!pipe->stream) 2670 continue; 2671 else { 2672 timing = pipe->stream->timing; 2673 if (timing.h_border_left + timing.h_border_right 2674 + timing.v_border_top + timing.v_border_bottom > 0) { 2675 avoid_split = true; 2676 break; 2677 } 2678 } 2679 } 2680 2681 /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */ 2682 if (avoid_split) { 2683 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2684 if (!context->res_ctx.pipe_ctx[i].stream) 2685 continue; 2686 2687 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) 2688 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 && 2689 v->ModeSupport[vlevel][0]) 2690 break; 2691 /* Impossible to not split this pipe */ 2692 if (vlevel > context->bw_ctx.dml.soc.num_states) 2693 vlevel = vlevel_split; 2694 else 2695 max_mpc_comb = 0; 2696 pipe_idx++; 2697 } 2698 v->maxMpcComb = max_mpc_comb; 2699 } 2700 2701 /* Split loop sets which pipe should be split based on dml outputs and dc flags */ 2702 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2703 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2704 int pipe_plane = v->pipe_plane[pipe_idx]; 2705 bool split4mpc = context->stream_count == 1 && plane_count == 1 2706 && dc->config.enable_4to1MPC && dc->res_pool->pipe_count >= 4; 2707 2708 if (!context->res_ctx.pipe_ctx[i].stream) 2709 continue; 2710 2711 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4) 2712 split[i] = 4; 2713 else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2) 2714 split[i] = 2; 2715 2716 if ((pipe->stream->view_format == 2717 VIEW_3D_FORMAT_SIDE_BY_SIDE || 2718 pipe->stream->view_format == 2719 VIEW_3D_FORMAT_TOP_AND_BOTTOM) && 2720 (pipe->stream->timing.timing_3d_format == 2721 TIMING_3D_FORMAT_TOP_AND_BOTTOM || 2722 pipe->stream->timing.timing_3d_format == 2723 TIMING_3D_FORMAT_SIDE_BY_SIDE)) 2724 split[i] = 2; 2725 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) { 2726 split[i] = 2; 2727 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1; 2728 } 2729 if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) { 2730 split[i] = 4; 2731 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1; 2732 } 2733 /*420 format workaround*/ 2734 if (pipe->stream->timing.h_addressable > 7680 && 2735 pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 2736 split[i] = 4; 2737 } 2738 v->ODMCombineEnabled[pipe_plane] = 2739 v->ODMCombineEnablePerState[vlevel][pipe_plane]; 2740 2741 if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) { 2742 if (get_num_mpc_splits(pipe) == 1) { 2743 /*If need split for mpc but 2 way split already*/ 2744 if (split[i] == 4) 2745 split[i] = 2; /* 2 -> 4 MPC */ 2746 else if (split[i] == 2) 2747 split[i] = 0; /* 2 -> 2 MPC */ 2748 else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) 2749 merge[i] = true; /* 2 -> 1 MPC */ 2750 } else if (get_num_mpc_splits(pipe) == 3) { 2751 /*If need split for mpc but 4 way split already*/ 2752 if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe) 2753 || !pipe->bottom_pipe)) { 2754 merge[i] = true; /* 4 -> 2 MPC */ 2755 } else if (split[i] == 0 && pipe->top_pipe && 2756 pipe->top_pipe->plane_state == pipe->plane_state) 2757 merge[i] = true; /* 4 -> 1 MPC */ 2758 split[i] = 0; 2759 } else if (get_num_odm_splits(pipe)) { 2760 /* ODM -> MPC transition */ 2761 if (pipe->prev_odm_pipe) { 2762 split[i] = 0; 2763 merge[i] = true; 2764 } 2765 } 2766 } else { 2767 if (get_num_odm_splits(pipe) == 1) { 2768 /*If need split for odm but 2 way split already*/ 2769 if (split[i] == 4) 2770 split[i] = 2; /* 2 -> 4 ODM */ 2771 else if (split[i] == 2) 2772 split[i] = 0; /* 2 -> 2 ODM */ 2773 else if (pipe->prev_odm_pipe) { 2774 ASSERT(0); /* NOT expected yet */ 2775 merge[i] = true; /* exit ODM */ 2776 } 2777 } else if (get_num_odm_splits(pipe) == 3) { 2778 /*If need split for odm but 4 way split already*/ 2779 if (split[i] == 2 && ((pipe->prev_odm_pipe && !pipe->prev_odm_pipe->prev_odm_pipe) 2780 || !pipe->next_odm_pipe)) { 2781 ASSERT(0); /* NOT expected yet */ 2782 merge[i] = true; /* 4 -> 2 ODM */ 2783 } else if (split[i] == 0 && pipe->prev_odm_pipe) { 2784 ASSERT(0); /* NOT expected yet */ 2785 merge[i] = true; /* exit ODM */ 2786 } 2787 split[i] = 0; 2788 } else if (get_num_mpc_splits(pipe)) { 2789 /* MPC -> ODM transition */ 2790 ASSERT(0); /* NOT expected yet */ 2791 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { 2792 split[i] = 0; 2793 merge[i] = true; 2794 } 2795 } 2796 } 2797 2798 /* Adjust dppclk when split is forced, do not bother with dispclk */ 2799 if (split[i] != 0 && v->NoOfDPP[vlevel][max_mpc_comb][pipe_idx] == 1) 2800 v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2; 2801 pipe_idx++; 2802 } 2803 2804 return vlevel; 2805 } 2806 2807 bool dcn20_fast_validate_bw( 2808 struct dc *dc, 2809 struct dc_state *context, 2810 display_e2e_pipe_params_st *pipes, 2811 int *pipe_cnt_out, 2812 int *pipe_split_from, 2813 int *vlevel_out, 2814 bool fast_validate) 2815 { 2816 bool out = false; 2817 int split[MAX_PIPES] = { 0 }; 2818 int pipe_cnt, i, pipe_idx, vlevel; 2819 2820 ASSERT(pipes); 2821 if (!pipes) 2822 return false; 2823 2824 dcn20_merge_pipes_for_validate(dc, context); 2825 2826 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 2827 2828 *pipe_cnt_out = pipe_cnt; 2829 2830 if (!pipe_cnt) { 2831 out = true; 2832 goto validate_out; 2833 } 2834 2835 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 2836 2837 if (vlevel > context->bw_ctx.dml.soc.num_states) 2838 goto validate_fail; 2839 2840 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL); 2841 2842 /*initialize pipe_just_split_from to invalid idx*/ 2843 for (i = 0; i < MAX_PIPES; i++) 2844 pipe_split_from[i] = -1; 2845 2846 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { 2847 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2848 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 2849 2850 if (!pipe->stream || pipe_split_from[i] >= 0) 2851 continue; 2852 2853 pipe_idx++; 2854 2855 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 2856 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 2857 ASSERT(hsplit_pipe); 2858 if (!dcn20_split_stream_for_odm( 2859 dc, &context->res_ctx, 2860 pipe, hsplit_pipe)) 2861 goto validate_fail; 2862 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 2863 dcn20_build_mapped_resource(dc, context, pipe->stream); 2864 } 2865 2866 if (!pipe->plane_state) 2867 continue; 2868 /* Skip 2nd half of already split pipe */ 2869 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state) 2870 continue; 2871 2872 /* We do not support mpo + odm at the moment */ 2873 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state 2874 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) 2875 goto validate_fail; 2876 2877 if (split[i] == 2) { 2878 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) { 2879 /* pipe not split previously needs split */ 2880 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 2881 ASSERT(hsplit_pipe); 2882 if (!hsplit_pipe) { 2883 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2; 2884 continue; 2885 } 2886 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 2887 if (!dcn20_split_stream_for_odm( 2888 dc, &context->res_ctx, 2889 pipe, hsplit_pipe)) 2890 goto validate_fail; 2891 dcn20_build_mapped_resource(dc, context, pipe->stream); 2892 } else { 2893 dcn20_split_stream_for_mpc( 2894 &context->res_ctx, dc->res_pool, 2895 pipe, hsplit_pipe); 2896 resource_build_scaling_params(pipe); 2897 resource_build_scaling_params(hsplit_pipe); 2898 } 2899 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 2900 } 2901 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { 2902 /* merge should already have been done */ 2903 ASSERT(0); 2904 } 2905 } 2906 /* Actual dsc count per stream dsc validation*/ 2907 if (!dcn20_validate_dsc(dc, context)) { 2908 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = 2909 DML_FAIL_DSC_VALIDATION_FAILURE; 2910 goto validate_fail; 2911 } 2912 2913 *vlevel_out = vlevel; 2914 2915 out = true; 2916 goto validate_out; 2917 2918 validate_fail: 2919 out = false; 2920 2921 validate_out: 2922 return out; 2923 } 2924 2925 static void dcn20_calculate_wm( 2926 struct dc *dc, struct dc_state *context, 2927 display_e2e_pipe_params_st *pipes, 2928 int *out_pipe_cnt, 2929 int *pipe_split_from, 2930 int vlevel, 2931 bool fast_validate) 2932 { 2933 int pipe_cnt, i, pipe_idx; 2934 2935 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 2936 if (!context->res_ctx.pipe_ctx[i].stream) 2937 continue; 2938 2939 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 2940 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 2941 2942 if (pipe_split_from[i] < 0) { 2943 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 2944 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; 2945 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) 2946 pipes[pipe_cnt].pipe.dest.odm_combine = 2947 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]; 2948 else 2949 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 2950 pipe_idx++; 2951 } else { 2952 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 2953 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; 2954 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) 2955 pipes[pipe_cnt].pipe.dest.odm_combine = 2956 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]]; 2957 else 2958 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 2959 } 2960 2961 if (dc->config.forced_clocks) { 2962 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 2963 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 2964 } 2965 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000) 2966 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 2967 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000) 2968 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 2969 2970 pipe_cnt++; 2971 } 2972 2973 if (pipe_cnt != pipe_idx) { 2974 if (dc->res_pool->funcs->populate_dml_pipes) 2975 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, 2976 context, pipes, fast_validate); 2977 else 2978 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, 2979 context, pipes, fast_validate); 2980 } 2981 2982 *out_pipe_cnt = pipe_cnt; 2983 2984 pipes[0].clks_cfg.voltage = vlevel; 2985 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; 2986 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 2987 2988 /* only pipe 0 is read for voltage and dcf/soc clocks */ 2989 if (vlevel < 1) { 2990 pipes[0].clks_cfg.voltage = 1; 2991 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz; 2992 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz; 2993 } 2994 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2995 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2996 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2997 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2998 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2999 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3000 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3001 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3002 3003 if (vlevel < 2) { 3004 pipes[0].clks_cfg.voltage = 2; 3005 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; 3006 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; 3007 } 3008 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3009 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3010 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3011 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3012 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3013 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3014 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3015 3016 if (vlevel < 3) { 3017 pipes[0].clks_cfg.voltage = 3; 3018 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; 3019 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; 3020 } 3021 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3022 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3023 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3024 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3025 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3026 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3027 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3028 3029 pipes[0].clks_cfg.voltage = vlevel; 3030 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; 3031 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 3032 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3033 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3034 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3035 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3036 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3037 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3038 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3039 } 3040 3041 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context) 3042 { 3043 int i; 3044 for (i = 0; i < dc->res_pool->pipe_count; i++) { 3045 if (!context->res_ctx.pipe_ctx[i].stream) 3046 continue; 3047 } 3048 return false; 3049 } 3050 3051 static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struct dc_state *context) 3052 { 3053 int plane_count; 3054 int i; 3055 3056 plane_count = 0; 3057 for (i = 0; i < dc->res_pool->pipe_count; i++) { 3058 if (context->res_ctx.pipe_ctx[i].plane_state) 3059 plane_count++; 3060 } 3061 3062 /* 3063 * Zstate is allowed in following scenarios: 3064 * 1. Single eDP with PSR enabled 3065 * 2. 0 planes (No memory requests) 3066 * 3. Single eDP without PSR but > 5ms stutter period 3067 */ 3068 if (plane_count == 0) 3069 return DCN_ZSTATE_SUPPORT_ALLOW; 3070 else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) { 3071 struct dc_link *link = context->streams[0]->sink->link; 3072 3073 if ((link->link_index == 0 && link->psr_settings.psr_feature_enabled) 3074 || context->bw_ctx.dml.vba.StutterPeriod > 5000.0) 3075 return DCN_ZSTATE_SUPPORT_ALLOW; 3076 else 3077 return DCN_ZSTATE_SUPPORT_DISALLOW; 3078 } else 3079 return DCN_ZSTATE_SUPPORT_DISALLOW; 3080 } 3081 3082 void dcn20_calculate_dlg_params( 3083 struct dc *dc, struct dc_state *context, 3084 display_e2e_pipe_params_st *pipes, 3085 int pipe_cnt, 3086 int vlevel) 3087 { 3088 int i, pipe_idx; 3089 3090 /* Writeback MCIF_WB arbitration parameters */ 3091 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); 3092 3093 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; 3094 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; 3095 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; 3096 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; 3097 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; 3098 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; 3099 context->bw_ctx.bw.dcn.clk.p_state_change_support = 3100 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] 3101 != dm_dram_clock_change_unsupported; 3102 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 3103 3104 context->bw_ctx.bw.dcn.clk.zstate_support = decide_zstate_support(dc, context); 3105 3106 context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); 3107 3108 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) 3109 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; 3110 3111 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 3112 if (!context->res_ctx.pipe_ctx[i].stream) 3113 continue; 3114 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 3115 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 3116 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 3117 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 3118 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes; 3119 context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode; 3120 3121 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 3122 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 3123 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 3124 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 3125 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; 3126 pipe_idx++; 3127 } 3128 /*save a original dppclock copy*/ 3129 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; 3130 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; 3131 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000; 3132 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000; 3133 3134 context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes 3135 - context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx; 3136 3137 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 3138 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2; 3139 3140 if (!context->res_ctx.pipe_ctx[i].stream) 3141 continue; 3142 3143 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml, 3144 &context->res_ctx.pipe_ctx[i].dlg_regs, 3145 &context->res_ctx.pipe_ctx[i].ttu_regs, 3146 pipes, 3147 pipe_cnt, 3148 pipe_idx, 3149 cstate_en, 3150 context->bw_ctx.bw.dcn.clk.p_state_change_support, 3151 false, false, true); 3152 3153 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml, 3154 &context->res_ctx.pipe_ctx[i].rq_regs, 3155 pipes[pipe_idx].pipe); 3156 pipe_idx++; 3157 } 3158 } 3159 3160 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context, 3161 bool fast_validate) 3162 { 3163 bool out = false; 3164 3165 BW_VAL_TRACE_SETUP(); 3166 3167 int vlevel = 0; 3168 int pipe_split_from[MAX_PIPES]; 3169 int pipe_cnt = 0; 3170 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC); 3171 DC_LOGGER_INIT(dc->ctx->logger); 3172 3173 BW_VAL_TRACE_COUNT(); 3174 3175 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate); 3176 3177 if (pipe_cnt == 0) 3178 goto validate_out; 3179 3180 if (!out) 3181 goto validate_fail; 3182 3183 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 3184 3185 if (fast_validate) { 3186 BW_VAL_TRACE_SKIP(fast); 3187 goto validate_out; 3188 } 3189 3190 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate); 3191 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 3192 3193 BW_VAL_TRACE_END_WATERMARKS(); 3194 3195 goto validate_out; 3196 3197 validate_fail: 3198 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 3199 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 3200 3201 BW_VAL_TRACE_SKIP(fail); 3202 out = false; 3203 3204 validate_out: 3205 kfree(pipes); 3206 3207 BW_VAL_TRACE_FINISH(); 3208 3209 return out; 3210 } 3211 3212 /* 3213 * This must be noinline to ensure anything that deals with FP registers 3214 * is contained within this call; previously our compiling with hard-float 3215 * would result in fp instructions being emitted outside of the boundaries 3216 * of the DC_FP_START/END macros, which makes sense as the compiler has no 3217 * idea about what is wrapped and what is not 3218 * 3219 * This is largely just a workaround to avoid breakage introduced with 5.6, 3220 * ideally all fp-using code should be moved into its own file, only that 3221 * should be compiled with hard-float, and all code exported from there 3222 * should be strictly wrapped with DC_FP_START/END 3223 */ 3224 static noinline bool dcn20_validate_bandwidth_fp(struct dc *dc, 3225 struct dc_state *context, bool fast_validate) 3226 { 3227 bool voltage_supported = false; 3228 bool full_pstate_supported = false; 3229 bool dummy_pstate_supported = false; 3230 double p_state_latency_us; 3231 3232 p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us; 3233 context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support = 3234 dc->debug.disable_dram_clock_change_vactive_support; 3235 context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive = 3236 dc->debug.enable_dram_clock_change_one_display_vactive; 3237 3238 /*Unsafe due to current pipe merge and split logic*/ 3239 ASSERT(context != dc->current_state); 3240 3241 if (fast_validate) { 3242 return dcn20_validate_bandwidth_internal(dc, context, true); 3243 } 3244 3245 // Best case, we support full UCLK switch latency 3246 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); 3247 full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; 3248 3249 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 || 3250 (voltage_supported && full_pstate_supported)) { 3251 context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported; 3252 goto restore_dml_state; 3253 } 3254 3255 // Fallback: Try to only support G6 temperature read latency 3256 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us; 3257 3258 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); 3259 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; 3260 3261 if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) { 3262 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; 3263 goto restore_dml_state; 3264 } 3265 3266 // ERROR: fallback is supposed to always work. 3267 ASSERT(false); 3268 3269 restore_dml_state: 3270 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us; 3271 return voltage_supported; 3272 } 3273 3274 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, 3275 bool fast_validate) 3276 { 3277 bool voltage_supported; 3278 DC_FP_START(); 3279 voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate); 3280 DC_FP_END(); 3281 return voltage_supported; 3282 } 3283 3284 struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer( 3285 struct dc_state *state, 3286 const struct resource_pool *pool, 3287 struct dc_stream_state *stream) 3288 { 3289 struct resource_context *res_ctx = &state->res_ctx; 3290 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 3291 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe); 3292 3293 if (!head_pipe) 3294 ASSERT(0); 3295 3296 if (!idle_pipe) 3297 return NULL; 3298 3299 idle_pipe->stream = head_pipe->stream; 3300 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 3301 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 3302 3303 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 3304 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 3305 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 3306 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 3307 3308 return idle_pipe; 3309 } 3310 3311 bool dcn20_get_dcc_compression_cap(const struct dc *dc, 3312 const struct dc_dcc_surface_param *input, 3313 struct dc_surface_dcc_cap *output) 3314 { 3315 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 3316 dc->res_pool->hubbub, 3317 input, 3318 output); 3319 } 3320 3321 static void dcn20_destroy_resource_pool(struct resource_pool **pool) 3322 { 3323 struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool); 3324 3325 dcn20_resource_destruct(dcn20_pool); 3326 kfree(dcn20_pool); 3327 *pool = NULL; 3328 } 3329 3330 3331 static struct dc_cap_funcs cap_funcs = { 3332 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 3333 }; 3334 3335 3336 enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state) 3337 { 3338 enum surface_pixel_format surf_pix_format = plane_state->format; 3339 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 3340 3341 enum swizzle_mode_values swizzle = DC_SW_LINEAR; 3342 3343 if (bpp == 64) 3344 swizzle = DC_SW_64KB_D; 3345 else 3346 swizzle = DC_SW_64KB_S; 3347 3348 plane_state->tiling_info.gfx9.swizzle = swizzle; 3349 return DC_OK; 3350 } 3351 3352 static const struct resource_funcs dcn20_res_pool_funcs = { 3353 .destroy = dcn20_destroy_resource_pool, 3354 .link_enc_create = dcn20_link_encoder_create, 3355 .panel_cntl_create = dcn20_panel_cntl_create, 3356 .validate_bandwidth = dcn20_validate_bandwidth, 3357 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 3358 .add_stream_to_ctx = dcn20_add_stream_to_ctx, 3359 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 3360 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 3361 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, 3362 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 3363 .set_mcif_arb_params = dcn20_set_mcif_arb_params, 3364 .populate_dml_pipes = dcn20_populate_dml_pipes_from_context, 3365 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link 3366 }; 3367 3368 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 3369 { 3370 int i; 3371 uint32_t pipe_count = pool->res_cap->num_dwb; 3372 3373 for (i = 0; i < pipe_count; i++) { 3374 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc), 3375 GFP_KERNEL); 3376 3377 if (!dwbc20) { 3378 dm_error("DC: failed to create dwbc20!\n"); 3379 return false; 3380 } 3381 dcn20_dwbc_construct(dwbc20, ctx, 3382 &dwbc20_regs[i], 3383 &dwbc20_shift, 3384 &dwbc20_mask, 3385 i); 3386 pool->dwbc[i] = &dwbc20->base; 3387 } 3388 return true; 3389 } 3390 3391 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 3392 { 3393 int i; 3394 uint32_t pipe_count = pool->res_cap->num_dwb; 3395 3396 ASSERT(pipe_count > 0); 3397 3398 for (i = 0; i < pipe_count; i++) { 3399 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub), 3400 GFP_KERNEL); 3401 3402 if (!mcif_wb20) { 3403 dm_error("DC: failed to create mcif_wb20!\n"); 3404 return false; 3405 } 3406 3407 dcn20_mmhubbub_construct(mcif_wb20, ctx, 3408 &mcif_wb20_regs[i], 3409 &mcif_wb20_shift, 3410 &mcif_wb20_mask, 3411 i); 3412 3413 pool->mcif_wb[i] = &mcif_wb20->base; 3414 } 3415 return true; 3416 } 3417 3418 static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx) 3419 { 3420 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_ATOMIC); 3421 3422 if (!pp_smu) 3423 return pp_smu; 3424 3425 dm_pp_get_funcs(ctx, pp_smu); 3426 3427 if (pp_smu->ctx.ver != PP_SMU_VER_NV) 3428 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); 3429 3430 return pp_smu; 3431 } 3432 3433 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu) 3434 { 3435 if (pp_smu && *pp_smu) { 3436 kfree(*pp_smu); 3437 *pp_smu = NULL; 3438 } 3439 } 3440 3441 void dcn20_cap_soc_clocks( 3442 struct _vcs_dpi_soc_bounding_box_st *bb, 3443 struct pp_smu_nv_clock_table max_clocks) 3444 { 3445 int i; 3446 3447 // First pass - cap all clocks higher than the reported max 3448 for (i = 0; i < bb->num_states; i++) { 3449 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000)) 3450 && max_clocks.dcfClockInKhz != 0) 3451 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000); 3452 3453 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16) 3454 && max_clocks.uClockInKhz != 0) 3455 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16; 3456 3457 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000)) 3458 && max_clocks.fabricClockInKhz != 0) 3459 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000); 3460 3461 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000)) 3462 && max_clocks.displayClockInKhz != 0) 3463 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000); 3464 3465 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000)) 3466 && max_clocks.dppClockInKhz != 0) 3467 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000); 3468 3469 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000)) 3470 && max_clocks.phyClockInKhz != 0) 3471 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000); 3472 3473 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000)) 3474 && max_clocks.socClockInKhz != 0) 3475 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000); 3476 3477 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000)) 3478 && max_clocks.dscClockInKhz != 0) 3479 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000); 3480 } 3481 3482 // Second pass - remove all duplicate clock states 3483 for (i = bb->num_states - 1; i > 1; i--) { 3484 bool duplicate = true; 3485 3486 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz) 3487 duplicate = false; 3488 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz) 3489 duplicate = false; 3490 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz) 3491 duplicate = false; 3492 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts) 3493 duplicate = false; 3494 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz) 3495 duplicate = false; 3496 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz) 3497 duplicate = false; 3498 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz) 3499 duplicate = false; 3500 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz) 3501 duplicate = false; 3502 3503 if (duplicate) 3504 bb->num_states--; 3505 } 3506 } 3507 3508 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb, 3509 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) 3510 { 3511 struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES]; 3512 int i; 3513 int num_calculated_states = 0; 3514 int min_dcfclk = 0; 3515 3516 if (num_states == 0) 3517 return; 3518 3519 memset(calculated_states, 0, sizeof(calculated_states)); 3520 3521 if (dc->bb_overrides.min_dcfclk_mhz > 0) 3522 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz; 3523 else { 3524 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) 3525 min_dcfclk = 310; 3526 else 3527 // Accounting for SOC/DCF relationship, we can go as high as 3528 // 506Mhz in Vmin. 3529 min_dcfclk = 506; 3530 } 3531 3532 for (i = 0; i < num_states; i++) { 3533 int min_fclk_required_by_uclk; 3534 calculated_states[i].state = i; 3535 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000; 3536 3537 // FCLK:UCLK ratio is 1.08 3538 min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080, 3539 1000000); 3540 3541 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? 3542 min_dcfclk : min_fclk_required_by_uclk; 3543 3544 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ? 3545 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; 3546 3547 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ? 3548 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; 3549 3550 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000; 3551 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000; 3552 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3); 3553 3554 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000; 3555 3556 num_calculated_states++; 3557 } 3558 3559 calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000; 3560 calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000; 3561 calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000; 3562 3563 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits)); 3564 bb->num_states = num_calculated_states; 3565 3566 // Duplicate the last state, DML always an extra state identical to max state to work 3567 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st)); 3568 bb->clock_limits[num_calculated_states].state = bb->num_states; 3569 } 3570 3571 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) 3572 { 3573 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns 3574 && dc->bb_overrides.sr_exit_time_ns) { 3575 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; 3576 } 3577 3578 if ((int)(bb->sr_enter_plus_exit_time_us * 1000) 3579 != dc->bb_overrides.sr_enter_plus_exit_time_ns 3580 && dc->bb_overrides.sr_enter_plus_exit_time_ns) { 3581 bb->sr_enter_plus_exit_time_us = 3582 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 3583 } 3584 3585 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns 3586 && dc->bb_overrides.urgent_latency_ns) { 3587 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 3588 } 3589 3590 if ((int)(bb->dram_clock_change_latency_us * 1000) 3591 != dc->bb_overrides.dram_clock_change_latency_ns 3592 && dc->bb_overrides.dram_clock_change_latency_ns) { 3593 bb->dram_clock_change_latency_us = 3594 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 3595 } 3596 3597 if ((int)(bb->dummy_pstate_latency_us * 1000) 3598 != dc->bb_overrides.dummy_clock_change_latency_ns 3599 && dc->bb_overrides.dummy_clock_change_latency_ns) { 3600 bb->dummy_pstate_latency_us = 3601 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0; 3602 } 3603 } 3604 3605 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb( 3606 uint32_t hw_internal_rev) 3607 { 3608 if (ASICREV_IS_NAVI14_M(hw_internal_rev)) 3609 return &dcn2_0_nv14_soc; 3610 3611 if (ASICREV_IS_NAVI12_P(hw_internal_rev)) 3612 return &dcn2_0_nv12_soc; 3613 3614 return &dcn2_0_soc; 3615 } 3616 3617 static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params( 3618 uint32_t hw_internal_rev) 3619 { 3620 /* NV14 */ 3621 if (ASICREV_IS_NAVI14_M(hw_internal_rev)) 3622 return &dcn2_0_nv14_ip; 3623 3624 /* NV12 and NV10 */ 3625 return &dcn2_0_ip; 3626 } 3627 3628 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev) 3629 { 3630 return DML_PROJECT_NAVI10v2; 3631 } 3632 3633 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16))) 3634 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) 3635 3636 static bool init_soc_bounding_box(struct dc *dc, 3637 struct dcn20_resource_pool *pool) 3638 { 3639 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = 3640 get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev); 3641 struct _vcs_dpi_ip_params_st *loaded_ip = 3642 get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev); 3643 3644 DC_LOGGER_INIT(dc->ctx->logger); 3645 3646 if (pool->base.pp_smu) { 3647 struct pp_smu_nv_clock_table max_clocks = {0}; 3648 unsigned int uclk_states[8] = {0}; 3649 unsigned int num_states = 0; 3650 enum pp_smu_status status; 3651 bool clock_limits_available = false; 3652 bool uclk_states_available = false; 3653 3654 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) { 3655 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) 3656 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); 3657 3658 uclk_states_available = (status == PP_SMU_RESULT_OK); 3659 } 3660 3661 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) { 3662 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) 3663 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks); 3664 /* SMU cannot set DCF clock to anything equal to or higher than SOC clock 3665 */ 3666 if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz) 3667 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000; 3668 clock_limits_available = (status == PP_SMU_RESULT_OK); 3669 } 3670 3671 if (clock_limits_available && uclk_states_available && num_states) 3672 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states); 3673 else if (clock_limits_available) 3674 dcn20_cap_soc_clocks(loaded_bb, max_clocks); 3675 } 3676 3677 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; 3678 loaded_ip->max_num_dpp = pool->base.pipe_count; 3679 dcn20_patch_bounding_box(dc, loaded_bb); 3680 3681 return true; 3682 } 3683 3684 static bool dcn20_resource_construct( 3685 uint8_t num_virtual_links, 3686 struct dc *dc, 3687 struct dcn20_resource_pool *pool) 3688 { 3689 int i; 3690 struct dc_context *ctx = dc->ctx; 3691 struct irq_service_init_data init_data; 3692 struct ddc_service_init_data ddc_init_data = {0}; 3693 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = 3694 get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev); 3695 struct _vcs_dpi_ip_params_st *loaded_ip = 3696 get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev); 3697 enum dml_project dml_project_version = 3698 get_dml_project_version(ctx->asic_id.hw_internal_rev); 3699 3700 DC_FP_START(); 3701 3702 ctx->dc_bios->regs = &bios_regs; 3703 pool->base.funcs = &dcn20_res_pool_funcs; 3704 3705 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) { 3706 pool->base.res_cap = &res_cap_nv14; 3707 pool->base.pipe_count = 5; 3708 pool->base.mpcc_count = 5; 3709 } else { 3710 pool->base.res_cap = &res_cap_nv10; 3711 pool->base.pipe_count = 6; 3712 pool->base.mpcc_count = 6; 3713 } 3714 /************************************************* 3715 * Resource + asic cap harcoding * 3716 *************************************************/ 3717 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 3718 3719 dc->caps.max_downscale_ratio = 200; 3720 dc->caps.i2c_speed_in_khz = 100; 3721 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/ 3722 dc->caps.max_cursor_size = 256; 3723 dc->caps.min_horizontal_blanking_period = 80; 3724 dc->caps.dmdata_alloc_size = 2048; 3725 3726 dc->caps.max_slave_planes = 1; 3727 dc->caps.max_slave_yuv_planes = 1; 3728 dc->caps.max_slave_rgb_planes = 1; 3729 dc->caps.post_blend_color_processing = true; 3730 dc->caps.force_dp_tps4_for_cp2520 = true; 3731 dc->caps.extended_aux_timeout_support = true; 3732 3733 /* Color pipeline capabilities */ 3734 dc->caps.color.dpp.dcn_arch = 1; 3735 dc->caps.color.dpp.input_lut_shared = 0; 3736 dc->caps.color.dpp.icsc = 1; 3737 dc->caps.color.dpp.dgam_ram = 1; 3738 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 3739 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 3740 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0; 3741 dc->caps.color.dpp.dgam_rom_caps.pq = 0; 3742 dc->caps.color.dpp.dgam_rom_caps.hlg = 0; 3743 dc->caps.color.dpp.post_csc = 0; 3744 dc->caps.color.dpp.gamma_corr = 0; 3745 dc->caps.color.dpp.dgam_rom_for_yuv = 1; 3746 3747 dc->caps.color.dpp.hw_3d_lut = 1; 3748 dc->caps.color.dpp.ogam_ram = 1; 3749 // no OGAM ROM on DCN2, only MPC ROM 3750 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 3751 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 3752 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 3753 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 3754 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 3755 dc->caps.color.dpp.ocsc = 0; 3756 3757 dc->caps.color.mpc.gamut_remap = 0; 3758 dc->caps.color.mpc.num_3dluts = 0; 3759 dc->caps.color.mpc.shared_3d_lut = 0; 3760 dc->caps.color.mpc.ogam_ram = 1; 3761 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 3762 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 3763 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 3764 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 3765 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 3766 dc->caps.color.mpc.ocsc = 1; 3767 3768 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) { 3769 dc->debug = debug_defaults_drv; 3770 } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 3771 pool->base.pipe_count = 4; 3772 pool->base.mpcc_count = pool->base.pipe_count; 3773 dc->debug = debug_defaults_diags; 3774 } else { 3775 dc->debug = debug_defaults_diags; 3776 } 3777 //dcn2.0x 3778 dc->work_arounds.dedcn20_305_wa = true; 3779 3780 // Init the vm_helper 3781 if (dc->vm_helper) 3782 vm_helper_init(dc->vm_helper, 16); 3783 3784 /************************************************* 3785 * Create resources * 3786 *************************************************/ 3787 3788 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = 3789 dcn20_clock_source_create(ctx, ctx->dc_bios, 3790 CLOCK_SOURCE_COMBO_PHY_PLL0, 3791 &clk_src_regs[0], false); 3792 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = 3793 dcn20_clock_source_create(ctx, ctx->dc_bios, 3794 CLOCK_SOURCE_COMBO_PHY_PLL1, 3795 &clk_src_regs[1], false); 3796 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = 3797 dcn20_clock_source_create(ctx, ctx->dc_bios, 3798 CLOCK_SOURCE_COMBO_PHY_PLL2, 3799 &clk_src_regs[2], false); 3800 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] = 3801 dcn20_clock_source_create(ctx, ctx->dc_bios, 3802 CLOCK_SOURCE_COMBO_PHY_PLL3, 3803 &clk_src_regs[3], false); 3804 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] = 3805 dcn20_clock_source_create(ctx, ctx->dc_bios, 3806 CLOCK_SOURCE_COMBO_PHY_PLL4, 3807 &clk_src_regs[4], false); 3808 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] = 3809 dcn20_clock_source_create(ctx, ctx->dc_bios, 3810 CLOCK_SOURCE_COMBO_PHY_PLL5, 3811 &clk_src_regs[5], false); 3812 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL; 3813 /* todo: not reuse phy_pll registers */ 3814 pool->base.dp_clock_source = 3815 dcn20_clock_source_create(ctx, ctx->dc_bios, 3816 CLOCK_SOURCE_ID_DP_DTO, 3817 &clk_src_regs[0], true); 3818 3819 for (i = 0; i < pool->base.clk_src_count; i++) { 3820 if (pool->base.clock_sources[i] == NULL) { 3821 dm_error("DC: failed to create clock sources!\n"); 3822 BREAK_TO_DEBUGGER(); 3823 goto create_fail; 3824 } 3825 } 3826 3827 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 3828 if (pool->base.dccg == NULL) { 3829 dm_error("DC: failed to create dccg!\n"); 3830 BREAK_TO_DEBUGGER(); 3831 goto create_fail; 3832 } 3833 3834 pool->base.dmcu = dcn20_dmcu_create(ctx, 3835 &dmcu_regs, 3836 &dmcu_shift, 3837 &dmcu_mask); 3838 if (pool->base.dmcu == NULL) { 3839 dm_error("DC: failed to create dmcu!\n"); 3840 BREAK_TO_DEBUGGER(); 3841 goto create_fail; 3842 } 3843 3844 pool->base.abm = dce_abm_create(ctx, 3845 &abm_regs, 3846 &abm_shift, 3847 &abm_mask); 3848 if (pool->base.abm == NULL) { 3849 dm_error("DC: failed to create abm!\n"); 3850 BREAK_TO_DEBUGGER(); 3851 goto create_fail; 3852 } 3853 3854 pool->base.pp_smu = dcn20_pp_smu_create(ctx); 3855 3856 3857 if (!init_soc_bounding_box(dc, pool)) { 3858 dm_error("DC: failed to initialize soc bounding box!\n"); 3859 BREAK_TO_DEBUGGER(); 3860 goto create_fail; 3861 } 3862 3863 dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version); 3864 3865 if (!dc->debug.disable_pplib_wm_range) { 3866 struct pp_smu_wm_range_sets ranges = {0}; 3867 int i = 0; 3868 3869 ranges.num_reader_wm_sets = 0; 3870 3871 if (loaded_bb->num_states == 1) { 3872 ranges.reader_wm_sets[0].wm_inst = i; 3873 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3874 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3875 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3876 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3877 3878 ranges.num_reader_wm_sets = 1; 3879 } else if (loaded_bb->num_states > 1) { 3880 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { 3881 ranges.reader_wm_sets[i].wm_inst = i; 3882 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3883 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3884 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; 3885 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; 3886 3887 ranges.num_reader_wm_sets = i + 1; 3888 } 3889 3890 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3891 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3892 } 3893 3894 ranges.num_writer_wm_sets = 1; 3895 3896 ranges.writer_wm_sets[0].wm_inst = 0; 3897 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3898 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3899 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3900 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3901 3902 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 3903 if (pool->base.pp_smu->nv_funcs.set_wm_ranges) 3904 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges); 3905 } 3906 3907 init_data.ctx = dc->ctx; 3908 pool->base.irqs = dal_irq_service_dcn20_create(&init_data); 3909 if (!pool->base.irqs) 3910 goto create_fail; 3911 3912 /* mem input -> ipp -> dpp -> opp -> TG */ 3913 for (i = 0; i < pool->base.pipe_count; i++) { 3914 pool->base.hubps[i] = dcn20_hubp_create(ctx, i); 3915 if (pool->base.hubps[i] == NULL) { 3916 BREAK_TO_DEBUGGER(); 3917 dm_error( 3918 "DC: failed to create memory input!\n"); 3919 goto create_fail; 3920 } 3921 3922 pool->base.ipps[i] = dcn20_ipp_create(ctx, i); 3923 if (pool->base.ipps[i] == NULL) { 3924 BREAK_TO_DEBUGGER(); 3925 dm_error( 3926 "DC: failed to create input pixel processor!\n"); 3927 goto create_fail; 3928 } 3929 3930 pool->base.dpps[i] = dcn20_dpp_create(ctx, i); 3931 if (pool->base.dpps[i] == NULL) { 3932 BREAK_TO_DEBUGGER(); 3933 dm_error( 3934 "DC: failed to create dpps!\n"); 3935 goto create_fail; 3936 } 3937 } 3938 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 3939 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i); 3940 if (pool->base.engines[i] == NULL) { 3941 BREAK_TO_DEBUGGER(); 3942 dm_error( 3943 "DC:failed to create aux engine!!\n"); 3944 goto create_fail; 3945 } 3946 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i); 3947 if (pool->base.hw_i2cs[i] == NULL) { 3948 BREAK_TO_DEBUGGER(); 3949 dm_error( 3950 "DC:failed to create hw i2c!!\n"); 3951 goto create_fail; 3952 } 3953 pool->base.sw_i2cs[i] = NULL; 3954 } 3955 3956 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 3957 pool->base.opps[i] = dcn20_opp_create(ctx, i); 3958 if (pool->base.opps[i] == NULL) { 3959 BREAK_TO_DEBUGGER(); 3960 dm_error( 3961 "DC: failed to create output pixel processor!\n"); 3962 goto create_fail; 3963 } 3964 } 3965 3966 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 3967 pool->base.timing_generators[i] = dcn20_timing_generator_create( 3968 ctx, i); 3969 if (pool->base.timing_generators[i] == NULL) { 3970 BREAK_TO_DEBUGGER(); 3971 dm_error("DC: failed to create tg!\n"); 3972 goto create_fail; 3973 } 3974 } 3975 3976 pool->base.timing_generator_count = i; 3977 3978 pool->base.mpc = dcn20_mpc_create(ctx); 3979 if (pool->base.mpc == NULL) { 3980 BREAK_TO_DEBUGGER(); 3981 dm_error("DC: failed to create mpc!\n"); 3982 goto create_fail; 3983 } 3984 3985 pool->base.hubbub = dcn20_hubbub_create(ctx); 3986 if (pool->base.hubbub == NULL) { 3987 BREAK_TO_DEBUGGER(); 3988 dm_error("DC: failed to create hubbub!\n"); 3989 goto create_fail; 3990 } 3991 3992 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 3993 pool->base.dscs[i] = dcn20_dsc_create(ctx, i); 3994 if (pool->base.dscs[i] == NULL) { 3995 BREAK_TO_DEBUGGER(); 3996 dm_error("DC: failed to create display stream compressor %d!\n", i); 3997 goto create_fail; 3998 } 3999 } 4000 4001 if (!dcn20_dwbc_create(ctx, &pool->base)) { 4002 BREAK_TO_DEBUGGER(); 4003 dm_error("DC: failed to create dwbc!\n"); 4004 goto create_fail; 4005 } 4006 if (!dcn20_mmhubbub_create(ctx, &pool->base)) { 4007 BREAK_TO_DEBUGGER(); 4008 dm_error("DC: failed to create mcif_wb!\n"); 4009 goto create_fail; 4010 } 4011 4012 if (!resource_construct(num_virtual_links, dc, &pool->base, 4013 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 4014 &res_create_funcs : &res_create_maximus_funcs))) 4015 goto create_fail; 4016 4017 dcn20_hw_sequencer_construct(dc); 4018 4019 // IF NV12, set PG function pointer to NULL. It's not that 4020 // PG isn't supported for NV12, it's that we don't want to 4021 // program the registers because that will cause more power 4022 // to be consumed. We could have created dcn20_init_hw to get 4023 // the same effect by checking ASIC rev, but there was a 4024 // request at some point to not check ASIC rev on hw sequencer. 4025 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) { 4026 dc->hwseq->funcs.enable_power_gating_plane = NULL; 4027 dc->debug.disable_dpp_power_gate = true; 4028 dc->debug.disable_hubp_power_gate = true; 4029 } 4030 4031 4032 dc->caps.max_planes = pool->base.pipe_count; 4033 4034 for (i = 0; i < dc->caps.max_planes; ++i) 4035 dc->caps.planes[i] = plane_cap; 4036 4037 dc->cap_funcs = cap_funcs; 4038 4039 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 4040 ddc_init_data.ctx = dc->ctx; 4041 ddc_init_data.link = NULL; 4042 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 4043 ddc_init_data.id.enum_id = 0; 4044 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 4045 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); 4046 } else { 4047 pool->base.oem_device = NULL; 4048 } 4049 4050 DC_FP_END(); 4051 return true; 4052 4053 create_fail: 4054 4055 DC_FP_END(); 4056 dcn20_resource_destruct(pool); 4057 4058 return false; 4059 } 4060 4061 struct resource_pool *dcn20_create_resource_pool( 4062 const struct dc_init_data *init_data, 4063 struct dc *dc) 4064 { 4065 struct dcn20_resource_pool *pool = 4066 kzalloc(sizeof(struct dcn20_resource_pool), GFP_ATOMIC); 4067 4068 if (!pool) 4069 return NULL; 4070 4071 if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool)) 4072 return &pool->base; 4073 4074 BREAK_TO_DEBUGGER(); 4075 kfree(pool); 4076 return NULL; 4077 } 4078