1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 #include "dc.h" 30 31 #include "dcn20_init.h" 32 33 #include "resource.h" 34 #include "include/irq_service_interface.h" 35 #include "dcn20/dcn20_resource.h" 36 37 #include "dcn10/dcn10_hubp.h" 38 #include "dcn10/dcn10_ipp.h" 39 #include "dcn20_hubbub.h" 40 #include "dcn20_mpc.h" 41 #include "dcn20_hubp.h" 42 #include "irq/dcn20/irq_service_dcn20.h" 43 #include "dcn20_dpp.h" 44 #include "dcn20_optc.h" 45 #include "dcn20_hwseq.h" 46 #include "dce110/dce110_hw_sequencer.h" 47 #include "dcn10/dcn10_resource.h" 48 #include "dcn20_opp.h" 49 50 #include "dcn20_dsc.h" 51 52 #include "dcn20_link_encoder.h" 53 #include "dcn20_stream_encoder.h" 54 #include "dce/dce_clock_source.h" 55 #include "dce/dce_audio.h" 56 #include "dce/dce_hwseq.h" 57 #include "virtual/virtual_stream_encoder.h" 58 #include "dce110/dce110_resource.h" 59 #include "dml/display_mode_vba.h" 60 #include "dcn20_dccg.h" 61 #include "dcn20_vmid.h" 62 #include "dc_link_ddc.h" 63 64 #include "navi10_ip_offset.h" 65 66 #include "dcn/dcn_2_0_0_offset.h" 67 #include "dcn/dcn_2_0_0_sh_mask.h" 68 69 #include "nbio/nbio_2_3_offset.h" 70 71 #include "dcn20/dcn20_dwb.h" 72 #include "dcn20/dcn20_mmhubbub.h" 73 74 #include "mmhub/mmhub_2_0_0_offset.h" 75 #include "mmhub/mmhub_2_0_0_sh_mask.h" 76 77 #include "reg_helper.h" 78 #include "dce/dce_abm.h" 79 #include "dce/dce_dmcu.h" 80 #include "dce/dce_aux.h" 81 #include "dce/dce_i2c.h" 82 #include "vm_helper.h" 83 84 #include "amdgpu_socbb.h" 85 86 #define DC_LOGGER_INIT(logger) 87 88 struct _vcs_dpi_ip_params_st dcn2_0_ip = { 89 .odm_capable = 1, 90 .gpuvm_enable = 0, 91 .hostvm_enable = 0, 92 .gpuvm_max_page_table_levels = 4, 93 .hostvm_max_page_table_levels = 4, 94 .hostvm_cached_page_table_levels = 0, 95 .pte_group_size_bytes = 2048, 96 .num_dsc = 6, 97 .rob_buffer_size_kbytes = 168, 98 .det_buffer_size_kbytes = 164, 99 .dpte_buffer_size_in_pte_reqs_luma = 84, 100 .pde_proc_buffer_size_64k_reqs = 48, 101 .dpp_output_buffer_pixels = 2560, 102 .opp_output_buffer_lines = 1, 103 .pixel_chunk_size_kbytes = 8, 104 .pte_chunk_size_kbytes = 2, 105 .meta_chunk_size_kbytes = 2, 106 .writeback_chunk_size_kbytes = 2, 107 .line_buffer_size_bits = 789504, 108 .is_line_buffer_bpp_fixed = 0, 109 .line_buffer_fixed_bpp = 0, 110 .dcc_supported = true, 111 .max_line_buffer_lines = 12, 112 .writeback_luma_buffer_size_kbytes = 12, 113 .writeback_chroma_buffer_size_kbytes = 8, 114 .writeback_chroma_line_buffer_width_pixels = 4, 115 .writeback_max_hscl_ratio = 1, 116 .writeback_max_vscl_ratio = 1, 117 .writeback_min_hscl_ratio = 1, 118 .writeback_min_vscl_ratio = 1, 119 .writeback_max_hscl_taps = 12, 120 .writeback_max_vscl_taps = 12, 121 .writeback_line_buffer_luma_buffer_size = 0, 122 .writeback_line_buffer_chroma_buffer_size = 14643, 123 .cursor_buffer_size = 8, 124 .cursor_chunk_size = 2, 125 .max_num_otg = 6, 126 .max_num_dpp = 6, 127 .max_num_wb = 1, 128 .max_dchub_pscl_bw_pix_per_clk = 4, 129 .max_pscl_lb_bw_pix_per_clk = 2, 130 .max_lb_vscl_bw_pix_per_clk = 4, 131 .max_vscl_hscl_bw_pix_per_clk = 4, 132 .max_hscl_ratio = 8, 133 .max_vscl_ratio = 8, 134 .hscl_mults = 4, 135 .vscl_mults = 4, 136 .max_hscl_taps = 8, 137 .max_vscl_taps = 8, 138 .dispclk_ramp_margin_percent = 1, 139 .underscan_factor = 1.10, 140 .min_vblank_lines = 32, // 141 .dppclk_delay_subtotal = 77, // 142 .dppclk_delay_scl_lb_only = 16, 143 .dppclk_delay_scl = 50, 144 .dppclk_delay_cnvc_formatter = 8, 145 .dppclk_delay_cnvc_cursor = 6, 146 .dispclk_delay_subtotal = 87, // 147 .dcfclk_cstate_latency = 10, // SRExitTime 148 .max_inter_dcn_tile_repeaters = 8, 149 150 .xfc_supported = true, 151 .xfc_fill_bw_overhead_percent = 10.0, 152 .xfc_fill_constant_bytes = 0, 153 }; 154 155 struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = { 156 .odm_capable = 1, 157 .gpuvm_enable = 0, 158 .hostvm_enable = 0, 159 .gpuvm_max_page_table_levels = 4, 160 .hostvm_max_page_table_levels = 4, 161 .hostvm_cached_page_table_levels = 0, 162 .num_dsc = 5, 163 .rob_buffer_size_kbytes = 168, 164 .det_buffer_size_kbytes = 164, 165 .dpte_buffer_size_in_pte_reqs_luma = 84, 166 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo 167 .dpp_output_buffer_pixels = 2560, 168 .opp_output_buffer_lines = 1, 169 .pixel_chunk_size_kbytes = 8, 170 .pte_enable = 1, 171 .max_page_table_levels = 4, 172 .pte_chunk_size_kbytes = 2, 173 .meta_chunk_size_kbytes = 2, 174 .writeback_chunk_size_kbytes = 2, 175 .line_buffer_size_bits = 789504, 176 .is_line_buffer_bpp_fixed = 0, 177 .line_buffer_fixed_bpp = 0, 178 .dcc_supported = true, 179 .max_line_buffer_lines = 12, 180 .writeback_luma_buffer_size_kbytes = 12, 181 .writeback_chroma_buffer_size_kbytes = 8, 182 .writeback_chroma_line_buffer_width_pixels = 4, 183 .writeback_max_hscl_ratio = 1, 184 .writeback_max_vscl_ratio = 1, 185 .writeback_min_hscl_ratio = 1, 186 .writeback_min_vscl_ratio = 1, 187 .writeback_max_hscl_taps = 12, 188 .writeback_max_vscl_taps = 12, 189 .writeback_line_buffer_luma_buffer_size = 0, 190 .writeback_line_buffer_chroma_buffer_size = 14643, 191 .cursor_buffer_size = 8, 192 .cursor_chunk_size = 2, 193 .max_num_otg = 5, 194 .max_num_dpp = 5, 195 .max_num_wb = 1, 196 .max_dchub_pscl_bw_pix_per_clk = 4, 197 .max_pscl_lb_bw_pix_per_clk = 2, 198 .max_lb_vscl_bw_pix_per_clk = 4, 199 .max_vscl_hscl_bw_pix_per_clk = 4, 200 .max_hscl_ratio = 8, 201 .max_vscl_ratio = 8, 202 .hscl_mults = 4, 203 .vscl_mults = 4, 204 .max_hscl_taps = 8, 205 .max_vscl_taps = 8, 206 .dispclk_ramp_margin_percent = 1, 207 .underscan_factor = 1.10, 208 .min_vblank_lines = 32, // 209 .dppclk_delay_subtotal = 77, // 210 .dppclk_delay_scl_lb_only = 16, 211 .dppclk_delay_scl = 50, 212 .dppclk_delay_cnvc_formatter = 8, 213 .dppclk_delay_cnvc_cursor = 6, 214 .dispclk_delay_subtotal = 87, // 215 .dcfclk_cstate_latency = 10, // SRExitTime 216 .max_inter_dcn_tile_repeaters = 8, 217 .xfc_supported = true, 218 .xfc_fill_bw_overhead_percent = 10.0, 219 .xfc_fill_constant_bytes = 0, 220 .ptoi_supported = 0 221 }; 222 223 struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { 224 /* Defaults that get patched on driver load from firmware. */ 225 .clock_limits = { 226 { 227 .state = 0, 228 .dcfclk_mhz = 560.0, 229 .fabricclk_mhz = 560.0, 230 .dispclk_mhz = 513.0, 231 .dppclk_mhz = 513.0, 232 .phyclk_mhz = 540.0, 233 .socclk_mhz = 560.0, 234 .dscclk_mhz = 171.0, 235 .dram_speed_mts = 8960.0, 236 }, 237 { 238 .state = 1, 239 .dcfclk_mhz = 694.0, 240 .fabricclk_mhz = 694.0, 241 .dispclk_mhz = 642.0, 242 .dppclk_mhz = 642.0, 243 .phyclk_mhz = 600.0, 244 .socclk_mhz = 694.0, 245 .dscclk_mhz = 214.0, 246 .dram_speed_mts = 11104.0, 247 }, 248 { 249 .state = 2, 250 .dcfclk_mhz = 875.0, 251 .fabricclk_mhz = 875.0, 252 .dispclk_mhz = 734.0, 253 .dppclk_mhz = 734.0, 254 .phyclk_mhz = 810.0, 255 .socclk_mhz = 875.0, 256 .dscclk_mhz = 245.0, 257 .dram_speed_mts = 14000.0, 258 }, 259 { 260 .state = 3, 261 .dcfclk_mhz = 1000.0, 262 .fabricclk_mhz = 1000.0, 263 .dispclk_mhz = 1100.0, 264 .dppclk_mhz = 1100.0, 265 .phyclk_mhz = 810.0, 266 .socclk_mhz = 1000.0, 267 .dscclk_mhz = 367.0, 268 .dram_speed_mts = 16000.0, 269 }, 270 { 271 .state = 4, 272 .dcfclk_mhz = 1200.0, 273 .fabricclk_mhz = 1200.0, 274 .dispclk_mhz = 1284.0, 275 .dppclk_mhz = 1284.0, 276 .phyclk_mhz = 810.0, 277 .socclk_mhz = 1200.0, 278 .dscclk_mhz = 428.0, 279 .dram_speed_mts = 16000.0, 280 }, 281 /*Extra state, no dispclk ramping*/ 282 { 283 .state = 5, 284 .dcfclk_mhz = 1200.0, 285 .fabricclk_mhz = 1200.0, 286 .dispclk_mhz = 1284.0, 287 .dppclk_mhz = 1284.0, 288 .phyclk_mhz = 810.0, 289 .socclk_mhz = 1200.0, 290 .dscclk_mhz = 428.0, 291 .dram_speed_mts = 16000.0, 292 }, 293 }, 294 .num_states = 5, 295 .sr_exit_time_us = 8.6, 296 .sr_enter_plus_exit_time_us = 10.9, 297 .urgent_latency_us = 4.0, 298 .urgent_latency_pixel_data_only_us = 4.0, 299 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 300 .urgent_latency_vm_data_only_us = 4.0, 301 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 302 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 303 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 304 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0, 305 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0, 306 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 307 .max_avg_sdp_bw_use_normal_percent = 40.0, 308 .max_avg_dram_bw_use_normal_percent = 40.0, 309 .writeback_latency_us = 12.0, 310 .ideal_dram_bw_after_urgent_percent = 40.0, 311 .max_request_size_bytes = 256, 312 .dram_channel_width_bytes = 2, 313 .fabric_datapath_to_dcn_data_return_bytes = 64, 314 .dcn_downspread_percent = 0.5, 315 .downspread_percent = 0.38, 316 .dram_page_open_time_ns = 50.0, 317 .dram_rw_turnaround_time_ns = 17.5, 318 .dram_return_buffer_per_channel_bytes = 8192, 319 .round_trip_ping_latency_dcfclk_cycles = 131, 320 .urgent_out_of_order_return_per_channel_bytes = 256, 321 .channel_interleave_bytes = 256, 322 .num_banks = 8, 323 .num_chans = 16, 324 .vmm_page_size_bytes = 4096, 325 .dram_clock_change_latency_us = 404.0, 326 .dummy_pstate_latency_us = 5.0, 327 .writeback_dram_clock_change_latency_us = 23.0, 328 .return_bus_width_bytes = 64, 329 .dispclk_dppclk_vco_speed_mhz = 3850, 330 .xfc_bus_transport_time_us = 20, 331 .xfc_xbuf_latency_tolerance_us = 4, 332 .use_urgent_burst_bw = 0 333 }; 334 335 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 }; 336 337 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 338 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 339 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 340 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 341 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 342 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 343 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 344 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 345 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 346 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 347 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 348 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 349 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 350 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 351 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 352 #endif 353 354 355 enum dcn20_clk_src_array_id { 356 DCN20_CLK_SRC_PLL0, 357 DCN20_CLK_SRC_PLL1, 358 DCN20_CLK_SRC_PLL2, 359 DCN20_CLK_SRC_PLL3, 360 DCN20_CLK_SRC_PLL4, 361 DCN20_CLK_SRC_PLL5, 362 DCN20_CLK_SRC_TOTAL 363 }; 364 365 /* begin ********************* 366 * macros to expend register list macro defined in HW object header file */ 367 368 /* DCN */ 369 /* TODO awful hack. fixup dcn20_dwb.h */ 370 #undef BASE_INNER 371 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 372 373 #define BASE(seg) BASE_INNER(seg) 374 375 #define SR(reg_name)\ 376 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 377 mm ## reg_name 378 379 #define SRI(reg_name, block, id)\ 380 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 381 mm ## block ## id ## _ ## reg_name 382 383 #define SRIR(var_name, reg_name, block, id)\ 384 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 385 mm ## block ## id ## _ ## reg_name 386 387 #define SRII(reg_name, block, id)\ 388 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 389 mm ## block ## id ## _ ## reg_name 390 391 #define DCCG_SRII(reg_name, block, id)\ 392 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 393 mm ## block ## id ## _ ## reg_name 394 395 /* NBIO */ 396 #define NBIO_BASE_INNER(seg) \ 397 NBIO_BASE__INST0_SEG ## seg 398 399 #define NBIO_BASE(seg) \ 400 NBIO_BASE_INNER(seg) 401 402 #define NBIO_SR(reg_name)\ 403 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 404 mm ## reg_name 405 406 /* MMHUB */ 407 #define MMHUB_BASE_INNER(seg) \ 408 MMHUB_BASE__INST0_SEG ## seg 409 410 #define MMHUB_BASE(seg) \ 411 MMHUB_BASE_INNER(seg) 412 413 #define MMHUB_SR(reg_name)\ 414 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 415 mmMM ## reg_name 416 417 static const struct bios_registers bios_regs = { 418 NBIO_SR(BIOS_SCRATCH_3), 419 NBIO_SR(BIOS_SCRATCH_6) 420 }; 421 422 #define clk_src_regs(index, pllid)\ 423 [index] = {\ 424 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\ 425 } 426 427 static const struct dce110_clk_src_regs clk_src_regs[] = { 428 clk_src_regs(0, A), 429 clk_src_regs(1, B), 430 clk_src_regs(2, C), 431 clk_src_regs(3, D), 432 clk_src_regs(4, E), 433 clk_src_regs(5, F) 434 }; 435 436 static const struct dce110_clk_src_shift cs_shift = { 437 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 438 }; 439 440 static const struct dce110_clk_src_mask cs_mask = { 441 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 442 }; 443 444 static const struct dce_dmcu_registers dmcu_regs = { 445 DMCU_DCN10_REG_LIST() 446 }; 447 448 static const struct dce_dmcu_shift dmcu_shift = { 449 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 450 }; 451 452 static const struct dce_dmcu_mask dmcu_mask = { 453 DMCU_MASK_SH_LIST_DCN10(_MASK) 454 }; 455 456 static const struct dce_abm_registers abm_regs = { 457 ABM_DCN20_REG_LIST() 458 }; 459 460 static const struct dce_abm_shift abm_shift = { 461 ABM_MASK_SH_LIST_DCN20(__SHIFT) 462 }; 463 464 static const struct dce_abm_mask abm_mask = { 465 ABM_MASK_SH_LIST_DCN20(_MASK) 466 }; 467 468 #define audio_regs(id)\ 469 [id] = {\ 470 AUD_COMMON_REG_LIST(id)\ 471 } 472 473 static const struct dce_audio_registers audio_regs[] = { 474 audio_regs(0), 475 audio_regs(1), 476 audio_regs(2), 477 audio_regs(3), 478 audio_regs(4), 479 audio_regs(5), 480 audio_regs(6), 481 }; 482 483 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 484 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 485 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 486 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 487 488 static const struct dce_audio_shift audio_shift = { 489 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 490 }; 491 492 static const struct dce_audio_mask audio_mask = { 493 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 494 }; 495 496 #define stream_enc_regs(id)\ 497 [id] = {\ 498 SE_DCN2_REG_LIST(id)\ 499 } 500 501 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 502 stream_enc_regs(0), 503 stream_enc_regs(1), 504 stream_enc_regs(2), 505 stream_enc_regs(3), 506 stream_enc_regs(4), 507 stream_enc_regs(5), 508 }; 509 510 static const struct dcn10_stream_encoder_shift se_shift = { 511 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) 512 }; 513 514 static const struct dcn10_stream_encoder_mask se_mask = { 515 SE_COMMON_MASK_SH_LIST_DCN20(_MASK) 516 }; 517 518 519 #define aux_regs(id)\ 520 [id] = {\ 521 DCN2_AUX_REG_LIST(id)\ 522 } 523 524 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 525 aux_regs(0), 526 aux_regs(1), 527 aux_regs(2), 528 aux_regs(3), 529 aux_regs(4), 530 aux_regs(5) 531 }; 532 533 #define hpd_regs(id)\ 534 [id] = {\ 535 HPD_REG_LIST(id)\ 536 } 537 538 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 539 hpd_regs(0), 540 hpd_regs(1), 541 hpd_regs(2), 542 hpd_regs(3), 543 hpd_regs(4), 544 hpd_regs(5) 545 }; 546 547 #define link_regs(id, phyid)\ 548 [id] = {\ 549 LE_DCN10_REG_LIST(id), \ 550 UNIPHY_DCN2_REG_LIST(phyid), \ 551 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 552 } 553 554 static const struct dcn10_link_enc_registers link_enc_regs[] = { 555 link_regs(0, A), 556 link_regs(1, B), 557 link_regs(2, C), 558 link_regs(3, D), 559 link_regs(4, E), 560 link_regs(5, F) 561 }; 562 563 static const struct dcn10_link_enc_shift le_shift = { 564 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT) 565 }; 566 567 static const struct dcn10_link_enc_mask le_mask = { 568 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK) 569 }; 570 571 #define ipp_regs(id)\ 572 [id] = {\ 573 IPP_REG_LIST_DCN20(id),\ 574 } 575 576 static const struct dcn10_ipp_registers ipp_regs[] = { 577 ipp_regs(0), 578 ipp_regs(1), 579 ipp_regs(2), 580 ipp_regs(3), 581 ipp_regs(4), 582 ipp_regs(5), 583 }; 584 585 static const struct dcn10_ipp_shift ipp_shift = { 586 IPP_MASK_SH_LIST_DCN20(__SHIFT) 587 }; 588 589 static const struct dcn10_ipp_mask ipp_mask = { 590 IPP_MASK_SH_LIST_DCN20(_MASK), 591 }; 592 593 #define opp_regs(id)\ 594 [id] = {\ 595 OPP_REG_LIST_DCN20(id),\ 596 } 597 598 static const struct dcn20_opp_registers opp_regs[] = { 599 opp_regs(0), 600 opp_regs(1), 601 opp_regs(2), 602 opp_regs(3), 603 opp_regs(4), 604 opp_regs(5), 605 }; 606 607 static const struct dcn20_opp_shift opp_shift = { 608 OPP_MASK_SH_LIST_DCN20(__SHIFT) 609 }; 610 611 static const struct dcn20_opp_mask opp_mask = { 612 OPP_MASK_SH_LIST_DCN20(_MASK) 613 }; 614 615 #define aux_engine_regs(id)\ 616 [id] = {\ 617 AUX_COMMON_REG_LIST0(id), \ 618 .AUXN_IMPCAL = 0, \ 619 .AUXP_IMPCAL = 0, \ 620 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 621 } 622 623 static const struct dce110_aux_registers aux_engine_regs[] = { 624 aux_engine_regs(0), 625 aux_engine_regs(1), 626 aux_engine_regs(2), 627 aux_engine_regs(3), 628 aux_engine_regs(4), 629 aux_engine_regs(5) 630 }; 631 632 #define tf_regs(id)\ 633 [id] = {\ 634 TF_REG_LIST_DCN20(id),\ 635 } 636 637 static const struct dcn2_dpp_registers tf_regs[] = { 638 tf_regs(0), 639 tf_regs(1), 640 tf_regs(2), 641 tf_regs(3), 642 tf_regs(4), 643 tf_regs(5), 644 }; 645 646 static const struct dcn2_dpp_shift tf_shift = { 647 TF_REG_LIST_SH_MASK_DCN20(__SHIFT), 648 TF_DEBUG_REG_LIST_SH_DCN10 649 }; 650 651 static const struct dcn2_dpp_mask tf_mask = { 652 TF_REG_LIST_SH_MASK_DCN20(_MASK), 653 TF_DEBUG_REG_LIST_MASK_DCN10 654 }; 655 656 #define dwbc_regs_dcn2(id)\ 657 [id] = {\ 658 DWBC_COMMON_REG_LIST_DCN2_0(id),\ 659 } 660 661 static const struct dcn20_dwbc_registers dwbc20_regs[] = { 662 dwbc_regs_dcn2(0), 663 }; 664 665 static const struct dcn20_dwbc_shift dwbc20_shift = { 666 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 667 }; 668 669 static const struct dcn20_dwbc_mask dwbc20_mask = { 670 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 671 }; 672 673 #define mcif_wb_regs_dcn2(id)\ 674 [id] = {\ 675 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\ 676 } 677 678 static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = { 679 mcif_wb_regs_dcn2(0), 680 }; 681 682 static const struct dcn20_mmhubbub_shift mcif_wb20_shift = { 683 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 684 }; 685 686 static const struct dcn20_mmhubbub_mask mcif_wb20_mask = { 687 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 688 }; 689 690 static const struct dcn20_mpc_registers mpc_regs = { 691 MPC_REG_LIST_DCN2_0(0), 692 MPC_REG_LIST_DCN2_0(1), 693 MPC_REG_LIST_DCN2_0(2), 694 MPC_REG_LIST_DCN2_0(3), 695 MPC_REG_LIST_DCN2_0(4), 696 MPC_REG_LIST_DCN2_0(5), 697 MPC_OUT_MUX_REG_LIST_DCN2_0(0), 698 MPC_OUT_MUX_REG_LIST_DCN2_0(1), 699 MPC_OUT_MUX_REG_LIST_DCN2_0(2), 700 MPC_OUT_MUX_REG_LIST_DCN2_0(3), 701 MPC_OUT_MUX_REG_LIST_DCN2_0(4), 702 MPC_OUT_MUX_REG_LIST_DCN2_0(5), 703 }; 704 705 static const struct dcn20_mpc_shift mpc_shift = { 706 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 707 }; 708 709 static const struct dcn20_mpc_mask mpc_mask = { 710 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 711 }; 712 713 #define tg_regs(id)\ 714 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)} 715 716 717 static const struct dcn_optc_registers tg_regs[] = { 718 tg_regs(0), 719 tg_regs(1), 720 tg_regs(2), 721 tg_regs(3), 722 tg_regs(4), 723 tg_regs(5) 724 }; 725 726 static const struct dcn_optc_shift tg_shift = { 727 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 728 }; 729 730 static const struct dcn_optc_mask tg_mask = { 731 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 732 }; 733 734 #define hubp_regs(id)\ 735 [id] = {\ 736 HUBP_REG_LIST_DCN20(id)\ 737 } 738 739 static const struct dcn_hubp2_registers hubp_regs[] = { 740 hubp_regs(0), 741 hubp_regs(1), 742 hubp_regs(2), 743 hubp_regs(3), 744 hubp_regs(4), 745 hubp_regs(5) 746 }; 747 748 static const struct dcn_hubp2_shift hubp_shift = { 749 HUBP_MASK_SH_LIST_DCN20(__SHIFT) 750 }; 751 752 static const struct dcn_hubp2_mask hubp_mask = { 753 HUBP_MASK_SH_LIST_DCN20(_MASK) 754 }; 755 756 static const struct dcn_hubbub_registers hubbub_reg = { 757 HUBBUB_REG_LIST_DCN20(0) 758 }; 759 760 static const struct dcn_hubbub_shift hubbub_shift = { 761 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT) 762 }; 763 764 static const struct dcn_hubbub_mask hubbub_mask = { 765 HUBBUB_MASK_SH_LIST_DCN20(_MASK) 766 }; 767 768 #define vmid_regs(id)\ 769 [id] = {\ 770 DCN20_VMID_REG_LIST(id)\ 771 } 772 773 static const struct dcn_vmid_registers vmid_regs[] = { 774 vmid_regs(0), 775 vmid_regs(1), 776 vmid_regs(2), 777 vmid_regs(3), 778 vmid_regs(4), 779 vmid_regs(5), 780 vmid_regs(6), 781 vmid_regs(7), 782 vmid_regs(8), 783 vmid_regs(9), 784 vmid_regs(10), 785 vmid_regs(11), 786 vmid_regs(12), 787 vmid_regs(13), 788 vmid_regs(14), 789 vmid_regs(15) 790 }; 791 792 static const struct dcn20_vmid_shift vmid_shifts = { 793 DCN20_VMID_MASK_SH_LIST(__SHIFT) 794 }; 795 796 static const struct dcn20_vmid_mask vmid_masks = { 797 DCN20_VMID_MASK_SH_LIST(_MASK) 798 }; 799 800 static const struct dce110_aux_registers_shift aux_shift = { 801 DCN_AUX_MASK_SH_LIST(__SHIFT) 802 }; 803 804 static const struct dce110_aux_registers_mask aux_mask = { 805 DCN_AUX_MASK_SH_LIST(_MASK) 806 }; 807 808 static int map_transmitter_id_to_phy_instance( 809 enum transmitter transmitter) 810 { 811 switch (transmitter) { 812 case TRANSMITTER_UNIPHY_A: 813 return 0; 814 break; 815 case TRANSMITTER_UNIPHY_B: 816 return 1; 817 break; 818 case TRANSMITTER_UNIPHY_C: 819 return 2; 820 break; 821 case TRANSMITTER_UNIPHY_D: 822 return 3; 823 break; 824 case TRANSMITTER_UNIPHY_E: 825 return 4; 826 break; 827 case TRANSMITTER_UNIPHY_F: 828 return 5; 829 break; 830 default: 831 ASSERT(0); 832 return 0; 833 } 834 } 835 836 #define dsc_regsDCN20(id)\ 837 [id] = {\ 838 DSC_REG_LIST_DCN20(id)\ 839 } 840 841 static const struct dcn20_dsc_registers dsc_regs[] = { 842 dsc_regsDCN20(0), 843 dsc_regsDCN20(1), 844 dsc_regsDCN20(2), 845 dsc_regsDCN20(3), 846 dsc_regsDCN20(4), 847 dsc_regsDCN20(5) 848 }; 849 850 static const struct dcn20_dsc_shift dsc_shift = { 851 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 852 }; 853 854 static const struct dcn20_dsc_mask dsc_mask = { 855 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 856 }; 857 858 static const struct dccg_registers dccg_regs = { 859 DCCG_REG_LIST_DCN2() 860 }; 861 862 static const struct dccg_shift dccg_shift = { 863 DCCG_MASK_SH_LIST_DCN2(__SHIFT) 864 }; 865 866 static const struct dccg_mask dccg_mask = { 867 DCCG_MASK_SH_LIST_DCN2(_MASK) 868 }; 869 870 static const struct resource_caps res_cap_nv10 = { 871 .num_timing_generator = 6, 872 .num_opp = 6, 873 .num_video_plane = 6, 874 .num_audio = 7, 875 .num_stream_encoder = 6, 876 .num_pll = 6, 877 .num_dwb = 1, 878 .num_ddc = 6, 879 .num_vmid = 16, 880 .num_dsc = 6, 881 }; 882 883 static const struct dc_plane_cap plane_cap = { 884 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 885 .blends_with_above = true, 886 .blends_with_below = true, 887 .per_pixel_alpha = true, 888 889 .pixel_format_support = { 890 .argb8888 = true, 891 .nv12 = true, 892 .fp16 = true 893 }, 894 895 .max_upscale_factor = { 896 .argb8888 = 16000, 897 .nv12 = 16000, 898 .fp16 = 1 899 }, 900 901 .max_downscale_factor = { 902 .argb8888 = 250, 903 .nv12 = 250, 904 .fp16 = 1 905 } 906 }; 907 static const struct resource_caps res_cap_nv14 = { 908 .num_timing_generator = 5, 909 .num_opp = 5, 910 .num_video_plane = 5, 911 .num_audio = 6, 912 .num_stream_encoder = 5, 913 .num_pll = 5, 914 .num_dwb = 1, 915 .num_ddc = 5, 916 .num_vmid = 16, 917 .num_dsc = 5, 918 }; 919 920 static const struct dc_debug_options debug_defaults_drv = { 921 .disable_dmcu = true, 922 .force_abm_enable = false, 923 .timing_trace = false, 924 .clock_trace = true, 925 .disable_pplib_clock_request = true, 926 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 927 .force_single_disp_pipe_split = false, 928 .disable_dcc = DCC_ENABLE, 929 .vsr_support = true, 930 .performance_trace = false, 931 .max_downscale_src_width = 5120,/*upto 5K*/ 932 .disable_pplib_wm_range = false, 933 .scl_reset_length10 = true, 934 .sanity_checks = false, 935 .disable_tri_buf = true, 936 .underflow_assert_delay_us = 0xFFFFFFFF, 937 }; 938 939 static const struct dc_debug_options debug_defaults_diags = { 940 .disable_dmcu = true, 941 .force_abm_enable = false, 942 .timing_trace = true, 943 .clock_trace = true, 944 .disable_dpp_power_gate = true, 945 .disable_hubp_power_gate = true, 946 .disable_clock_gate = true, 947 .disable_pplib_clock_request = true, 948 .disable_pplib_wm_range = true, 949 .disable_stutter = true, 950 .scl_reset_length10 = true, 951 .underflow_assert_delay_us = 0xFFFFFFFF, 952 }; 953 954 void dcn20_dpp_destroy(struct dpp **dpp) 955 { 956 kfree(TO_DCN20_DPP(*dpp)); 957 *dpp = NULL; 958 } 959 960 struct dpp *dcn20_dpp_create( 961 struct dc_context *ctx, 962 uint32_t inst) 963 { 964 struct dcn20_dpp *dpp = 965 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL); 966 967 if (!dpp) 968 return NULL; 969 970 if (dpp2_construct(dpp, ctx, inst, 971 &tf_regs[inst], &tf_shift, &tf_mask)) 972 return &dpp->base; 973 974 BREAK_TO_DEBUGGER(); 975 kfree(dpp); 976 return NULL; 977 } 978 979 struct input_pixel_processor *dcn20_ipp_create( 980 struct dc_context *ctx, uint32_t inst) 981 { 982 struct dcn10_ipp *ipp = 983 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 984 985 if (!ipp) { 986 BREAK_TO_DEBUGGER(); 987 return NULL; 988 } 989 990 dcn20_ipp_construct(ipp, ctx, inst, 991 &ipp_regs[inst], &ipp_shift, &ipp_mask); 992 return &ipp->base; 993 } 994 995 996 struct output_pixel_processor *dcn20_opp_create( 997 struct dc_context *ctx, uint32_t inst) 998 { 999 struct dcn20_opp *opp = 1000 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1001 1002 if (!opp) { 1003 BREAK_TO_DEBUGGER(); 1004 return NULL; 1005 } 1006 1007 dcn20_opp_construct(opp, ctx, inst, 1008 &opp_regs[inst], &opp_shift, &opp_mask); 1009 return &opp->base; 1010 } 1011 1012 struct dce_aux *dcn20_aux_engine_create( 1013 struct dc_context *ctx, 1014 uint32_t inst) 1015 { 1016 struct aux_engine_dce110 *aux_engine = 1017 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 1018 1019 if (!aux_engine) 1020 return NULL; 1021 1022 dce110_aux_engine_construct(aux_engine, ctx, inst, 1023 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1024 &aux_engine_regs[inst], 1025 &aux_mask, 1026 &aux_shift, 1027 ctx->dc->caps.extended_aux_timeout_support); 1028 1029 return &aux_engine->base; 1030 } 1031 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 1032 1033 static const struct dce_i2c_registers i2c_hw_regs[] = { 1034 i2c_inst_regs(1), 1035 i2c_inst_regs(2), 1036 i2c_inst_regs(3), 1037 i2c_inst_regs(4), 1038 i2c_inst_regs(5), 1039 i2c_inst_regs(6), 1040 }; 1041 1042 static const struct dce_i2c_shift i2c_shifts = { 1043 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 1044 }; 1045 1046 static const struct dce_i2c_mask i2c_masks = { 1047 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 1048 }; 1049 1050 struct dce_i2c_hw *dcn20_i2c_hw_create( 1051 struct dc_context *ctx, 1052 uint32_t inst) 1053 { 1054 struct dce_i2c_hw *dce_i2c_hw = 1055 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1056 1057 if (!dce_i2c_hw) 1058 return NULL; 1059 1060 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1061 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1062 1063 return dce_i2c_hw; 1064 } 1065 struct mpc *dcn20_mpc_create(struct dc_context *ctx) 1066 { 1067 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), 1068 GFP_KERNEL); 1069 1070 if (!mpc20) 1071 return NULL; 1072 1073 dcn20_mpc_construct(mpc20, ctx, 1074 &mpc_regs, 1075 &mpc_shift, 1076 &mpc_mask, 1077 6); 1078 1079 return &mpc20->base; 1080 } 1081 1082 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx) 1083 { 1084 int i; 1085 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), 1086 GFP_KERNEL); 1087 1088 if (!hubbub) 1089 return NULL; 1090 1091 hubbub2_construct(hubbub, ctx, 1092 &hubbub_reg, 1093 &hubbub_shift, 1094 &hubbub_mask); 1095 1096 for (i = 0; i < res_cap_nv10.num_vmid; i++) { 1097 struct dcn20_vmid *vmid = &hubbub->vmid[i]; 1098 1099 vmid->ctx = ctx; 1100 1101 vmid->regs = &vmid_regs[i]; 1102 vmid->shifts = &vmid_shifts; 1103 vmid->masks = &vmid_masks; 1104 } 1105 1106 return &hubbub->base; 1107 } 1108 1109 struct timing_generator *dcn20_timing_generator_create( 1110 struct dc_context *ctx, 1111 uint32_t instance) 1112 { 1113 struct optc *tgn10 = 1114 kzalloc(sizeof(struct optc), GFP_KERNEL); 1115 1116 if (!tgn10) 1117 return NULL; 1118 1119 tgn10->base.inst = instance; 1120 tgn10->base.ctx = ctx; 1121 1122 tgn10->tg_regs = &tg_regs[instance]; 1123 tgn10->tg_shift = &tg_shift; 1124 tgn10->tg_mask = &tg_mask; 1125 1126 dcn20_timing_generator_init(tgn10); 1127 1128 return &tgn10->base; 1129 } 1130 1131 static const struct encoder_feature_support link_enc_feature = { 1132 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1133 .max_hdmi_pixel_clock = 600000, 1134 .hdmi_ycbcr420_supported = true, 1135 .dp_ycbcr420_supported = true, 1136 .flags.bits.IS_HBR2_CAPABLE = true, 1137 .flags.bits.IS_HBR3_CAPABLE = true, 1138 .flags.bits.IS_TPS3_CAPABLE = true, 1139 .flags.bits.IS_TPS4_CAPABLE = true 1140 }; 1141 1142 struct link_encoder *dcn20_link_encoder_create( 1143 const struct encoder_init_data *enc_init_data) 1144 { 1145 struct dcn20_link_encoder *enc20 = 1146 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1147 int link_regs_id; 1148 1149 if (!enc20) 1150 return NULL; 1151 1152 link_regs_id = 1153 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 1154 1155 dcn20_link_encoder_construct(enc20, 1156 enc_init_data, 1157 &link_enc_feature, 1158 &link_enc_regs[link_regs_id], 1159 &link_enc_aux_regs[enc_init_data->channel - 1], 1160 &link_enc_hpd_regs[enc_init_data->hpd_source], 1161 &le_shift, 1162 &le_mask); 1163 1164 return &enc20->enc10.base; 1165 } 1166 1167 struct clock_source *dcn20_clock_source_create( 1168 struct dc_context *ctx, 1169 struct dc_bios *bios, 1170 enum clock_source_id id, 1171 const struct dce110_clk_src_regs *regs, 1172 bool dp_clk_src) 1173 { 1174 struct dce110_clk_src *clk_src = 1175 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1176 1177 if (!clk_src) 1178 return NULL; 1179 1180 if (dcn20_clk_src_construct(clk_src, ctx, bios, id, 1181 regs, &cs_shift, &cs_mask)) { 1182 clk_src->base.dp_clk_src = dp_clk_src; 1183 return &clk_src->base; 1184 } 1185 1186 kfree(clk_src); 1187 BREAK_TO_DEBUGGER(); 1188 return NULL; 1189 } 1190 1191 static void read_dce_straps( 1192 struct dc_context *ctx, 1193 struct resource_straps *straps) 1194 { 1195 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1196 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1197 } 1198 1199 static struct audio *dcn20_create_audio( 1200 struct dc_context *ctx, unsigned int inst) 1201 { 1202 return dce_audio_create(ctx, inst, 1203 &audio_regs[inst], &audio_shift, &audio_mask); 1204 } 1205 1206 struct stream_encoder *dcn20_stream_encoder_create( 1207 enum engine_id eng_id, 1208 struct dc_context *ctx) 1209 { 1210 struct dcn10_stream_encoder *enc1 = 1211 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1212 1213 if (!enc1) 1214 return NULL; 1215 1216 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) { 1217 if (eng_id >= ENGINE_ID_DIGD) 1218 eng_id++; 1219 } 1220 1221 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1222 &stream_enc_regs[eng_id], 1223 &se_shift, &se_mask); 1224 1225 return &enc1->base; 1226 } 1227 1228 static const struct dce_hwseq_registers hwseq_reg = { 1229 HWSEQ_DCN2_REG_LIST() 1230 }; 1231 1232 static const struct dce_hwseq_shift hwseq_shift = { 1233 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT) 1234 }; 1235 1236 static const struct dce_hwseq_mask hwseq_mask = { 1237 HWSEQ_DCN2_MASK_SH_LIST(_MASK) 1238 }; 1239 1240 struct dce_hwseq *dcn20_hwseq_create( 1241 struct dc_context *ctx) 1242 { 1243 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1244 1245 if (hws) { 1246 hws->ctx = ctx; 1247 hws->regs = &hwseq_reg; 1248 hws->shifts = &hwseq_shift; 1249 hws->masks = &hwseq_mask; 1250 } 1251 return hws; 1252 } 1253 1254 static const struct resource_create_funcs res_create_funcs = { 1255 .read_dce_straps = read_dce_straps, 1256 .create_audio = dcn20_create_audio, 1257 .create_stream_encoder = dcn20_stream_encoder_create, 1258 .create_hwseq = dcn20_hwseq_create, 1259 }; 1260 1261 static const struct resource_create_funcs res_create_maximus_funcs = { 1262 .read_dce_straps = NULL, 1263 .create_audio = NULL, 1264 .create_stream_encoder = NULL, 1265 .create_hwseq = dcn20_hwseq_create, 1266 }; 1267 1268 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu); 1269 1270 void dcn20_clock_source_destroy(struct clock_source **clk_src) 1271 { 1272 kfree(TO_DCE110_CLK_SRC(*clk_src)); 1273 *clk_src = NULL; 1274 } 1275 1276 1277 struct display_stream_compressor *dcn20_dsc_create( 1278 struct dc_context *ctx, uint32_t inst) 1279 { 1280 struct dcn20_dsc *dsc = 1281 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1282 1283 if (!dsc) { 1284 BREAK_TO_DEBUGGER(); 1285 return NULL; 1286 } 1287 1288 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1289 return &dsc->base; 1290 } 1291 1292 void dcn20_dsc_destroy(struct display_stream_compressor **dsc) 1293 { 1294 kfree(container_of(*dsc, struct dcn20_dsc, base)); 1295 *dsc = NULL; 1296 } 1297 1298 1299 static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) 1300 { 1301 unsigned int i; 1302 1303 for (i = 0; i < pool->base.stream_enc_count; i++) { 1304 if (pool->base.stream_enc[i] != NULL) { 1305 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1306 pool->base.stream_enc[i] = NULL; 1307 } 1308 } 1309 1310 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1311 if (pool->base.dscs[i] != NULL) 1312 dcn20_dsc_destroy(&pool->base.dscs[i]); 1313 } 1314 1315 if (pool->base.mpc != NULL) { 1316 kfree(TO_DCN20_MPC(pool->base.mpc)); 1317 pool->base.mpc = NULL; 1318 } 1319 if (pool->base.hubbub != NULL) { 1320 kfree(pool->base.hubbub); 1321 pool->base.hubbub = NULL; 1322 } 1323 for (i = 0; i < pool->base.pipe_count; i++) { 1324 if (pool->base.dpps[i] != NULL) 1325 dcn20_dpp_destroy(&pool->base.dpps[i]); 1326 1327 if (pool->base.ipps[i] != NULL) 1328 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1329 1330 if (pool->base.hubps[i] != NULL) { 1331 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1332 pool->base.hubps[i] = NULL; 1333 } 1334 1335 if (pool->base.irqs != NULL) { 1336 dal_irq_service_destroy(&pool->base.irqs); 1337 } 1338 } 1339 1340 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1341 if (pool->base.engines[i] != NULL) 1342 dce110_engine_destroy(&pool->base.engines[i]); 1343 if (pool->base.hw_i2cs[i] != NULL) { 1344 kfree(pool->base.hw_i2cs[i]); 1345 pool->base.hw_i2cs[i] = NULL; 1346 } 1347 if (pool->base.sw_i2cs[i] != NULL) { 1348 kfree(pool->base.sw_i2cs[i]); 1349 pool->base.sw_i2cs[i] = NULL; 1350 } 1351 } 1352 1353 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1354 if (pool->base.opps[i] != NULL) 1355 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1356 } 1357 1358 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1359 if (pool->base.timing_generators[i] != NULL) { 1360 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1361 pool->base.timing_generators[i] = NULL; 1362 } 1363 } 1364 1365 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1366 if (pool->base.dwbc[i] != NULL) { 1367 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); 1368 pool->base.dwbc[i] = NULL; 1369 } 1370 if (pool->base.mcif_wb[i] != NULL) { 1371 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); 1372 pool->base.mcif_wb[i] = NULL; 1373 } 1374 } 1375 1376 for (i = 0; i < pool->base.audio_count; i++) { 1377 if (pool->base.audios[i]) 1378 dce_aud_destroy(&pool->base.audios[i]); 1379 } 1380 1381 for (i = 0; i < pool->base.clk_src_count; i++) { 1382 if (pool->base.clock_sources[i] != NULL) { 1383 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1384 pool->base.clock_sources[i] = NULL; 1385 } 1386 } 1387 1388 if (pool->base.dp_clock_source != NULL) { 1389 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1390 pool->base.dp_clock_source = NULL; 1391 } 1392 1393 1394 if (pool->base.abm != NULL) 1395 dce_abm_destroy(&pool->base.abm); 1396 1397 if (pool->base.dmcu != NULL) 1398 dce_dmcu_destroy(&pool->base.dmcu); 1399 1400 if (pool->base.dccg != NULL) 1401 dcn_dccg_destroy(&pool->base.dccg); 1402 1403 if (pool->base.pp_smu != NULL) 1404 dcn20_pp_smu_destroy(&pool->base.pp_smu); 1405 1406 if (pool->base.oem_device != NULL) 1407 dal_ddc_service_destroy(&pool->base.oem_device); 1408 } 1409 1410 struct hubp *dcn20_hubp_create( 1411 struct dc_context *ctx, 1412 uint32_t inst) 1413 { 1414 struct dcn20_hubp *hubp2 = 1415 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1416 1417 if (!hubp2) 1418 return NULL; 1419 1420 if (hubp2_construct(hubp2, ctx, inst, 1421 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1422 return &hubp2->base; 1423 1424 BREAK_TO_DEBUGGER(); 1425 kfree(hubp2); 1426 return NULL; 1427 } 1428 1429 static void get_pixel_clock_parameters( 1430 struct pipe_ctx *pipe_ctx, 1431 struct pixel_clk_params *pixel_clk_params) 1432 { 1433 const struct dc_stream_state *stream = pipe_ctx->stream; 1434 struct pipe_ctx *odm_pipe; 1435 int opp_cnt = 1; 1436 1437 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1438 opp_cnt++; 1439 1440 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 1441 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 1442 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 1443 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 1444 /* TODO: un-hardcode*/ 1445 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 1446 LINK_RATE_REF_FREQ_IN_KHZ; 1447 pixel_clk_params->flags.ENABLE_SS = 0; 1448 pixel_clk_params->color_depth = 1449 stream->timing.display_color_depth; 1450 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 1451 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 1452 1453 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1454 pixel_clk_params->color_depth = COLOR_DEPTH_888; 1455 1456 if (opp_cnt == 4) 1457 pixel_clk_params->requested_pix_clk_100hz /= 4; 1458 else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2) 1459 pixel_clk_params->requested_pix_clk_100hz /= 2; 1460 1461 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1462 pixel_clk_params->requested_pix_clk_100hz *= 2; 1463 1464 } 1465 1466 static void build_clamping_params(struct dc_stream_state *stream) 1467 { 1468 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1469 stream->clamping.c_depth = stream->timing.display_color_depth; 1470 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1471 } 1472 1473 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1474 { 1475 1476 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1477 1478 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1479 pipe_ctx->clock_source, 1480 &pipe_ctx->stream_res.pix_clk_params, 1481 &pipe_ctx->pll_settings); 1482 1483 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1484 1485 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1486 &pipe_ctx->stream->bit_depth_params); 1487 build_clamping_params(pipe_ctx->stream); 1488 1489 return DC_OK; 1490 } 1491 1492 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream) 1493 { 1494 enum dc_status status = DC_OK; 1495 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1496 1497 /*TODO Seems unneeded anymore */ 1498 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) { 1499 if (stream != NULL && old_context->streams[i] != NULL) { 1500 todo: shouldn't have to copy missing parameter here 1501 resource_build_bit_depth_reduction_params(stream, 1502 &stream->bit_depth_params); 1503 stream->clamping.pixel_encoding = 1504 stream->timing.pixel_encoding; 1505 1506 resource_build_bit_depth_reduction_params(stream, 1507 &stream->bit_depth_params); 1508 build_clamping_params(stream); 1509 1510 continue; 1511 } 1512 } 1513 */ 1514 1515 if (!pipe_ctx) 1516 return DC_ERROR_UNEXPECTED; 1517 1518 1519 status = build_pipe_hw_param(pipe_ctx); 1520 1521 return status; 1522 } 1523 1524 1525 static void acquire_dsc(struct resource_context *res_ctx, 1526 const struct resource_pool *pool, 1527 struct display_stream_compressor **dsc) 1528 { 1529 int i; 1530 1531 ASSERT(*dsc == NULL); 1532 *dsc = NULL; 1533 1534 /* Find first free DSC */ 1535 for (i = 0; i < pool->res_cap->num_dsc; i++) 1536 if (!res_ctx->is_dsc_acquired[i]) { 1537 *dsc = pool->dscs[i]; 1538 res_ctx->is_dsc_acquired[i] = true; 1539 break; 1540 } 1541 } 1542 1543 static void release_dsc(struct resource_context *res_ctx, 1544 const struct resource_pool *pool, 1545 struct display_stream_compressor **dsc) 1546 { 1547 int i; 1548 1549 for (i = 0; i < pool->res_cap->num_dsc; i++) 1550 if (pool->dscs[i] == *dsc) { 1551 res_ctx->is_dsc_acquired[i] = false; 1552 *dsc = NULL; 1553 break; 1554 } 1555 } 1556 1557 1558 1559 static enum dc_status add_dsc_to_stream_resource(struct dc *dc, 1560 struct dc_state *dc_ctx, 1561 struct dc_stream_state *dc_stream) 1562 { 1563 enum dc_status result = DC_OK; 1564 int i; 1565 const struct resource_pool *pool = dc->res_pool; 1566 1567 /* Get a DSC if required and available */ 1568 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1569 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i]; 1570 1571 if (pipe_ctx->stream != dc_stream) 1572 continue; 1573 1574 acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc); 1575 1576 /* The number of DSCs can be less than the number of pipes */ 1577 if (!pipe_ctx->stream_res.dsc) { 1578 dm_output_to_console("No DSCs available\n"); 1579 result = DC_NO_DSC_RESOURCE; 1580 } 1581 1582 break; 1583 } 1584 1585 return result; 1586 } 1587 1588 1589 static enum dc_status remove_dsc_from_stream_resource(struct dc *dc, 1590 struct dc_state *new_ctx, 1591 struct dc_stream_state *dc_stream) 1592 { 1593 struct pipe_ctx *pipe_ctx = NULL; 1594 int i; 1595 1596 for (i = 0; i < MAX_PIPES; i++) { 1597 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { 1598 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; 1599 1600 if (pipe_ctx->stream_res.dsc) 1601 release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); 1602 } 1603 } 1604 1605 if (!pipe_ctx) 1606 return DC_ERROR_UNEXPECTED; 1607 else 1608 return DC_OK; 1609 } 1610 1611 1612 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) 1613 { 1614 enum dc_status result = DC_ERROR_UNEXPECTED; 1615 1616 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1617 1618 if (result == DC_OK) 1619 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1620 1621 /* Get a DSC if required and available */ 1622 if (result == DC_OK && dc_stream->timing.flags.DSC) 1623 result = add_dsc_to_stream_resource(dc, new_ctx, dc_stream); 1624 1625 if (result == DC_OK) 1626 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream); 1627 1628 return result; 1629 } 1630 1631 1632 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) 1633 { 1634 enum dc_status result = DC_OK; 1635 1636 result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream); 1637 1638 return result; 1639 } 1640 1641 1642 static void swizzle_to_dml_params( 1643 enum swizzle_mode_values swizzle, 1644 unsigned int *sw_mode) 1645 { 1646 switch (swizzle) { 1647 case DC_SW_LINEAR: 1648 *sw_mode = dm_sw_linear; 1649 break; 1650 case DC_SW_4KB_S: 1651 *sw_mode = dm_sw_4kb_s; 1652 break; 1653 case DC_SW_4KB_S_X: 1654 *sw_mode = dm_sw_4kb_s_x; 1655 break; 1656 case DC_SW_4KB_D: 1657 *sw_mode = dm_sw_4kb_d; 1658 break; 1659 case DC_SW_4KB_D_X: 1660 *sw_mode = dm_sw_4kb_d_x; 1661 break; 1662 case DC_SW_64KB_S: 1663 *sw_mode = dm_sw_64kb_s; 1664 break; 1665 case DC_SW_64KB_S_X: 1666 *sw_mode = dm_sw_64kb_s_x; 1667 break; 1668 case DC_SW_64KB_S_T: 1669 *sw_mode = dm_sw_64kb_s_t; 1670 break; 1671 case DC_SW_64KB_D: 1672 *sw_mode = dm_sw_64kb_d; 1673 break; 1674 case DC_SW_64KB_D_X: 1675 *sw_mode = dm_sw_64kb_d_x; 1676 break; 1677 case DC_SW_64KB_D_T: 1678 *sw_mode = dm_sw_64kb_d_t; 1679 break; 1680 case DC_SW_64KB_R_X: 1681 *sw_mode = dm_sw_64kb_r_x; 1682 break; 1683 case DC_SW_VAR_S: 1684 *sw_mode = dm_sw_var_s; 1685 break; 1686 case DC_SW_VAR_S_X: 1687 *sw_mode = dm_sw_var_s_x; 1688 break; 1689 case DC_SW_VAR_D: 1690 *sw_mode = dm_sw_var_d; 1691 break; 1692 case DC_SW_VAR_D_X: 1693 *sw_mode = dm_sw_var_d_x; 1694 break; 1695 1696 default: 1697 ASSERT(0); /* Not supported */ 1698 break; 1699 } 1700 } 1701 1702 bool dcn20_split_stream_for_odm( 1703 struct resource_context *res_ctx, 1704 const struct resource_pool *pool, 1705 struct pipe_ctx *prev_odm_pipe, 1706 struct pipe_ctx *next_odm_pipe) 1707 { 1708 int pipe_idx = next_odm_pipe->pipe_idx; 1709 1710 *next_odm_pipe = *prev_odm_pipe; 1711 1712 next_odm_pipe->pipe_idx = pipe_idx; 1713 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; 1714 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; 1715 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; 1716 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; 1717 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; 1718 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; 1719 next_odm_pipe->stream_res.dsc = NULL; 1720 if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) { 1721 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe; 1722 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe; 1723 } 1724 prev_odm_pipe->next_odm_pipe = next_odm_pipe; 1725 next_odm_pipe->prev_odm_pipe = prev_odm_pipe; 1726 ASSERT(next_odm_pipe->top_pipe == NULL); 1727 1728 if (prev_odm_pipe->plane_state) { 1729 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; 1730 int new_width; 1731 1732 /* HACTIVE halved for odm combine */ 1733 sd->h_active /= 2; 1734 /* Calculate new vp and recout for left pipe */ 1735 /* Need at least 16 pixels width per side */ 1736 if (sd->recout.x + 16 >= sd->h_active) 1737 return false; 1738 new_width = sd->h_active - sd->recout.x; 1739 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1740 sd->ratios.horz, sd->recout.width - new_width)); 1741 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1742 sd->ratios.horz_c, sd->recout.width - new_width)); 1743 sd->recout.width = new_width; 1744 1745 /* Calculate new vp and recout for right pipe */ 1746 sd = &next_odm_pipe->plane_res.scl_data; 1747 /* HACTIVE halved for odm combine */ 1748 sd->h_active /= 2; 1749 /* Need at least 16 pixels width per side */ 1750 if (new_width <= 16) 1751 return false; 1752 new_width = sd->recout.width + sd->recout.x - sd->h_active; 1753 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1754 sd->ratios.horz, sd->recout.width - new_width)); 1755 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1756 sd->ratios.horz_c, sd->recout.width - new_width)); 1757 sd->recout.width = new_width; 1758 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int( 1759 sd->ratios.horz, sd->h_active - sd->recout.x)); 1760 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int( 1761 sd->ratios.horz_c, sd->h_active - sd->recout.x)); 1762 sd->recout.x = 0; 1763 } 1764 next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; 1765 if (next_odm_pipe->stream->timing.flags.DSC == 1) { 1766 acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc); 1767 ASSERT(next_odm_pipe->stream_res.dsc); 1768 if (next_odm_pipe->stream_res.dsc == NULL) 1769 return false; 1770 } 1771 1772 return true; 1773 } 1774 1775 void dcn20_split_stream_for_mpc( 1776 struct resource_context *res_ctx, 1777 const struct resource_pool *pool, 1778 struct pipe_ctx *primary_pipe, 1779 struct pipe_ctx *secondary_pipe) 1780 { 1781 int pipe_idx = secondary_pipe->pipe_idx; 1782 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe; 1783 1784 *secondary_pipe = *primary_pipe; 1785 secondary_pipe->bottom_pipe = sec_bot_pipe; 1786 1787 secondary_pipe->pipe_idx = pipe_idx; 1788 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; 1789 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; 1790 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; 1791 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; 1792 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; 1793 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; 1794 secondary_pipe->stream_res.dsc = NULL; 1795 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { 1796 ASSERT(!secondary_pipe->bottom_pipe); 1797 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; 1798 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe; 1799 } 1800 primary_pipe->bottom_pipe = secondary_pipe; 1801 secondary_pipe->top_pipe = primary_pipe; 1802 1803 ASSERT(primary_pipe->plane_state); 1804 resource_build_scaling_params(primary_pipe); 1805 resource_build_scaling_params(secondary_pipe); 1806 } 1807 1808 void dcn20_populate_dml_writeback_from_context( 1809 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) 1810 { 1811 int pipe_cnt, i; 1812 1813 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1814 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; 1815 1816 if (!res_ctx->pipe_ctx[i].stream) 1817 continue; 1818 1819 /* Set writeback information */ 1820 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; 1821 pipes[pipe_cnt].dout.num_active_wb++; 1822 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; 1823 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; 1824 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; 1825 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; 1826 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1; 1827 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1; 1828 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c; 1829 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c; 1830 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0; 1831 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0; 1832 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) { 1833 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) 1834 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8; 1835 else 1836 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10; 1837 } else 1838 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32; 1839 1840 pipe_cnt++; 1841 } 1842 1843 } 1844 1845 int dcn20_populate_dml_pipes_from_context( 1846 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes) 1847 { 1848 int pipe_cnt, i; 1849 bool synchronized_vblank = true; 1850 struct resource_context *res_ctx = &context->res_ctx; 1851 1852 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) { 1853 if (!res_ctx->pipe_ctx[i].stream) 1854 continue; 1855 1856 if (pipe_cnt < 0) { 1857 pipe_cnt = i; 1858 continue; 1859 } 1860 if (dc->debug.disable_timing_sync || !resource_are_streams_timing_synchronizable( 1861 res_ctx->pipe_ctx[pipe_cnt].stream, 1862 res_ctx->pipe_ctx[i].stream)) { 1863 synchronized_vblank = false; 1864 break; 1865 } 1866 } 1867 1868 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1869 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing; 1870 unsigned int v_total; 1871 int output_bpc; 1872 1873 if (!res_ctx->pipe_ctx[i].stream) 1874 continue; 1875 1876 v_total = timing->v_total; 1877 /* todo: 1878 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0; 1879 pipes[pipe_cnt].pipe.src.dcc = 0; 1880 pipes[pipe_cnt].pipe.src.vm = 0;*/ 1881 1882 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC; 1883 /* todo: rotation?*/ 1884 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; 1885 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) { 1886 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true; 1887 /* 1/2 vblank */ 1888 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active = 1889 (v_total - timing->v_addressable 1890 - timing->v_border_top - timing->v_border_bottom) / 2; 1891 /* 36 bytes dp, 32 hdmi */ 1892 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes = 1893 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32; 1894 } 1895 pipes[pipe_cnt].pipe.src.dcc = false; 1896 pipes[pipe_cnt].pipe.src.dcc_rate = 1; 1897 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank; 1898 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch; 1899 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start 1900 - timing->h_addressable 1901 - timing->h_border_left 1902 - timing->h_border_right; 1903 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - timing->v_front_porch; 1904 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start 1905 - timing->v_addressable 1906 - timing->v_border_top 1907 - timing->v_border_bottom; 1908 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total; 1909 pipes[pipe_cnt].pipe.dest.vtotal = v_total; 1910 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable; 1911 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable; 1912 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE; 1913 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0; 1914 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1915 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2; 1916 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst; 1917 pipes[pipe_cnt].dout.dp_lanes = 4; 1918 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min; 1919 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max; 1920 pipes[pipe_cnt].pipe.dest.odm_combine = res_ctx->pipe_ctx[i].prev_odm_pipe 1921 || res_ctx->pipe_ctx[i].next_odm_pipe; 1922 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; 1923 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state 1924 == res_ctx->pipe_ctx[i].plane_state) 1925 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx; 1926 else if (res_ctx->pipe_ctx[i].prev_odm_pipe) { 1927 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe; 1928 1929 while (first_pipe->prev_odm_pipe) 1930 first_pipe = first_pipe->prev_odm_pipe; 1931 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx; 1932 } 1933 1934 switch (res_ctx->pipe_ctx[i].stream->signal) { 1935 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1936 case SIGNAL_TYPE_DISPLAY_PORT: 1937 pipes[pipe_cnt].dout.output_type = dm_dp; 1938 break; 1939 case SIGNAL_TYPE_EDP: 1940 pipes[pipe_cnt].dout.output_type = dm_edp; 1941 break; 1942 case SIGNAL_TYPE_HDMI_TYPE_A: 1943 case SIGNAL_TYPE_DVI_SINGLE_LINK: 1944 case SIGNAL_TYPE_DVI_DUAL_LINK: 1945 pipes[pipe_cnt].dout.output_type = dm_hdmi; 1946 break; 1947 default: 1948 /* In case there is no signal, set dp with 4 lanes to allow max config */ 1949 pipes[pipe_cnt].dout.output_type = dm_dp; 1950 pipes[pipe_cnt].dout.dp_lanes = 4; 1951 } 1952 1953 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) { 1954 case COLOR_DEPTH_666: 1955 output_bpc = 6; 1956 break; 1957 case COLOR_DEPTH_888: 1958 output_bpc = 8; 1959 break; 1960 case COLOR_DEPTH_101010: 1961 output_bpc = 10; 1962 break; 1963 case COLOR_DEPTH_121212: 1964 output_bpc = 12; 1965 break; 1966 case COLOR_DEPTH_141414: 1967 output_bpc = 14; 1968 break; 1969 case COLOR_DEPTH_161616: 1970 output_bpc = 16; 1971 break; 1972 case COLOR_DEPTH_999: 1973 output_bpc = 9; 1974 break; 1975 case COLOR_DEPTH_111111: 1976 output_bpc = 11; 1977 break; 1978 default: 1979 output_bpc = 8; 1980 break; 1981 } 1982 1983 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) { 1984 case PIXEL_ENCODING_RGB: 1985 case PIXEL_ENCODING_YCBCR444: 1986 pipes[pipe_cnt].dout.output_format = dm_444; 1987 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3; 1988 break; 1989 case PIXEL_ENCODING_YCBCR420: 1990 pipes[pipe_cnt].dout.output_format = dm_420; 1991 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2; 1992 break; 1993 case PIXEL_ENCODING_YCBCR422: 1994 if (true) /* todo */ 1995 pipes[pipe_cnt].dout.output_format = dm_s422; 1996 else 1997 pipes[pipe_cnt].dout.output_format = dm_n422; 1998 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2; 1999 break; 2000 default: 2001 pipes[pipe_cnt].dout.output_format = dm_444; 2002 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3; 2003 } 2004 2005 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC) 2006 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0; 2007 2008 /* todo: default max for now, until there is logic reflecting this in dc*/ 2009 pipes[pipe_cnt].dout.output_bpc = 12; 2010 /* 2011 * Use max cursor settings for calculations to minimize 2012 * bw calculations due to cursor on/off 2013 */ 2014 pipes[pipe_cnt].pipe.src.num_cursors = 2; 2015 pipes[pipe_cnt].pipe.src.cur0_src_width = 256; 2016 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit; 2017 pipes[pipe_cnt].pipe.src.cur1_src_width = 256; 2018 pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit; 2019 2020 if (!res_ctx->pipe_ctx[i].plane_state) { 2021 pipes[pipe_cnt].pipe.src.source_scan = dm_horz; 2022 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear; 2023 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile; 2024 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable; 2025 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920) 2026 pipes[pipe_cnt].pipe.src.viewport_width = 1920; 2027 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable; 2028 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080) 2029 pipes[pipe_cnt].pipe.src.viewport_height = 1080; 2030 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */ 2031 pipes[pipe_cnt].pipe.src.source_format = dm_444_32; 2032 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/ 2033 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/ 2034 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/ 2035 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/ 2036 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16; 2037 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0; 2038 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0; 2039 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/ 2040 pipes[pipe_cnt].pipe.scale_taps.htaps = 1; 2041 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1; 2042 pipes[pipe_cnt].pipe.src.is_hsplit = 0; 2043 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 2044 pipes[pipe_cnt].pipe.dest.vtotal_min = v_total; 2045 pipes[pipe_cnt].pipe.dest.vtotal_max = v_total; 2046 } else { 2047 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state; 2048 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data; 2049 2050 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate; 2051 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe 2052 && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) 2053 || (res_ctx->pipe_ctx[i].top_pipe 2054 && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln); 2055 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90 2056 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz; 2057 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y; 2058 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y; 2059 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width; 2060 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width; 2061 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height; 2062 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height; 2063 if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 2064 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch; 2065 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch; 2066 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; 2067 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c; 2068 } else { 2069 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch; 2070 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; 2071 } 2072 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable; 2073 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width; 2074 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height; 2075 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width; 2076 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height; 2077 if (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) { 2078 pipes[pipe_cnt].pipe.dest.full_recout_width += 2079 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.width; 2080 pipes[pipe_cnt].pipe.dest.full_recout_height += 2081 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.height; 2082 } else if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) { 2083 pipes[pipe_cnt].pipe.dest.full_recout_width += 2084 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.width; 2085 pipes[pipe_cnt].pipe.dest.full_recout_height += 2086 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height; 2087 } 2088 2089 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16; 2090 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32); 2091 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32); 2092 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32); 2093 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32); 2094 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 2095 scl->ratios.vert.value != dc_fixpt_one.value 2096 || scl->ratios.horz.value != dc_fixpt_one.value 2097 || scl->ratios.vert_c.value != dc_fixpt_one.value 2098 || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/ 2099 || dc->debug.always_scale; /*support always scale*/ 2100 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps; 2101 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c; 2102 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps; 2103 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c; 2104 2105 pipes[pipe_cnt].pipe.src.macro_tile_size = 2106 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); 2107 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, 2108 &pipes[pipe_cnt].pipe.src.sw_mode); 2109 2110 switch (pln->format) { 2111 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 2112 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 2113 pipes[pipe_cnt].pipe.src.source_format = dm_420_8; 2114 break; 2115 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 2116 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 2117 pipes[pipe_cnt].pipe.src.source_format = dm_420_10; 2118 break; 2119 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 2120 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 2121 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2122 pipes[pipe_cnt].pipe.src.source_format = dm_444_64; 2123 break; 2124 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 2125 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 2126 pipes[pipe_cnt].pipe.src.source_format = dm_444_16; 2127 break; 2128 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 2129 pipes[pipe_cnt].pipe.src.source_format = dm_444_8; 2130 break; 2131 default: 2132 pipes[pipe_cnt].pipe.src.source_format = dm_444_32; 2133 break; 2134 } 2135 } 2136 2137 pipe_cnt++; 2138 } 2139 2140 /* populate writeback information */ 2141 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes); 2142 2143 return pipe_cnt; 2144 } 2145 2146 unsigned int dcn20_calc_max_scaled_time( 2147 unsigned int time_per_pixel, 2148 enum mmhubbub_wbif_mode mode, 2149 unsigned int urgent_watermark) 2150 { 2151 unsigned int time_per_byte = 0; 2152 unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */ 2153 unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */ 2154 unsigned int small_free_entry, max_free_entry; 2155 unsigned int buf_lh_capability; 2156 unsigned int max_scaled_time; 2157 2158 if (mode == PACKED_444) /* packed mode */ 2159 time_per_byte = time_per_pixel/4; 2160 else if (mode == PLANAR_420_8BPC) 2161 time_per_byte = time_per_pixel; 2162 else if (mode == PLANAR_420_10BPC) /* p010 */ 2163 time_per_byte = time_per_pixel * 819/1024; 2164 2165 if (time_per_byte == 0) 2166 time_per_byte = 1; 2167 2168 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry; 2169 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry; 2170 buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */ 2171 max_scaled_time = buf_lh_capability - urgent_watermark; 2172 return max_scaled_time; 2173 } 2174 2175 void dcn20_set_mcif_arb_params( 2176 struct dc *dc, 2177 struct dc_state *context, 2178 display_e2e_pipe_params_st *pipes, 2179 int pipe_cnt) 2180 { 2181 enum mmhubbub_wbif_mode wbif_mode; 2182 struct mcif_arb_params *wb_arb_params; 2183 int i, j, k, dwb_pipe; 2184 2185 /* Writeback MCIF_WB arbitration parameters */ 2186 dwb_pipe = 0; 2187 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2188 2189 if (!context->res_ctx.pipe_ctx[i].stream) 2190 continue; 2191 2192 for (j = 0; j < MAX_DWB_PIPES; j++) { 2193 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false) 2194 continue; 2195 2196 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params; 2197 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe]; 2198 2199 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) { 2200 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) 2201 wbif_mode = PLANAR_420_8BPC; 2202 else 2203 wbif_mode = PLANAR_420_10BPC; 2204 } else 2205 wbif_mode = PACKED_444; 2206 2207 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) { 2208 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2209 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2210 } 2211 wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */ 2212 wb_arb_params->slice_lines = 32; 2213 wb_arb_params->arbitration_slice = 2; 2214 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel, 2215 wbif_mode, 2216 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */ 2217 2218 dwb_pipe++; 2219 2220 if (dwb_pipe >= MAX_DWB_PIPES) 2221 return; 2222 } 2223 if (dwb_pipe >= MAX_DWB_PIPES) 2224 return; 2225 } 2226 } 2227 2228 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) 2229 { 2230 int i; 2231 2232 /* Validate DSC config, dsc count validation is already done */ 2233 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2234 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; 2235 struct dc_stream_state *stream = pipe_ctx->stream; 2236 struct dsc_config dsc_cfg; 2237 struct pipe_ctx *odm_pipe; 2238 int opp_cnt = 1; 2239 2240 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 2241 opp_cnt++; 2242 2243 /* Only need to validate top pipe */ 2244 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC) 2245 continue; 2246 2247 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left 2248 + stream->timing.h_border_right) / opp_cnt; 2249 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top 2250 + stream->timing.v_border_bottom; 2251 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 2252 dsc_cfg.color_depth = stream->timing.display_color_depth; 2253 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 2254 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 2255 2256 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg)) 2257 return false; 2258 } 2259 return true; 2260 } 2261 2262 struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, 2263 struct resource_context *res_ctx, 2264 const struct resource_pool *pool, 2265 const struct pipe_ctx *primary_pipe) 2266 { 2267 struct pipe_ctx *secondary_pipe = NULL; 2268 2269 if (dc && primary_pipe) { 2270 int j; 2271 int preferred_pipe_idx = 0; 2272 2273 /* first check the prev dc state: 2274 * if this primary pipe has a bottom pipe in prev. state 2275 * and if the bottom pipe is still available (which it should be), 2276 * pick that pipe as secondary 2277 * Same logic applies for ODM pipes. Since mpo is not allowed with odm 2278 * check in else case. 2279 */ 2280 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) { 2281 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx; 2282 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2283 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2284 secondary_pipe->pipe_idx = preferred_pipe_idx; 2285 } 2286 } else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) { 2287 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx; 2288 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2289 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2290 secondary_pipe->pipe_idx = preferred_pipe_idx; 2291 } 2292 } 2293 2294 /* 2295 * if this primary pipe does not have a bottom pipe in prev. state 2296 * start backward and find a pipe that did not used to be a bottom pipe in 2297 * prev. dc state. This way we make sure we keep the same assignment as 2298 * last state and will not have to reprogram every pipe 2299 */ 2300 if (secondary_pipe == NULL) { 2301 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { 2302 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL 2303 && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) { 2304 preferred_pipe_idx = j; 2305 2306 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2307 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2308 secondary_pipe->pipe_idx = preferred_pipe_idx; 2309 break; 2310 } 2311 } 2312 } 2313 } 2314 /* 2315 * We should never hit this assert unless assignments are shuffled around 2316 * if this happens we will prob. hit a vsync tdr 2317 */ 2318 ASSERT(secondary_pipe); 2319 /* 2320 * search backwards for the second pipe to keep pipe 2321 * assignment more consistent 2322 */ 2323 if (secondary_pipe == NULL) { 2324 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { 2325 preferred_pipe_idx = j; 2326 2327 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2328 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2329 secondary_pipe->pipe_idx = preferred_pipe_idx; 2330 break; 2331 } 2332 } 2333 } 2334 } 2335 2336 return secondary_pipe; 2337 } 2338 2339 void dcn20_merge_pipes_for_validate( 2340 struct dc *dc, 2341 struct dc_state *context) 2342 { 2343 int i; 2344 2345 /* merge previously split odm pipes since mode support needs to make the decision */ 2346 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2347 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2348 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe; 2349 2350 if (pipe->prev_odm_pipe) 2351 continue; 2352 2353 pipe->next_odm_pipe = NULL; 2354 while (odm_pipe) { 2355 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe; 2356 2357 odm_pipe->plane_state = NULL; 2358 odm_pipe->stream = NULL; 2359 odm_pipe->top_pipe = NULL; 2360 odm_pipe->bottom_pipe = NULL; 2361 odm_pipe->prev_odm_pipe = NULL; 2362 odm_pipe->next_odm_pipe = NULL; 2363 if (odm_pipe->stream_res.dsc) 2364 release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); 2365 /* Clear plane_res and stream_res */ 2366 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res)); 2367 memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res)); 2368 odm_pipe = next_odm_pipe; 2369 } 2370 if (pipe->plane_state) 2371 resource_build_scaling_params(pipe); 2372 } 2373 2374 /* merge previously mpc split pipes since mode support needs to make the decision */ 2375 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2376 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2377 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 2378 2379 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) 2380 continue; 2381 2382 pipe->bottom_pipe = hsplit_pipe->bottom_pipe; 2383 if (hsplit_pipe->bottom_pipe) 2384 hsplit_pipe->bottom_pipe->top_pipe = pipe; 2385 hsplit_pipe->plane_state = NULL; 2386 hsplit_pipe->stream = NULL; 2387 hsplit_pipe->top_pipe = NULL; 2388 hsplit_pipe->bottom_pipe = NULL; 2389 2390 /* Clear plane_res and stream_res */ 2391 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res)); 2392 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res)); 2393 if (pipe->plane_state) 2394 resource_build_scaling_params(pipe); 2395 } 2396 } 2397 2398 int dcn20_validate_apply_pipe_split_flags( 2399 struct dc *dc, 2400 struct dc_state *context, 2401 int vlevel, 2402 bool *split) 2403 { 2404 int i, pipe_idx, vlevel_split; 2405 bool force_split = false; 2406 bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC; 2407 2408 /* Single display loop, exits if there is more than one display */ 2409 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2410 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2411 bool exit_loop = false; 2412 2413 if (!pipe->stream || pipe->top_pipe) 2414 continue; 2415 2416 if (dc->debug.force_single_disp_pipe_split) { 2417 if (!force_split) 2418 force_split = true; 2419 else { 2420 force_split = false; 2421 exit_loop = true; 2422 } 2423 } 2424 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) { 2425 if (avoid_split) 2426 avoid_split = false; 2427 else { 2428 avoid_split = true; 2429 exit_loop = true; 2430 } 2431 } 2432 if (exit_loop) 2433 break; 2434 } 2435 /* TODO: fix dc bugs and remove this split threshold thing */ 2436 if (context->stream_count > dc->res_pool->pipe_count / 2) 2437 avoid_split = true; 2438 2439 /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */ 2440 if (avoid_split) { 2441 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2442 if (!context->res_ctx.pipe_ctx[i].stream) 2443 continue; 2444 2445 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) 2446 if (context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1) 2447 break; 2448 /* Impossible to not split this pipe */ 2449 if (vlevel > context->bw_ctx.dml.soc.num_states) 2450 vlevel = vlevel_split; 2451 pipe_idx++; 2452 } 2453 context->bw_ctx.dml.vba.maxMpcComb = 0; 2454 } 2455 2456 /* Split loop sets which pipe should be split based on dml outputs and dc flags */ 2457 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2458 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2459 2460 if (!context->res_ctx.pipe_ctx[i].stream) 2461 continue; 2462 2463 if (force_split || context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] > 1) 2464 split[i] = true; 2465 if ((pipe->stream->view_format == 2466 VIEW_3D_FORMAT_SIDE_BY_SIDE || 2467 pipe->stream->view_format == 2468 VIEW_3D_FORMAT_TOP_AND_BOTTOM) && 2469 (pipe->stream->timing.timing_3d_format == 2470 TIMING_3D_FORMAT_TOP_AND_BOTTOM || 2471 pipe->stream->timing.timing_3d_format == 2472 TIMING_3D_FORMAT_SIDE_BY_SIDE)) 2473 split[i] = true; 2474 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) { 2475 split[i] = true; 2476 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true; 2477 } 2478 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] = 2479 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx]; 2480 /* Adjust dppclk when split is forced, do not bother with dispclk */ 2481 if (split[i] && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1) 2482 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2; 2483 pipe_idx++; 2484 } 2485 2486 return vlevel; 2487 } 2488 2489 bool dcn20_fast_validate_bw( 2490 struct dc *dc, 2491 struct dc_state *context, 2492 display_e2e_pipe_params_st *pipes, 2493 int *pipe_cnt_out, 2494 int *pipe_split_from, 2495 int *vlevel_out) 2496 { 2497 bool out = false; 2498 bool split[MAX_PIPES] = { false }; 2499 int pipe_cnt, i, pipe_idx, vlevel; 2500 2501 ASSERT(pipes); 2502 if (!pipes) 2503 return false; 2504 2505 dcn20_merge_pipes_for_validate(dc, context); 2506 2507 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes); 2508 2509 *pipe_cnt_out = pipe_cnt; 2510 2511 if (!pipe_cnt) { 2512 out = true; 2513 goto validate_out; 2514 } 2515 2516 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 2517 2518 if (vlevel > context->bw_ctx.dml.soc.num_states) 2519 goto validate_fail; 2520 2521 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split); 2522 2523 /*initialize pipe_just_split_from to invalid idx*/ 2524 for (i = 0; i < MAX_PIPES; i++) 2525 pipe_split_from[i] = -1; 2526 2527 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { 2528 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2529 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 2530 2531 if (!pipe->stream || pipe_split_from[i] >= 0) 2532 continue; 2533 2534 pipe_idx++; 2535 2536 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 2537 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 2538 ASSERT(hsplit_pipe); 2539 if (!dcn20_split_stream_for_odm( 2540 &context->res_ctx, dc->res_pool, 2541 pipe, hsplit_pipe)) 2542 goto validate_fail; 2543 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 2544 dcn20_build_mapped_resource(dc, context, pipe->stream); 2545 } 2546 2547 if (!pipe->plane_state) 2548 continue; 2549 /* Skip 2nd half of already split pipe */ 2550 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state) 2551 continue; 2552 2553 /* We do not support mpo + odm at the moment */ 2554 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state 2555 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) 2556 goto validate_fail; 2557 2558 if (split[i]) { 2559 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) { 2560 /* pipe not split previously needs split */ 2561 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 2562 ASSERT(hsplit_pipe); 2563 if (!hsplit_pipe) { 2564 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2; 2565 continue; 2566 } 2567 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 2568 if (!dcn20_split_stream_for_odm( 2569 &context->res_ctx, dc->res_pool, 2570 pipe, hsplit_pipe)) 2571 goto validate_fail; 2572 dcn20_build_mapped_resource(dc, context, pipe->stream); 2573 } else 2574 dcn20_split_stream_for_mpc( 2575 &context->res_ctx, dc->res_pool, 2576 pipe, hsplit_pipe); 2577 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 2578 } 2579 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { 2580 /* merge should already have been done */ 2581 ASSERT(0); 2582 } 2583 } 2584 /* Actual dsc count per stream dsc validation*/ 2585 if (!dcn20_validate_dsc(dc, context)) { 2586 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = 2587 DML_FAIL_DSC_VALIDATION_FAILURE; 2588 goto validate_fail; 2589 } 2590 2591 *vlevel_out = vlevel; 2592 2593 out = true; 2594 goto validate_out; 2595 2596 validate_fail: 2597 out = false; 2598 2599 validate_out: 2600 return out; 2601 } 2602 2603 static void dcn20_calculate_wm( 2604 struct dc *dc, struct dc_state *context, 2605 display_e2e_pipe_params_st *pipes, 2606 int *out_pipe_cnt, 2607 int *pipe_split_from, 2608 int vlevel) 2609 { 2610 int pipe_cnt, i, pipe_idx; 2611 2612 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 2613 if (!context->res_ctx.pipe_ctx[i].stream) 2614 continue; 2615 2616 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 2617 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 2618 2619 if (pipe_split_from[i] < 0) { 2620 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 2621 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; 2622 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) 2623 pipes[pipe_cnt].pipe.dest.odm_combine = 2624 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]; 2625 else 2626 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 2627 pipe_idx++; 2628 } else { 2629 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 2630 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; 2631 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) 2632 pipes[pipe_cnt].pipe.dest.odm_combine = 2633 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]]; 2634 else 2635 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 2636 } 2637 2638 if (dc->config.forced_clocks) { 2639 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 2640 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 2641 } 2642 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000) 2643 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 2644 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000) 2645 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 2646 2647 pipe_cnt++; 2648 } 2649 2650 if (pipe_cnt != pipe_idx) { 2651 if (dc->res_pool->funcs->populate_dml_pipes) 2652 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, 2653 context, pipes); 2654 else 2655 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, 2656 context, pipes); 2657 } 2658 2659 *out_pipe_cnt = pipe_cnt; 2660 2661 pipes[0].clks_cfg.voltage = vlevel; 2662 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; 2663 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 2664 2665 /* only pipe 0 is read for voltage and dcf/soc clocks */ 2666 if (vlevel < 1) { 2667 pipes[0].clks_cfg.voltage = 1; 2668 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz; 2669 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz; 2670 } 2671 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2672 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2673 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2674 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2675 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2676 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2677 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2678 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2679 2680 if (vlevel < 2) { 2681 pipes[0].clks_cfg.voltage = 2; 2682 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; 2683 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; 2684 } 2685 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2686 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2687 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2688 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2689 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2690 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2691 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2692 2693 if (vlevel < 3) { 2694 pipes[0].clks_cfg.voltage = 3; 2695 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; 2696 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; 2697 } 2698 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2699 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2700 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2701 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2702 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2703 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2704 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2705 2706 pipes[0].clks_cfg.voltage = vlevel; 2707 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; 2708 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 2709 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2710 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2711 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2712 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2713 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2714 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2715 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2716 } 2717 2718 void dcn20_calculate_dlg_params( 2719 struct dc *dc, struct dc_state *context, 2720 display_e2e_pipe_params_st *pipes, 2721 int pipe_cnt, 2722 int vlevel) 2723 { 2724 int i, j, pipe_idx, pipe_idx_unsplit; 2725 bool visited[MAX_PIPES] = { 0 }; 2726 2727 /* Writeback MCIF_WB arbitration parameters */ 2728 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); 2729 2730 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; 2731 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; 2732 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; 2733 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; 2734 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; 2735 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; 2736 context->bw_ctx.bw.dcn.clk.p_state_change_support = 2737 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] 2738 != dm_dram_clock_change_unsupported; 2739 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 2740 2741 /* 2742 * An artifact of dml pipe split/odm is that pipes get merged back together for 2743 * calculation. Therefore we need to only extract for first pipe in ascending index order 2744 * and copy into the other split half. 2745 */ 2746 for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) { 2747 if (!context->res_ctx.pipe_ctx[i].stream) 2748 continue; 2749 2750 if (!visited[pipe_idx]) { 2751 display_pipe_source_params_st *src = &pipes[pipe_idx].pipe.src; 2752 display_pipe_dest_params_st *dst = &pipes[pipe_idx].pipe.dest; 2753 2754 dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit]; 2755 dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit]; 2756 dst->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit]; 2757 dst->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit]; 2758 /* 2759 * j iterates inside pipes array, unlike i which iterates inside 2760 * pipe_ctx array 2761 */ 2762 if (src->is_hsplit) 2763 for (j = pipe_idx + 1; j < pipe_cnt; j++) { 2764 display_pipe_source_params_st *src_j = &pipes[j].pipe.src; 2765 display_pipe_dest_params_st *dst_j = &pipes[j].pipe.dest; 2766 2767 if (src_j->is_hsplit && !visited[j] 2768 && src->hsplit_grp == src_j->hsplit_grp) { 2769 dst_j->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit]; 2770 dst_j->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit]; 2771 dst_j->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit]; 2772 dst_j->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit]; 2773 visited[j] = true; 2774 } 2775 } 2776 visited[pipe_idx] = true; 2777 pipe_idx_unsplit++; 2778 } 2779 pipe_idx++; 2780 } 2781 2782 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2783 if (!context->res_ctx.pipe_ctx[i].stream) 2784 continue; 2785 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 2786 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 2787 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 2788 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 2789 ASSERT(visited[pipe_idx]); 2790 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; 2791 pipe_idx++; 2792 } 2793 /*save a original dppclock copy*/ 2794 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; 2795 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; 2796 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000; 2797 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000; 2798 2799 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2800 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2; 2801 2802 if (!context->res_ctx.pipe_ctx[i].stream) 2803 continue; 2804 2805 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml, 2806 &context->res_ctx.pipe_ctx[i].dlg_regs, 2807 &context->res_ctx.pipe_ctx[i].ttu_regs, 2808 pipes, 2809 pipe_cnt, 2810 pipe_idx, 2811 cstate_en, 2812 context->bw_ctx.bw.dcn.clk.p_state_change_support, 2813 false, false, false); 2814 2815 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml, 2816 &context->res_ctx.pipe_ctx[i].rq_regs, 2817 pipes[pipe_idx].pipe); 2818 pipe_idx++; 2819 } 2820 } 2821 2822 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context, 2823 bool fast_validate) 2824 { 2825 bool out = false; 2826 2827 BW_VAL_TRACE_SETUP(); 2828 2829 int vlevel = 0; 2830 int pipe_split_from[MAX_PIPES]; 2831 int pipe_cnt = 0; 2832 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 2833 DC_LOGGER_INIT(dc->ctx->logger); 2834 2835 BW_VAL_TRACE_COUNT(); 2836 2837 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel); 2838 2839 if (pipe_cnt == 0) 2840 goto validate_out; 2841 2842 if (!out) 2843 goto validate_fail; 2844 2845 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 2846 2847 if (fast_validate) { 2848 BW_VAL_TRACE_SKIP(fast); 2849 goto validate_out; 2850 } 2851 2852 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel); 2853 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 2854 2855 BW_VAL_TRACE_END_WATERMARKS(); 2856 2857 goto validate_out; 2858 2859 validate_fail: 2860 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 2861 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 2862 2863 BW_VAL_TRACE_SKIP(fail); 2864 out = false; 2865 2866 validate_out: 2867 kfree(pipes); 2868 2869 BW_VAL_TRACE_FINISH(); 2870 2871 return out; 2872 } 2873 2874 2875 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, 2876 bool fast_validate) 2877 { 2878 bool voltage_supported = false; 2879 bool full_pstate_supported = false; 2880 bool dummy_pstate_supported = false; 2881 double p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us; 2882 context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support = dc->debug.disable_dram_clock_change_vactive_support; 2883 2884 if (fast_validate) 2885 return dcn20_validate_bandwidth_internal(dc, context, true); 2886 2887 2888 // Best case, we support full UCLK switch latency 2889 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); 2890 full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; 2891 2892 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 || 2893 (voltage_supported && full_pstate_supported)) { 2894 context->bw_ctx.bw.dcn.clk.p_state_change_support = true; 2895 goto restore_dml_state; 2896 } 2897 2898 // Fallback: Try to only support G6 temperature read latency 2899 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us; 2900 2901 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); 2902 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; 2903 2904 if (voltage_supported && dummy_pstate_supported) { 2905 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; 2906 goto restore_dml_state; 2907 } 2908 2909 // ERROR: fallback is supposed to always work. 2910 ASSERT(false); 2911 2912 restore_dml_state: 2913 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us; 2914 2915 return voltage_supported; 2916 } 2917 2918 struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer( 2919 struct dc_state *state, 2920 const struct resource_pool *pool, 2921 struct dc_stream_state *stream) 2922 { 2923 struct resource_context *res_ctx = &state->res_ctx; 2924 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 2925 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe); 2926 2927 if (!head_pipe) 2928 ASSERT(0); 2929 2930 if (!idle_pipe) 2931 return NULL; 2932 2933 idle_pipe->stream = head_pipe->stream; 2934 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 2935 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 2936 2937 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 2938 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 2939 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 2940 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 2941 2942 return idle_pipe; 2943 } 2944 2945 bool dcn20_get_dcc_compression_cap(const struct dc *dc, 2946 const struct dc_dcc_surface_param *input, 2947 struct dc_surface_dcc_cap *output) 2948 { 2949 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 2950 dc->res_pool->hubbub, 2951 input, 2952 output); 2953 } 2954 2955 static void dcn20_destroy_resource_pool(struct resource_pool **pool) 2956 { 2957 struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool); 2958 2959 dcn20_resource_destruct(dcn20_pool); 2960 kfree(dcn20_pool); 2961 *pool = NULL; 2962 } 2963 2964 2965 static struct dc_cap_funcs cap_funcs = { 2966 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 2967 }; 2968 2969 2970 enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state) 2971 { 2972 enum dc_status result = DC_OK; 2973 2974 enum surface_pixel_format surf_pix_format = plane_state->format; 2975 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 2976 2977 enum swizzle_mode_values swizzle = DC_SW_LINEAR; 2978 2979 if (bpp == 64) 2980 swizzle = DC_SW_64KB_D; 2981 else 2982 swizzle = DC_SW_64KB_S; 2983 2984 plane_state->tiling_info.gfx9.swizzle = swizzle; 2985 return result; 2986 } 2987 2988 static struct resource_funcs dcn20_res_pool_funcs = { 2989 .destroy = dcn20_destroy_resource_pool, 2990 .link_enc_create = dcn20_link_encoder_create, 2991 .validate_bandwidth = dcn20_validate_bandwidth, 2992 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 2993 .add_stream_to_ctx = dcn20_add_stream_to_ctx, 2994 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 2995 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, 2996 .get_default_swizzle_mode = dcn20_get_default_swizzle_mode, 2997 .set_mcif_arb_params = dcn20_set_mcif_arb_params, 2998 .populate_dml_pipes = dcn20_populate_dml_pipes_from_context, 2999 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link 3000 }; 3001 3002 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 3003 { 3004 int i; 3005 uint32_t pipe_count = pool->res_cap->num_dwb; 3006 3007 for (i = 0; i < pipe_count; i++) { 3008 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc), 3009 GFP_KERNEL); 3010 3011 if (!dwbc20) { 3012 dm_error("DC: failed to create dwbc20!\n"); 3013 return false; 3014 } 3015 dcn20_dwbc_construct(dwbc20, ctx, 3016 &dwbc20_regs[i], 3017 &dwbc20_shift, 3018 &dwbc20_mask, 3019 i); 3020 pool->dwbc[i] = &dwbc20->base; 3021 } 3022 return true; 3023 } 3024 3025 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 3026 { 3027 int i; 3028 uint32_t pipe_count = pool->res_cap->num_dwb; 3029 3030 ASSERT(pipe_count > 0); 3031 3032 for (i = 0; i < pipe_count; i++) { 3033 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub), 3034 GFP_KERNEL); 3035 3036 if (!mcif_wb20) { 3037 dm_error("DC: failed to create mcif_wb20!\n"); 3038 return false; 3039 } 3040 3041 dcn20_mmhubbub_construct(mcif_wb20, ctx, 3042 &mcif_wb20_regs[i], 3043 &mcif_wb20_shift, 3044 &mcif_wb20_mask, 3045 i); 3046 3047 pool->mcif_wb[i] = &mcif_wb20->base; 3048 } 3049 return true; 3050 } 3051 3052 static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx) 3053 { 3054 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 3055 3056 if (!pp_smu) 3057 return pp_smu; 3058 3059 dm_pp_get_funcs(ctx, pp_smu); 3060 3061 if (pp_smu->ctx.ver != PP_SMU_VER_NV) 3062 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); 3063 3064 return pp_smu; 3065 } 3066 3067 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu) 3068 { 3069 if (pp_smu && *pp_smu) { 3070 kfree(*pp_smu); 3071 *pp_smu = NULL; 3072 } 3073 } 3074 3075 void dcn20_cap_soc_clocks( 3076 struct _vcs_dpi_soc_bounding_box_st *bb, 3077 struct pp_smu_nv_clock_table max_clocks) 3078 { 3079 int i; 3080 3081 // First pass - cap all clocks higher than the reported max 3082 for (i = 0; i < bb->num_states; i++) { 3083 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000)) 3084 && max_clocks.dcfClockInKhz != 0) 3085 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000); 3086 3087 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16) 3088 && max_clocks.uClockInKhz != 0) 3089 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16; 3090 3091 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000)) 3092 && max_clocks.fabricClockInKhz != 0) 3093 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000); 3094 3095 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000)) 3096 && max_clocks.displayClockInKhz != 0) 3097 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000); 3098 3099 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000)) 3100 && max_clocks.dppClockInKhz != 0) 3101 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000); 3102 3103 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000)) 3104 && max_clocks.phyClockInKhz != 0) 3105 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000); 3106 3107 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000)) 3108 && max_clocks.socClockInKhz != 0) 3109 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000); 3110 3111 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000)) 3112 && max_clocks.dscClockInKhz != 0) 3113 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000); 3114 } 3115 3116 // Second pass - remove all duplicate clock states 3117 for (i = bb->num_states - 1; i > 1; i--) { 3118 bool duplicate = true; 3119 3120 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz) 3121 duplicate = false; 3122 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz) 3123 duplicate = false; 3124 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz) 3125 duplicate = false; 3126 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts) 3127 duplicate = false; 3128 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz) 3129 duplicate = false; 3130 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz) 3131 duplicate = false; 3132 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz) 3133 duplicate = false; 3134 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz) 3135 duplicate = false; 3136 3137 if (duplicate) 3138 bb->num_states--; 3139 } 3140 } 3141 3142 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb, 3143 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) 3144 { 3145 struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES]; 3146 int i; 3147 int num_calculated_states = 0; 3148 int min_dcfclk = 0; 3149 3150 if (num_states == 0) 3151 return; 3152 3153 memset(calculated_states, 0, sizeof(calculated_states)); 3154 3155 if (dc->bb_overrides.min_dcfclk_mhz > 0) 3156 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz; 3157 else { 3158 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) 3159 min_dcfclk = 310; 3160 else 3161 // Accounting for SOC/DCF relationship, we can go as high as 3162 // 506Mhz in Vmin. 3163 min_dcfclk = 506; 3164 } 3165 3166 for (i = 0; i < num_states; i++) { 3167 int min_fclk_required_by_uclk; 3168 calculated_states[i].state = i; 3169 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000; 3170 3171 // FCLK:UCLK ratio is 1.08 3172 min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32); 3173 3174 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? 3175 min_dcfclk : min_fclk_required_by_uclk; 3176 3177 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ? 3178 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; 3179 3180 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ? 3181 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; 3182 3183 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000; 3184 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000; 3185 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3); 3186 3187 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000; 3188 3189 num_calculated_states++; 3190 } 3191 3192 calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000; 3193 calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000; 3194 calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000; 3195 3196 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits)); 3197 bb->num_states = num_calculated_states; 3198 3199 // Duplicate the last state, DML always an extra state identical to max state to work 3200 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st)); 3201 bb->clock_limits[num_calculated_states].state = bb->num_states; 3202 } 3203 3204 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) 3205 { 3206 kernel_fpu_begin(); 3207 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns 3208 && dc->bb_overrides.sr_exit_time_ns) { 3209 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; 3210 } 3211 3212 if ((int)(bb->sr_enter_plus_exit_time_us * 1000) 3213 != dc->bb_overrides.sr_enter_plus_exit_time_ns 3214 && dc->bb_overrides.sr_enter_plus_exit_time_ns) { 3215 bb->sr_enter_plus_exit_time_us = 3216 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 3217 } 3218 3219 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns 3220 && dc->bb_overrides.urgent_latency_ns) { 3221 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 3222 } 3223 3224 if ((int)(bb->dram_clock_change_latency_us * 1000) 3225 != dc->bb_overrides.dram_clock_change_latency_ns 3226 && dc->bb_overrides.dram_clock_change_latency_ns) { 3227 bb->dram_clock_change_latency_us = 3228 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 3229 } 3230 kernel_fpu_end(); 3231 } 3232 3233 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb( 3234 uint32_t hw_internal_rev) 3235 { 3236 if (ASICREV_IS_NAVI12_P(hw_internal_rev)) 3237 return &dcn2_0_nv12_soc; 3238 3239 return &dcn2_0_soc; 3240 } 3241 3242 static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params( 3243 uint32_t hw_internal_rev) 3244 { 3245 /* NV14 */ 3246 if (ASICREV_IS_NAVI14_M(hw_internal_rev)) 3247 return &dcn2_0_nv14_ip; 3248 3249 /* NV12 and NV10 */ 3250 return &dcn2_0_ip; 3251 } 3252 3253 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev) 3254 { 3255 return DML_PROJECT_NAVI10v2; 3256 } 3257 3258 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16))) 3259 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) 3260 3261 static bool init_soc_bounding_box(struct dc *dc, 3262 struct dcn20_resource_pool *pool) 3263 { 3264 const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box; 3265 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = 3266 get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev); 3267 struct _vcs_dpi_ip_params_st *loaded_ip = 3268 get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev); 3269 3270 DC_LOGGER_INIT(dc->ctx->logger); 3271 3272 /* TODO: upstream NV12 bounding box when its launched */ 3273 if (!bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) { 3274 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); 3275 return false; 3276 } 3277 3278 if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) { 3279 int i; 3280 3281 dcn2_0_nv12_soc.sr_exit_time_us = 3282 fixed16_to_double_to_cpu(bb->sr_exit_time_us); 3283 dcn2_0_nv12_soc.sr_enter_plus_exit_time_us = 3284 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us); 3285 dcn2_0_nv12_soc.urgent_latency_us = 3286 fixed16_to_double_to_cpu(bb->urgent_latency_us); 3287 dcn2_0_nv12_soc.urgent_latency_pixel_data_only_us = 3288 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us); 3289 dcn2_0_nv12_soc.urgent_latency_pixel_mixed_with_vm_data_us = 3290 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us); 3291 dcn2_0_nv12_soc.urgent_latency_vm_data_only_us = 3292 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us); 3293 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes = 3294 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes); 3295 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 3296 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes); 3297 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_vm_only_bytes = 3298 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes); 3299 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 3300 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only); 3301 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 3302 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm); 3303 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 3304 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only); 3305 dcn2_0_nv12_soc.max_avg_sdp_bw_use_normal_percent = 3306 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent); 3307 dcn2_0_nv12_soc.max_avg_dram_bw_use_normal_percent = 3308 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent); 3309 dcn2_0_nv12_soc.writeback_latency_us = 3310 fixed16_to_double_to_cpu(bb->writeback_latency_us); 3311 dcn2_0_nv12_soc.ideal_dram_bw_after_urgent_percent = 3312 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent); 3313 dcn2_0_nv12_soc.max_request_size_bytes = 3314 le32_to_cpu(bb->max_request_size_bytes); 3315 dcn2_0_nv12_soc.dram_channel_width_bytes = 3316 le32_to_cpu(bb->dram_channel_width_bytes); 3317 dcn2_0_nv12_soc.fabric_datapath_to_dcn_data_return_bytes = 3318 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes); 3319 dcn2_0_nv12_soc.dcn_downspread_percent = 3320 fixed16_to_double_to_cpu(bb->dcn_downspread_percent); 3321 dcn2_0_nv12_soc.downspread_percent = 3322 fixed16_to_double_to_cpu(bb->downspread_percent); 3323 dcn2_0_nv12_soc.dram_page_open_time_ns = 3324 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns); 3325 dcn2_0_nv12_soc.dram_rw_turnaround_time_ns = 3326 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns); 3327 dcn2_0_nv12_soc.dram_return_buffer_per_channel_bytes = 3328 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes); 3329 dcn2_0_nv12_soc.round_trip_ping_latency_dcfclk_cycles = 3330 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles); 3331 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_bytes = 3332 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes); 3333 dcn2_0_nv12_soc.channel_interleave_bytes = 3334 le32_to_cpu(bb->channel_interleave_bytes); 3335 dcn2_0_nv12_soc.num_banks = 3336 le32_to_cpu(bb->num_banks); 3337 dcn2_0_nv12_soc.num_chans = 3338 le32_to_cpu(bb->num_chans); 3339 dcn2_0_nv12_soc.vmm_page_size_bytes = 3340 le32_to_cpu(bb->vmm_page_size_bytes); 3341 dcn2_0_nv12_soc.dram_clock_change_latency_us = 3342 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us); 3343 // HACK!! Lower uclock latency switch time so we don't switch 3344 dcn2_0_nv12_soc.dram_clock_change_latency_us = 10; 3345 dcn2_0_nv12_soc.writeback_dram_clock_change_latency_us = 3346 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us); 3347 dcn2_0_nv12_soc.return_bus_width_bytes = 3348 le32_to_cpu(bb->return_bus_width_bytes); 3349 dcn2_0_nv12_soc.dispclk_dppclk_vco_speed_mhz = 3350 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz); 3351 dcn2_0_nv12_soc.xfc_bus_transport_time_us = 3352 le32_to_cpu(bb->xfc_bus_transport_time_us); 3353 dcn2_0_nv12_soc.xfc_xbuf_latency_tolerance_us = 3354 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us); 3355 dcn2_0_nv12_soc.use_urgent_burst_bw = 3356 le32_to_cpu(bb->use_urgent_burst_bw); 3357 dcn2_0_nv12_soc.num_states = 3358 le32_to_cpu(bb->num_states); 3359 3360 for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) { 3361 dcn2_0_nv12_soc.clock_limits[i].state = 3362 le32_to_cpu(bb->clock_limits[i].state); 3363 dcn2_0_nv12_soc.clock_limits[i].dcfclk_mhz = 3364 fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz); 3365 dcn2_0_nv12_soc.clock_limits[i].fabricclk_mhz = 3366 fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz); 3367 dcn2_0_nv12_soc.clock_limits[i].dispclk_mhz = 3368 fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz); 3369 dcn2_0_nv12_soc.clock_limits[i].dppclk_mhz = 3370 fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz); 3371 dcn2_0_nv12_soc.clock_limits[i].phyclk_mhz = 3372 fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz); 3373 dcn2_0_nv12_soc.clock_limits[i].socclk_mhz = 3374 fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz); 3375 dcn2_0_nv12_soc.clock_limits[i].dscclk_mhz = 3376 fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz); 3377 dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts = 3378 fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts); 3379 } 3380 } 3381 3382 if (pool->base.pp_smu) { 3383 struct pp_smu_nv_clock_table max_clocks = {0}; 3384 unsigned int uclk_states[8] = {0}; 3385 unsigned int num_states = 0; 3386 enum pp_smu_status status; 3387 bool clock_limits_available = false; 3388 bool uclk_states_available = false; 3389 3390 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) { 3391 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) 3392 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); 3393 3394 uclk_states_available = (status == PP_SMU_RESULT_OK); 3395 } 3396 3397 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) { 3398 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) 3399 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks); 3400 /* SMU cannot set DCF clock to anything equal to or higher than SOC clock 3401 */ 3402 if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz) 3403 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000; 3404 clock_limits_available = (status == PP_SMU_RESULT_OK); 3405 } 3406 3407 if (clock_limits_available && uclk_states_available && num_states) 3408 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states); 3409 else if (clock_limits_available) 3410 dcn20_cap_soc_clocks(loaded_bb, max_clocks); 3411 } 3412 3413 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; 3414 loaded_ip->max_num_dpp = pool->base.pipe_count; 3415 dcn20_patch_bounding_box(dc, loaded_bb); 3416 3417 return true; 3418 } 3419 3420 static bool dcn20_resource_construct( 3421 uint8_t num_virtual_links, 3422 struct dc *dc, 3423 struct dcn20_resource_pool *pool) 3424 { 3425 int i; 3426 struct dc_context *ctx = dc->ctx; 3427 struct irq_service_init_data init_data; 3428 struct ddc_service_init_data ddc_init_data; 3429 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = 3430 get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev); 3431 struct _vcs_dpi_ip_params_st *loaded_ip = 3432 get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev); 3433 enum dml_project dml_project_version = 3434 get_dml_project_version(ctx->asic_id.hw_internal_rev); 3435 3436 ctx->dc_bios->regs = &bios_regs; 3437 pool->base.funcs = &dcn20_res_pool_funcs; 3438 3439 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) { 3440 pool->base.res_cap = &res_cap_nv14; 3441 pool->base.pipe_count = 5; 3442 pool->base.mpcc_count = 5; 3443 } else { 3444 pool->base.res_cap = &res_cap_nv10; 3445 pool->base.pipe_count = 6; 3446 pool->base.mpcc_count = 6; 3447 } 3448 /************************************************* 3449 * Resource + asic cap harcoding * 3450 *************************************************/ 3451 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 3452 3453 dc->caps.max_downscale_ratio = 200; 3454 dc->caps.i2c_speed_in_khz = 100; 3455 dc->caps.max_cursor_size = 256; 3456 dc->caps.dmdata_alloc_size = 2048; 3457 3458 dc->caps.max_slave_planes = 1; 3459 dc->caps.post_blend_color_processing = true; 3460 dc->caps.force_dp_tps4_for_cp2520 = true; 3461 dc->caps.hw_3d_lut = true; 3462 dc->caps.extended_aux_timeout_support = true; 3463 3464 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) { 3465 dc->debug = debug_defaults_drv; 3466 } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 3467 pool->base.pipe_count = 4; 3468 pool->base.mpcc_count = pool->base.pipe_count; 3469 dc->debug = debug_defaults_diags; 3470 } else { 3471 dc->debug = debug_defaults_diags; 3472 } 3473 //dcn2.0x 3474 dc->work_arounds.dedcn20_305_wa = true; 3475 3476 // Init the vm_helper 3477 if (dc->vm_helper) 3478 vm_helper_init(dc->vm_helper, 16); 3479 3480 /************************************************* 3481 * Create resources * 3482 *************************************************/ 3483 3484 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = 3485 dcn20_clock_source_create(ctx, ctx->dc_bios, 3486 CLOCK_SOURCE_COMBO_PHY_PLL0, 3487 &clk_src_regs[0], false); 3488 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = 3489 dcn20_clock_source_create(ctx, ctx->dc_bios, 3490 CLOCK_SOURCE_COMBO_PHY_PLL1, 3491 &clk_src_regs[1], false); 3492 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = 3493 dcn20_clock_source_create(ctx, ctx->dc_bios, 3494 CLOCK_SOURCE_COMBO_PHY_PLL2, 3495 &clk_src_regs[2], false); 3496 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] = 3497 dcn20_clock_source_create(ctx, ctx->dc_bios, 3498 CLOCK_SOURCE_COMBO_PHY_PLL3, 3499 &clk_src_regs[3], false); 3500 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] = 3501 dcn20_clock_source_create(ctx, ctx->dc_bios, 3502 CLOCK_SOURCE_COMBO_PHY_PLL4, 3503 &clk_src_regs[4], false); 3504 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] = 3505 dcn20_clock_source_create(ctx, ctx->dc_bios, 3506 CLOCK_SOURCE_COMBO_PHY_PLL5, 3507 &clk_src_regs[5], false); 3508 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL; 3509 /* todo: not reuse phy_pll registers */ 3510 pool->base.dp_clock_source = 3511 dcn20_clock_source_create(ctx, ctx->dc_bios, 3512 CLOCK_SOURCE_ID_DP_DTO, 3513 &clk_src_regs[0], true); 3514 3515 for (i = 0; i < pool->base.clk_src_count; i++) { 3516 if (pool->base.clock_sources[i] == NULL) { 3517 dm_error("DC: failed to create clock sources!\n"); 3518 BREAK_TO_DEBUGGER(); 3519 goto create_fail; 3520 } 3521 } 3522 3523 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 3524 if (pool->base.dccg == NULL) { 3525 dm_error("DC: failed to create dccg!\n"); 3526 BREAK_TO_DEBUGGER(); 3527 goto create_fail; 3528 } 3529 3530 pool->base.dmcu = dcn20_dmcu_create(ctx, 3531 &dmcu_regs, 3532 &dmcu_shift, 3533 &dmcu_mask); 3534 if (pool->base.dmcu == NULL) { 3535 dm_error("DC: failed to create dmcu!\n"); 3536 BREAK_TO_DEBUGGER(); 3537 goto create_fail; 3538 } 3539 3540 pool->base.abm = dce_abm_create(ctx, 3541 &abm_regs, 3542 &abm_shift, 3543 &abm_mask); 3544 if (pool->base.abm == NULL) { 3545 dm_error("DC: failed to create abm!\n"); 3546 BREAK_TO_DEBUGGER(); 3547 goto create_fail; 3548 } 3549 3550 pool->base.pp_smu = dcn20_pp_smu_create(ctx); 3551 3552 3553 if (!init_soc_bounding_box(dc, pool)) { 3554 dm_error("DC: failed to initialize soc bounding box!\n"); 3555 BREAK_TO_DEBUGGER(); 3556 goto create_fail; 3557 } 3558 3559 dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version); 3560 3561 if (!dc->debug.disable_pplib_wm_range) { 3562 struct pp_smu_wm_range_sets ranges = {0}; 3563 int i = 0; 3564 3565 ranges.num_reader_wm_sets = 0; 3566 3567 if (loaded_bb->num_states == 1) { 3568 ranges.reader_wm_sets[0].wm_inst = i; 3569 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3570 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3571 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3572 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3573 3574 ranges.num_reader_wm_sets = 1; 3575 } else if (loaded_bb->num_states > 1) { 3576 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { 3577 ranges.reader_wm_sets[i].wm_inst = i; 3578 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3579 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3580 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; 3581 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; 3582 3583 ranges.num_reader_wm_sets = i + 1; 3584 } 3585 3586 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3587 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3588 } 3589 3590 ranges.num_writer_wm_sets = 1; 3591 3592 ranges.writer_wm_sets[0].wm_inst = 0; 3593 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3594 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3595 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3596 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3597 3598 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 3599 if (pool->base.pp_smu->nv_funcs.set_wm_ranges) 3600 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges); 3601 } 3602 3603 init_data.ctx = dc->ctx; 3604 pool->base.irqs = dal_irq_service_dcn20_create(&init_data); 3605 if (!pool->base.irqs) 3606 goto create_fail; 3607 3608 /* mem input -> ipp -> dpp -> opp -> TG */ 3609 for (i = 0; i < pool->base.pipe_count; i++) { 3610 pool->base.hubps[i] = dcn20_hubp_create(ctx, i); 3611 if (pool->base.hubps[i] == NULL) { 3612 BREAK_TO_DEBUGGER(); 3613 dm_error( 3614 "DC: failed to create memory input!\n"); 3615 goto create_fail; 3616 } 3617 3618 pool->base.ipps[i] = dcn20_ipp_create(ctx, i); 3619 if (pool->base.ipps[i] == NULL) { 3620 BREAK_TO_DEBUGGER(); 3621 dm_error( 3622 "DC: failed to create input pixel processor!\n"); 3623 goto create_fail; 3624 } 3625 3626 pool->base.dpps[i] = dcn20_dpp_create(ctx, i); 3627 if (pool->base.dpps[i] == NULL) { 3628 BREAK_TO_DEBUGGER(); 3629 dm_error( 3630 "DC: failed to create dpps!\n"); 3631 goto create_fail; 3632 } 3633 } 3634 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 3635 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i); 3636 if (pool->base.engines[i] == NULL) { 3637 BREAK_TO_DEBUGGER(); 3638 dm_error( 3639 "DC:failed to create aux engine!!\n"); 3640 goto create_fail; 3641 } 3642 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i); 3643 if (pool->base.hw_i2cs[i] == NULL) { 3644 BREAK_TO_DEBUGGER(); 3645 dm_error( 3646 "DC:failed to create hw i2c!!\n"); 3647 goto create_fail; 3648 } 3649 pool->base.sw_i2cs[i] = NULL; 3650 } 3651 3652 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 3653 pool->base.opps[i] = dcn20_opp_create(ctx, i); 3654 if (pool->base.opps[i] == NULL) { 3655 BREAK_TO_DEBUGGER(); 3656 dm_error( 3657 "DC: failed to create output pixel processor!\n"); 3658 goto create_fail; 3659 } 3660 } 3661 3662 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 3663 pool->base.timing_generators[i] = dcn20_timing_generator_create( 3664 ctx, i); 3665 if (pool->base.timing_generators[i] == NULL) { 3666 BREAK_TO_DEBUGGER(); 3667 dm_error("DC: failed to create tg!\n"); 3668 goto create_fail; 3669 } 3670 } 3671 3672 pool->base.timing_generator_count = i; 3673 3674 pool->base.mpc = dcn20_mpc_create(ctx); 3675 if (pool->base.mpc == NULL) { 3676 BREAK_TO_DEBUGGER(); 3677 dm_error("DC: failed to create mpc!\n"); 3678 goto create_fail; 3679 } 3680 3681 pool->base.hubbub = dcn20_hubbub_create(ctx); 3682 if (pool->base.hubbub == NULL) { 3683 BREAK_TO_DEBUGGER(); 3684 dm_error("DC: failed to create hubbub!\n"); 3685 goto create_fail; 3686 } 3687 3688 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 3689 pool->base.dscs[i] = dcn20_dsc_create(ctx, i); 3690 if (pool->base.dscs[i] == NULL) { 3691 BREAK_TO_DEBUGGER(); 3692 dm_error("DC: failed to create display stream compressor %d!\n", i); 3693 goto create_fail; 3694 } 3695 } 3696 3697 if (!dcn20_dwbc_create(ctx, &pool->base)) { 3698 BREAK_TO_DEBUGGER(); 3699 dm_error("DC: failed to create dwbc!\n"); 3700 goto create_fail; 3701 } 3702 if (!dcn20_mmhubbub_create(ctx, &pool->base)) { 3703 BREAK_TO_DEBUGGER(); 3704 dm_error("DC: failed to create mcif_wb!\n"); 3705 goto create_fail; 3706 } 3707 3708 if (!resource_construct(num_virtual_links, dc, &pool->base, 3709 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 3710 &res_create_funcs : &res_create_maximus_funcs))) 3711 goto create_fail; 3712 3713 dcn20_hw_sequencer_construct(dc); 3714 3715 dc->caps.max_planes = pool->base.pipe_count; 3716 3717 for (i = 0; i < dc->caps.max_planes; ++i) 3718 dc->caps.planes[i] = plane_cap; 3719 3720 dc->cap_funcs = cap_funcs; 3721 3722 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 3723 ddc_init_data.ctx = dc->ctx; 3724 ddc_init_data.link = NULL; 3725 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 3726 ddc_init_data.id.enum_id = 0; 3727 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 3728 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); 3729 } else { 3730 pool->base.oem_device = NULL; 3731 } 3732 3733 return true; 3734 3735 create_fail: 3736 3737 dcn20_resource_destruct(pool); 3738 3739 return false; 3740 } 3741 3742 struct resource_pool *dcn20_create_resource_pool( 3743 const struct dc_init_data *init_data, 3744 struct dc *dc) 3745 { 3746 struct dcn20_resource_pool *pool = 3747 kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL); 3748 3749 if (!pool) 3750 return NULL; 3751 3752 if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool)) 3753 return &pool->base; 3754 3755 BREAK_TO_DEBUGGER(); 3756 kfree(pool); 3757 return NULL; 3758 } 3759