1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * Copyright 2019 Raptor Engineering, LLC 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 #include "dc.h" 31 32 #include "dcn20_init.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dcn20/dcn20_resource.h" 37 38 #include "dcn10/dcn10_hubp.h" 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn20_hubbub.h" 41 #include "dcn20_mpc.h" 42 #include "dcn20_hubp.h" 43 #include "irq/dcn20/irq_service_dcn20.h" 44 #include "dcn20_dpp.h" 45 #include "dcn20_optc.h" 46 #include "dcn20_hwseq.h" 47 #include "dce110/dce110_hw_sequencer.h" 48 #include "dcn10/dcn10_resource.h" 49 #include "dcn20_opp.h" 50 51 #include "dcn20_dsc.h" 52 53 #include "dcn20_link_encoder.h" 54 #include "dcn20_stream_encoder.h" 55 #include "dce/dce_clock_source.h" 56 #include "dce/dce_audio.h" 57 #include "dce/dce_hwseq.h" 58 #include "virtual/virtual_stream_encoder.h" 59 #include "dce110/dce110_resource.h" 60 #include "dml/display_mode_vba.h" 61 #include "dcn20_dccg.h" 62 #include "dcn20_vmid.h" 63 #include "dc_link_ddc.h" 64 65 #include "navi10_ip_offset.h" 66 67 #include "dcn/dcn_2_0_0_offset.h" 68 #include "dcn/dcn_2_0_0_sh_mask.h" 69 #include "dpcs/dpcs_2_0_0_offset.h" 70 #include "dpcs/dpcs_2_0_0_sh_mask.h" 71 72 #include "nbio/nbio_2_3_offset.h" 73 74 #include "dcn20/dcn20_dwb.h" 75 #include "dcn20/dcn20_mmhubbub.h" 76 77 #include "mmhub/mmhub_2_0_0_offset.h" 78 #include "mmhub/mmhub_2_0_0_sh_mask.h" 79 80 #include "reg_helper.h" 81 #include "dce/dce_abm.h" 82 #include "dce/dce_dmcu.h" 83 #include "dce/dce_aux.h" 84 #include "dce/dce_i2c.h" 85 #include "vm_helper.h" 86 87 #include "amdgpu_socbb.h" 88 89 #define DC_LOGGER_INIT(logger) 90 91 struct _vcs_dpi_ip_params_st dcn2_0_ip = { 92 .odm_capable = 1, 93 .gpuvm_enable = 0, 94 .hostvm_enable = 0, 95 .gpuvm_max_page_table_levels = 4, 96 .hostvm_max_page_table_levels = 4, 97 .hostvm_cached_page_table_levels = 0, 98 .pte_group_size_bytes = 2048, 99 .num_dsc = 6, 100 .rob_buffer_size_kbytes = 168, 101 .det_buffer_size_kbytes = 164, 102 .dpte_buffer_size_in_pte_reqs_luma = 84, 103 .pde_proc_buffer_size_64k_reqs = 48, 104 .dpp_output_buffer_pixels = 2560, 105 .opp_output_buffer_lines = 1, 106 .pixel_chunk_size_kbytes = 8, 107 .pte_chunk_size_kbytes = 2, 108 .meta_chunk_size_kbytes = 2, 109 .writeback_chunk_size_kbytes = 2, 110 .line_buffer_size_bits = 789504, 111 .is_line_buffer_bpp_fixed = 0, 112 .line_buffer_fixed_bpp = 0, 113 .dcc_supported = true, 114 .max_line_buffer_lines = 12, 115 .writeback_luma_buffer_size_kbytes = 12, 116 .writeback_chroma_buffer_size_kbytes = 8, 117 .writeback_chroma_line_buffer_width_pixels = 4, 118 .writeback_max_hscl_ratio = 1, 119 .writeback_max_vscl_ratio = 1, 120 .writeback_min_hscl_ratio = 1, 121 .writeback_min_vscl_ratio = 1, 122 .writeback_max_hscl_taps = 12, 123 .writeback_max_vscl_taps = 12, 124 .writeback_line_buffer_luma_buffer_size = 0, 125 .writeback_line_buffer_chroma_buffer_size = 14643, 126 .cursor_buffer_size = 8, 127 .cursor_chunk_size = 2, 128 .max_num_otg = 6, 129 .max_num_dpp = 6, 130 .max_num_wb = 1, 131 .max_dchub_pscl_bw_pix_per_clk = 4, 132 .max_pscl_lb_bw_pix_per_clk = 2, 133 .max_lb_vscl_bw_pix_per_clk = 4, 134 .max_vscl_hscl_bw_pix_per_clk = 4, 135 .max_hscl_ratio = 8, 136 .max_vscl_ratio = 8, 137 .hscl_mults = 4, 138 .vscl_mults = 4, 139 .max_hscl_taps = 8, 140 .max_vscl_taps = 8, 141 .dispclk_ramp_margin_percent = 1, 142 .underscan_factor = 1.10, 143 .min_vblank_lines = 32, // 144 .dppclk_delay_subtotal = 77, // 145 .dppclk_delay_scl_lb_only = 16, 146 .dppclk_delay_scl = 50, 147 .dppclk_delay_cnvc_formatter = 8, 148 .dppclk_delay_cnvc_cursor = 6, 149 .dispclk_delay_subtotal = 87, // 150 .dcfclk_cstate_latency = 10, // SRExitTime 151 .max_inter_dcn_tile_repeaters = 8, 152 153 .xfc_supported = true, 154 .xfc_fill_bw_overhead_percent = 10.0, 155 .xfc_fill_constant_bytes = 0, 156 .number_of_cursors = 1, 157 }; 158 159 struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = { 160 .odm_capable = 1, 161 .gpuvm_enable = 0, 162 .hostvm_enable = 0, 163 .gpuvm_max_page_table_levels = 4, 164 .hostvm_max_page_table_levels = 4, 165 .hostvm_cached_page_table_levels = 0, 166 .num_dsc = 5, 167 .rob_buffer_size_kbytes = 168, 168 .det_buffer_size_kbytes = 164, 169 .dpte_buffer_size_in_pte_reqs_luma = 84, 170 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo 171 .dpp_output_buffer_pixels = 2560, 172 .opp_output_buffer_lines = 1, 173 .pixel_chunk_size_kbytes = 8, 174 .pte_enable = 1, 175 .max_page_table_levels = 4, 176 .pte_chunk_size_kbytes = 2, 177 .meta_chunk_size_kbytes = 2, 178 .writeback_chunk_size_kbytes = 2, 179 .line_buffer_size_bits = 789504, 180 .is_line_buffer_bpp_fixed = 0, 181 .line_buffer_fixed_bpp = 0, 182 .dcc_supported = true, 183 .max_line_buffer_lines = 12, 184 .writeback_luma_buffer_size_kbytes = 12, 185 .writeback_chroma_buffer_size_kbytes = 8, 186 .writeback_chroma_line_buffer_width_pixels = 4, 187 .writeback_max_hscl_ratio = 1, 188 .writeback_max_vscl_ratio = 1, 189 .writeback_min_hscl_ratio = 1, 190 .writeback_min_vscl_ratio = 1, 191 .writeback_max_hscl_taps = 12, 192 .writeback_max_vscl_taps = 12, 193 .writeback_line_buffer_luma_buffer_size = 0, 194 .writeback_line_buffer_chroma_buffer_size = 14643, 195 .cursor_buffer_size = 8, 196 .cursor_chunk_size = 2, 197 .max_num_otg = 5, 198 .max_num_dpp = 5, 199 .max_num_wb = 1, 200 .max_dchub_pscl_bw_pix_per_clk = 4, 201 .max_pscl_lb_bw_pix_per_clk = 2, 202 .max_lb_vscl_bw_pix_per_clk = 4, 203 .max_vscl_hscl_bw_pix_per_clk = 4, 204 .max_hscl_ratio = 8, 205 .max_vscl_ratio = 8, 206 .hscl_mults = 4, 207 .vscl_mults = 4, 208 .max_hscl_taps = 8, 209 .max_vscl_taps = 8, 210 .dispclk_ramp_margin_percent = 1, 211 .underscan_factor = 1.10, 212 .min_vblank_lines = 32, // 213 .dppclk_delay_subtotal = 77, // 214 .dppclk_delay_scl_lb_only = 16, 215 .dppclk_delay_scl = 50, 216 .dppclk_delay_cnvc_formatter = 8, 217 .dppclk_delay_cnvc_cursor = 6, 218 .dispclk_delay_subtotal = 87, // 219 .dcfclk_cstate_latency = 10, // SRExitTime 220 .max_inter_dcn_tile_repeaters = 8, 221 .xfc_supported = true, 222 .xfc_fill_bw_overhead_percent = 10.0, 223 .xfc_fill_constant_bytes = 0, 224 .ptoi_supported = 0, 225 .number_of_cursors = 1, 226 }; 227 228 struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { 229 /* Defaults that get patched on driver load from firmware. */ 230 .clock_limits = { 231 { 232 .state = 0, 233 .dcfclk_mhz = 560.0, 234 .fabricclk_mhz = 560.0, 235 .dispclk_mhz = 513.0, 236 .dppclk_mhz = 513.0, 237 .phyclk_mhz = 540.0, 238 .socclk_mhz = 560.0, 239 .dscclk_mhz = 171.0, 240 .dram_speed_mts = 8960.0, 241 }, 242 { 243 .state = 1, 244 .dcfclk_mhz = 694.0, 245 .fabricclk_mhz = 694.0, 246 .dispclk_mhz = 642.0, 247 .dppclk_mhz = 642.0, 248 .phyclk_mhz = 600.0, 249 .socclk_mhz = 694.0, 250 .dscclk_mhz = 214.0, 251 .dram_speed_mts = 11104.0, 252 }, 253 { 254 .state = 2, 255 .dcfclk_mhz = 875.0, 256 .fabricclk_mhz = 875.0, 257 .dispclk_mhz = 734.0, 258 .dppclk_mhz = 734.0, 259 .phyclk_mhz = 810.0, 260 .socclk_mhz = 875.0, 261 .dscclk_mhz = 245.0, 262 .dram_speed_mts = 14000.0, 263 }, 264 { 265 .state = 3, 266 .dcfclk_mhz = 1000.0, 267 .fabricclk_mhz = 1000.0, 268 .dispclk_mhz = 1100.0, 269 .dppclk_mhz = 1100.0, 270 .phyclk_mhz = 810.0, 271 .socclk_mhz = 1000.0, 272 .dscclk_mhz = 367.0, 273 .dram_speed_mts = 16000.0, 274 }, 275 { 276 .state = 4, 277 .dcfclk_mhz = 1200.0, 278 .fabricclk_mhz = 1200.0, 279 .dispclk_mhz = 1284.0, 280 .dppclk_mhz = 1284.0, 281 .phyclk_mhz = 810.0, 282 .socclk_mhz = 1200.0, 283 .dscclk_mhz = 428.0, 284 .dram_speed_mts = 16000.0, 285 }, 286 /*Extra state, no dispclk ramping*/ 287 { 288 .state = 5, 289 .dcfclk_mhz = 1200.0, 290 .fabricclk_mhz = 1200.0, 291 .dispclk_mhz = 1284.0, 292 .dppclk_mhz = 1284.0, 293 .phyclk_mhz = 810.0, 294 .socclk_mhz = 1200.0, 295 .dscclk_mhz = 428.0, 296 .dram_speed_mts = 16000.0, 297 }, 298 }, 299 .num_states = 5, 300 .sr_exit_time_us = 8.6, 301 .sr_enter_plus_exit_time_us = 10.9, 302 .urgent_latency_us = 4.0, 303 .urgent_latency_pixel_data_only_us = 4.0, 304 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 305 .urgent_latency_vm_data_only_us = 4.0, 306 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 307 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 308 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 309 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0, 310 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0, 311 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 312 .max_avg_sdp_bw_use_normal_percent = 40.0, 313 .max_avg_dram_bw_use_normal_percent = 40.0, 314 .writeback_latency_us = 12.0, 315 .ideal_dram_bw_after_urgent_percent = 40.0, 316 .max_request_size_bytes = 256, 317 .dram_channel_width_bytes = 2, 318 .fabric_datapath_to_dcn_data_return_bytes = 64, 319 .dcn_downspread_percent = 0.5, 320 .downspread_percent = 0.38, 321 .dram_page_open_time_ns = 50.0, 322 .dram_rw_turnaround_time_ns = 17.5, 323 .dram_return_buffer_per_channel_bytes = 8192, 324 .round_trip_ping_latency_dcfclk_cycles = 131, 325 .urgent_out_of_order_return_per_channel_bytes = 256, 326 .channel_interleave_bytes = 256, 327 .num_banks = 8, 328 .num_chans = 16, 329 .vmm_page_size_bytes = 4096, 330 .dram_clock_change_latency_us = 404.0, 331 .dummy_pstate_latency_us = 5.0, 332 .writeback_dram_clock_change_latency_us = 23.0, 333 .return_bus_width_bytes = 64, 334 .dispclk_dppclk_vco_speed_mhz = 3850, 335 .xfc_bus_transport_time_us = 20, 336 .xfc_xbuf_latency_tolerance_us = 4, 337 .use_urgent_burst_bw = 0 338 }; 339 340 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 }; 341 342 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 343 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 344 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 345 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 346 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 347 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 348 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 349 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 350 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 351 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 352 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 353 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 354 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 355 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 356 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 357 #endif 358 359 360 enum dcn20_clk_src_array_id { 361 DCN20_CLK_SRC_PLL0, 362 DCN20_CLK_SRC_PLL1, 363 DCN20_CLK_SRC_PLL2, 364 DCN20_CLK_SRC_PLL3, 365 DCN20_CLK_SRC_PLL4, 366 DCN20_CLK_SRC_PLL5, 367 DCN20_CLK_SRC_TOTAL 368 }; 369 370 /* begin ********************* 371 * macros to expend register list macro defined in HW object header file */ 372 373 /* DCN */ 374 /* TODO awful hack. fixup dcn20_dwb.h */ 375 #undef BASE_INNER 376 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 377 378 #define BASE(seg) BASE_INNER(seg) 379 380 #define SR(reg_name)\ 381 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 382 mm ## reg_name 383 384 #define SRI(reg_name, block, id)\ 385 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 386 mm ## block ## id ## _ ## reg_name 387 388 #define SRIR(var_name, reg_name, block, id)\ 389 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 390 mm ## block ## id ## _ ## reg_name 391 392 #define SRII(reg_name, block, id)\ 393 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 394 mm ## block ## id ## _ ## reg_name 395 396 #define DCCG_SRII(reg_name, block, id)\ 397 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 398 mm ## block ## id ## _ ## reg_name 399 400 /* NBIO */ 401 #define NBIO_BASE_INNER(seg) \ 402 NBIO_BASE__INST0_SEG ## seg 403 404 #define NBIO_BASE(seg) \ 405 NBIO_BASE_INNER(seg) 406 407 #define NBIO_SR(reg_name)\ 408 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 409 mm ## reg_name 410 411 /* MMHUB */ 412 #define MMHUB_BASE_INNER(seg) \ 413 MMHUB_BASE__INST0_SEG ## seg 414 415 #define MMHUB_BASE(seg) \ 416 MMHUB_BASE_INNER(seg) 417 418 #define MMHUB_SR(reg_name)\ 419 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 420 mmMM ## reg_name 421 422 static const struct bios_registers bios_regs = { 423 NBIO_SR(BIOS_SCRATCH_3), 424 NBIO_SR(BIOS_SCRATCH_6) 425 }; 426 427 #define clk_src_regs(index, pllid)\ 428 [index] = {\ 429 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\ 430 } 431 432 static const struct dce110_clk_src_regs clk_src_regs[] = { 433 clk_src_regs(0, A), 434 clk_src_regs(1, B), 435 clk_src_regs(2, C), 436 clk_src_regs(3, D), 437 clk_src_regs(4, E), 438 clk_src_regs(5, F) 439 }; 440 441 static const struct dce110_clk_src_shift cs_shift = { 442 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 443 }; 444 445 static const struct dce110_clk_src_mask cs_mask = { 446 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 447 }; 448 449 static const struct dce_dmcu_registers dmcu_regs = { 450 DMCU_DCN10_REG_LIST() 451 }; 452 453 static const struct dce_dmcu_shift dmcu_shift = { 454 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 455 }; 456 457 static const struct dce_dmcu_mask dmcu_mask = { 458 DMCU_MASK_SH_LIST_DCN10(_MASK) 459 }; 460 461 static const struct dce_abm_registers abm_regs = { 462 ABM_DCN20_REG_LIST() 463 }; 464 465 static const struct dce_abm_shift abm_shift = { 466 ABM_MASK_SH_LIST_DCN20(__SHIFT) 467 }; 468 469 static const struct dce_abm_mask abm_mask = { 470 ABM_MASK_SH_LIST_DCN20(_MASK) 471 }; 472 473 #define audio_regs(id)\ 474 [id] = {\ 475 AUD_COMMON_REG_LIST(id)\ 476 } 477 478 static const struct dce_audio_registers audio_regs[] = { 479 audio_regs(0), 480 audio_regs(1), 481 audio_regs(2), 482 audio_regs(3), 483 audio_regs(4), 484 audio_regs(5), 485 audio_regs(6), 486 }; 487 488 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 489 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 490 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 491 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 492 493 static const struct dce_audio_shift audio_shift = { 494 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 495 }; 496 497 static const struct dce_audio_mask audio_mask = { 498 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 499 }; 500 501 #define stream_enc_regs(id)\ 502 [id] = {\ 503 SE_DCN2_REG_LIST(id)\ 504 } 505 506 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 507 stream_enc_regs(0), 508 stream_enc_regs(1), 509 stream_enc_regs(2), 510 stream_enc_regs(3), 511 stream_enc_regs(4), 512 stream_enc_regs(5), 513 }; 514 515 static const struct dcn10_stream_encoder_shift se_shift = { 516 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) 517 }; 518 519 static const struct dcn10_stream_encoder_mask se_mask = { 520 SE_COMMON_MASK_SH_LIST_DCN20(_MASK) 521 }; 522 523 524 #define aux_regs(id)\ 525 [id] = {\ 526 DCN2_AUX_REG_LIST(id)\ 527 } 528 529 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 530 aux_regs(0), 531 aux_regs(1), 532 aux_regs(2), 533 aux_regs(3), 534 aux_regs(4), 535 aux_regs(5) 536 }; 537 538 #define hpd_regs(id)\ 539 [id] = {\ 540 HPD_REG_LIST(id)\ 541 } 542 543 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 544 hpd_regs(0), 545 hpd_regs(1), 546 hpd_regs(2), 547 hpd_regs(3), 548 hpd_regs(4), 549 hpd_regs(5) 550 }; 551 552 #define link_regs(id, phyid)\ 553 [id] = {\ 554 LE_DCN10_REG_LIST(id), \ 555 UNIPHY_DCN2_REG_LIST(phyid), \ 556 DPCS_DCN2_REG_LIST(id), \ 557 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 558 } 559 560 static const struct dcn10_link_enc_registers link_enc_regs[] = { 561 link_regs(0, A), 562 link_regs(1, B), 563 link_regs(2, C), 564 link_regs(3, D), 565 link_regs(4, E), 566 link_regs(5, F) 567 }; 568 569 static const struct dcn10_link_enc_shift le_shift = { 570 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\ 571 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 572 }; 573 574 static const struct dcn10_link_enc_mask le_mask = { 575 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\ 576 DPCS_DCN2_MASK_SH_LIST(_MASK) 577 }; 578 579 #define ipp_regs(id)\ 580 [id] = {\ 581 IPP_REG_LIST_DCN20(id),\ 582 } 583 584 static const struct dcn10_ipp_registers ipp_regs[] = { 585 ipp_regs(0), 586 ipp_regs(1), 587 ipp_regs(2), 588 ipp_regs(3), 589 ipp_regs(4), 590 ipp_regs(5), 591 }; 592 593 static const struct dcn10_ipp_shift ipp_shift = { 594 IPP_MASK_SH_LIST_DCN20(__SHIFT) 595 }; 596 597 static const struct dcn10_ipp_mask ipp_mask = { 598 IPP_MASK_SH_LIST_DCN20(_MASK), 599 }; 600 601 #define opp_regs(id)\ 602 [id] = {\ 603 OPP_REG_LIST_DCN20(id),\ 604 } 605 606 static const struct dcn20_opp_registers opp_regs[] = { 607 opp_regs(0), 608 opp_regs(1), 609 opp_regs(2), 610 opp_regs(3), 611 opp_regs(4), 612 opp_regs(5), 613 }; 614 615 static const struct dcn20_opp_shift opp_shift = { 616 OPP_MASK_SH_LIST_DCN20(__SHIFT) 617 }; 618 619 static const struct dcn20_opp_mask opp_mask = { 620 OPP_MASK_SH_LIST_DCN20(_MASK) 621 }; 622 623 #define aux_engine_regs(id)\ 624 [id] = {\ 625 AUX_COMMON_REG_LIST0(id), \ 626 .AUXN_IMPCAL = 0, \ 627 .AUXP_IMPCAL = 0, \ 628 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 629 } 630 631 static const struct dce110_aux_registers aux_engine_regs[] = { 632 aux_engine_regs(0), 633 aux_engine_regs(1), 634 aux_engine_regs(2), 635 aux_engine_regs(3), 636 aux_engine_regs(4), 637 aux_engine_regs(5) 638 }; 639 640 #define tf_regs(id)\ 641 [id] = {\ 642 TF_REG_LIST_DCN20(id),\ 643 TF_REG_LIST_DCN20_COMMON_APPEND(id),\ 644 } 645 646 static const struct dcn2_dpp_registers tf_regs[] = { 647 tf_regs(0), 648 tf_regs(1), 649 tf_regs(2), 650 tf_regs(3), 651 tf_regs(4), 652 tf_regs(5), 653 }; 654 655 static const struct dcn2_dpp_shift tf_shift = { 656 TF_REG_LIST_SH_MASK_DCN20(__SHIFT), 657 TF_DEBUG_REG_LIST_SH_DCN20 658 }; 659 660 static const struct dcn2_dpp_mask tf_mask = { 661 TF_REG_LIST_SH_MASK_DCN20(_MASK), 662 TF_DEBUG_REG_LIST_MASK_DCN20 663 }; 664 665 #define dwbc_regs_dcn2(id)\ 666 [id] = {\ 667 DWBC_COMMON_REG_LIST_DCN2_0(id),\ 668 } 669 670 static const struct dcn20_dwbc_registers dwbc20_regs[] = { 671 dwbc_regs_dcn2(0), 672 }; 673 674 static const struct dcn20_dwbc_shift dwbc20_shift = { 675 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 676 }; 677 678 static const struct dcn20_dwbc_mask dwbc20_mask = { 679 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 680 }; 681 682 #define mcif_wb_regs_dcn2(id)\ 683 [id] = {\ 684 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\ 685 } 686 687 static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = { 688 mcif_wb_regs_dcn2(0), 689 }; 690 691 static const struct dcn20_mmhubbub_shift mcif_wb20_shift = { 692 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 693 }; 694 695 static const struct dcn20_mmhubbub_mask mcif_wb20_mask = { 696 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 697 }; 698 699 static const struct dcn20_mpc_registers mpc_regs = { 700 MPC_REG_LIST_DCN2_0(0), 701 MPC_REG_LIST_DCN2_0(1), 702 MPC_REG_LIST_DCN2_0(2), 703 MPC_REG_LIST_DCN2_0(3), 704 MPC_REG_LIST_DCN2_0(4), 705 MPC_REG_LIST_DCN2_0(5), 706 MPC_OUT_MUX_REG_LIST_DCN2_0(0), 707 MPC_OUT_MUX_REG_LIST_DCN2_0(1), 708 MPC_OUT_MUX_REG_LIST_DCN2_0(2), 709 MPC_OUT_MUX_REG_LIST_DCN2_0(3), 710 MPC_OUT_MUX_REG_LIST_DCN2_0(4), 711 MPC_OUT_MUX_REG_LIST_DCN2_0(5), 712 MPC_DBG_REG_LIST_DCN2_0() 713 }; 714 715 static const struct dcn20_mpc_shift mpc_shift = { 716 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT), 717 MPC_DEBUG_REG_LIST_SH_DCN20 718 }; 719 720 static const struct dcn20_mpc_mask mpc_mask = { 721 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK), 722 MPC_DEBUG_REG_LIST_MASK_DCN20 723 }; 724 725 #define tg_regs(id)\ 726 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)} 727 728 729 static const struct dcn_optc_registers tg_regs[] = { 730 tg_regs(0), 731 tg_regs(1), 732 tg_regs(2), 733 tg_regs(3), 734 tg_regs(4), 735 tg_regs(5) 736 }; 737 738 static const struct dcn_optc_shift tg_shift = { 739 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 740 }; 741 742 static const struct dcn_optc_mask tg_mask = { 743 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 744 }; 745 746 #define hubp_regs(id)\ 747 [id] = {\ 748 HUBP_REG_LIST_DCN20(id)\ 749 } 750 751 static const struct dcn_hubp2_registers hubp_regs[] = { 752 hubp_regs(0), 753 hubp_regs(1), 754 hubp_regs(2), 755 hubp_regs(3), 756 hubp_regs(4), 757 hubp_regs(5) 758 }; 759 760 static const struct dcn_hubp2_shift hubp_shift = { 761 HUBP_MASK_SH_LIST_DCN20(__SHIFT) 762 }; 763 764 static const struct dcn_hubp2_mask hubp_mask = { 765 HUBP_MASK_SH_LIST_DCN20(_MASK) 766 }; 767 768 static const struct dcn_hubbub_registers hubbub_reg = { 769 HUBBUB_REG_LIST_DCN20(0) 770 }; 771 772 static const struct dcn_hubbub_shift hubbub_shift = { 773 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT) 774 }; 775 776 static const struct dcn_hubbub_mask hubbub_mask = { 777 HUBBUB_MASK_SH_LIST_DCN20(_MASK) 778 }; 779 780 #define vmid_regs(id)\ 781 [id] = {\ 782 DCN20_VMID_REG_LIST(id)\ 783 } 784 785 static const struct dcn_vmid_registers vmid_regs[] = { 786 vmid_regs(0), 787 vmid_regs(1), 788 vmid_regs(2), 789 vmid_regs(3), 790 vmid_regs(4), 791 vmid_regs(5), 792 vmid_regs(6), 793 vmid_regs(7), 794 vmid_regs(8), 795 vmid_regs(9), 796 vmid_regs(10), 797 vmid_regs(11), 798 vmid_regs(12), 799 vmid_regs(13), 800 vmid_regs(14), 801 vmid_regs(15) 802 }; 803 804 static const struct dcn20_vmid_shift vmid_shifts = { 805 DCN20_VMID_MASK_SH_LIST(__SHIFT) 806 }; 807 808 static const struct dcn20_vmid_mask vmid_masks = { 809 DCN20_VMID_MASK_SH_LIST(_MASK) 810 }; 811 812 static const struct dce110_aux_registers_shift aux_shift = { 813 DCN_AUX_MASK_SH_LIST(__SHIFT) 814 }; 815 816 static const struct dce110_aux_registers_mask aux_mask = { 817 DCN_AUX_MASK_SH_LIST(_MASK) 818 }; 819 820 static int map_transmitter_id_to_phy_instance( 821 enum transmitter transmitter) 822 { 823 switch (transmitter) { 824 case TRANSMITTER_UNIPHY_A: 825 return 0; 826 break; 827 case TRANSMITTER_UNIPHY_B: 828 return 1; 829 break; 830 case TRANSMITTER_UNIPHY_C: 831 return 2; 832 break; 833 case TRANSMITTER_UNIPHY_D: 834 return 3; 835 break; 836 case TRANSMITTER_UNIPHY_E: 837 return 4; 838 break; 839 case TRANSMITTER_UNIPHY_F: 840 return 5; 841 break; 842 default: 843 ASSERT(0); 844 return 0; 845 } 846 } 847 848 #define dsc_regsDCN20(id)\ 849 [id] = {\ 850 DSC_REG_LIST_DCN20(id)\ 851 } 852 853 static const struct dcn20_dsc_registers dsc_regs[] = { 854 dsc_regsDCN20(0), 855 dsc_regsDCN20(1), 856 dsc_regsDCN20(2), 857 dsc_regsDCN20(3), 858 dsc_regsDCN20(4), 859 dsc_regsDCN20(5) 860 }; 861 862 static const struct dcn20_dsc_shift dsc_shift = { 863 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 864 }; 865 866 static const struct dcn20_dsc_mask dsc_mask = { 867 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 868 }; 869 870 static const struct dccg_registers dccg_regs = { 871 DCCG_REG_LIST_DCN2() 872 }; 873 874 static const struct dccg_shift dccg_shift = { 875 DCCG_MASK_SH_LIST_DCN2(__SHIFT) 876 }; 877 878 static const struct dccg_mask dccg_mask = { 879 DCCG_MASK_SH_LIST_DCN2(_MASK) 880 }; 881 882 static const struct resource_caps res_cap_nv10 = { 883 .num_timing_generator = 6, 884 .num_opp = 6, 885 .num_video_plane = 6, 886 .num_audio = 7, 887 .num_stream_encoder = 6, 888 .num_pll = 6, 889 .num_dwb = 1, 890 .num_ddc = 6, 891 .num_vmid = 16, 892 .num_dsc = 6, 893 }; 894 895 static const struct dc_plane_cap plane_cap = { 896 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 897 .blends_with_above = true, 898 .blends_with_below = true, 899 .per_pixel_alpha = true, 900 901 .pixel_format_support = { 902 .argb8888 = true, 903 .nv12 = true, 904 .fp16 = true 905 }, 906 907 .max_upscale_factor = { 908 .argb8888 = 16000, 909 .nv12 = 16000, 910 .fp16 = 1 911 }, 912 913 .max_downscale_factor = { 914 .argb8888 = 250, 915 .nv12 = 250, 916 .fp16 = 1 917 } 918 }; 919 static const struct resource_caps res_cap_nv14 = { 920 .num_timing_generator = 5, 921 .num_opp = 5, 922 .num_video_plane = 5, 923 .num_audio = 6, 924 .num_stream_encoder = 5, 925 .num_pll = 5, 926 .num_dwb = 1, 927 .num_ddc = 5, 928 .num_vmid = 16, 929 .num_dsc = 5, 930 }; 931 932 static const struct dc_debug_options debug_defaults_drv = { 933 .disable_dmcu = true, 934 .force_abm_enable = false, 935 .timing_trace = false, 936 .clock_trace = true, 937 .disable_pplib_clock_request = true, 938 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 939 .force_single_disp_pipe_split = false, 940 .disable_dcc = DCC_ENABLE, 941 .vsr_support = true, 942 .performance_trace = false, 943 .max_downscale_src_width = 5120,/*upto 5K*/ 944 .disable_pplib_wm_range = false, 945 .scl_reset_length10 = true, 946 .sanity_checks = false, 947 .disable_tri_buf = true, 948 .underflow_assert_delay_us = 0xFFFFFFFF, 949 }; 950 951 static const struct dc_debug_options debug_defaults_diags = { 952 .disable_dmcu = true, 953 .force_abm_enable = false, 954 .timing_trace = true, 955 .clock_trace = true, 956 .disable_dpp_power_gate = true, 957 .disable_hubp_power_gate = true, 958 .disable_clock_gate = true, 959 .disable_pplib_clock_request = true, 960 .disable_pplib_wm_range = true, 961 .disable_stutter = true, 962 .scl_reset_length10 = true, 963 .underflow_assert_delay_us = 0xFFFFFFFF, 964 }; 965 966 void dcn20_dpp_destroy(struct dpp **dpp) 967 { 968 kfree(TO_DCN20_DPP(*dpp)); 969 *dpp = NULL; 970 } 971 972 struct dpp *dcn20_dpp_create( 973 struct dc_context *ctx, 974 uint32_t inst) 975 { 976 struct dcn20_dpp *dpp = 977 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL); 978 979 if (!dpp) 980 return NULL; 981 982 if (dpp2_construct(dpp, ctx, inst, 983 &tf_regs[inst], &tf_shift, &tf_mask)) 984 return &dpp->base; 985 986 BREAK_TO_DEBUGGER(); 987 kfree(dpp); 988 return NULL; 989 } 990 991 struct input_pixel_processor *dcn20_ipp_create( 992 struct dc_context *ctx, uint32_t inst) 993 { 994 struct dcn10_ipp *ipp = 995 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 996 997 if (!ipp) { 998 BREAK_TO_DEBUGGER(); 999 return NULL; 1000 } 1001 1002 dcn20_ipp_construct(ipp, ctx, inst, 1003 &ipp_regs[inst], &ipp_shift, &ipp_mask); 1004 return &ipp->base; 1005 } 1006 1007 1008 struct output_pixel_processor *dcn20_opp_create( 1009 struct dc_context *ctx, uint32_t inst) 1010 { 1011 struct dcn20_opp *opp = 1012 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1013 1014 if (!opp) { 1015 BREAK_TO_DEBUGGER(); 1016 return NULL; 1017 } 1018 1019 dcn20_opp_construct(opp, ctx, inst, 1020 &opp_regs[inst], &opp_shift, &opp_mask); 1021 return &opp->base; 1022 } 1023 1024 struct dce_aux *dcn20_aux_engine_create( 1025 struct dc_context *ctx, 1026 uint32_t inst) 1027 { 1028 struct aux_engine_dce110 *aux_engine = 1029 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 1030 1031 if (!aux_engine) 1032 return NULL; 1033 1034 dce110_aux_engine_construct(aux_engine, ctx, inst, 1035 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1036 &aux_engine_regs[inst], 1037 &aux_mask, 1038 &aux_shift, 1039 ctx->dc->caps.extended_aux_timeout_support); 1040 1041 return &aux_engine->base; 1042 } 1043 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 1044 1045 static const struct dce_i2c_registers i2c_hw_regs[] = { 1046 i2c_inst_regs(1), 1047 i2c_inst_regs(2), 1048 i2c_inst_regs(3), 1049 i2c_inst_regs(4), 1050 i2c_inst_regs(5), 1051 i2c_inst_regs(6), 1052 }; 1053 1054 static const struct dce_i2c_shift i2c_shifts = { 1055 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 1056 }; 1057 1058 static const struct dce_i2c_mask i2c_masks = { 1059 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 1060 }; 1061 1062 struct dce_i2c_hw *dcn20_i2c_hw_create( 1063 struct dc_context *ctx, 1064 uint32_t inst) 1065 { 1066 struct dce_i2c_hw *dce_i2c_hw = 1067 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1068 1069 if (!dce_i2c_hw) 1070 return NULL; 1071 1072 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1073 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1074 1075 return dce_i2c_hw; 1076 } 1077 struct mpc *dcn20_mpc_create(struct dc_context *ctx) 1078 { 1079 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), 1080 GFP_KERNEL); 1081 1082 if (!mpc20) 1083 return NULL; 1084 1085 dcn20_mpc_construct(mpc20, ctx, 1086 &mpc_regs, 1087 &mpc_shift, 1088 &mpc_mask, 1089 6); 1090 1091 return &mpc20->base; 1092 } 1093 1094 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx) 1095 { 1096 int i; 1097 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), 1098 GFP_KERNEL); 1099 1100 if (!hubbub) 1101 return NULL; 1102 1103 hubbub2_construct(hubbub, ctx, 1104 &hubbub_reg, 1105 &hubbub_shift, 1106 &hubbub_mask); 1107 1108 for (i = 0; i < res_cap_nv10.num_vmid; i++) { 1109 struct dcn20_vmid *vmid = &hubbub->vmid[i]; 1110 1111 vmid->ctx = ctx; 1112 1113 vmid->regs = &vmid_regs[i]; 1114 vmid->shifts = &vmid_shifts; 1115 vmid->masks = &vmid_masks; 1116 } 1117 1118 return &hubbub->base; 1119 } 1120 1121 struct timing_generator *dcn20_timing_generator_create( 1122 struct dc_context *ctx, 1123 uint32_t instance) 1124 { 1125 struct optc *tgn10 = 1126 kzalloc(sizeof(struct optc), GFP_KERNEL); 1127 1128 if (!tgn10) 1129 return NULL; 1130 1131 tgn10->base.inst = instance; 1132 tgn10->base.ctx = ctx; 1133 1134 tgn10->tg_regs = &tg_regs[instance]; 1135 tgn10->tg_shift = &tg_shift; 1136 tgn10->tg_mask = &tg_mask; 1137 1138 dcn20_timing_generator_init(tgn10); 1139 1140 return &tgn10->base; 1141 } 1142 1143 static const struct encoder_feature_support link_enc_feature = { 1144 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1145 .max_hdmi_pixel_clock = 600000, 1146 .hdmi_ycbcr420_supported = true, 1147 .dp_ycbcr420_supported = true, 1148 .fec_supported = true, 1149 .flags.bits.IS_HBR2_CAPABLE = true, 1150 .flags.bits.IS_HBR3_CAPABLE = true, 1151 .flags.bits.IS_TPS3_CAPABLE = true, 1152 .flags.bits.IS_TPS4_CAPABLE = true 1153 }; 1154 1155 struct link_encoder *dcn20_link_encoder_create( 1156 const struct encoder_init_data *enc_init_data) 1157 { 1158 struct dcn20_link_encoder *enc20 = 1159 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1160 int link_regs_id; 1161 1162 if (!enc20) 1163 return NULL; 1164 1165 link_regs_id = 1166 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 1167 1168 dcn20_link_encoder_construct(enc20, 1169 enc_init_data, 1170 &link_enc_feature, 1171 &link_enc_regs[link_regs_id], 1172 &link_enc_aux_regs[enc_init_data->channel - 1], 1173 &link_enc_hpd_regs[enc_init_data->hpd_source], 1174 &le_shift, 1175 &le_mask); 1176 1177 return &enc20->enc10.base; 1178 } 1179 1180 struct clock_source *dcn20_clock_source_create( 1181 struct dc_context *ctx, 1182 struct dc_bios *bios, 1183 enum clock_source_id id, 1184 const struct dce110_clk_src_regs *regs, 1185 bool dp_clk_src) 1186 { 1187 struct dce110_clk_src *clk_src = 1188 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1189 1190 if (!clk_src) 1191 return NULL; 1192 1193 if (dcn20_clk_src_construct(clk_src, ctx, bios, id, 1194 regs, &cs_shift, &cs_mask)) { 1195 clk_src->base.dp_clk_src = dp_clk_src; 1196 return &clk_src->base; 1197 } 1198 1199 kfree(clk_src); 1200 BREAK_TO_DEBUGGER(); 1201 return NULL; 1202 } 1203 1204 static void read_dce_straps( 1205 struct dc_context *ctx, 1206 struct resource_straps *straps) 1207 { 1208 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1209 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1210 } 1211 1212 static struct audio *dcn20_create_audio( 1213 struct dc_context *ctx, unsigned int inst) 1214 { 1215 return dce_audio_create(ctx, inst, 1216 &audio_regs[inst], &audio_shift, &audio_mask); 1217 } 1218 1219 struct stream_encoder *dcn20_stream_encoder_create( 1220 enum engine_id eng_id, 1221 struct dc_context *ctx) 1222 { 1223 struct dcn10_stream_encoder *enc1 = 1224 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1225 1226 if (!enc1) 1227 return NULL; 1228 1229 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) { 1230 if (eng_id >= ENGINE_ID_DIGD) 1231 eng_id++; 1232 } 1233 1234 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1235 &stream_enc_regs[eng_id], 1236 &se_shift, &se_mask); 1237 1238 return &enc1->base; 1239 } 1240 1241 static const struct dce_hwseq_registers hwseq_reg = { 1242 HWSEQ_DCN2_REG_LIST() 1243 }; 1244 1245 static const struct dce_hwseq_shift hwseq_shift = { 1246 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT) 1247 }; 1248 1249 static const struct dce_hwseq_mask hwseq_mask = { 1250 HWSEQ_DCN2_MASK_SH_LIST(_MASK) 1251 }; 1252 1253 struct dce_hwseq *dcn20_hwseq_create( 1254 struct dc_context *ctx) 1255 { 1256 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1257 1258 if (hws) { 1259 hws->ctx = ctx; 1260 hws->regs = &hwseq_reg; 1261 hws->shifts = &hwseq_shift; 1262 hws->masks = &hwseq_mask; 1263 } 1264 return hws; 1265 } 1266 1267 static const struct resource_create_funcs res_create_funcs = { 1268 .read_dce_straps = read_dce_straps, 1269 .create_audio = dcn20_create_audio, 1270 .create_stream_encoder = dcn20_stream_encoder_create, 1271 .create_hwseq = dcn20_hwseq_create, 1272 }; 1273 1274 static const struct resource_create_funcs res_create_maximus_funcs = { 1275 .read_dce_straps = NULL, 1276 .create_audio = NULL, 1277 .create_stream_encoder = NULL, 1278 .create_hwseq = dcn20_hwseq_create, 1279 }; 1280 1281 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu); 1282 1283 void dcn20_clock_source_destroy(struct clock_source **clk_src) 1284 { 1285 kfree(TO_DCE110_CLK_SRC(*clk_src)); 1286 *clk_src = NULL; 1287 } 1288 1289 1290 struct display_stream_compressor *dcn20_dsc_create( 1291 struct dc_context *ctx, uint32_t inst) 1292 { 1293 struct dcn20_dsc *dsc = 1294 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1295 1296 if (!dsc) { 1297 BREAK_TO_DEBUGGER(); 1298 return NULL; 1299 } 1300 1301 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1302 return &dsc->base; 1303 } 1304 1305 void dcn20_dsc_destroy(struct display_stream_compressor **dsc) 1306 { 1307 kfree(container_of(*dsc, struct dcn20_dsc, base)); 1308 *dsc = NULL; 1309 } 1310 1311 1312 static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) 1313 { 1314 unsigned int i; 1315 1316 for (i = 0; i < pool->base.stream_enc_count; i++) { 1317 if (pool->base.stream_enc[i] != NULL) { 1318 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1319 pool->base.stream_enc[i] = NULL; 1320 } 1321 } 1322 1323 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1324 if (pool->base.dscs[i] != NULL) 1325 dcn20_dsc_destroy(&pool->base.dscs[i]); 1326 } 1327 1328 if (pool->base.mpc != NULL) { 1329 kfree(TO_DCN20_MPC(pool->base.mpc)); 1330 pool->base.mpc = NULL; 1331 } 1332 if (pool->base.hubbub != NULL) { 1333 kfree(pool->base.hubbub); 1334 pool->base.hubbub = NULL; 1335 } 1336 for (i = 0; i < pool->base.pipe_count; i++) { 1337 if (pool->base.dpps[i] != NULL) 1338 dcn20_dpp_destroy(&pool->base.dpps[i]); 1339 1340 if (pool->base.ipps[i] != NULL) 1341 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1342 1343 if (pool->base.hubps[i] != NULL) { 1344 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1345 pool->base.hubps[i] = NULL; 1346 } 1347 1348 if (pool->base.irqs != NULL) { 1349 dal_irq_service_destroy(&pool->base.irqs); 1350 } 1351 } 1352 1353 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1354 if (pool->base.engines[i] != NULL) 1355 dce110_engine_destroy(&pool->base.engines[i]); 1356 if (pool->base.hw_i2cs[i] != NULL) { 1357 kfree(pool->base.hw_i2cs[i]); 1358 pool->base.hw_i2cs[i] = NULL; 1359 } 1360 if (pool->base.sw_i2cs[i] != NULL) { 1361 kfree(pool->base.sw_i2cs[i]); 1362 pool->base.sw_i2cs[i] = NULL; 1363 } 1364 } 1365 1366 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1367 if (pool->base.opps[i] != NULL) 1368 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1369 } 1370 1371 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1372 if (pool->base.timing_generators[i] != NULL) { 1373 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1374 pool->base.timing_generators[i] = NULL; 1375 } 1376 } 1377 1378 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1379 if (pool->base.dwbc[i] != NULL) { 1380 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); 1381 pool->base.dwbc[i] = NULL; 1382 } 1383 if (pool->base.mcif_wb[i] != NULL) { 1384 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); 1385 pool->base.mcif_wb[i] = NULL; 1386 } 1387 } 1388 1389 for (i = 0; i < pool->base.audio_count; i++) { 1390 if (pool->base.audios[i]) 1391 dce_aud_destroy(&pool->base.audios[i]); 1392 } 1393 1394 for (i = 0; i < pool->base.clk_src_count; i++) { 1395 if (pool->base.clock_sources[i] != NULL) { 1396 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1397 pool->base.clock_sources[i] = NULL; 1398 } 1399 } 1400 1401 if (pool->base.dp_clock_source != NULL) { 1402 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1403 pool->base.dp_clock_source = NULL; 1404 } 1405 1406 1407 if (pool->base.abm != NULL) 1408 dce_abm_destroy(&pool->base.abm); 1409 1410 if (pool->base.dmcu != NULL) 1411 dce_dmcu_destroy(&pool->base.dmcu); 1412 1413 if (pool->base.dccg != NULL) 1414 dcn_dccg_destroy(&pool->base.dccg); 1415 1416 if (pool->base.pp_smu != NULL) 1417 dcn20_pp_smu_destroy(&pool->base.pp_smu); 1418 1419 if (pool->base.oem_device != NULL) 1420 dal_ddc_service_destroy(&pool->base.oem_device); 1421 } 1422 1423 struct hubp *dcn20_hubp_create( 1424 struct dc_context *ctx, 1425 uint32_t inst) 1426 { 1427 struct dcn20_hubp *hubp2 = 1428 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1429 1430 if (!hubp2) 1431 return NULL; 1432 1433 if (hubp2_construct(hubp2, ctx, inst, 1434 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1435 return &hubp2->base; 1436 1437 BREAK_TO_DEBUGGER(); 1438 kfree(hubp2); 1439 return NULL; 1440 } 1441 1442 static void get_pixel_clock_parameters( 1443 struct pipe_ctx *pipe_ctx, 1444 struct pixel_clk_params *pixel_clk_params) 1445 { 1446 const struct dc_stream_state *stream = pipe_ctx->stream; 1447 struct pipe_ctx *odm_pipe; 1448 int opp_cnt = 1; 1449 1450 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1451 opp_cnt++; 1452 1453 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 1454 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 1455 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 1456 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 1457 /* TODO: un-hardcode*/ 1458 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 1459 LINK_RATE_REF_FREQ_IN_KHZ; 1460 pixel_clk_params->flags.ENABLE_SS = 0; 1461 pixel_clk_params->color_depth = 1462 stream->timing.display_color_depth; 1463 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 1464 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 1465 1466 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1467 pixel_clk_params->color_depth = COLOR_DEPTH_888; 1468 1469 if (opp_cnt == 4) 1470 pixel_clk_params->requested_pix_clk_100hz /= 4; 1471 else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2) 1472 pixel_clk_params->requested_pix_clk_100hz /= 2; 1473 1474 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1475 pixel_clk_params->requested_pix_clk_100hz *= 2; 1476 1477 } 1478 1479 static void build_clamping_params(struct dc_stream_state *stream) 1480 { 1481 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1482 stream->clamping.c_depth = stream->timing.display_color_depth; 1483 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1484 } 1485 1486 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1487 { 1488 1489 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1490 1491 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1492 pipe_ctx->clock_source, 1493 &pipe_ctx->stream_res.pix_clk_params, 1494 &pipe_ctx->pll_settings); 1495 1496 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1497 1498 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1499 &pipe_ctx->stream->bit_depth_params); 1500 build_clamping_params(pipe_ctx->stream); 1501 1502 return DC_OK; 1503 } 1504 1505 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream) 1506 { 1507 enum dc_status status = DC_OK; 1508 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1509 1510 /*TODO Seems unneeded anymore */ 1511 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) { 1512 if (stream != NULL && old_context->streams[i] != NULL) { 1513 todo: shouldn't have to copy missing parameter here 1514 resource_build_bit_depth_reduction_params(stream, 1515 &stream->bit_depth_params); 1516 stream->clamping.pixel_encoding = 1517 stream->timing.pixel_encoding; 1518 1519 resource_build_bit_depth_reduction_params(stream, 1520 &stream->bit_depth_params); 1521 build_clamping_params(stream); 1522 1523 continue; 1524 } 1525 } 1526 */ 1527 1528 if (!pipe_ctx) 1529 return DC_ERROR_UNEXPECTED; 1530 1531 1532 status = build_pipe_hw_param(pipe_ctx); 1533 1534 return status; 1535 } 1536 1537 1538 static void acquire_dsc(struct resource_context *res_ctx, 1539 const struct resource_pool *pool, 1540 struct display_stream_compressor **dsc, 1541 int pipe_idx) 1542 { 1543 int i; 1544 1545 ASSERT(*dsc == NULL); 1546 *dsc = NULL; 1547 1548 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { 1549 *dsc = pool->dscs[pipe_idx]; 1550 res_ctx->is_dsc_acquired[pipe_idx] = true; 1551 return; 1552 } 1553 1554 /* Find first free DSC */ 1555 for (i = 0; i < pool->res_cap->num_dsc; i++) 1556 if (!res_ctx->is_dsc_acquired[i]) { 1557 *dsc = pool->dscs[i]; 1558 res_ctx->is_dsc_acquired[i] = true; 1559 break; 1560 } 1561 } 1562 1563 static void release_dsc(struct resource_context *res_ctx, 1564 const struct resource_pool *pool, 1565 struct display_stream_compressor **dsc) 1566 { 1567 int i; 1568 1569 for (i = 0; i < pool->res_cap->num_dsc; i++) 1570 if (pool->dscs[i] == *dsc) { 1571 res_ctx->is_dsc_acquired[i] = false; 1572 *dsc = NULL; 1573 break; 1574 } 1575 } 1576 1577 1578 1579 enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, 1580 struct dc_state *dc_ctx, 1581 struct dc_stream_state *dc_stream) 1582 { 1583 enum dc_status result = DC_OK; 1584 int i; 1585 const struct resource_pool *pool = dc->res_pool; 1586 1587 /* Get a DSC if required and available */ 1588 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1589 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i]; 1590 1591 if (pipe_ctx->stream != dc_stream) 1592 continue; 1593 1594 if (pipe_ctx->stream_res.dsc) 1595 continue; 1596 1597 acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc, i); 1598 1599 /* The number of DSCs can be less than the number of pipes */ 1600 if (!pipe_ctx->stream_res.dsc) { 1601 result = DC_NO_DSC_RESOURCE; 1602 } 1603 1604 break; 1605 } 1606 1607 return result; 1608 } 1609 1610 1611 static enum dc_status remove_dsc_from_stream_resource(struct dc *dc, 1612 struct dc_state *new_ctx, 1613 struct dc_stream_state *dc_stream) 1614 { 1615 struct pipe_ctx *pipe_ctx = NULL; 1616 int i; 1617 1618 for (i = 0; i < MAX_PIPES; i++) { 1619 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { 1620 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; 1621 1622 if (pipe_ctx->stream_res.dsc) 1623 release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); 1624 } 1625 } 1626 1627 if (!pipe_ctx) 1628 return DC_ERROR_UNEXPECTED; 1629 else 1630 return DC_OK; 1631 } 1632 1633 1634 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) 1635 { 1636 enum dc_status result = DC_ERROR_UNEXPECTED; 1637 1638 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1639 1640 if (result == DC_OK) 1641 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1642 1643 /* Get a DSC if required and available */ 1644 if (result == DC_OK && dc_stream->timing.flags.DSC) 1645 result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream); 1646 1647 if (result == DC_OK) 1648 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream); 1649 1650 return result; 1651 } 1652 1653 1654 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) 1655 { 1656 enum dc_status result = DC_OK; 1657 1658 result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream); 1659 1660 return result; 1661 } 1662 1663 1664 static void swizzle_to_dml_params( 1665 enum swizzle_mode_values swizzle, 1666 unsigned int *sw_mode) 1667 { 1668 switch (swizzle) { 1669 case DC_SW_LINEAR: 1670 *sw_mode = dm_sw_linear; 1671 break; 1672 case DC_SW_4KB_S: 1673 *sw_mode = dm_sw_4kb_s; 1674 break; 1675 case DC_SW_4KB_S_X: 1676 *sw_mode = dm_sw_4kb_s_x; 1677 break; 1678 case DC_SW_4KB_D: 1679 *sw_mode = dm_sw_4kb_d; 1680 break; 1681 case DC_SW_4KB_D_X: 1682 *sw_mode = dm_sw_4kb_d_x; 1683 break; 1684 case DC_SW_64KB_S: 1685 *sw_mode = dm_sw_64kb_s; 1686 break; 1687 case DC_SW_64KB_S_X: 1688 *sw_mode = dm_sw_64kb_s_x; 1689 break; 1690 case DC_SW_64KB_S_T: 1691 *sw_mode = dm_sw_64kb_s_t; 1692 break; 1693 case DC_SW_64KB_D: 1694 *sw_mode = dm_sw_64kb_d; 1695 break; 1696 case DC_SW_64KB_D_X: 1697 *sw_mode = dm_sw_64kb_d_x; 1698 break; 1699 case DC_SW_64KB_D_T: 1700 *sw_mode = dm_sw_64kb_d_t; 1701 break; 1702 case DC_SW_64KB_R_X: 1703 *sw_mode = dm_sw_64kb_r_x; 1704 break; 1705 case DC_SW_VAR_S: 1706 *sw_mode = dm_sw_var_s; 1707 break; 1708 case DC_SW_VAR_S_X: 1709 *sw_mode = dm_sw_var_s_x; 1710 break; 1711 case DC_SW_VAR_D: 1712 *sw_mode = dm_sw_var_d; 1713 break; 1714 case DC_SW_VAR_D_X: 1715 *sw_mode = dm_sw_var_d_x; 1716 break; 1717 1718 default: 1719 ASSERT(0); /* Not supported */ 1720 break; 1721 } 1722 } 1723 1724 bool dcn20_split_stream_for_odm( 1725 struct resource_context *res_ctx, 1726 const struct resource_pool *pool, 1727 struct pipe_ctx *prev_odm_pipe, 1728 struct pipe_ctx *next_odm_pipe) 1729 { 1730 int pipe_idx = next_odm_pipe->pipe_idx; 1731 1732 *next_odm_pipe = *prev_odm_pipe; 1733 1734 next_odm_pipe->pipe_idx = pipe_idx; 1735 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; 1736 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; 1737 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; 1738 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; 1739 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; 1740 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; 1741 next_odm_pipe->stream_res.dsc = NULL; 1742 if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) { 1743 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe; 1744 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe; 1745 } 1746 prev_odm_pipe->next_odm_pipe = next_odm_pipe; 1747 next_odm_pipe->prev_odm_pipe = prev_odm_pipe; 1748 ASSERT(next_odm_pipe->top_pipe == NULL); 1749 1750 if (prev_odm_pipe->plane_state) { 1751 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; 1752 int new_width; 1753 1754 /* HACTIVE halved for odm combine */ 1755 sd->h_active /= 2; 1756 /* Calculate new vp and recout for left pipe */ 1757 /* Need at least 16 pixels width per side */ 1758 if (sd->recout.x + 16 >= sd->h_active) 1759 return false; 1760 new_width = sd->h_active - sd->recout.x; 1761 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1762 sd->ratios.horz, sd->recout.width - new_width)); 1763 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1764 sd->ratios.horz_c, sd->recout.width - new_width)); 1765 sd->recout.width = new_width; 1766 1767 /* Calculate new vp and recout for right pipe */ 1768 sd = &next_odm_pipe->plane_res.scl_data; 1769 /* HACTIVE halved for odm combine */ 1770 sd->h_active /= 2; 1771 /* Need at least 16 pixels width per side */ 1772 if (new_width <= 16) 1773 return false; 1774 new_width = sd->recout.width + sd->recout.x - sd->h_active; 1775 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1776 sd->ratios.horz, sd->recout.width - new_width)); 1777 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1778 sd->ratios.horz_c, sd->recout.width - new_width)); 1779 sd->recout.width = new_width; 1780 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int( 1781 sd->ratios.horz, sd->h_active - sd->recout.x)); 1782 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int( 1783 sd->ratios.horz_c, sd->h_active - sd->recout.x)); 1784 sd->recout.x = 0; 1785 } 1786 next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; 1787 if (next_odm_pipe->stream->timing.flags.DSC == 1) { 1788 acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx); 1789 ASSERT(next_odm_pipe->stream_res.dsc); 1790 if (next_odm_pipe->stream_res.dsc == NULL) 1791 return false; 1792 } 1793 1794 return true; 1795 } 1796 1797 void dcn20_split_stream_for_mpc( 1798 struct resource_context *res_ctx, 1799 const struct resource_pool *pool, 1800 struct pipe_ctx *primary_pipe, 1801 struct pipe_ctx *secondary_pipe) 1802 { 1803 int pipe_idx = secondary_pipe->pipe_idx; 1804 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe; 1805 1806 *secondary_pipe = *primary_pipe; 1807 secondary_pipe->bottom_pipe = sec_bot_pipe; 1808 1809 secondary_pipe->pipe_idx = pipe_idx; 1810 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; 1811 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; 1812 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; 1813 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; 1814 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; 1815 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; 1816 secondary_pipe->stream_res.dsc = NULL; 1817 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { 1818 ASSERT(!secondary_pipe->bottom_pipe); 1819 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; 1820 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe; 1821 } 1822 primary_pipe->bottom_pipe = secondary_pipe; 1823 secondary_pipe->top_pipe = primary_pipe; 1824 1825 ASSERT(primary_pipe->plane_state); 1826 resource_build_scaling_params(primary_pipe); 1827 resource_build_scaling_params(secondary_pipe); 1828 } 1829 1830 void dcn20_populate_dml_writeback_from_context( 1831 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) 1832 { 1833 int pipe_cnt, i; 1834 1835 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1836 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; 1837 1838 if (!res_ctx->pipe_ctx[i].stream) 1839 continue; 1840 1841 /* Set writeback information */ 1842 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; 1843 pipes[pipe_cnt].dout.num_active_wb++; 1844 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; 1845 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; 1846 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; 1847 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; 1848 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1; 1849 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1; 1850 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c; 1851 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c; 1852 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0; 1853 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0; 1854 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) { 1855 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) 1856 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8; 1857 else 1858 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10; 1859 } else 1860 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32; 1861 1862 pipe_cnt++; 1863 } 1864 1865 } 1866 1867 int dcn20_populate_dml_pipes_from_context( 1868 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes) 1869 { 1870 int pipe_cnt, i; 1871 bool synchronized_vblank = true; 1872 struct resource_context *res_ctx = &context->res_ctx; 1873 1874 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) { 1875 if (!res_ctx->pipe_ctx[i].stream) 1876 continue; 1877 1878 if (pipe_cnt < 0) { 1879 pipe_cnt = i; 1880 continue; 1881 } 1882 if (dc->debug.disable_timing_sync || !resource_are_streams_timing_synchronizable( 1883 res_ctx->pipe_ctx[pipe_cnt].stream, 1884 res_ctx->pipe_ctx[i].stream)) { 1885 synchronized_vblank = false; 1886 break; 1887 } 1888 } 1889 1890 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1891 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing; 1892 unsigned int v_total; 1893 unsigned int front_porch; 1894 int output_bpc; 1895 1896 if (!res_ctx->pipe_ctx[i].stream) 1897 continue; 1898 1899 v_total = timing->v_total; 1900 front_porch = timing->v_front_porch; 1901 /* todo: 1902 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0; 1903 pipes[pipe_cnt].pipe.src.dcc = 0; 1904 pipes[pipe_cnt].pipe.src.vm = 0;*/ 1905 1906 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 1907 1908 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC; 1909 /* todo: rotation?*/ 1910 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; 1911 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) { 1912 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true; 1913 /* 1/2 vblank */ 1914 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active = 1915 (v_total - timing->v_addressable 1916 - timing->v_border_top - timing->v_border_bottom) / 2; 1917 /* 36 bytes dp, 32 hdmi */ 1918 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes = 1919 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32; 1920 } 1921 pipes[pipe_cnt].pipe.src.dcc = false; 1922 pipes[pipe_cnt].pipe.src.dcc_rate = 1; 1923 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank; 1924 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch; 1925 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start 1926 - timing->h_addressable 1927 - timing->h_border_left 1928 - timing->h_border_right; 1929 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch; 1930 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start 1931 - timing->v_addressable 1932 - timing->v_border_top 1933 - timing->v_border_bottom; 1934 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total; 1935 pipes[pipe_cnt].pipe.dest.vtotal = v_total; 1936 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable; 1937 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable; 1938 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE; 1939 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0; 1940 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1941 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2; 1942 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst; 1943 pipes[pipe_cnt].dout.dp_lanes = 4; 1944 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min; 1945 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max; 1946 switch (get_num_odm_splits(&res_ctx->pipe_ctx[i])) { 1947 case 1: 1948 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1; 1949 break; 1950 default: 1951 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled; 1952 } 1953 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; 1954 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state 1955 == res_ctx->pipe_ctx[i].plane_state) { 1956 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe; 1957 1958 while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state 1959 == res_ctx->pipe_ctx[i].plane_state) 1960 first_pipe = first_pipe->top_pipe; 1961 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx; 1962 } else if (res_ctx->pipe_ctx[i].prev_odm_pipe) { 1963 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe; 1964 1965 while (first_pipe->prev_odm_pipe) 1966 first_pipe = first_pipe->prev_odm_pipe; 1967 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx; 1968 } 1969 1970 switch (res_ctx->pipe_ctx[i].stream->signal) { 1971 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1972 case SIGNAL_TYPE_DISPLAY_PORT: 1973 pipes[pipe_cnt].dout.output_type = dm_dp; 1974 break; 1975 case SIGNAL_TYPE_EDP: 1976 pipes[pipe_cnt].dout.output_type = dm_edp; 1977 break; 1978 case SIGNAL_TYPE_HDMI_TYPE_A: 1979 case SIGNAL_TYPE_DVI_SINGLE_LINK: 1980 case SIGNAL_TYPE_DVI_DUAL_LINK: 1981 pipes[pipe_cnt].dout.output_type = dm_hdmi; 1982 break; 1983 default: 1984 /* In case there is no signal, set dp with 4 lanes to allow max config */ 1985 pipes[pipe_cnt].dout.output_type = dm_dp; 1986 pipes[pipe_cnt].dout.dp_lanes = 4; 1987 } 1988 1989 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) { 1990 case COLOR_DEPTH_666: 1991 output_bpc = 6; 1992 break; 1993 case COLOR_DEPTH_888: 1994 output_bpc = 8; 1995 break; 1996 case COLOR_DEPTH_101010: 1997 output_bpc = 10; 1998 break; 1999 case COLOR_DEPTH_121212: 2000 output_bpc = 12; 2001 break; 2002 case COLOR_DEPTH_141414: 2003 output_bpc = 14; 2004 break; 2005 case COLOR_DEPTH_161616: 2006 output_bpc = 16; 2007 break; 2008 case COLOR_DEPTH_999: 2009 output_bpc = 9; 2010 break; 2011 case COLOR_DEPTH_111111: 2012 output_bpc = 11; 2013 break; 2014 default: 2015 output_bpc = 8; 2016 break; 2017 } 2018 2019 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) { 2020 case PIXEL_ENCODING_RGB: 2021 case PIXEL_ENCODING_YCBCR444: 2022 pipes[pipe_cnt].dout.output_format = dm_444; 2023 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3; 2024 break; 2025 case PIXEL_ENCODING_YCBCR420: 2026 pipes[pipe_cnt].dout.output_format = dm_420; 2027 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2; 2028 break; 2029 case PIXEL_ENCODING_YCBCR422: 2030 if (true) /* todo */ 2031 pipes[pipe_cnt].dout.output_format = dm_s422; 2032 else 2033 pipes[pipe_cnt].dout.output_format = dm_n422; 2034 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2; 2035 break; 2036 default: 2037 pipes[pipe_cnt].dout.output_format = dm_444; 2038 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3; 2039 } 2040 2041 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC) 2042 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0; 2043 2044 /* todo: default max for now, until there is logic reflecting this in dc*/ 2045 pipes[pipe_cnt].dout.output_bpc = 12; 2046 /* 2047 * For graphic plane, cursor number is 1, nv12 is 0 2048 * bw calculations due to cursor on/off 2049 */ 2050 if (res_ctx->pipe_ctx[i].plane_state && 2051 res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 2052 pipes[pipe_cnt].pipe.src.num_cursors = 0; 2053 else 2054 pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors; 2055 2056 pipes[pipe_cnt].pipe.src.cur0_src_width = 256; 2057 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit; 2058 2059 if (!res_ctx->pipe_ctx[i].plane_state) { 2060 pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled; 2061 pipes[pipe_cnt].pipe.src.source_scan = dm_horz; 2062 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear; 2063 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile; 2064 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable; 2065 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920) 2066 pipes[pipe_cnt].pipe.src.viewport_width = 1920; 2067 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable; 2068 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080) 2069 pipes[pipe_cnt].pipe.src.viewport_height = 1080; 2070 pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height; 2071 pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width; 2072 pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height; 2073 pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width; 2074 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */ 2075 pipes[pipe_cnt].pipe.src.source_format = dm_444_32; 2076 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/ 2077 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/ 2078 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/ 2079 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/ 2080 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16; 2081 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0; 2082 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0; 2083 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/ 2084 pipes[pipe_cnt].pipe.scale_taps.htaps = 1; 2085 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1; 2086 pipes[pipe_cnt].pipe.dest.vtotal_min = v_total; 2087 pipes[pipe_cnt].pipe.dest.vtotal_max = v_total; 2088 2089 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) { 2090 pipes[pipe_cnt].pipe.src.viewport_width /= 2; 2091 pipes[pipe_cnt].pipe.dest.recout_width /= 2; 2092 } 2093 } else { 2094 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state; 2095 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data; 2096 2097 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate; 2098 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) 2099 || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) 2100 || pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled; 2101 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90 2102 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz; 2103 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y; 2104 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y; 2105 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width; 2106 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width; 2107 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height; 2108 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height; 2109 pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width; 2110 pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height; 2111 pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width; 2112 pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height; 2113 if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 2114 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch; 2115 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch; 2116 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; 2117 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c; 2118 } else { 2119 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch; 2120 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; 2121 } 2122 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable; 2123 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width; 2124 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height; 2125 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height; 2126 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width; 2127 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) 2128 pipes[pipe_cnt].pipe.dest.full_recout_width *= 2; 2129 else { 2130 struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe; 2131 2132 while (split_pipe && split_pipe->plane_state == pln) { 2133 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; 2134 split_pipe = split_pipe->bottom_pipe; 2135 } 2136 split_pipe = res_ctx->pipe_ctx[i].top_pipe; 2137 while (split_pipe && split_pipe->plane_state == pln) { 2138 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; 2139 split_pipe = split_pipe->top_pipe; 2140 } 2141 } 2142 2143 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16; 2144 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32); 2145 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32); 2146 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32); 2147 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32); 2148 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 2149 scl->ratios.vert.value != dc_fixpt_one.value 2150 || scl->ratios.horz.value != dc_fixpt_one.value 2151 || scl->ratios.vert_c.value != dc_fixpt_one.value 2152 || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/ 2153 || dc->debug.always_scale; /*support always scale*/ 2154 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps; 2155 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c; 2156 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps; 2157 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c; 2158 2159 pipes[pipe_cnt].pipe.src.macro_tile_size = 2160 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); 2161 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, 2162 &pipes[pipe_cnt].pipe.src.sw_mode); 2163 2164 switch (pln->format) { 2165 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 2166 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 2167 pipes[pipe_cnt].pipe.src.source_format = dm_420_8; 2168 break; 2169 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 2170 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 2171 pipes[pipe_cnt].pipe.src.source_format = dm_420_10; 2172 break; 2173 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 2174 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 2175 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2176 pipes[pipe_cnt].pipe.src.source_format = dm_444_64; 2177 break; 2178 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 2179 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 2180 pipes[pipe_cnt].pipe.src.source_format = dm_444_16; 2181 break; 2182 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 2183 pipes[pipe_cnt].pipe.src.source_format = dm_444_8; 2184 break; 2185 default: 2186 pipes[pipe_cnt].pipe.src.source_format = dm_444_32; 2187 break; 2188 } 2189 } 2190 2191 pipe_cnt++; 2192 } 2193 2194 /* populate writeback information */ 2195 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes); 2196 2197 return pipe_cnt; 2198 } 2199 2200 unsigned int dcn20_calc_max_scaled_time( 2201 unsigned int time_per_pixel, 2202 enum mmhubbub_wbif_mode mode, 2203 unsigned int urgent_watermark) 2204 { 2205 unsigned int time_per_byte = 0; 2206 unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */ 2207 unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */ 2208 unsigned int small_free_entry, max_free_entry; 2209 unsigned int buf_lh_capability; 2210 unsigned int max_scaled_time; 2211 2212 if (mode == PACKED_444) /* packed mode */ 2213 time_per_byte = time_per_pixel/4; 2214 else if (mode == PLANAR_420_8BPC) 2215 time_per_byte = time_per_pixel; 2216 else if (mode == PLANAR_420_10BPC) /* p010 */ 2217 time_per_byte = time_per_pixel * 819/1024; 2218 2219 if (time_per_byte == 0) 2220 time_per_byte = 1; 2221 2222 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry; 2223 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry; 2224 buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */ 2225 max_scaled_time = buf_lh_capability - urgent_watermark; 2226 return max_scaled_time; 2227 } 2228 2229 void dcn20_set_mcif_arb_params( 2230 struct dc *dc, 2231 struct dc_state *context, 2232 display_e2e_pipe_params_st *pipes, 2233 int pipe_cnt) 2234 { 2235 enum mmhubbub_wbif_mode wbif_mode; 2236 struct mcif_arb_params *wb_arb_params; 2237 int i, j, k, dwb_pipe; 2238 2239 /* Writeback MCIF_WB arbitration parameters */ 2240 dwb_pipe = 0; 2241 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2242 2243 if (!context->res_ctx.pipe_ctx[i].stream) 2244 continue; 2245 2246 for (j = 0; j < MAX_DWB_PIPES; j++) { 2247 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false) 2248 continue; 2249 2250 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params; 2251 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe]; 2252 2253 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) { 2254 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) 2255 wbif_mode = PLANAR_420_8BPC; 2256 else 2257 wbif_mode = PLANAR_420_10BPC; 2258 } else 2259 wbif_mode = PACKED_444; 2260 2261 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) { 2262 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2263 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2264 } 2265 wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */ 2266 wb_arb_params->slice_lines = 32; 2267 wb_arb_params->arbitration_slice = 2; 2268 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel, 2269 wbif_mode, 2270 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */ 2271 2272 dwb_pipe++; 2273 2274 if (dwb_pipe >= MAX_DWB_PIPES) 2275 return; 2276 } 2277 if (dwb_pipe >= MAX_DWB_PIPES) 2278 return; 2279 } 2280 } 2281 2282 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) 2283 { 2284 int i; 2285 2286 /* Validate DSC config, dsc count validation is already done */ 2287 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2288 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; 2289 struct dc_stream_state *stream = pipe_ctx->stream; 2290 struct dsc_config dsc_cfg; 2291 struct pipe_ctx *odm_pipe; 2292 int opp_cnt = 1; 2293 2294 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 2295 opp_cnt++; 2296 2297 /* Only need to validate top pipe */ 2298 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC) 2299 continue; 2300 2301 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left 2302 + stream->timing.h_border_right) / opp_cnt; 2303 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top 2304 + stream->timing.v_border_bottom; 2305 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 2306 dsc_cfg.color_depth = stream->timing.display_color_depth; 2307 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 2308 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 2309 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 2310 2311 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg)) 2312 return false; 2313 } 2314 return true; 2315 } 2316 2317 struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, 2318 struct resource_context *res_ctx, 2319 const struct resource_pool *pool, 2320 const struct pipe_ctx *primary_pipe) 2321 { 2322 struct pipe_ctx *secondary_pipe = NULL; 2323 2324 if (dc && primary_pipe) { 2325 int j; 2326 int preferred_pipe_idx = 0; 2327 2328 /* first check the prev dc state: 2329 * if this primary pipe has a bottom pipe in prev. state 2330 * and if the bottom pipe is still available (which it should be), 2331 * pick that pipe as secondary 2332 * Same logic applies for ODM pipes. Since mpo is not allowed with odm 2333 * check in else case. 2334 */ 2335 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) { 2336 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx; 2337 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2338 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2339 secondary_pipe->pipe_idx = preferred_pipe_idx; 2340 } 2341 } else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) { 2342 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx; 2343 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2344 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2345 secondary_pipe->pipe_idx = preferred_pipe_idx; 2346 } 2347 } 2348 2349 /* 2350 * if this primary pipe does not have a bottom pipe in prev. state 2351 * start backward and find a pipe that did not used to be a bottom pipe in 2352 * prev. dc state. This way we make sure we keep the same assignment as 2353 * last state and will not have to reprogram every pipe 2354 */ 2355 if (secondary_pipe == NULL) { 2356 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { 2357 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL 2358 && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) { 2359 preferred_pipe_idx = j; 2360 2361 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2362 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2363 secondary_pipe->pipe_idx = preferred_pipe_idx; 2364 break; 2365 } 2366 } 2367 } 2368 } 2369 /* 2370 * We should never hit this assert unless assignments are shuffled around 2371 * if this happens we will prob. hit a vsync tdr 2372 */ 2373 ASSERT(secondary_pipe); 2374 /* 2375 * search backwards for the second pipe to keep pipe 2376 * assignment more consistent 2377 */ 2378 if (secondary_pipe == NULL) { 2379 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { 2380 preferred_pipe_idx = j; 2381 2382 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2383 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2384 secondary_pipe->pipe_idx = preferred_pipe_idx; 2385 break; 2386 } 2387 } 2388 } 2389 } 2390 2391 return secondary_pipe; 2392 } 2393 2394 void dcn20_merge_pipes_for_validate( 2395 struct dc *dc, 2396 struct dc_state *context) 2397 { 2398 int i; 2399 2400 /* merge previously split odm pipes since mode support needs to make the decision */ 2401 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2402 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2403 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe; 2404 2405 if (pipe->prev_odm_pipe) 2406 continue; 2407 2408 pipe->next_odm_pipe = NULL; 2409 while (odm_pipe) { 2410 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe; 2411 2412 odm_pipe->plane_state = NULL; 2413 odm_pipe->stream = NULL; 2414 odm_pipe->top_pipe = NULL; 2415 odm_pipe->bottom_pipe = NULL; 2416 odm_pipe->prev_odm_pipe = NULL; 2417 odm_pipe->next_odm_pipe = NULL; 2418 if (odm_pipe->stream_res.dsc) 2419 release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); 2420 /* Clear plane_res and stream_res */ 2421 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res)); 2422 memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res)); 2423 odm_pipe = next_odm_pipe; 2424 } 2425 if (pipe->plane_state) 2426 resource_build_scaling_params(pipe); 2427 } 2428 2429 /* merge previously mpc split pipes since mode support needs to make the decision */ 2430 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2431 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2432 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 2433 2434 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) 2435 continue; 2436 2437 pipe->bottom_pipe = hsplit_pipe->bottom_pipe; 2438 if (hsplit_pipe->bottom_pipe) 2439 hsplit_pipe->bottom_pipe->top_pipe = pipe; 2440 hsplit_pipe->plane_state = NULL; 2441 hsplit_pipe->stream = NULL; 2442 hsplit_pipe->top_pipe = NULL; 2443 hsplit_pipe->bottom_pipe = NULL; 2444 2445 /* Clear plane_res and stream_res */ 2446 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res)); 2447 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res)); 2448 if (pipe->plane_state) 2449 resource_build_scaling_params(pipe); 2450 } 2451 } 2452 2453 int dcn20_validate_apply_pipe_split_flags( 2454 struct dc *dc, 2455 struct dc_state *context, 2456 int vlevel, 2457 bool *split) 2458 { 2459 int i, pipe_idx, vlevel_split; 2460 bool force_split = false; 2461 bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC; 2462 2463 /* Single display loop, exits if there is more than one display */ 2464 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2465 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2466 bool exit_loop = false; 2467 2468 if (!pipe->stream || pipe->top_pipe) 2469 continue; 2470 2471 if (dc->debug.force_single_disp_pipe_split) { 2472 if (!force_split) 2473 force_split = true; 2474 else { 2475 force_split = false; 2476 exit_loop = true; 2477 } 2478 } 2479 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) { 2480 if (avoid_split) 2481 avoid_split = false; 2482 else { 2483 avoid_split = true; 2484 exit_loop = true; 2485 } 2486 } 2487 if (exit_loop) 2488 break; 2489 } 2490 /* TODO: fix dc bugs and remove this split threshold thing */ 2491 if (context->stream_count > dc->res_pool->pipe_count / 2) 2492 avoid_split = true; 2493 2494 /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */ 2495 if (avoid_split) { 2496 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2497 if (!context->res_ctx.pipe_ctx[i].stream) 2498 continue; 2499 2500 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) 2501 if (context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1) 2502 break; 2503 /* Impossible to not split this pipe */ 2504 if (vlevel > context->bw_ctx.dml.soc.num_states) 2505 vlevel = vlevel_split; 2506 pipe_idx++; 2507 } 2508 context->bw_ctx.dml.vba.maxMpcComb = 0; 2509 } 2510 2511 /* Split loop sets which pipe should be split based on dml outputs and dc flags */ 2512 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2513 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2514 2515 if (!context->res_ctx.pipe_ctx[i].stream) 2516 continue; 2517 2518 if (force_split || context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] > 1) 2519 split[i] = true; 2520 if ((pipe->stream->view_format == 2521 VIEW_3D_FORMAT_SIDE_BY_SIDE || 2522 pipe->stream->view_format == 2523 VIEW_3D_FORMAT_TOP_AND_BOTTOM) && 2524 (pipe->stream->timing.timing_3d_format == 2525 TIMING_3D_FORMAT_TOP_AND_BOTTOM || 2526 pipe->stream->timing.timing_3d_format == 2527 TIMING_3D_FORMAT_SIDE_BY_SIDE)) 2528 split[i] = true; 2529 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) { 2530 split[i] = true; 2531 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = dm_odm_combine_mode_2to1; 2532 } 2533 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] = 2534 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx]; 2535 /* Adjust dppclk when split is forced, do not bother with dispclk */ 2536 if (split[i] && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1) 2537 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2; 2538 pipe_idx++; 2539 } 2540 2541 return vlevel; 2542 } 2543 2544 bool dcn20_fast_validate_bw( 2545 struct dc *dc, 2546 struct dc_state *context, 2547 display_e2e_pipe_params_st *pipes, 2548 int *pipe_cnt_out, 2549 int *pipe_split_from, 2550 int *vlevel_out) 2551 { 2552 bool out = false; 2553 bool split[MAX_PIPES] = { false }; 2554 int pipe_cnt, i, pipe_idx, vlevel; 2555 2556 ASSERT(pipes); 2557 if (!pipes) 2558 return false; 2559 2560 dcn20_merge_pipes_for_validate(dc, context); 2561 2562 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes); 2563 2564 *pipe_cnt_out = pipe_cnt; 2565 2566 if (!pipe_cnt) { 2567 out = true; 2568 goto validate_out; 2569 } 2570 2571 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 2572 2573 if (vlevel > context->bw_ctx.dml.soc.num_states) 2574 goto validate_fail; 2575 2576 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split); 2577 2578 /*initialize pipe_just_split_from to invalid idx*/ 2579 for (i = 0; i < MAX_PIPES; i++) 2580 pipe_split_from[i] = -1; 2581 2582 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { 2583 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2584 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 2585 2586 if (!pipe->stream || pipe_split_from[i] >= 0) 2587 continue; 2588 2589 pipe_idx++; 2590 2591 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 2592 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 2593 ASSERT(hsplit_pipe); 2594 if (!dcn20_split_stream_for_odm( 2595 &context->res_ctx, dc->res_pool, 2596 pipe, hsplit_pipe)) 2597 goto validate_fail; 2598 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 2599 dcn20_build_mapped_resource(dc, context, pipe->stream); 2600 } 2601 2602 if (!pipe->plane_state) 2603 continue; 2604 /* Skip 2nd half of already split pipe */ 2605 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state) 2606 continue; 2607 2608 /* We do not support mpo + odm at the moment */ 2609 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state 2610 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) 2611 goto validate_fail; 2612 2613 if (split[i]) { 2614 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) { 2615 /* pipe not split previously needs split */ 2616 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 2617 ASSERT(hsplit_pipe); 2618 if (!hsplit_pipe) { 2619 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2; 2620 continue; 2621 } 2622 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 2623 if (!dcn20_split_stream_for_odm( 2624 &context->res_ctx, dc->res_pool, 2625 pipe, hsplit_pipe)) 2626 goto validate_fail; 2627 dcn20_build_mapped_resource(dc, context, pipe->stream); 2628 } else 2629 dcn20_split_stream_for_mpc( 2630 &context->res_ctx, dc->res_pool, 2631 pipe, hsplit_pipe); 2632 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 2633 } 2634 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { 2635 /* merge should already have been done */ 2636 ASSERT(0); 2637 } 2638 } 2639 /* Actual dsc count per stream dsc validation*/ 2640 if (!dcn20_validate_dsc(dc, context)) { 2641 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = 2642 DML_FAIL_DSC_VALIDATION_FAILURE; 2643 goto validate_fail; 2644 } 2645 2646 *vlevel_out = vlevel; 2647 2648 out = true; 2649 goto validate_out; 2650 2651 validate_fail: 2652 out = false; 2653 2654 validate_out: 2655 return out; 2656 } 2657 2658 static void dcn20_calculate_wm( 2659 struct dc *dc, struct dc_state *context, 2660 display_e2e_pipe_params_st *pipes, 2661 int *out_pipe_cnt, 2662 int *pipe_split_from, 2663 int vlevel) 2664 { 2665 int pipe_cnt, i, pipe_idx; 2666 2667 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 2668 if (!context->res_ctx.pipe_ctx[i].stream) 2669 continue; 2670 2671 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 2672 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 2673 2674 if (pipe_split_from[i] < 0) { 2675 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 2676 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; 2677 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) 2678 pipes[pipe_cnt].pipe.dest.odm_combine = 2679 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]; 2680 else 2681 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 2682 pipe_idx++; 2683 } else { 2684 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 2685 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; 2686 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) 2687 pipes[pipe_cnt].pipe.dest.odm_combine = 2688 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]]; 2689 else 2690 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 2691 } 2692 2693 if (dc->config.forced_clocks) { 2694 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 2695 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 2696 } 2697 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000) 2698 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 2699 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000) 2700 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 2701 2702 pipe_cnt++; 2703 } 2704 2705 if (pipe_cnt != pipe_idx) { 2706 if (dc->res_pool->funcs->populate_dml_pipes) 2707 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, 2708 context, pipes); 2709 else 2710 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, 2711 context, pipes); 2712 } 2713 2714 *out_pipe_cnt = pipe_cnt; 2715 2716 pipes[0].clks_cfg.voltage = vlevel; 2717 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; 2718 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 2719 2720 /* only pipe 0 is read for voltage and dcf/soc clocks */ 2721 if (vlevel < 1) { 2722 pipes[0].clks_cfg.voltage = 1; 2723 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz; 2724 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz; 2725 } 2726 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2727 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2728 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2729 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2730 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2731 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2732 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2733 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2734 2735 if (vlevel < 2) { 2736 pipes[0].clks_cfg.voltage = 2; 2737 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; 2738 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; 2739 } 2740 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2741 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2742 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2743 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2744 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2745 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2746 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2747 2748 if (vlevel < 3) { 2749 pipes[0].clks_cfg.voltage = 3; 2750 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; 2751 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; 2752 } 2753 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2754 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2755 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2756 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2757 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2758 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2759 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2760 2761 pipes[0].clks_cfg.voltage = vlevel; 2762 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; 2763 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 2764 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2765 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2766 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2767 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2768 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2769 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2770 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2771 } 2772 2773 void dcn20_calculate_dlg_params( 2774 struct dc *dc, struct dc_state *context, 2775 display_e2e_pipe_params_st *pipes, 2776 int pipe_cnt, 2777 int vlevel) 2778 { 2779 int i, j, pipe_idx, pipe_idx_unsplit; 2780 bool visited[MAX_PIPES] = { 0 }; 2781 2782 /* Writeback MCIF_WB arbitration parameters */ 2783 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); 2784 2785 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; 2786 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; 2787 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; 2788 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; 2789 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; 2790 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; 2791 context->bw_ctx.bw.dcn.clk.p_state_change_support = 2792 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] 2793 != dm_dram_clock_change_unsupported; 2794 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 2795 2796 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) 2797 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; 2798 2799 /* 2800 * An artifact of dml pipe split/odm is that pipes get merged back together for 2801 * calculation. Therefore we need to only extract for first pipe in ascending index order 2802 * and copy into the other split half. 2803 */ 2804 for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) { 2805 if (!context->res_ctx.pipe_ctx[i].stream) 2806 continue; 2807 2808 if (!visited[pipe_idx]) { 2809 display_pipe_source_params_st *src = &pipes[pipe_idx].pipe.src; 2810 display_pipe_dest_params_st *dst = &pipes[pipe_idx].pipe.dest; 2811 2812 dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit]; 2813 dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit]; 2814 dst->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit]; 2815 dst->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit]; 2816 /* 2817 * j iterates inside pipes array, unlike i which iterates inside 2818 * pipe_ctx array 2819 */ 2820 if (src->is_hsplit) 2821 for (j = pipe_idx + 1; j < pipe_cnt; j++) { 2822 display_pipe_source_params_st *src_j = &pipes[j].pipe.src; 2823 display_pipe_dest_params_st *dst_j = &pipes[j].pipe.dest; 2824 2825 if (src_j->is_hsplit && !visited[j] 2826 && src->hsplit_grp == src_j->hsplit_grp) { 2827 dst_j->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit]; 2828 dst_j->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit]; 2829 dst_j->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit]; 2830 dst_j->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit]; 2831 visited[j] = true; 2832 } 2833 } 2834 visited[pipe_idx] = true; 2835 pipe_idx_unsplit++; 2836 } 2837 pipe_idx++; 2838 } 2839 2840 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2841 if (!context->res_ctx.pipe_ctx[i].stream) 2842 continue; 2843 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 2844 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 2845 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 2846 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 2847 ASSERT(visited[pipe_idx]); 2848 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; 2849 pipe_idx++; 2850 } 2851 /*save a original dppclock copy*/ 2852 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; 2853 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; 2854 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000; 2855 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000; 2856 2857 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2858 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2; 2859 2860 if (!context->res_ctx.pipe_ctx[i].stream) 2861 continue; 2862 2863 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml, 2864 &context->res_ctx.pipe_ctx[i].dlg_regs, 2865 &context->res_ctx.pipe_ctx[i].ttu_regs, 2866 pipes, 2867 pipe_cnt, 2868 pipe_idx, 2869 cstate_en, 2870 context->bw_ctx.bw.dcn.clk.p_state_change_support, 2871 false, false, false); 2872 2873 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml, 2874 &context->res_ctx.pipe_ctx[i].rq_regs, 2875 pipes[pipe_idx].pipe); 2876 pipe_idx++; 2877 } 2878 } 2879 2880 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context, 2881 bool fast_validate) 2882 { 2883 bool out = false; 2884 2885 BW_VAL_TRACE_SETUP(); 2886 2887 int vlevel = 0; 2888 int pipe_split_from[MAX_PIPES]; 2889 int pipe_cnt = 0; 2890 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 2891 DC_LOGGER_INIT(dc->ctx->logger); 2892 2893 BW_VAL_TRACE_COUNT(); 2894 2895 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel); 2896 2897 if (pipe_cnt == 0) 2898 goto validate_out; 2899 2900 if (!out) 2901 goto validate_fail; 2902 2903 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 2904 2905 if (fast_validate) { 2906 BW_VAL_TRACE_SKIP(fast); 2907 goto validate_out; 2908 } 2909 2910 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel); 2911 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 2912 2913 BW_VAL_TRACE_END_WATERMARKS(); 2914 2915 goto validate_out; 2916 2917 validate_fail: 2918 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 2919 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 2920 2921 BW_VAL_TRACE_SKIP(fail); 2922 out = false; 2923 2924 validate_out: 2925 kfree(pipes); 2926 2927 BW_VAL_TRACE_FINISH(); 2928 2929 return out; 2930 } 2931 2932 2933 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, 2934 bool fast_validate) 2935 { 2936 bool voltage_supported = false; 2937 bool full_pstate_supported = false; 2938 bool dummy_pstate_supported = false; 2939 double p_state_latency_us; 2940 2941 DC_FP_START(); 2942 p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us; 2943 context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support = 2944 dc->debug.disable_dram_clock_change_vactive_support; 2945 2946 if (fast_validate) { 2947 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, true); 2948 2949 DC_FP_END(); 2950 return voltage_supported; 2951 } 2952 2953 // Best case, we support full UCLK switch latency 2954 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); 2955 full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; 2956 2957 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 || 2958 (voltage_supported && full_pstate_supported)) { 2959 context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported; 2960 goto restore_dml_state; 2961 } 2962 2963 // Fallback: Try to only support G6 temperature read latency 2964 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us; 2965 2966 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); 2967 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; 2968 2969 if (voltage_supported && dummy_pstate_supported) { 2970 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; 2971 goto restore_dml_state; 2972 } 2973 2974 // ERROR: fallback is supposed to always work. 2975 ASSERT(false); 2976 2977 restore_dml_state: 2978 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us; 2979 2980 DC_FP_END(); 2981 return voltage_supported; 2982 } 2983 2984 struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer( 2985 struct dc_state *state, 2986 const struct resource_pool *pool, 2987 struct dc_stream_state *stream) 2988 { 2989 struct resource_context *res_ctx = &state->res_ctx; 2990 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 2991 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe); 2992 2993 if (!head_pipe) 2994 ASSERT(0); 2995 2996 if (!idle_pipe) 2997 return NULL; 2998 2999 idle_pipe->stream = head_pipe->stream; 3000 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 3001 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 3002 3003 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 3004 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 3005 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 3006 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 3007 3008 return idle_pipe; 3009 } 3010 3011 bool dcn20_get_dcc_compression_cap(const struct dc *dc, 3012 const struct dc_dcc_surface_param *input, 3013 struct dc_surface_dcc_cap *output) 3014 { 3015 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 3016 dc->res_pool->hubbub, 3017 input, 3018 output); 3019 } 3020 3021 static void dcn20_destroy_resource_pool(struct resource_pool **pool) 3022 { 3023 struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool); 3024 3025 dcn20_resource_destruct(dcn20_pool); 3026 kfree(dcn20_pool); 3027 *pool = NULL; 3028 } 3029 3030 3031 static struct dc_cap_funcs cap_funcs = { 3032 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 3033 }; 3034 3035 3036 enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state) 3037 { 3038 enum dc_status result = DC_OK; 3039 3040 enum surface_pixel_format surf_pix_format = plane_state->format; 3041 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 3042 3043 enum swizzle_mode_values swizzle = DC_SW_LINEAR; 3044 3045 if (bpp == 64) 3046 swizzle = DC_SW_64KB_D; 3047 else 3048 swizzle = DC_SW_64KB_S; 3049 3050 plane_state->tiling_info.gfx9.swizzle = swizzle; 3051 return result; 3052 } 3053 3054 static struct resource_funcs dcn20_res_pool_funcs = { 3055 .destroy = dcn20_destroy_resource_pool, 3056 .link_enc_create = dcn20_link_encoder_create, 3057 .validate_bandwidth = dcn20_validate_bandwidth, 3058 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 3059 .add_stream_to_ctx = dcn20_add_stream_to_ctx, 3060 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 3061 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, 3062 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 3063 .set_mcif_arb_params = dcn20_set_mcif_arb_params, 3064 .populate_dml_pipes = dcn20_populate_dml_pipes_from_context, 3065 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link 3066 }; 3067 3068 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 3069 { 3070 int i; 3071 uint32_t pipe_count = pool->res_cap->num_dwb; 3072 3073 for (i = 0; i < pipe_count; i++) { 3074 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc), 3075 GFP_KERNEL); 3076 3077 if (!dwbc20) { 3078 dm_error("DC: failed to create dwbc20!\n"); 3079 return false; 3080 } 3081 dcn20_dwbc_construct(dwbc20, ctx, 3082 &dwbc20_regs[i], 3083 &dwbc20_shift, 3084 &dwbc20_mask, 3085 i); 3086 pool->dwbc[i] = &dwbc20->base; 3087 } 3088 return true; 3089 } 3090 3091 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 3092 { 3093 int i; 3094 uint32_t pipe_count = pool->res_cap->num_dwb; 3095 3096 ASSERT(pipe_count > 0); 3097 3098 for (i = 0; i < pipe_count; i++) { 3099 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub), 3100 GFP_KERNEL); 3101 3102 if (!mcif_wb20) { 3103 dm_error("DC: failed to create mcif_wb20!\n"); 3104 return false; 3105 } 3106 3107 dcn20_mmhubbub_construct(mcif_wb20, ctx, 3108 &mcif_wb20_regs[i], 3109 &mcif_wb20_shift, 3110 &mcif_wb20_mask, 3111 i); 3112 3113 pool->mcif_wb[i] = &mcif_wb20->base; 3114 } 3115 return true; 3116 } 3117 3118 static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx) 3119 { 3120 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 3121 3122 if (!pp_smu) 3123 return pp_smu; 3124 3125 dm_pp_get_funcs(ctx, pp_smu); 3126 3127 if (pp_smu->ctx.ver != PP_SMU_VER_NV) 3128 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); 3129 3130 return pp_smu; 3131 } 3132 3133 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu) 3134 { 3135 if (pp_smu && *pp_smu) { 3136 kfree(*pp_smu); 3137 *pp_smu = NULL; 3138 } 3139 } 3140 3141 void dcn20_cap_soc_clocks( 3142 struct _vcs_dpi_soc_bounding_box_st *bb, 3143 struct pp_smu_nv_clock_table max_clocks) 3144 { 3145 int i; 3146 3147 // First pass - cap all clocks higher than the reported max 3148 for (i = 0; i < bb->num_states; i++) { 3149 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000)) 3150 && max_clocks.dcfClockInKhz != 0) 3151 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000); 3152 3153 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16) 3154 && max_clocks.uClockInKhz != 0) 3155 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16; 3156 3157 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000)) 3158 && max_clocks.fabricClockInKhz != 0) 3159 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000); 3160 3161 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000)) 3162 && max_clocks.displayClockInKhz != 0) 3163 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000); 3164 3165 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000)) 3166 && max_clocks.dppClockInKhz != 0) 3167 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000); 3168 3169 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000)) 3170 && max_clocks.phyClockInKhz != 0) 3171 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000); 3172 3173 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000)) 3174 && max_clocks.socClockInKhz != 0) 3175 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000); 3176 3177 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000)) 3178 && max_clocks.dscClockInKhz != 0) 3179 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000); 3180 } 3181 3182 // Second pass - remove all duplicate clock states 3183 for (i = bb->num_states - 1; i > 1; i--) { 3184 bool duplicate = true; 3185 3186 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz) 3187 duplicate = false; 3188 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz) 3189 duplicate = false; 3190 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz) 3191 duplicate = false; 3192 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts) 3193 duplicate = false; 3194 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz) 3195 duplicate = false; 3196 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz) 3197 duplicate = false; 3198 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz) 3199 duplicate = false; 3200 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz) 3201 duplicate = false; 3202 3203 if (duplicate) 3204 bb->num_states--; 3205 } 3206 } 3207 3208 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb, 3209 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) 3210 { 3211 struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES]; 3212 int i; 3213 int num_calculated_states = 0; 3214 int min_dcfclk = 0; 3215 3216 if (num_states == 0) 3217 return; 3218 3219 memset(calculated_states, 0, sizeof(calculated_states)); 3220 3221 if (dc->bb_overrides.min_dcfclk_mhz > 0) 3222 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz; 3223 else { 3224 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) 3225 min_dcfclk = 310; 3226 else 3227 // Accounting for SOC/DCF relationship, we can go as high as 3228 // 506Mhz in Vmin. 3229 min_dcfclk = 506; 3230 } 3231 3232 for (i = 0; i < num_states; i++) { 3233 int min_fclk_required_by_uclk; 3234 calculated_states[i].state = i; 3235 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000; 3236 3237 // FCLK:UCLK ratio is 1.08 3238 min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32); 3239 3240 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? 3241 min_dcfclk : min_fclk_required_by_uclk; 3242 3243 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ? 3244 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; 3245 3246 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ? 3247 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; 3248 3249 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000; 3250 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000; 3251 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3); 3252 3253 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000; 3254 3255 num_calculated_states++; 3256 } 3257 3258 calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000; 3259 calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000; 3260 calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000; 3261 3262 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits)); 3263 bb->num_states = num_calculated_states; 3264 3265 // Duplicate the last state, DML always an extra state identical to max state to work 3266 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st)); 3267 bb->clock_limits[num_calculated_states].state = bb->num_states; 3268 } 3269 3270 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) 3271 { 3272 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns 3273 && dc->bb_overrides.sr_exit_time_ns) { 3274 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; 3275 } 3276 3277 if ((int)(bb->sr_enter_plus_exit_time_us * 1000) 3278 != dc->bb_overrides.sr_enter_plus_exit_time_ns 3279 && dc->bb_overrides.sr_enter_plus_exit_time_ns) { 3280 bb->sr_enter_plus_exit_time_us = 3281 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 3282 } 3283 3284 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns 3285 && dc->bb_overrides.urgent_latency_ns) { 3286 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 3287 } 3288 3289 if ((int)(bb->dram_clock_change_latency_us * 1000) 3290 != dc->bb_overrides.dram_clock_change_latency_ns 3291 && dc->bb_overrides.dram_clock_change_latency_ns) { 3292 bb->dram_clock_change_latency_us = 3293 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 3294 } 3295 } 3296 3297 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb( 3298 uint32_t hw_internal_rev) 3299 { 3300 if (ASICREV_IS_NAVI12_P(hw_internal_rev)) 3301 return &dcn2_0_nv12_soc; 3302 3303 return &dcn2_0_soc; 3304 } 3305 3306 static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params( 3307 uint32_t hw_internal_rev) 3308 { 3309 /* NV14 */ 3310 if (ASICREV_IS_NAVI14_M(hw_internal_rev)) 3311 return &dcn2_0_nv14_ip; 3312 3313 /* NV12 and NV10 */ 3314 return &dcn2_0_ip; 3315 } 3316 3317 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev) 3318 { 3319 return DML_PROJECT_NAVI10v2; 3320 } 3321 3322 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16))) 3323 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) 3324 3325 static bool init_soc_bounding_box(struct dc *dc, 3326 struct dcn20_resource_pool *pool) 3327 { 3328 const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box; 3329 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = 3330 get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev); 3331 struct _vcs_dpi_ip_params_st *loaded_ip = 3332 get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev); 3333 3334 DC_LOGGER_INIT(dc->ctx->logger); 3335 3336 /* TODO: upstream NV12 bounding box when its launched */ 3337 if (!bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) { 3338 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); 3339 return false; 3340 } 3341 3342 if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) { 3343 int i; 3344 3345 dcn2_0_nv12_soc.sr_exit_time_us = 3346 fixed16_to_double_to_cpu(bb->sr_exit_time_us); 3347 dcn2_0_nv12_soc.sr_enter_plus_exit_time_us = 3348 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us); 3349 dcn2_0_nv12_soc.urgent_latency_us = 3350 fixed16_to_double_to_cpu(bb->urgent_latency_us); 3351 dcn2_0_nv12_soc.urgent_latency_pixel_data_only_us = 3352 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us); 3353 dcn2_0_nv12_soc.urgent_latency_pixel_mixed_with_vm_data_us = 3354 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us); 3355 dcn2_0_nv12_soc.urgent_latency_vm_data_only_us = 3356 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us); 3357 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes = 3358 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes); 3359 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 3360 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes); 3361 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_vm_only_bytes = 3362 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes); 3363 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 3364 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only); 3365 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 3366 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm); 3367 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 3368 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only); 3369 dcn2_0_nv12_soc.max_avg_sdp_bw_use_normal_percent = 3370 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent); 3371 dcn2_0_nv12_soc.max_avg_dram_bw_use_normal_percent = 3372 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent); 3373 dcn2_0_nv12_soc.writeback_latency_us = 3374 fixed16_to_double_to_cpu(bb->writeback_latency_us); 3375 dcn2_0_nv12_soc.ideal_dram_bw_after_urgent_percent = 3376 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent); 3377 dcn2_0_nv12_soc.max_request_size_bytes = 3378 le32_to_cpu(bb->max_request_size_bytes); 3379 dcn2_0_nv12_soc.dram_channel_width_bytes = 3380 le32_to_cpu(bb->dram_channel_width_bytes); 3381 dcn2_0_nv12_soc.fabric_datapath_to_dcn_data_return_bytes = 3382 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes); 3383 dcn2_0_nv12_soc.dcn_downspread_percent = 3384 fixed16_to_double_to_cpu(bb->dcn_downspread_percent); 3385 dcn2_0_nv12_soc.downspread_percent = 3386 fixed16_to_double_to_cpu(bb->downspread_percent); 3387 dcn2_0_nv12_soc.dram_page_open_time_ns = 3388 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns); 3389 dcn2_0_nv12_soc.dram_rw_turnaround_time_ns = 3390 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns); 3391 dcn2_0_nv12_soc.dram_return_buffer_per_channel_bytes = 3392 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes); 3393 dcn2_0_nv12_soc.round_trip_ping_latency_dcfclk_cycles = 3394 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles); 3395 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_bytes = 3396 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes); 3397 dcn2_0_nv12_soc.channel_interleave_bytes = 3398 le32_to_cpu(bb->channel_interleave_bytes); 3399 dcn2_0_nv12_soc.num_banks = 3400 le32_to_cpu(bb->num_banks); 3401 dcn2_0_nv12_soc.num_chans = 3402 le32_to_cpu(bb->num_chans); 3403 dcn2_0_nv12_soc.vmm_page_size_bytes = 3404 le32_to_cpu(bb->vmm_page_size_bytes); 3405 dcn2_0_nv12_soc.dram_clock_change_latency_us = 3406 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us); 3407 // HACK!! Lower uclock latency switch time so we don't switch 3408 dcn2_0_nv12_soc.dram_clock_change_latency_us = 10; 3409 dcn2_0_nv12_soc.writeback_dram_clock_change_latency_us = 3410 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us); 3411 dcn2_0_nv12_soc.return_bus_width_bytes = 3412 le32_to_cpu(bb->return_bus_width_bytes); 3413 dcn2_0_nv12_soc.dispclk_dppclk_vco_speed_mhz = 3414 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz); 3415 dcn2_0_nv12_soc.xfc_bus_transport_time_us = 3416 le32_to_cpu(bb->xfc_bus_transport_time_us); 3417 dcn2_0_nv12_soc.xfc_xbuf_latency_tolerance_us = 3418 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us); 3419 dcn2_0_nv12_soc.use_urgent_burst_bw = 3420 le32_to_cpu(bb->use_urgent_burst_bw); 3421 dcn2_0_nv12_soc.num_states = 3422 le32_to_cpu(bb->num_states); 3423 3424 for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) { 3425 dcn2_0_nv12_soc.clock_limits[i].state = 3426 le32_to_cpu(bb->clock_limits[i].state); 3427 dcn2_0_nv12_soc.clock_limits[i].dcfclk_mhz = 3428 fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz); 3429 dcn2_0_nv12_soc.clock_limits[i].fabricclk_mhz = 3430 fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz); 3431 dcn2_0_nv12_soc.clock_limits[i].dispclk_mhz = 3432 fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz); 3433 dcn2_0_nv12_soc.clock_limits[i].dppclk_mhz = 3434 fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz); 3435 dcn2_0_nv12_soc.clock_limits[i].phyclk_mhz = 3436 fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz); 3437 dcn2_0_nv12_soc.clock_limits[i].socclk_mhz = 3438 fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz); 3439 dcn2_0_nv12_soc.clock_limits[i].dscclk_mhz = 3440 fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz); 3441 dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts = 3442 fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts); 3443 } 3444 } 3445 3446 if (pool->base.pp_smu) { 3447 struct pp_smu_nv_clock_table max_clocks = {0}; 3448 unsigned int uclk_states[8] = {0}; 3449 unsigned int num_states = 0; 3450 enum pp_smu_status status; 3451 bool clock_limits_available = false; 3452 bool uclk_states_available = false; 3453 3454 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) { 3455 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) 3456 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); 3457 3458 uclk_states_available = (status == PP_SMU_RESULT_OK); 3459 } 3460 3461 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) { 3462 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) 3463 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks); 3464 /* SMU cannot set DCF clock to anything equal to or higher than SOC clock 3465 */ 3466 if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz) 3467 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000; 3468 clock_limits_available = (status == PP_SMU_RESULT_OK); 3469 } 3470 3471 if (clock_limits_available && uclk_states_available && num_states) 3472 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states); 3473 else if (clock_limits_available) 3474 dcn20_cap_soc_clocks(loaded_bb, max_clocks); 3475 } 3476 3477 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; 3478 loaded_ip->max_num_dpp = pool->base.pipe_count; 3479 dcn20_patch_bounding_box(dc, loaded_bb); 3480 3481 return true; 3482 } 3483 3484 static bool dcn20_resource_construct( 3485 uint8_t num_virtual_links, 3486 struct dc *dc, 3487 struct dcn20_resource_pool *pool) 3488 { 3489 int i; 3490 struct dc_context *ctx = dc->ctx; 3491 struct irq_service_init_data init_data; 3492 struct ddc_service_init_data ddc_init_data; 3493 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = 3494 get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev); 3495 struct _vcs_dpi_ip_params_st *loaded_ip = 3496 get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev); 3497 enum dml_project dml_project_version = 3498 get_dml_project_version(ctx->asic_id.hw_internal_rev); 3499 3500 DC_FP_START(); 3501 3502 ctx->dc_bios->regs = &bios_regs; 3503 pool->base.funcs = &dcn20_res_pool_funcs; 3504 3505 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) { 3506 pool->base.res_cap = &res_cap_nv14; 3507 pool->base.pipe_count = 5; 3508 pool->base.mpcc_count = 5; 3509 } else { 3510 pool->base.res_cap = &res_cap_nv10; 3511 pool->base.pipe_count = 6; 3512 pool->base.mpcc_count = 6; 3513 } 3514 /************************************************* 3515 * Resource + asic cap harcoding * 3516 *************************************************/ 3517 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 3518 3519 dc->caps.max_downscale_ratio = 200; 3520 dc->caps.i2c_speed_in_khz = 100; 3521 dc->caps.max_cursor_size = 256; 3522 dc->caps.dmdata_alloc_size = 2048; 3523 3524 dc->caps.max_slave_planes = 1; 3525 dc->caps.post_blend_color_processing = true; 3526 dc->caps.force_dp_tps4_for_cp2520 = true; 3527 dc->caps.hw_3d_lut = true; 3528 dc->caps.extended_aux_timeout_support = true; 3529 3530 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) { 3531 dc->debug = debug_defaults_drv; 3532 } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 3533 pool->base.pipe_count = 4; 3534 pool->base.mpcc_count = pool->base.pipe_count; 3535 dc->debug = debug_defaults_diags; 3536 } else { 3537 dc->debug = debug_defaults_diags; 3538 } 3539 //dcn2.0x 3540 dc->work_arounds.dedcn20_305_wa = true; 3541 3542 // Init the vm_helper 3543 if (dc->vm_helper) 3544 vm_helper_init(dc->vm_helper, 16); 3545 3546 /************************************************* 3547 * Create resources * 3548 *************************************************/ 3549 3550 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = 3551 dcn20_clock_source_create(ctx, ctx->dc_bios, 3552 CLOCK_SOURCE_COMBO_PHY_PLL0, 3553 &clk_src_regs[0], false); 3554 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = 3555 dcn20_clock_source_create(ctx, ctx->dc_bios, 3556 CLOCK_SOURCE_COMBO_PHY_PLL1, 3557 &clk_src_regs[1], false); 3558 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = 3559 dcn20_clock_source_create(ctx, ctx->dc_bios, 3560 CLOCK_SOURCE_COMBO_PHY_PLL2, 3561 &clk_src_regs[2], false); 3562 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] = 3563 dcn20_clock_source_create(ctx, ctx->dc_bios, 3564 CLOCK_SOURCE_COMBO_PHY_PLL3, 3565 &clk_src_regs[3], false); 3566 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] = 3567 dcn20_clock_source_create(ctx, ctx->dc_bios, 3568 CLOCK_SOURCE_COMBO_PHY_PLL4, 3569 &clk_src_regs[4], false); 3570 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] = 3571 dcn20_clock_source_create(ctx, ctx->dc_bios, 3572 CLOCK_SOURCE_COMBO_PHY_PLL5, 3573 &clk_src_regs[5], false); 3574 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL; 3575 /* todo: not reuse phy_pll registers */ 3576 pool->base.dp_clock_source = 3577 dcn20_clock_source_create(ctx, ctx->dc_bios, 3578 CLOCK_SOURCE_ID_DP_DTO, 3579 &clk_src_regs[0], true); 3580 3581 for (i = 0; i < pool->base.clk_src_count; i++) { 3582 if (pool->base.clock_sources[i] == NULL) { 3583 dm_error("DC: failed to create clock sources!\n"); 3584 BREAK_TO_DEBUGGER(); 3585 goto create_fail; 3586 } 3587 } 3588 3589 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 3590 if (pool->base.dccg == NULL) { 3591 dm_error("DC: failed to create dccg!\n"); 3592 BREAK_TO_DEBUGGER(); 3593 goto create_fail; 3594 } 3595 3596 pool->base.dmcu = dcn20_dmcu_create(ctx, 3597 &dmcu_regs, 3598 &dmcu_shift, 3599 &dmcu_mask); 3600 if (pool->base.dmcu == NULL) { 3601 dm_error("DC: failed to create dmcu!\n"); 3602 BREAK_TO_DEBUGGER(); 3603 goto create_fail; 3604 } 3605 3606 pool->base.abm = dce_abm_create(ctx, 3607 &abm_regs, 3608 &abm_shift, 3609 &abm_mask); 3610 if (pool->base.abm == NULL) { 3611 dm_error("DC: failed to create abm!\n"); 3612 BREAK_TO_DEBUGGER(); 3613 goto create_fail; 3614 } 3615 3616 pool->base.pp_smu = dcn20_pp_smu_create(ctx); 3617 3618 3619 if (!init_soc_bounding_box(dc, pool)) { 3620 dm_error("DC: failed to initialize soc bounding box!\n"); 3621 BREAK_TO_DEBUGGER(); 3622 goto create_fail; 3623 } 3624 3625 dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version); 3626 3627 if (!dc->debug.disable_pplib_wm_range) { 3628 struct pp_smu_wm_range_sets ranges = {0}; 3629 int i = 0; 3630 3631 ranges.num_reader_wm_sets = 0; 3632 3633 if (loaded_bb->num_states == 1) { 3634 ranges.reader_wm_sets[0].wm_inst = i; 3635 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3636 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3637 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3638 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3639 3640 ranges.num_reader_wm_sets = 1; 3641 } else if (loaded_bb->num_states > 1) { 3642 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { 3643 ranges.reader_wm_sets[i].wm_inst = i; 3644 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3645 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3646 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; 3647 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; 3648 3649 ranges.num_reader_wm_sets = i + 1; 3650 } 3651 3652 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3653 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3654 } 3655 3656 ranges.num_writer_wm_sets = 1; 3657 3658 ranges.writer_wm_sets[0].wm_inst = 0; 3659 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3660 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3661 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3662 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3663 3664 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 3665 if (pool->base.pp_smu->nv_funcs.set_wm_ranges) 3666 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges); 3667 } 3668 3669 init_data.ctx = dc->ctx; 3670 pool->base.irqs = dal_irq_service_dcn20_create(&init_data); 3671 if (!pool->base.irqs) 3672 goto create_fail; 3673 3674 /* mem input -> ipp -> dpp -> opp -> TG */ 3675 for (i = 0; i < pool->base.pipe_count; i++) { 3676 pool->base.hubps[i] = dcn20_hubp_create(ctx, i); 3677 if (pool->base.hubps[i] == NULL) { 3678 BREAK_TO_DEBUGGER(); 3679 dm_error( 3680 "DC: failed to create memory input!\n"); 3681 goto create_fail; 3682 } 3683 3684 pool->base.ipps[i] = dcn20_ipp_create(ctx, i); 3685 if (pool->base.ipps[i] == NULL) { 3686 BREAK_TO_DEBUGGER(); 3687 dm_error( 3688 "DC: failed to create input pixel processor!\n"); 3689 goto create_fail; 3690 } 3691 3692 pool->base.dpps[i] = dcn20_dpp_create(ctx, i); 3693 if (pool->base.dpps[i] == NULL) { 3694 BREAK_TO_DEBUGGER(); 3695 dm_error( 3696 "DC: failed to create dpps!\n"); 3697 goto create_fail; 3698 } 3699 } 3700 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 3701 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i); 3702 if (pool->base.engines[i] == NULL) { 3703 BREAK_TO_DEBUGGER(); 3704 dm_error( 3705 "DC:failed to create aux engine!!\n"); 3706 goto create_fail; 3707 } 3708 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i); 3709 if (pool->base.hw_i2cs[i] == NULL) { 3710 BREAK_TO_DEBUGGER(); 3711 dm_error( 3712 "DC:failed to create hw i2c!!\n"); 3713 goto create_fail; 3714 } 3715 pool->base.sw_i2cs[i] = NULL; 3716 } 3717 3718 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 3719 pool->base.opps[i] = dcn20_opp_create(ctx, i); 3720 if (pool->base.opps[i] == NULL) { 3721 BREAK_TO_DEBUGGER(); 3722 dm_error( 3723 "DC: failed to create output pixel processor!\n"); 3724 goto create_fail; 3725 } 3726 } 3727 3728 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 3729 pool->base.timing_generators[i] = dcn20_timing_generator_create( 3730 ctx, i); 3731 if (pool->base.timing_generators[i] == NULL) { 3732 BREAK_TO_DEBUGGER(); 3733 dm_error("DC: failed to create tg!\n"); 3734 goto create_fail; 3735 } 3736 } 3737 3738 pool->base.timing_generator_count = i; 3739 3740 pool->base.mpc = dcn20_mpc_create(ctx); 3741 if (pool->base.mpc == NULL) { 3742 BREAK_TO_DEBUGGER(); 3743 dm_error("DC: failed to create mpc!\n"); 3744 goto create_fail; 3745 } 3746 3747 pool->base.hubbub = dcn20_hubbub_create(ctx); 3748 if (pool->base.hubbub == NULL) { 3749 BREAK_TO_DEBUGGER(); 3750 dm_error("DC: failed to create hubbub!\n"); 3751 goto create_fail; 3752 } 3753 3754 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 3755 pool->base.dscs[i] = dcn20_dsc_create(ctx, i); 3756 if (pool->base.dscs[i] == NULL) { 3757 BREAK_TO_DEBUGGER(); 3758 dm_error("DC: failed to create display stream compressor %d!\n", i); 3759 goto create_fail; 3760 } 3761 } 3762 3763 if (!dcn20_dwbc_create(ctx, &pool->base)) { 3764 BREAK_TO_DEBUGGER(); 3765 dm_error("DC: failed to create dwbc!\n"); 3766 goto create_fail; 3767 } 3768 if (!dcn20_mmhubbub_create(ctx, &pool->base)) { 3769 BREAK_TO_DEBUGGER(); 3770 dm_error("DC: failed to create mcif_wb!\n"); 3771 goto create_fail; 3772 } 3773 3774 if (!resource_construct(num_virtual_links, dc, &pool->base, 3775 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 3776 &res_create_funcs : &res_create_maximus_funcs))) 3777 goto create_fail; 3778 3779 dcn20_hw_sequencer_construct(dc); 3780 3781 // IF NV12, set PG function pointer to NULL. It's not that 3782 // PG isn't supported for NV12, it's that we don't want to 3783 // program the registers because that will cause more power 3784 // to be consumed. We could have created dcn20_init_hw to get 3785 // the same effect by checking ASIC rev, but there was a 3786 // request at some point to not check ASIC rev on hw sequencer. 3787 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) 3788 dc->hwseq->funcs.enable_power_gating_plane = NULL; 3789 3790 dc->caps.max_planes = pool->base.pipe_count; 3791 3792 for (i = 0; i < dc->caps.max_planes; ++i) 3793 dc->caps.planes[i] = plane_cap; 3794 3795 dc->cap_funcs = cap_funcs; 3796 3797 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 3798 ddc_init_data.ctx = dc->ctx; 3799 ddc_init_data.link = NULL; 3800 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 3801 ddc_init_data.id.enum_id = 0; 3802 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 3803 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); 3804 } else { 3805 pool->base.oem_device = NULL; 3806 } 3807 3808 DC_FP_END(); 3809 return true; 3810 3811 create_fail: 3812 3813 DC_FP_END(); 3814 dcn20_resource_destruct(pool); 3815 3816 return false; 3817 } 3818 3819 struct resource_pool *dcn20_create_resource_pool( 3820 const struct dc_init_data *init_data, 3821 struct dc *dc) 3822 { 3823 struct dcn20_resource_pool *pool = 3824 kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL); 3825 3826 if (!pool) 3827 return NULL; 3828 3829 if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool)) 3830 return &pool->base; 3831 3832 BREAK_TO_DEBUGGER(); 3833 kfree(pool); 3834 return NULL; 3835 } 3836