1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 #include "dc.h" 30 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dcn20/dcn20_resource.h" 34 35 #include "dcn10/dcn10_hubp.h" 36 #include "dcn10/dcn10_ipp.h" 37 #include "dcn20_hubbub.h" 38 #include "dcn20_mpc.h" 39 #include "dcn20_hubp.h" 40 #include "irq/dcn20/irq_service_dcn20.h" 41 #include "dcn20_dpp.h" 42 #include "dcn20_optc.h" 43 #include "dcn20_hwseq.h" 44 #include "dce110/dce110_hw_sequencer.h" 45 #include "dcn10/dcn10_resource.h" 46 #include "dcn20_opp.h" 47 48 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 49 #include "dcn20_dsc.h" 50 #endif 51 52 #include "dcn20_link_encoder.h" 53 #include "dcn20_stream_encoder.h" 54 #include "dce/dce_clock_source.h" 55 #include "dce/dce_audio.h" 56 #include "dce/dce_hwseq.h" 57 #include "virtual/virtual_stream_encoder.h" 58 #include "dce110/dce110_resource.h" 59 #include "dml/display_mode_vba.h" 60 #include "dcn20_dccg.h" 61 #include "dcn20_vmid.h" 62 63 #include "navi10_ip_offset.h" 64 65 #include "dcn/dcn_2_0_0_offset.h" 66 #include "dcn/dcn_2_0_0_sh_mask.h" 67 68 #include "nbio/nbio_2_3_offset.h" 69 70 #include "dcn20/dcn20_dwb.h" 71 #include "dcn20/dcn20_mmhubbub.h" 72 73 #include "mmhub/mmhub_2_0_0_offset.h" 74 #include "mmhub/mmhub_2_0_0_sh_mask.h" 75 76 #include "reg_helper.h" 77 #include "dce/dce_abm.h" 78 #include "dce/dce_dmcu.h" 79 #include "dce/dce_aux.h" 80 #include "dce/dce_i2c.h" 81 #include "vm_helper.h" 82 83 #include "amdgpu_socbb.h" 84 85 /* NV12 SOC BB is currently in FW, mark SW bounding box invalid. */ 86 #define SOC_BOUNDING_BOX_VALID false 87 #define DC_LOGGER_INIT(logger) 88 89 struct _vcs_dpi_ip_params_st dcn2_0_ip = { 90 .odm_capable = 1, 91 .gpuvm_enable = 0, 92 .hostvm_enable = 0, 93 .gpuvm_max_page_table_levels = 4, 94 .hostvm_max_page_table_levels = 4, 95 .hostvm_cached_page_table_levels = 0, 96 .pte_group_size_bytes = 2048, 97 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 98 .num_dsc = 6, 99 #else 100 .num_dsc = 0, 101 #endif 102 .rob_buffer_size_kbytes = 168, 103 .det_buffer_size_kbytes = 164, 104 .dpte_buffer_size_in_pte_reqs_luma = 84, 105 .pde_proc_buffer_size_64k_reqs = 48, 106 .dpp_output_buffer_pixels = 2560, 107 .opp_output_buffer_lines = 1, 108 .pixel_chunk_size_kbytes = 8, 109 .pte_chunk_size_kbytes = 2, 110 .meta_chunk_size_kbytes = 2, 111 .writeback_chunk_size_kbytes = 2, 112 .line_buffer_size_bits = 789504, 113 .is_line_buffer_bpp_fixed = 0, 114 .line_buffer_fixed_bpp = 0, 115 .dcc_supported = true, 116 .max_line_buffer_lines = 12, 117 .writeback_luma_buffer_size_kbytes = 12, 118 .writeback_chroma_buffer_size_kbytes = 8, 119 .writeback_chroma_line_buffer_width_pixels = 4, 120 .writeback_max_hscl_ratio = 1, 121 .writeback_max_vscl_ratio = 1, 122 .writeback_min_hscl_ratio = 1, 123 .writeback_min_vscl_ratio = 1, 124 .writeback_max_hscl_taps = 12, 125 .writeback_max_vscl_taps = 12, 126 .writeback_line_buffer_luma_buffer_size = 0, 127 .writeback_line_buffer_chroma_buffer_size = 14643, 128 .cursor_buffer_size = 8, 129 .cursor_chunk_size = 2, 130 .max_num_otg = 6, 131 .max_num_dpp = 6, 132 .max_num_wb = 1, 133 .max_dchub_pscl_bw_pix_per_clk = 4, 134 .max_pscl_lb_bw_pix_per_clk = 2, 135 .max_lb_vscl_bw_pix_per_clk = 4, 136 .max_vscl_hscl_bw_pix_per_clk = 4, 137 .max_hscl_ratio = 8, 138 .max_vscl_ratio = 8, 139 .hscl_mults = 4, 140 .vscl_mults = 4, 141 .max_hscl_taps = 8, 142 .max_vscl_taps = 8, 143 .dispclk_ramp_margin_percent = 1, 144 .underscan_factor = 1.10, 145 .min_vblank_lines = 32, // 146 .dppclk_delay_subtotal = 77, // 147 .dppclk_delay_scl_lb_only = 16, 148 .dppclk_delay_scl = 50, 149 .dppclk_delay_cnvc_formatter = 8, 150 .dppclk_delay_cnvc_cursor = 6, 151 .dispclk_delay_subtotal = 87, // 152 .dcfclk_cstate_latency = 10, // SRExitTime 153 .max_inter_dcn_tile_repeaters = 8, 154 155 .xfc_supported = true, 156 .xfc_fill_bw_overhead_percent = 10.0, 157 .xfc_fill_constant_bytes = 0, 158 }; 159 160 struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = { 161 .odm_capable = 1, 162 .gpuvm_enable = 0, 163 .hostvm_enable = 0, 164 .gpuvm_max_page_table_levels = 4, 165 .hostvm_max_page_table_levels = 4, 166 .hostvm_cached_page_table_levels = 0, 167 .num_dsc = 5, 168 .rob_buffer_size_kbytes = 168, 169 .det_buffer_size_kbytes = 164, 170 .dpte_buffer_size_in_pte_reqs_luma = 84, 171 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo 172 .dpp_output_buffer_pixels = 2560, 173 .opp_output_buffer_lines = 1, 174 .pixel_chunk_size_kbytes = 8, 175 .pte_enable = 1, 176 .max_page_table_levels = 4, 177 .pte_chunk_size_kbytes = 2, 178 .meta_chunk_size_kbytes = 2, 179 .writeback_chunk_size_kbytes = 2, 180 .line_buffer_size_bits = 789504, 181 .is_line_buffer_bpp_fixed = 0, 182 .line_buffer_fixed_bpp = 0, 183 .dcc_supported = true, 184 .max_line_buffer_lines = 12, 185 .writeback_luma_buffer_size_kbytes = 12, 186 .writeback_chroma_buffer_size_kbytes = 8, 187 .writeback_chroma_line_buffer_width_pixels = 4, 188 .writeback_max_hscl_ratio = 1, 189 .writeback_max_vscl_ratio = 1, 190 .writeback_min_hscl_ratio = 1, 191 .writeback_min_vscl_ratio = 1, 192 .writeback_max_hscl_taps = 12, 193 .writeback_max_vscl_taps = 12, 194 .writeback_line_buffer_luma_buffer_size = 0, 195 .writeback_line_buffer_chroma_buffer_size = 14643, 196 .cursor_buffer_size = 8, 197 .cursor_chunk_size = 2, 198 .max_num_otg = 5, 199 .max_num_dpp = 5, 200 .max_num_wb = 1, 201 .max_dchub_pscl_bw_pix_per_clk = 4, 202 .max_pscl_lb_bw_pix_per_clk = 2, 203 .max_lb_vscl_bw_pix_per_clk = 4, 204 .max_vscl_hscl_bw_pix_per_clk = 4, 205 .max_hscl_ratio = 8, 206 .max_vscl_ratio = 8, 207 .hscl_mults = 4, 208 .vscl_mults = 4, 209 .max_hscl_taps = 8, 210 .max_vscl_taps = 8, 211 .dispclk_ramp_margin_percent = 1, 212 .underscan_factor = 1.10, 213 .min_vblank_lines = 32, // 214 .dppclk_delay_subtotal = 77, // 215 .dppclk_delay_scl_lb_only = 16, 216 .dppclk_delay_scl = 50, 217 .dppclk_delay_cnvc_formatter = 8, 218 .dppclk_delay_cnvc_cursor = 6, 219 .dispclk_delay_subtotal = 87, // 220 .dcfclk_cstate_latency = 10, // SRExitTime 221 .max_inter_dcn_tile_repeaters = 8, 222 .xfc_supported = true, 223 .xfc_fill_bw_overhead_percent = 10.0, 224 .xfc_fill_constant_bytes = 0, 225 .ptoi_supported = 0 226 }; 227 228 struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { 229 /* Defaults that get patched on driver load from firmware. */ 230 .clock_limits = { 231 { 232 .state = 0, 233 .dcfclk_mhz = 560.0, 234 .fabricclk_mhz = 560.0, 235 .dispclk_mhz = 513.0, 236 .dppclk_mhz = 513.0, 237 .phyclk_mhz = 540.0, 238 .socclk_mhz = 560.0, 239 .dscclk_mhz = 171.0, 240 .dram_speed_mts = 8960.0, 241 }, 242 { 243 .state = 1, 244 .dcfclk_mhz = 694.0, 245 .fabricclk_mhz = 694.0, 246 .dispclk_mhz = 642.0, 247 .dppclk_mhz = 642.0, 248 .phyclk_mhz = 600.0, 249 .socclk_mhz = 694.0, 250 .dscclk_mhz = 214.0, 251 .dram_speed_mts = 11104.0, 252 }, 253 { 254 .state = 2, 255 .dcfclk_mhz = 875.0, 256 .fabricclk_mhz = 875.0, 257 .dispclk_mhz = 734.0, 258 .dppclk_mhz = 734.0, 259 .phyclk_mhz = 810.0, 260 .socclk_mhz = 875.0, 261 .dscclk_mhz = 245.0, 262 .dram_speed_mts = 14000.0, 263 }, 264 { 265 .state = 3, 266 .dcfclk_mhz = 1000.0, 267 .fabricclk_mhz = 1000.0, 268 .dispclk_mhz = 1100.0, 269 .dppclk_mhz = 1100.0, 270 .phyclk_mhz = 810.0, 271 .socclk_mhz = 1000.0, 272 .dscclk_mhz = 367.0, 273 .dram_speed_mts = 16000.0, 274 }, 275 { 276 .state = 4, 277 .dcfclk_mhz = 1200.0, 278 .fabricclk_mhz = 1200.0, 279 .dispclk_mhz = 1284.0, 280 .dppclk_mhz = 1284.0, 281 .phyclk_mhz = 810.0, 282 .socclk_mhz = 1200.0, 283 .dscclk_mhz = 428.0, 284 .dram_speed_mts = 16000.0, 285 }, 286 /*Extra state, no dispclk ramping*/ 287 { 288 .state = 5, 289 .dcfclk_mhz = 1200.0, 290 .fabricclk_mhz = 1200.0, 291 .dispclk_mhz = 1284.0, 292 .dppclk_mhz = 1284.0, 293 .phyclk_mhz = 810.0, 294 .socclk_mhz = 1200.0, 295 .dscclk_mhz = 428.0, 296 .dram_speed_mts = 16000.0, 297 }, 298 }, 299 .num_states = 5, 300 .sr_exit_time_us = 8.6, 301 .sr_enter_plus_exit_time_us = 10.9, 302 .urgent_latency_us = 4.0, 303 .urgent_latency_pixel_data_only_us = 4.0, 304 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 305 .urgent_latency_vm_data_only_us = 4.0, 306 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 307 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 308 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 309 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0, 310 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0, 311 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 312 .max_avg_sdp_bw_use_normal_percent = 40.0, 313 .max_avg_dram_bw_use_normal_percent = 40.0, 314 .writeback_latency_us = 12.0, 315 .ideal_dram_bw_after_urgent_percent = 40.0, 316 .max_request_size_bytes = 256, 317 .dram_channel_width_bytes = 2, 318 .fabric_datapath_to_dcn_data_return_bytes = 64, 319 .dcn_downspread_percent = 0.5, 320 .downspread_percent = 0.38, 321 .dram_page_open_time_ns = 50.0, 322 .dram_rw_turnaround_time_ns = 17.5, 323 .dram_return_buffer_per_channel_bytes = 8192, 324 .round_trip_ping_latency_dcfclk_cycles = 131, 325 .urgent_out_of_order_return_per_channel_bytes = 256, 326 .channel_interleave_bytes = 256, 327 .num_banks = 8, 328 .num_chans = 16, 329 .vmm_page_size_bytes = 4096, 330 .dram_clock_change_latency_us = 404.0, 331 .dummy_pstate_latency_us = 5.0, 332 .writeback_dram_clock_change_latency_us = 23.0, 333 .return_bus_width_bytes = 64, 334 .dispclk_dppclk_vco_speed_mhz = 3850, 335 .xfc_bus_transport_time_us = 20, 336 .xfc_xbuf_latency_tolerance_us = 4, 337 .use_urgent_burst_bw = 0 338 }; 339 340 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 }; 341 342 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 343 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 344 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 345 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 346 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 347 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 348 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 349 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 350 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 351 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 352 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 353 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 354 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 355 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 356 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 357 #endif 358 359 360 enum dcn20_clk_src_array_id { 361 DCN20_CLK_SRC_PLL0, 362 DCN20_CLK_SRC_PLL1, 363 DCN20_CLK_SRC_PLL2, 364 DCN20_CLK_SRC_PLL3, 365 DCN20_CLK_SRC_PLL4, 366 DCN20_CLK_SRC_PLL5, 367 DCN20_CLK_SRC_TOTAL 368 }; 369 370 /* begin ********************* 371 * macros to expend register list macro defined in HW object header file */ 372 373 /* DCN */ 374 /* TODO awful hack. fixup dcn20_dwb.h */ 375 #undef BASE_INNER 376 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 377 378 #define BASE(seg) BASE_INNER(seg) 379 380 #define SR(reg_name)\ 381 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 382 mm ## reg_name 383 384 #define SRI(reg_name, block, id)\ 385 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 386 mm ## block ## id ## _ ## reg_name 387 388 #define SRIR(var_name, reg_name, block, id)\ 389 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 390 mm ## block ## id ## _ ## reg_name 391 392 #define SRII(reg_name, block, id)\ 393 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 394 mm ## block ## id ## _ ## reg_name 395 396 #define DCCG_SRII(reg_name, block, id)\ 397 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 398 mm ## block ## id ## _ ## reg_name 399 400 /* NBIO */ 401 #define NBIO_BASE_INNER(seg) \ 402 NBIO_BASE__INST0_SEG ## seg 403 404 #define NBIO_BASE(seg) \ 405 NBIO_BASE_INNER(seg) 406 407 #define NBIO_SR(reg_name)\ 408 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 409 mm ## reg_name 410 411 /* MMHUB */ 412 #define MMHUB_BASE_INNER(seg) \ 413 MMHUB_BASE__INST0_SEG ## seg 414 415 #define MMHUB_BASE(seg) \ 416 MMHUB_BASE_INNER(seg) 417 418 #define MMHUB_SR(reg_name)\ 419 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 420 mmMM ## reg_name 421 422 static const struct bios_registers bios_regs = { 423 NBIO_SR(BIOS_SCRATCH_3), 424 NBIO_SR(BIOS_SCRATCH_6) 425 }; 426 427 #define clk_src_regs(index, pllid)\ 428 [index] = {\ 429 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\ 430 } 431 432 static const struct dce110_clk_src_regs clk_src_regs[] = { 433 clk_src_regs(0, A), 434 clk_src_regs(1, B), 435 clk_src_regs(2, C), 436 clk_src_regs(3, D), 437 clk_src_regs(4, E), 438 clk_src_regs(5, F) 439 }; 440 441 static const struct dce110_clk_src_shift cs_shift = { 442 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 443 }; 444 445 static const struct dce110_clk_src_mask cs_mask = { 446 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 447 }; 448 449 static const struct dce_dmcu_registers dmcu_regs = { 450 DMCU_DCN10_REG_LIST() 451 }; 452 453 static const struct dce_dmcu_shift dmcu_shift = { 454 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 455 }; 456 457 static const struct dce_dmcu_mask dmcu_mask = { 458 DMCU_MASK_SH_LIST_DCN10(_MASK) 459 }; 460 461 static const struct dce_abm_registers abm_regs = { 462 ABM_DCN20_REG_LIST() 463 }; 464 465 static const struct dce_abm_shift abm_shift = { 466 ABM_MASK_SH_LIST_DCN20(__SHIFT) 467 }; 468 469 static const struct dce_abm_mask abm_mask = { 470 ABM_MASK_SH_LIST_DCN20(_MASK) 471 }; 472 473 #define audio_regs(id)\ 474 [id] = {\ 475 AUD_COMMON_REG_LIST(id)\ 476 } 477 478 static const struct dce_audio_registers audio_regs[] = { 479 audio_regs(0), 480 audio_regs(1), 481 audio_regs(2), 482 audio_regs(3), 483 audio_regs(4), 484 audio_regs(5), 485 audio_regs(6), 486 }; 487 488 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 489 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 490 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 491 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 492 493 static const struct dce_audio_shift audio_shift = { 494 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 495 }; 496 497 static const struct dce_audio_mask audio_mask = { 498 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 499 }; 500 501 #define stream_enc_regs(id)\ 502 [id] = {\ 503 SE_DCN2_REG_LIST(id)\ 504 } 505 506 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 507 stream_enc_regs(0), 508 stream_enc_regs(1), 509 stream_enc_regs(2), 510 stream_enc_regs(3), 511 stream_enc_regs(4), 512 stream_enc_regs(5), 513 }; 514 515 static const struct dcn10_stream_encoder_shift se_shift = { 516 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) 517 }; 518 519 static const struct dcn10_stream_encoder_mask se_mask = { 520 SE_COMMON_MASK_SH_LIST_DCN20(_MASK) 521 }; 522 523 524 #define aux_regs(id)\ 525 [id] = {\ 526 DCN2_AUX_REG_LIST(id)\ 527 } 528 529 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 530 aux_regs(0), 531 aux_regs(1), 532 aux_regs(2), 533 aux_regs(3), 534 aux_regs(4), 535 aux_regs(5) 536 }; 537 538 #define hpd_regs(id)\ 539 [id] = {\ 540 HPD_REG_LIST(id)\ 541 } 542 543 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 544 hpd_regs(0), 545 hpd_regs(1), 546 hpd_regs(2), 547 hpd_regs(3), 548 hpd_regs(4), 549 hpd_regs(5) 550 }; 551 552 #define link_regs(id, phyid)\ 553 [id] = {\ 554 LE_DCN10_REG_LIST(id), \ 555 UNIPHY_DCN2_REG_LIST(phyid), \ 556 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 557 } 558 559 static const struct dcn10_link_enc_registers link_enc_regs[] = { 560 link_regs(0, A), 561 link_regs(1, B), 562 link_regs(2, C), 563 link_regs(3, D), 564 link_regs(4, E), 565 link_regs(5, F) 566 }; 567 568 static const struct dcn10_link_enc_shift le_shift = { 569 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT) 570 }; 571 572 static const struct dcn10_link_enc_mask le_mask = { 573 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK) 574 }; 575 576 #define ipp_regs(id)\ 577 [id] = {\ 578 IPP_REG_LIST_DCN20(id),\ 579 } 580 581 static const struct dcn10_ipp_registers ipp_regs[] = { 582 ipp_regs(0), 583 ipp_regs(1), 584 ipp_regs(2), 585 ipp_regs(3), 586 ipp_regs(4), 587 ipp_regs(5), 588 }; 589 590 static const struct dcn10_ipp_shift ipp_shift = { 591 IPP_MASK_SH_LIST_DCN20(__SHIFT) 592 }; 593 594 static const struct dcn10_ipp_mask ipp_mask = { 595 IPP_MASK_SH_LIST_DCN20(_MASK), 596 }; 597 598 #define opp_regs(id)\ 599 [id] = {\ 600 OPP_REG_LIST_DCN20(id),\ 601 } 602 603 static const struct dcn20_opp_registers opp_regs[] = { 604 opp_regs(0), 605 opp_regs(1), 606 opp_regs(2), 607 opp_regs(3), 608 opp_regs(4), 609 opp_regs(5), 610 }; 611 612 static const struct dcn20_opp_shift opp_shift = { 613 OPP_MASK_SH_LIST_DCN20(__SHIFT) 614 }; 615 616 static const struct dcn20_opp_mask opp_mask = { 617 OPP_MASK_SH_LIST_DCN20(_MASK) 618 }; 619 620 #define aux_engine_regs(id)\ 621 [id] = {\ 622 AUX_COMMON_REG_LIST0(id), \ 623 .AUXN_IMPCAL = 0, \ 624 .AUXP_IMPCAL = 0, \ 625 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 626 } 627 628 static const struct dce110_aux_registers aux_engine_regs[] = { 629 aux_engine_regs(0), 630 aux_engine_regs(1), 631 aux_engine_regs(2), 632 aux_engine_regs(3), 633 aux_engine_regs(4), 634 aux_engine_regs(5) 635 }; 636 637 #define tf_regs(id)\ 638 [id] = {\ 639 TF_REG_LIST_DCN20(id),\ 640 } 641 642 static const struct dcn2_dpp_registers tf_regs[] = { 643 tf_regs(0), 644 tf_regs(1), 645 tf_regs(2), 646 tf_regs(3), 647 tf_regs(4), 648 tf_regs(5), 649 }; 650 651 static const struct dcn2_dpp_shift tf_shift = { 652 TF_REG_LIST_SH_MASK_DCN20(__SHIFT), 653 TF_DEBUG_REG_LIST_SH_DCN10 654 }; 655 656 static const struct dcn2_dpp_mask tf_mask = { 657 TF_REG_LIST_SH_MASK_DCN20(_MASK), 658 TF_DEBUG_REG_LIST_MASK_DCN10 659 }; 660 661 #define dwbc_regs_dcn2(id)\ 662 [id] = {\ 663 DWBC_COMMON_REG_LIST_DCN2_0(id),\ 664 } 665 666 static const struct dcn20_dwbc_registers dwbc20_regs[] = { 667 dwbc_regs_dcn2(0), 668 }; 669 670 static const struct dcn20_dwbc_shift dwbc20_shift = { 671 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 672 }; 673 674 static const struct dcn20_dwbc_mask dwbc20_mask = { 675 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 676 }; 677 678 #define mcif_wb_regs_dcn2(id)\ 679 [id] = {\ 680 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\ 681 } 682 683 static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = { 684 mcif_wb_regs_dcn2(0), 685 }; 686 687 static const struct dcn20_mmhubbub_shift mcif_wb20_shift = { 688 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 689 }; 690 691 static const struct dcn20_mmhubbub_mask mcif_wb20_mask = { 692 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 693 }; 694 695 static const struct dcn20_mpc_registers mpc_regs = { 696 MPC_REG_LIST_DCN2_0(0), 697 MPC_REG_LIST_DCN2_0(1), 698 MPC_REG_LIST_DCN2_0(2), 699 MPC_REG_LIST_DCN2_0(3), 700 MPC_REG_LIST_DCN2_0(4), 701 MPC_REG_LIST_DCN2_0(5), 702 MPC_OUT_MUX_REG_LIST_DCN2_0(0), 703 MPC_OUT_MUX_REG_LIST_DCN2_0(1), 704 MPC_OUT_MUX_REG_LIST_DCN2_0(2), 705 MPC_OUT_MUX_REG_LIST_DCN2_0(3), 706 MPC_OUT_MUX_REG_LIST_DCN2_0(4), 707 MPC_OUT_MUX_REG_LIST_DCN2_0(5), 708 }; 709 710 static const struct dcn20_mpc_shift mpc_shift = { 711 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 712 }; 713 714 static const struct dcn20_mpc_mask mpc_mask = { 715 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 716 }; 717 718 #define tg_regs(id)\ 719 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)} 720 721 722 static const struct dcn_optc_registers tg_regs[] = { 723 tg_regs(0), 724 tg_regs(1), 725 tg_regs(2), 726 tg_regs(3), 727 tg_regs(4), 728 tg_regs(5) 729 }; 730 731 static const struct dcn_optc_shift tg_shift = { 732 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 733 }; 734 735 static const struct dcn_optc_mask tg_mask = { 736 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 737 }; 738 739 #define hubp_regs(id)\ 740 [id] = {\ 741 HUBP_REG_LIST_DCN20(id)\ 742 } 743 744 static const struct dcn_hubp2_registers hubp_regs[] = { 745 hubp_regs(0), 746 hubp_regs(1), 747 hubp_regs(2), 748 hubp_regs(3), 749 hubp_regs(4), 750 hubp_regs(5) 751 }; 752 753 static const struct dcn_hubp2_shift hubp_shift = { 754 HUBP_MASK_SH_LIST_DCN20(__SHIFT) 755 }; 756 757 static const struct dcn_hubp2_mask hubp_mask = { 758 HUBP_MASK_SH_LIST_DCN20(_MASK) 759 }; 760 761 static const struct dcn_hubbub_registers hubbub_reg = { 762 HUBBUB_REG_LIST_DCN20(0) 763 }; 764 765 static const struct dcn_hubbub_shift hubbub_shift = { 766 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT) 767 }; 768 769 static const struct dcn_hubbub_mask hubbub_mask = { 770 HUBBUB_MASK_SH_LIST_DCN20(_MASK) 771 }; 772 773 #define vmid_regs(id)\ 774 [id] = {\ 775 DCN20_VMID_REG_LIST(id)\ 776 } 777 778 static const struct dcn_vmid_registers vmid_regs[] = { 779 vmid_regs(0), 780 vmid_regs(1), 781 vmid_regs(2), 782 vmid_regs(3), 783 vmid_regs(4), 784 vmid_regs(5), 785 vmid_regs(6), 786 vmid_regs(7), 787 vmid_regs(8), 788 vmid_regs(9), 789 vmid_regs(10), 790 vmid_regs(11), 791 vmid_regs(12), 792 vmid_regs(13), 793 vmid_regs(14), 794 vmid_regs(15) 795 }; 796 797 static const struct dcn20_vmid_shift vmid_shifts = { 798 DCN20_VMID_MASK_SH_LIST(__SHIFT) 799 }; 800 801 static const struct dcn20_vmid_mask vmid_masks = { 802 DCN20_VMID_MASK_SH_LIST(_MASK) 803 }; 804 805 static const struct dce110_aux_registers_shift aux_shift = { 806 DCN_AUX_MASK_SH_LIST(__SHIFT) 807 }; 808 809 static const struct dce110_aux_registers_mask aux_mask = { 810 DCN_AUX_MASK_SH_LIST(_MASK) 811 }; 812 813 static int map_transmitter_id_to_phy_instance( 814 enum transmitter transmitter) 815 { 816 switch (transmitter) { 817 case TRANSMITTER_UNIPHY_A: 818 return 0; 819 break; 820 case TRANSMITTER_UNIPHY_B: 821 return 1; 822 break; 823 case TRANSMITTER_UNIPHY_C: 824 return 2; 825 break; 826 case TRANSMITTER_UNIPHY_D: 827 return 3; 828 break; 829 case TRANSMITTER_UNIPHY_E: 830 return 4; 831 break; 832 case TRANSMITTER_UNIPHY_F: 833 return 5; 834 break; 835 default: 836 ASSERT(0); 837 return 0; 838 } 839 } 840 841 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 842 #define dsc_regsDCN20(id)\ 843 [id] = {\ 844 DSC_REG_LIST_DCN20(id)\ 845 } 846 847 static const struct dcn20_dsc_registers dsc_regs[] = { 848 dsc_regsDCN20(0), 849 dsc_regsDCN20(1), 850 dsc_regsDCN20(2), 851 dsc_regsDCN20(3), 852 dsc_regsDCN20(4), 853 dsc_regsDCN20(5) 854 }; 855 856 static const struct dcn20_dsc_shift dsc_shift = { 857 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 858 }; 859 860 static const struct dcn20_dsc_mask dsc_mask = { 861 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 862 }; 863 #endif 864 865 static const struct dccg_registers dccg_regs = { 866 DCCG_REG_LIST_DCN2() 867 }; 868 869 static const struct dccg_shift dccg_shift = { 870 DCCG_MASK_SH_LIST_DCN2(__SHIFT) 871 }; 872 873 static const struct dccg_mask dccg_mask = { 874 DCCG_MASK_SH_LIST_DCN2(_MASK) 875 }; 876 877 static const struct resource_caps res_cap_nv10 = { 878 .num_timing_generator = 6, 879 .num_opp = 6, 880 .num_video_plane = 6, 881 .num_audio = 7, 882 .num_stream_encoder = 6, 883 .num_pll = 6, 884 .num_dwb = 1, 885 .num_ddc = 6, 886 .num_vmid = 16, 887 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 888 .num_dsc = 6, 889 #endif 890 }; 891 892 static const struct dc_plane_cap plane_cap = { 893 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 894 .blends_with_above = true, 895 .blends_with_below = true, 896 .per_pixel_alpha = true, 897 898 .pixel_format_support = { 899 .argb8888 = true, 900 .nv12 = true, 901 .fp16 = true 902 }, 903 904 .max_upscale_factor = { 905 .argb8888 = 16000, 906 .nv12 = 16000, 907 .fp16 = 1 908 }, 909 910 .max_downscale_factor = { 911 .argb8888 = 250, 912 .nv12 = 250, 913 .fp16 = 1 914 } 915 }; 916 static const struct resource_caps res_cap_nv14 = { 917 .num_timing_generator = 5, 918 .num_opp = 5, 919 .num_video_plane = 5, 920 .num_audio = 6, 921 .num_stream_encoder = 5, 922 .num_pll = 5, 923 .num_dwb = 1, 924 .num_ddc = 5, 925 .num_vmid = 16, 926 .num_dsc = 5, 927 }; 928 929 static const struct dc_debug_options debug_defaults_drv = { 930 .disable_dmcu = true, 931 .force_abm_enable = false, 932 .timing_trace = false, 933 .clock_trace = true, 934 .disable_pplib_clock_request = true, 935 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 936 .force_single_disp_pipe_split = false, 937 .disable_dcc = DCC_ENABLE, 938 .vsr_support = true, 939 .performance_trace = false, 940 .max_downscale_src_width = 5120,/*upto 5K*/ 941 .disable_pplib_wm_range = false, 942 .scl_reset_length10 = true, 943 .sanity_checks = false, 944 .disable_tri_buf = true, 945 .underflow_assert_delay_us = 0xFFFFFFFF, 946 }; 947 948 static const struct dc_debug_options debug_defaults_diags = { 949 .disable_dmcu = true, 950 .force_abm_enable = false, 951 .timing_trace = true, 952 .clock_trace = true, 953 .disable_dpp_power_gate = true, 954 .disable_hubp_power_gate = true, 955 .disable_clock_gate = true, 956 .disable_pplib_clock_request = true, 957 .disable_pplib_wm_range = true, 958 .disable_stutter = true, 959 .scl_reset_length10 = true, 960 .underflow_assert_delay_us = 0xFFFFFFFF, 961 }; 962 963 void dcn20_dpp_destroy(struct dpp **dpp) 964 { 965 kfree(TO_DCN20_DPP(*dpp)); 966 *dpp = NULL; 967 } 968 969 struct dpp *dcn20_dpp_create( 970 struct dc_context *ctx, 971 uint32_t inst) 972 { 973 struct dcn20_dpp *dpp = 974 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL); 975 976 if (!dpp) 977 return NULL; 978 979 if (dpp2_construct(dpp, ctx, inst, 980 &tf_regs[inst], &tf_shift, &tf_mask)) 981 return &dpp->base; 982 983 BREAK_TO_DEBUGGER(); 984 kfree(dpp); 985 return NULL; 986 } 987 988 struct input_pixel_processor *dcn20_ipp_create( 989 struct dc_context *ctx, uint32_t inst) 990 { 991 struct dcn10_ipp *ipp = 992 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 993 994 if (!ipp) { 995 BREAK_TO_DEBUGGER(); 996 return NULL; 997 } 998 999 dcn20_ipp_construct(ipp, ctx, inst, 1000 &ipp_regs[inst], &ipp_shift, &ipp_mask); 1001 return &ipp->base; 1002 } 1003 1004 1005 struct output_pixel_processor *dcn20_opp_create( 1006 struct dc_context *ctx, uint32_t inst) 1007 { 1008 struct dcn20_opp *opp = 1009 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1010 1011 if (!opp) { 1012 BREAK_TO_DEBUGGER(); 1013 return NULL; 1014 } 1015 1016 dcn20_opp_construct(opp, ctx, inst, 1017 &opp_regs[inst], &opp_shift, &opp_mask); 1018 return &opp->base; 1019 } 1020 1021 struct dce_aux *dcn20_aux_engine_create( 1022 struct dc_context *ctx, 1023 uint32_t inst) 1024 { 1025 struct aux_engine_dce110 *aux_engine = 1026 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 1027 1028 if (!aux_engine) 1029 return NULL; 1030 1031 dce110_aux_engine_construct(aux_engine, ctx, inst, 1032 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1033 &aux_engine_regs[inst], 1034 &aux_mask, 1035 &aux_shift, 1036 ctx->dc->caps.extended_aux_timeout_support); 1037 1038 return &aux_engine->base; 1039 } 1040 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 1041 1042 static const struct dce_i2c_registers i2c_hw_regs[] = { 1043 i2c_inst_regs(1), 1044 i2c_inst_regs(2), 1045 i2c_inst_regs(3), 1046 i2c_inst_regs(4), 1047 i2c_inst_regs(5), 1048 i2c_inst_regs(6), 1049 }; 1050 1051 static const struct dce_i2c_shift i2c_shifts = { 1052 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 1053 }; 1054 1055 static const struct dce_i2c_mask i2c_masks = { 1056 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 1057 }; 1058 1059 struct dce_i2c_hw *dcn20_i2c_hw_create( 1060 struct dc_context *ctx, 1061 uint32_t inst) 1062 { 1063 struct dce_i2c_hw *dce_i2c_hw = 1064 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1065 1066 if (!dce_i2c_hw) 1067 return NULL; 1068 1069 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1070 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1071 1072 return dce_i2c_hw; 1073 } 1074 struct mpc *dcn20_mpc_create(struct dc_context *ctx) 1075 { 1076 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), 1077 GFP_KERNEL); 1078 1079 if (!mpc20) 1080 return NULL; 1081 1082 dcn20_mpc_construct(mpc20, ctx, 1083 &mpc_regs, 1084 &mpc_shift, 1085 &mpc_mask, 1086 6); 1087 1088 return &mpc20->base; 1089 } 1090 1091 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx) 1092 { 1093 int i; 1094 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), 1095 GFP_KERNEL); 1096 1097 if (!hubbub) 1098 return NULL; 1099 1100 hubbub2_construct(hubbub, ctx, 1101 &hubbub_reg, 1102 &hubbub_shift, 1103 &hubbub_mask); 1104 1105 for (i = 0; i < res_cap_nv10.num_vmid; i++) { 1106 struct dcn20_vmid *vmid = &hubbub->vmid[i]; 1107 1108 vmid->ctx = ctx; 1109 1110 vmid->regs = &vmid_regs[i]; 1111 vmid->shifts = &vmid_shifts; 1112 vmid->masks = &vmid_masks; 1113 } 1114 1115 return &hubbub->base; 1116 } 1117 1118 struct timing_generator *dcn20_timing_generator_create( 1119 struct dc_context *ctx, 1120 uint32_t instance) 1121 { 1122 struct optc *tgn10 = 1123 kzalloc(sizeof(struct optc), GFP_KERNEL); 1124 1125 if (!tgn10) 1126 return NULL; 1127 1128 tgn10->base.inst = instance; 1129 tgn10->base.ctx = ctx; 1130 1131 tgn10->tg_regs = &tg_regs[instance]; 1132 tgn10->tg_shift = &tg_shift; 1133 tgn10->tg_mask = &tg_mask; 1134 1135 dcn20_timing_generator_init(tgn10); 1136 1137 return &tgn10->base; 1138 } 1139 1140 static const struct encoder_feature_support link_enc_feature = { 1141 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1142 .max_hdmi_pixel_clock = 600000, 1143 .hdmi_ycbcr420_supported = true, 1144 .dp_ycbcr420_supported = true, 1145 .flags.bits.IS_HBR2_CAPABLE = true, 1146 .flags.bits.IS_HBR3_CAPABLE = true, 1147 .flags.bits.IS_TPS3_CAPABLE = true, 1148 .flags.bits.IS_TPS4_CAPABLE = true 1149 }; 1150 1151 struct link_encoder *dcn20_link_encoder_create( 1152 const struct encoder_init_data *enc_init_data) 1153 { 1154 struct dcn20_link_encoder *enc20 = 1155 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1156 int link_regs_id; 1157 1158 if (!enc20) 1159 return NULL; 1160 1161 link_regs_id = 1162 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 1163 1164 dcn20_link_encoder_construct(enc20, 1165 enc_init_data, 1166 &link_enc_feature, 1167 &link_enc_regs[link_regs_id], 1168 &link_enc_aux_regs[enc_init_data->channel - 1], 1169 &link_enc_hpd_regs[enc_init_data->hpd_source], 1170 &le_shift, 1171 &le_mask); 1172 1173 return &enc20->enc10.base; 1174 } 1175 1176 struct clock_source *dcn20_clock_source_create( 1177 struct dc_context *ctx, 1178 struct dc_bios *bios, 1179 enum clock_source_id id, 1180 const struct dce110_clk_src_regs *regs, 1181 bool dp_clk_src) 1182 { 1183 struct dce110_clk_src *clk_src = 1184 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1185 1186 if (!clk_src) 1187 return NULL; 1188 1189 if (dcn20_clk_src_construct(clk_src, ctx, bios, id, 1190 regs, &cs_shift, &cs_mask)) { 1191 clk_src->base.dp_clk_src = dp_clk_src; 1192 return &clk_src->base; 1193 } 1194 1195 kfree(clk_src); 1196 BREAK_TO_DEBUGGER(); 1197 return NULL; 1198 } 1199 1200 static void read_dce_straps( 1201 struct dc_context *ctx, 1202 struct resource_straps *straps) 1203 { 1204 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1205 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1206 } 1207 1208 static struct audio *dcn20_create_audio( 1209 struct dc_context *ctx, unsigned int inst) 1210 { 1211 return dce_audio_create(ctx, inst, 1212 &audio_regs[inst], &audio_shift, &audio_mask); 1213 } 1214 1215 struct stream_encoder *dcn20_stream_encoder_create( 1216 enum engine_id eng_id, 1217 struct dc_context *ctx) 1218 { 1219 struct dcn10_stream_encoder *enc1 = 1220 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1221 1222 if (!enc1) 1223 return NULL; 1224 1225 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) { 1226 if (eng_id >= ENGINE_ID_DIGD) 1227 eng_id++; 1228 } 1229 1230 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1231 &stream_enc_regs[eng_id], 1232 &se_shift, &se_mask); 1233 1234 return &enc1->base; 1235 } 1236 1237 static const struct dce_hwseq_registers hwseq_reg = { 1238 HWSEQ_DCN2_REG_LIST() 1239 }; 1240 1241 static const struct dce_hwseq_shift hwseq_shift = { 1242 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT) 1243 }; 1244 1245 static const struct dce_hwseq_mask hwseq_mask = { 1246 HWSEQ_DCN2_MASK_SH_LIST(_MASK) 1247 }; 1248 1249 struct dce_hwseq *dcn20_hwseq_create( 1250 struct dc_context *ctx) 1251 { 1252 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1253 1254 if (hws) { 1255 hws->ctx = ctx; 1256 hws->regs = &hwseq_reg; 1257 hws->shifts = &hwseq_shift; 1258 hws->masks = &hwseq_mask; 1259 } 1260 return hws; 1261 } 1262 1263 static const struct resource_create_funcs res_create_funcs = { 1264 .read_dce_straps = read_dce_straps, 1265 .create_audio = dcn20_create_audio, 1266 .create_stream_encoder = dcn20_stream_encoder_create, 1267 .create_hwseq = dcn20_hwseq_create, 1268 }; 1269 1270 static const struct resource_create_funcs res_create_maximus_funcs = { 1271 .read_dce_straps = NULL, 1272 .create_audio = NULL, 1273 .create_stream_encoder = NULL, 1274 .create_hwseq = dcn20_hwseq_create, 1275 }; 1276 1277 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu); 1278 1279 void dcn20_clock_source_destroy(struct clock_source **clk_src) 1280 { 1281 kfree(TO_DCE110_CLK_SRC(*clk_src)); 1282 *clk_src = NULL; 1283 } 1284 1285 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1286 1287 struct display_stream_compressor *dcn20_dsc_create( 1288 struct dc_context *ctx, uint32_t inst) 1289 { 1290 struct dcn20_dsc *dsc = 1291 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1292 1293 if (!dsc) { 1294 BREAK_TO_DEBUGGER(); 1295 return NULL; 1296 } 1297 1298 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1299 return &dsc->base; 1300 } 1301 1302 void dcn20_dsc_destroy(struct display_stream_compressor **dsc) 1303 { 1304 kfree(container_of(*dsc, struct dcn20_dsc, base)); 1305 *dsc = NULL; 1306 } 1307 1308 #endif 1309 1310 static void destruct(struct dcn20_resource_pool *pool) 1311 { 1312 unsigned int i; 1313 1314 for (i = 0; i < pool->base.stream_enc_count; i++) { 1315 if (pool->base.stream_enc[i] != NULL) { 1316 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1317 pool->base.stream_enc[i] = NULL; 1318 } 1319 } 1320 1321 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1322 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1323 if (pool->base.dscs[i] != NULL) 1324 dcn20_dsc_destroy(&pool->base.dscs[i]); 1325 } 1326 #endif 1327 1328 if (pool->base.mpc != NULL) { 1329 kfree(TO_DCN20_MPC(pool->base.mpc)); 1330 pool->base.mpc = NULL; 1331 } 1332 if (pool->base.hubbub != NULL) { 1333 kfree(pool->base.hubbub); 1334 pool->base.hubbub = NULL; 1335 } 1336 for (i = 0; i < pool->base.pipe_count; i++) { 1337 if (pool->base.dpps[i] != NULL) 1338 dcn20_dpp_destroy(&pool->base.dpps[i]); 1339 1340 if (pool->base.ipps[i] != NULL) 1341 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1342 1343 if (pool->base.hubps[i] != NULL) { 1344 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1345 pool->base.hubps[i] = NULL; 1346 } 1347 1348 if (pool->base.irqs != NULL) { 1349 dal_irq_service_destroy(&pool->base.irqs); 1350 } 1351 } 1352 1353 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1354 if (pool->base.engines[i] != NULL) 1355 dce110_engine_destroy(&pool->base.engines[i]); 1356 if (pool->base.hw_i2cs[i] != NULL) { 1357 kfree(pool->base.hw_i2cs[i]); 1358 pool->base.hw_i2cs[i] = NULL; 1359 } 1360 if (pool->base.sw_i2cs[i] != NULL) { 1361 kfree(pool->base.sw_i2cs[i]); 1362 pool->base.sw_i2cs[i] = NULL; 1363 } 1364 } 1365 1366 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1367 if (pool->base.opps[i] != NULL) 1368 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1369 } 1370 1371 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1372 if (pool->base.timing_generators[i] != NULL) { 1373 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1374 pool->base.timing_generators[i] = NULL; 1375 } 1376 } 1377 1378 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1379 if (pool->base.dwbc[i] != NULL) { 1380 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); 1381 pool->base.dwbc[i] = NULL; 1382 } 1383 if (pool->base.mcif_wb[i] != NULL) { 1384 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); 1385 pool->base.mcif_wb[i] = NULL; 1386 } 1387 } 1388 1389 for (i = 0; i < pool->base.audio_count; i++) { 1390 if (pool->base.audios[i]) 1391 dce_aud_destroy(&pool->base.audios[i]); 1392 } 1393 1394 for (i = 0; i < pool->base.clk_src_count; i++) { 1395 if (pool->base.clock_sources[i] != NULL) { 1396 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1397 pool->base.clock_sources[i] = NULL; 1398 } 1399 } 1400 1401 if (pool->base.dp_clock_source != NULL) { 1402 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1403 pool->base.dp_clock_source = NULL; 1404 } 1405 1406 1407 if (pool->base.abm != NULL) 1408 dce_abm_destroy(&pool->base.abm); 1409 1410 if (pool->base.dmcu != NULL) 1411 dce_dmcu_destroy(&pool->base.dmcu); 1412 1413 if (pool->base.dccg != NULL) 1414 dcn_dccg_destroy(&pool->base.dccg); 1415 1416 if (pool->base.pp_smu != NULL) 1417 dcn20_pp_smu_destroy(&pool->base.pp_smu); 1418 1419 } 1420 1421 struct hubp *dcn20_hubp_create( 1422 struct dc_context *ctx, 1423 uint32_t inst) 1424 { 1425 struct dcn20_hubp *hubp2 = 1426 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1427 1428 if (!hubp2) 1429 return NULL; 1430 1431 if (hubp2_construct(hubp2, ctx, inst, 1432 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1433 return &hubp2->base; 1434 1435 BREAK_TO_DEBUGGER(); 1436 kfree(hubp2); 1437 return NULL; 1438 } 1439 1440 static void get_pixel_clock_parameters( 1441 struct pipe_ctx *pipe_ctx, 1442 struct pixel_clk_params *pixel_clk_params) 1443 { 1444 const struct dc_stream_state *stream = pipe_ctx->stream; 1445 struct pipe_ctx *odm_pipe; 1446 int opp_cnt = 1; 1447 1448 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1449 opp_cnt++; 1450 1451 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 1452 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 1453 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 1454 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 1455 /* TODO: un-hardcode*/ 1456 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 1457 LINK_RATE_REF_FREQ_IN_KHZ; 1458 pixel_clk_params->flags.ENABLE_SS = 0; 1459 pixel_clk_params->color_depth = 1460 stream->timing.display_color_depth; 1461 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 1462 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 1463 1464 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1465 pixel_clk_params->color_depth = COLOR_DEPTH_888; 1466 1467 if (opp_cnt == 4) 1468 pixel_clk_params->requested_pix_clk_100hz /= 4; 1469 else if (optc1_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2) 1470 pixel_clk_params->requested_pix_clk_100hz /= 2; 1471 1472 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1473 pixel_clk_params->requested_pix_clk_100hz *= 2; 1474 1475 } 1476 1477 static void build_clamping_params(struct dc_stream_state *stream) 1478 { 1479 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1480 stream->clamping.c_depth = stream->timing.display_color_depth; 1481 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1482 } 1483 1484 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1485 { 1486 1487 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1488 1489 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1490 pipe_ctx->clock_source, 1491 &pipe_ctx->stream_res.pix_clk_params, 1492 &pipe_ctx->pll_settings); 1493 1494 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1495 1496 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1497 &pipe_ctx->stream->bit_depth_params); 1498 build_clamping_params(pipe_ctx->stream); 1499 1500 return DC_OK; 1501 } 1502 1503 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream) 1504 { 1505 enum dc_status status = DC_OK; 1506 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1507 1508 /*TODO Seems unneeded anymore */ 1509 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) { 1510 if (stream != NULL && old_context->streams[i] != NULL) { 1511 todo: shouldn't have to copy missing parameter here 1512 resource_build_bit_depth_reduction_params(stream, 1513 &stream->bit_depth_params); 1514 stream->clamping.pixel_encoding = 1515 stream->timing.pixel_encoding; 1516 1517 resource_build_bit_depth_reduction_params(stream, 1518 &stream->bit_depth_params); 1519 build_clamping_params(stream); 1520 1521 continue; 1522 } 1523 } 1524 */ 1525 1526 if (!pipe_ctx) 1527 return DC_ERROR_UNEXPECTED; 1528 1529 1530 status = build_pipe_hw_param(pipe_ctx); 1531 1532 return status; 1533 } 1534 1535 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1536 1537 static void acquire_dsc(struct resource_context *res_ctx, 1538 const struct resource_pool *pool, 1539 struct display_stream_compressor **dsc) 1540 { 1541 int i; 1542 1543 ASSERT(*dsc == NULL); 1544 *dsc = NULL; 1545 1546 /* Find first free DSC */ 1547 for (i = 0; i < pool->res_cap->num_dsc; i++) 1548 if (!res_ctx->is_dsc_acquired[i]) { 1549 *dsc = pool->dscs[i]; 1550 res_ctx->is_dsc_acquired[i] = true; 1551 break; 1552 } 1553 } 1554 1555 static void release_dsc(struct resource_context *res_ctx, 1556 const struct resource_pool *pool, 1557 struct display_stream_compressor **dsc) 1558 { 1559 int i; 1560 1561 for (i = 0; i < pool->res_cap->num_dsc; i++) 1562 if (pool->dscs[i] == *dsc) { 1563 res_ctx->is_dsc_acquired[i] = false; 1564 *dsc = NULL; 1565 break; 1566 } 1567 } 1568 1569 #endif 1570 1571 1572 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1573 static enum dc_status add_dsc_to_stream_resource(struct dc *dc, 1574 struct dc_state *dc_ctx, 1575 struct dc_stream_state *dc_stream) 1576 { 1577 enum dc_status result = DC_OK; 1578 int i; 1579 const struct resource_pool *pool = dc->res_pool; 1580 1581 /* Get a DSC if required and available */ 1582 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1583 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i]; 1584 1585 if (pipe_ctx->stream != dc_stream) 1586 continue; 1587 1588 acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc); 1589 1590 /* The number of DSCs can be less than the number of pipes */ 1591 if (!pipe_ctx->stream_res.dsc) { 1592 dm_output_to_console("No DSCs available\n"); 1593 result = DC_NO_DSC_RESOURCE; 1594 } 1595 1596 break; 1597 } 1598 1599 return result; 1600 } 1601 1602 1603 static enum dc_status remove_dsc_from_stream_resource(struct dc *dc, 1604 struct dc_state *new_ctx, 1605 struct dc_stream_state *dc_stream) 1606 { 1607 struct pipe_ctx *pipe_ctx = NULL; 1608 int i; 1609 1610 for (i = 0; i < MAX_PIPES; i++) { 1611 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { 1612 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; 1613 1614 if (pipe_ctx->stream_res.dsc) 1615 release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); 1616 } 1617 } 1618 1619 if (!pipe_ctx) 1620 return DC_ERROR_UNEXPECTED; 1621 else 1622 return DC_OK; 1623 } 1624 #endif 1625 1626 1627 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) 1628 { 1629 enum dc_status result = DC_ERROR_UNEXPECTED; 1630 1631 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1632 1633 if (result == DC_OK) 1634 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1635 1636 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1637 /* Get a DSC if required and available */ 1638 if (result == DC_OK && dc_stream->timing.flags.DSC) 1639 result = add_dsc_to_stream_resource(dc, new_ctx, dc_stream); 1640 #endif 1641 1642 if (result == DC_OK) 1643 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream); 1644 1645 return result; 1646 } 1647 1648 1649 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) 1650 { 1651 enum dc_status result = DC_OK; 1652 1653 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1654 result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream); 1655 #endif 1656 1657 return result; 1658 } 1659 1660 1661 static void swizzle_to_dml_params( 1662 enum swizzle_mode_values swizzle, 1663 unsigned int *sw_mode) 1664 { 1665 switch (swizzle) { 1666 case DC_SW_LINEAR: 1667 *sw_mode = dm_sw_linear; 1668 break; 1669 case DC_SW_4KB_S: 1670 *sw_mode = dm_sw_4kb_s; 1671 break; 1672 case DC_SW_4KB_S_X: 1673 *sw_mode = dm_sw_4kb_s_x; 1674 break; 1675 case DC_SW_4KB_D: 1676 *sw_mode = dm_sw_4kb_d; 1677 break; 1678 case DC_SW_4KB_D_X: 1679 *sw_mode = dm_sw_4kb_d_x; 1680 break; 1681 case DC_SW_64KB_S: 1682 *sw_mode = dm_sw_64kb_s; 1683 break; 1684 case DC_SW_64KB_S_X: 1685 *sw_mode = dm_sw_64kb_s_x; 1686 break; 1687 case DC_SW_64KB_S_T: 1688 *sw_mode = dm_sw_64kb_s_t; 1689 break; 1690 case DC_SW_64KB_D: 1691 *sw_mode = dm_sw_64kb_d; 1692 break; 1693 case DC_SW_64KB_D_X: 1694 *sw_mode = dm_sw_64kb_d_x; 1695 break; 1696 case DC_SW_64KB_D_T: 1697 *sw_mode = dm_sw_64kb_d_t; 1698 break; 1699 case DC_SW_64KB_R_X: 1700 *sw_mode = dm_sw_64kb_r_x; 1701 break; 1702 case DC_SW_VAR_S: 1703 *sw_mode = dm_sw_var_s; 1704 break; 1705 case DC_SW_VAR_S_X: 1706 *sw_mode = dm_sw_var_s_x; 1707 break; 1708 case DC_SW_VAR_D: 1709 *sw_mode = dm_sw_var_d; 1710 break; 1711 case DC_SW_VAR_D_X: 1712 *sw_mode = dm_sw_var_d_x; 1713 break; 1714 1715 default: 1716 ASSERT(0); /* Not supported */ 1717 break; 1718 } 1719 } 1720 1721 bool dcn20_split_stream_for_odm( 1722 struct resource_context *res_ctx, 1723 const struct resource_pool *pool, 1724 struct pipe_ctx *prev_odm_pipe, 1725 struct pipe_ctx *next_odm_pipe) 1726 { 1727 int pipe_idx = next_odm_pipe->pipe_idx; 1728 1729 *next_odm_pipe = *prev_odm_pipe; 1730 1731 next_odm_pipe->pipe_idx = pipe_idx; 1732 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; 1733 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; 1734 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; 1735 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; 1736 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; 1737 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; 1738 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1739 next_odm_pipe->stream_res.dsc = NULL; 1740 #endif 1741 if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) { 1742 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe; 1743 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe; 1744 } 1745 prev_odm_pipe->next_odm_pipe = next_odm_pipe; 1746 next_odm_pipe->prev_odm_pipe = prev_odm_pipe; 1747 ASSERT(next_odm_pipe->top_pipe == NULL); 1748 1749 if (prev_odm_pipe->plane_state) { 1750 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; 1751 int new_width; 1752 1753 /* HACTIVE halved for odm combine */ 1754 sd->h_active /= 2; 1755 /* Calculate new vp and recout for left pipe */ 1756 /* Need at least 16 pixels width per side */ 1757 if (sd->recout.x + 16 >= sd->h_active) 1758 return false; 1759 new_width = sd->h_active - sd->recout.x; 1760 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1761 sd->ratios.horz, sd->recout.width - new_width)); 1762 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1763 sd->ratios.horz_c, sd->recout.width - new_width)); 1764 sd->recout.width = new_width; 1765 1766 /* Calculate new vp and recout for right pipe */ 1767 sd = &next_odm_pipe->plane_res.scl_data; 1768 /* HACTIVE halved for odm combine */ 1769 sd->h_active /= 2; 1770 /* Need at least 16 pixels width per side */ 1771 if (new_width <= 16) 1772 return false; 1773 new_width = sd->recout.width + sd->recout.x - sd->h_active; 1774 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1775 sd->ratios.horz, sd->recout.width - new_width)); 1776 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1777 sd->ratios.horz_c, sd->recout.width - new_width)); 1778 sd->recout.width = new_width; 1779 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int( 1780 sd->ratios.horz, sd->h_active - sd->recout.x)); 1781 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int( 1782 sd->ratios.horz_c, sd->h_active - sd->recout.x)); 1783 sd->recout.x = 0; 1784 } 1785 next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; 1786 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1787 if (next_odm_pipe->stream->timing.flags.DSC == 1) { 1788 acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc); 1789 ASSERT(next_odm_pipe->stream_res.dsc); 1790 if (next_odm_pipe->stream_res.dsc == NULL) 1791 return false; 1792 } 1793 #endif 1794 1795 return true; 1796 } 1797 1798 void dcn20_split_stream_for_mpc( 1799 struct resource_context *res_ctx, 1800 const struct resource_pool *pool, 1801 struct pipe_ctx *primary_pipe, 1802 struct pipe_ctx *secondary_pipe) 1803 { 1804 int pipe_idx = secondary_pipe->pipe_idx; 1805 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe; 1806 1807 *secondary_pipe = *primary_pipe; 1808 secondary_pipe->bottom_pipe = sec_bot_pipe; 1809 1810 secondary_pipe->pipe_idx = pipe_idx; 1811 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; 1812 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; 1813 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; 1814 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; 1815 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; 1816 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; 1817 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1818 secondary_pipe->stream_res.dsc = NULL; 1819 #endif 1820 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { 1821 ASSERT(!secondary_pipe->bottom_pipe); 1822 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; 1823 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe; 1824 } 1825 primary_pipe->bottom_pipe = secondary_pipe; 1826 secondary_pipe->top_pipe = primary_pipe; 1827 1828 ASSERT(primary_pipe->plane_state); 1829 resource_build_scaling_params(primary_pipe); 1830 resource_build_scaling_params(secondary_pipe); 1831 } 1832 1833 void dcn20_populate_dml_writeback_from_context( 1834 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) 1835 { 1836 int pipe_cnt, i; 1837 1838 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1839 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; 1840 1841 if (!res_ctx->pipe_ctx[i].stream) 1842 continue; 1843 1844 /* Set writeback information */ 1845 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; 1846 pipes[pipe_cnt].dout.num_active_wb++; 1847 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; 1848 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; 1849 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; 1850 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; 1851 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1; 1852 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1; 1853 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c; 1854 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c; 1855 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0; 1856 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0; 1857 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) { 1858 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) 1859 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8; 1860 else 1861 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10; 1862 } else 1863 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32; 1864 1865 pipe_cnt++; 1866 } 1867 1868 } 1869 1870 int dcn20_populate_dml_pipes_from_context( 1871 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) 1872 { 1873 int pipe_cnt, i; 1874 bool synchronized_vblank = true; 1875 1876 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) { 1877 if (!res_ctx->pipe_ctx[i].stream) 1878 continue; 1879 1880 if (pipe_cnt < 0) { 1881 pipe_cnt = i; 1882 continue; 1883 } 1884 if (dc->debug.disable_timing_sync || !resource_are_streams_timing_synchronizable( 1885 res_ctx->pipe_ctx[pipe_cnt].stream, 1886 res_ctx->pipe_ctx[i].stream)) { 1887 synchronized_vblank = false; 1888 break; 1889 } 1890 } 1891 1892 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1893 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing; 1894 int output_bpc; 1895 1896 if (!res_ctx->pipe_ctx[i].stream) 1897 continue; 1898 /* todo: 1899 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0; 1900 pipes[pipe_cnt].pipe.src.dcc = 0; 1901 pipes[pipe_cnt].pipe.src.vm = 0;*/ 1902 1903 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1904 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC; 1905 /* todo: rotation?*/ 1906 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; 1907 #endif 1908 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) { 1909 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true; 1910 /* 1/2 vblank */ 1911 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active = 1912 (timing->v_total - timing->v_addressable 1913 - timing->v_border_top - timing->v_border_bottom) / 2; 1914 /* 36 bytes dp, 32 hdmi */ 1915 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes = 1916 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32; 1917 } 1918 pipes[pipe_cnt].pipe.src.dcc = false; 1919 pipes[pipe_cnt].pipe.src.dcc_rate = 1; 1920 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank; 1921 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch; 1922 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start 1923 - timing->h_addressable 1924 - timing->h_border_left 1925 - timing->h_border_right; 1926 pipes[pipe_cnt].pipe.dest.vblank_start = timing->v_total - timing->v_front_porch; 1927 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start 1928 - timing->v_addressable 1929 - timing->v_border_top 1930 - timing->v_border_bottom; 1931 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total; 1932 pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total; 1933 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable; 1934 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable; 1935 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE; 1936 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0; 1937 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1938 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2; 1939 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst; 1940 pipes[pipe_cnt].dout.dp_lanes = 4; 1941 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min; 1942 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max; 1943 pipes[pipe_cnt].pipe.dest.odm_combine = res_ctx->pipe_ctx[i].prev_odm_pipe 1944 || res_ctx->pipe_ctx[i].next_odm_pipe; 1945 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; 1946 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state 1947 == res_ctx->pipe_ctx[i].plane_state) 1948 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx; 1949 else if (res_ctx->pipe_ctx[i].prev_odm_pipe) { 1950 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe; 1951 1952 while (first_pipe->prev_odm_pipe) 1953 first_pipe = first_pipe->prev_odm_pipe; 1954 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx; 1955 } 1956 1957 switch (res_ctx->pipe_ctx[i].stream->signal) { 1958 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1959 case SIGNAL_TYPE_DISPLAY_PORT: 1960 pipes[pipe_cnt].dout.output_type = dm_dp; 1961 break; 1962 case SIGNAL_TYPE_EDP: 1963 pipes[pipe_cnt].dout.output_type = dm_edp; 1964 break; 1965 case SIGNAL_TYPE_HDMI_TYPE_A: 1966 case SIGNAL_TYPE_DVI_SINGLE_LINK: 1967 case SIGNAL_TYPE_DVI_DUAL_LINK: 1968 pipes[pipe_cnt].dout.output_type = dm_hdmi; 1969 break; 1970 default: 1971 /* In case there is no signal, set dp with 4 lanes to allow max config */ 1972 pipes[pipe_cnt].dout.output_type = dm_dp; 1973 pipes[pipe_cnt].dout.dp_lanes = 4; 1974 } 1975 1976 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) { 1977 case COLOR_DEPTH_666: 1978 output_bpc = 6; 1979 break; 1980 case COLOR_DEPTH_888: 1981 output_bpc = 8; 1982 break; 1983 case COLOR_DEPTH_101010: 1984 output_bpc = 10; 1985 break; 1986 case COLOR_DEPTH_121212: 1987 output_bpc = 12; 1988 break; 1989 case COLOR_DEPTH_141414: 1990 output_bpc = 14; 1991 break; 1992 case COLOR_DEPTH_161616: 1993 output_bpc = 16; 1994 break; 1995 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 1996 case COLOR_DEPTH_999: 1997 output_bpc = 9; 1998 break; 1999 case COLOR_DEPTH_111111: 2000 output_bpc = 11; 2001 break; 2002 #endif 2003 default: 2004 output_bpc = 8; 2005 break; 2006 } 2007 2008 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) { 2009 case PIXEL_ENCODING_RGB: 2010 case PIXEL_ENCODING_YCBCR444: 2011 pipes[pipe_cnt].dout.output_format = dm_444; 2012 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3; 2013 break; 2014 case PIXEL_ENCODING_YCBCR420: 2015 pipes[pipe_cnt].dout.output_format = dm_420; 2016 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2; 2017 break; 2018 case PIXEL_ENCODING_YCBCR422: 2019 if (true) /* todo */ 2020 pipes[pipe_cnt].dout.output_format = dm_s422; 2021 else 2022 pipes[pipe_cnt].dout.output_format = dm_n422; 2023 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2; 2024 break; 2025 default: 2026 pipes[pipe_cnt].dout.output_format = dm_444; 2027 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3; 2028 } 2029 2030 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 2031 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC) 2032 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0; 2033 #endif 2034 2035 /* todo: default max for now, until there is logic reflecting this in dc*/ 2036 pipes[pipe_cnt].dout.output_bpc = 12; 2037 /* 2038 * Use max cursor settings for calculations to minimize 2039 * bw calculations due to cursor on/off 2040 */ 2041 pipes[pipe_cnt].pipe.src.num_cursors = 2; 2042 pipes[pipe_cnt].pipe.src.cur0_src_width = 256; 2043 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit; 2044 pipes[pipe_cnt].pipe.src.cur1_src_width = 256; 2045 pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit; 2046 2047 if (!res_ctx->pipe_ctx[i].plane_state) { 2048 pipes[pipe_cnt].pipe.src.source_scan = dm_horz; 2049 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear; 2050 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile; 2051 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable; 2052 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920) 2053 pipes[pipe_cnt].pipe.src.viewport_width = 1920; 2054 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable; 2055 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080) 2056 pipes[pipe_cnt].pipe.src.viewport_height = 1080; 2057 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */ 2058 pipes[pipe_cnt].pipe.src.source_format = dm_444_32; 2059 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/ 2060 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/ 2061 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/ 2062 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/ 2063 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16; 2064 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0; 2065 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0; 2066 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/ 2067 pipes[pipe_cnt].pipe.scale_taps.htaps = 1; 2068 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1; 2069 pipes[pipe_cnt].pipe.src.is_hsplit = 0; 2070 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 2071 pipes[pipe_cnt].pipe.dest.vtotal_min = timing->v_total; 2072 pipes[pipe_cnt].pipe.dest.vtotal_max = timing->v_total; 2073 } else { 2074 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state; 2075 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data; 2076 2077 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate; 2078 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe 2079 && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) 2080 || (res_ctx->pipe_ctx[i].top_pipe 2081 && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln); 2082 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90 2083 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz; 2084 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y; 2085 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y; 2086 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width; 2087 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width; 2088 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height; 2089 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height; 2090 if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 2091 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch; 2092 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch; 2093 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; 2094 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c; 2095 } else { 2096 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch; 2097 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; 2098 } 2099 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable; 2100 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width; 2101 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height; 2102 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width; 2103 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height; 2104 if (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) { 2105 pipes[pipe_cnt].pipe.dest.full_recout_width += 2106 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.width; 2107 pipes[pipe_cnt].pipe.dest.full_recout_height += 2108 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.height; 2109 } else if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) { 2110 pipes[pipe_cnt].pipe.dest.full_recout_width += 2111 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.width; 2112 pipes[pipe_cnt].pipe.dest.full_recout_height += 2113 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height; 2114 } 2115 2116 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16; 2117 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32); 2118 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32); 2119 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32); 2120 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32); 2121 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 2122 scl->ratios.vert.value != dc_fixpt_one.value 2123 || scl->ratios.horz.value != dc_fixpt_one.value 2124 || scl->ratios.vert_c.value != dc_fixpt_one.value 2125 || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/ 2126 || dc->debug.always_scale; /*support always scale*/ 2127 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps; 2128 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c; 2129 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps; 2130 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c; 2131 2132 pipes[pipe_cnt].pipe.src.macro_tile_size = 2133 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); 2134 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, 2135 &pipes[pipe_cnt].pipe.src.sw_mode); 2136 2137 switch (pln->format) { 2138 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 2139 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 2140 pipes[pipe_cnt].pipe.src.source_format = dm_420_8; 2141 break; 2142 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 2143 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 2144 pipes[pipe_cnt].pipe.src.source_format = dm_420_10; 2145 break; 2146 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 2147 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 2148 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2149 pipes[pipe_cnt].pipe.src.source_format = dm_444_64; 2150 break; 2151 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 2152 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 2153 pipes[pipe_cnt].pipe.src.source_format = dm_444_16; 2154 break; 2155 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 2156 pipes[pipe_cnt].pipe.src.source_format = dm_444_8; 2157 break; 2158 default: 2159 pipes[pipe_cnt].pipe.src.source_format = dm_444_32; 2160 break; 2161 } 2162 } 2163 2164 pipe_cnt++; 2165 } 2166 2167 /* populate writeback information */ 2168 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes); 2169 2170 return pipe_cnt; 2171 } 2172 2173 unsigned int dcn20_calc_max_scaled_time( 2174 unsigned int time_per_pixel, 2175 enum mmhubbub_wbif_mode mode, 2176 unsigned int urgent_watermark) 2177 { 2178 unsigned int time_per_byte = 0; 2179 unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */ 2180 unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */ 2181 unsigned int small_free_entry, max_free_entry; 2182 unsigned int buf_lh_capability; 2183 unsigned int max_scaled_time; 2184 2185 if (mode == PACKED_444) /* packed mode */ 2186 time_per_byte = time_per_pixel/4; 2187 else if (mode == PLANAR_420_8BPC) 2188 time_per_byte = time_per_pixel; 2189 else if (mode == PLANAR_420_10BPC) /* p010 */ 2190 time_per_byte = time_per_pixel * 819/1024; 2191 2192 if (time_per_byte == 0) 2193 time_per_byte = 1; 2194 2195 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry; 2196 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry; 2197 buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */ 2198 max_scaled_time = buf_lh_capability - urgent_watermark; 2199 return max_scaled_time; 2200 } 2201 2202 void dcn20_set_mcif_arb_params( 2203 struct dc *dc, 2204 struct dc_state *context, 2205 display_e2e_pipe_params_st *pipes, 2206 int pipe_cnt) 2207 { 2208 enum mmhubbub_wbif_mode wbif_mode; 2209 struct mcif_arb_params *wb_arb_params; 2210 int i, j, k, dwb_pipe; 2211 2212 /* Writeback MCIF_WB arbitration parameters */ 2213 dwb_pipe = 0; 2214 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2215 2216 if (!context->res_ctx.pipe_ctx[i].stream) 2217 continue; 2218 2219 for (j = 0; j < MAX_DWB_PIPES; j++) { 2220 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false) 2221 continue; 2222 2223 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params; 2224 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe]; 2225 2226 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) { 2227 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) 2228 wbif_mode = PLANAR_420_8BPC; 2229 else 2230 wbif_mode = PLANAR_420_10BPC; 2231 } else 2232 wbif_mode = PACKED_444; 2233 2234 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) { 2235 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2236 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2237 } 2238 wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */ 2239 wb_arb_params->slice_lines = 32; 2240 wb_arb_params->arbitration_slice = 2; 2241 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel, 2242 wbif_mode, 2243 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */ 2244 2245 dwb_pipe++; 2246 2247 if (dwb_pipe >= MAX_DWB_PIPES) 2248 return; 2249 } 2250 if (dwb_pipe >= MAX_DWB_PIPES) 2251 return; 2252 } 2253 } 2254 2255 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 2256 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) 2257 { 2258 int i; 2259 2260 /* Validate DSC config, dsc count validation is already done */ 2261 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2262 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; 2263 struct dc_stream_state *stream = pipe_ctx->stream; 2264 struct dsc_config dsc_cfg; 2265 struct pipe_ctx *odm_pipe; 2266 int opp_cnt = 1; 2267 2268 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 2269 opp_cnt++; 2270 2271 /* Only need to validate top pipe */ 2272 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC) 2273 continue; 2274 2275 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left 2276 + stream->timing.h_border_right) / opp_cnt; 2277 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top 2278 + stream->timing.v_border_bottom; 2279 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 2280 dsc_cfg.color_depth = stream->timing.display_color_depth; 2281 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 2282 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 2283 2284 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg)) 2285 return false; 2286 } 2287 return true; 2288 } 2289 #endif 2290 2291 struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, 2292 struct resource_context *res_ctx, 2293 const struct resource_pool *pool, 2294 const struct pipe_ctx *primary_pipe) 2295 { 2296 struct pipe_ctx *secondary_pipe = NULL; 2297 2298 if (dc && primary_pipe) { 2299 int j; 2300 int preferred_pipe_idx = 0; 2301 2302 /* first check the prev dc state: 2303 * if this primary pipe has a bottom pipe in prev. state 2304 * and if the bottom pipe is still available (which it should be), 2305 * pick that pipe as secondary 2306 * Same logic applies for ODM pipes. Since mpo is not allowed with odm 2307 * check in else case. 2308 */ 2309 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) { 2310 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx; 2311 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2312 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2313 secondary_pipe->pipe_idx = preferred_pipe_idx; 2314 } 2315 } else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) { 2316 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx; 2317 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2318 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2319 secondary_pipe->pipe_idx = preferred_pipe_idx; 2320 } 2321 } 2322 2323 /* 2324 * if this primary pipe does not have a bottom pipe in prev. state 2325 * start backward and find a pipe that did not used to be a bottom pipe in 2326 * prev. dc state. This way we make sure we keep the same assignment as 2327 * last state and will not have to reprogram every pipe 2328 */ 2329 if (secondary_pipe == NULL) { 2330 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { 2331 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL 2332 && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) { 2333 preferred_pipe_idx = j; 2334 2335 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2336 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2337 secondary_pipe->pipe_idx = preferred_pipe_idx; 2338 break; 2339 } 2340 } 2341 } 2342 } 2343 /* 2344 * We should never hit this assert unless assignments are shuffled around 2345 * if this happens we will prob. hit a vsync tdr 2346 */ 2347 ASSERT(secondary_pipe); 2348 /* 2349 * search backwards for the second pipe to keep pipe 2350 * assignment more consistent 2351 */ 2352 if (secondary_pipe == NULL) { 2353 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { 2354 preferred_pipe_idx = j; 2355 2356 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 2357 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2358 secondary_pipe->pipe_idx = preferred_pipe_idx; 2359 break; 2360 } 2361 } 2362 } 2363 } 2364 2365 return secondary_pipe; 2366 } 2367 2368 void dcn20_merge_pipes_for_validate( 2369 struct dc *dc, 2370 struct dc_state *context) 2371 { 2372 int i; 2373 2374 /* merge previously split odm pipes since mode support needs to make the decision */ 2375 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2376 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2377 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe; 2378 2379 if (pipe->prev_odm_pipe) 2380 continue; 2381 2382 pipe->next_odm_pipe = NULL; 2383 while (odm_pipe) { 2384 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe; 2385 2386 odm_pipe->plane_state = NULL; 2387 odm_pipe->stream = NULL; 2388 odm_pipe->top_pipe = NULL; 2389 odm_pipe->bottom_pipe = NULL; 2390 odm_pipe->prev_odm_pipe = NULL; 2391 odm_pipe->next_odm_pipe = NULL; 2392 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 2393 if (odm_pipe->stream_res.dsc) 2394 release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); 2395 #endif 2396 /* Clear plane_res and stream_res */ 2397 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res)); 2398 memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res)); 2399 odm_pipe = next_odm_pipe; 2400 } 2401 if (pipe->plane_state) 2402 resource_build_scaling_params(pipe); 2403 } 2404 2405 /* merge previously mpc split pipes since mode support needs to make the decision */ 2406 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2407 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2408 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 2409 2410 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) 2411 continue; 2412 2413 pipe->bottom_pipe = hsplit_pipe->bottom_pipe; 2414 if (hsplit_pipe->bottom_pipe) 2415 hsplit_pipe->bottom_pipe->top_pipe = pipe; 2416 hsplit_pipe->plane_state = NULL; 2417 hsplit_pipe->stream = NULL; 2418 hsplit_pipe->top_pipe = NULL; 2419 hsplit_pipe->bottom_pipe = NULL; 2420 2421 /* Clear plane_res and stream_res */ 2422 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res)); 2423 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res)); 2424 if (pipe->plane_state) 2425 resource_build_scaling_params(pipe); 2426 } 2427 } 2428 2429 int dcn20_validate_apply_pipe_split_flags( 2430 struct dc *dc, 2431 struct dc_state *context, 2432 int vlevel, 2433 bool *split) 2434 { 2435 int i, pipe_idx, vlevel_split; 2436 bool force_split = false; 2437 bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC; 2438 2439 /* Single display loop, exits if there is more than one display */ 2440 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2441 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2442 bool exit_loop = false; 2443 2444 if (!pipe->stream || pipe->top_pipe) 2445 continue; 2446 2447 if (dc->debug.force_single_disp_pipe_split) { 2448 if (!force_split) 2449 force_split = true; 2450 else { 2451 force_split = false; 2452 exit_loop = true; 2453 } 2454 } 2455 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) { 2456 if (avoid_split) 2457 avoid_split = false; 2458 else { 2459 avoid_split = true; 2460 exit_loop = true; 2461 } 2462 } 2463 if (exit_loop) 2464 break; 2465 } 2466 /* TODO: fix dc bugs and remove this split threshold thing */ 2467 if (context->stream_count > dc->res_pool->pipe_count / 2) 2468 avoid_split = true; 2469 2470 /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */ 2471 if (avoid_split) { 2472 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2473 if (!context->res_ctx.pipe_ctx[i].stream) 2474 continue; 2475 2476 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) 2477 if (context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1) 2478 break; 2479 /* Impossible to not split this pipe */ 2480 if (vlevel > context->bw_ctx.dml.soc.num_states) 2481 vlevel = vlevel_split; 2482 pipe_idx++; 2483 } 2484 context->bw_ctx.dml.vba.maxMpcComb = 0; 2485 } 2486 2487 /* Split loop sets which pipe should be split based on dml outputs and dc flags */ 2488 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2489 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2490 2491 if (!context->res_ctx.pipe_ctx[i].stream) 2492 continue; 2493 2494 if (force_split || context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] > 1) 2495 split[i] = true; 2496 if ((pipe->stream->view_format == 2497 VIEW_3D_FORMAT_SIDE_BY_SIDE || 2498 pipe->stream->view_format == 2499 VIEW_3D_FORMAT_TOP_AND_BOTTOM) && 2500 (pipe->stream->timing.timing_3d_format == 2501 TIMING_3D_FORMAT_TOP_AND_BOTTOM || 2502 pipe->stream->timing.timing_3d_format == 2503 TIMING_3D_FORMAT_SIDE_BY_SIDE)) 2504 split[i] = true; 2505 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) { 2506 split[i] = true; 2507 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true; 2508 } 2509 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] = 2510 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx]; 2511 /* Adjust dppclk when split is forced, do not bother with dispclk */ 2512 if (split[i] && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1) 2513 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2; 2514 pipe_idx++; 2515 } 2516 2517 return vlevel; 2518 } 2519 2520 bool dcn20_fast_validate_bw( 2521 struct dc *dc, 2522 struct dc_state *context, 2523 display_e2e_pipe_params_st *pipes, 2524 int *pipe_cnt_out, 2525 int *pipe_split_from, 2526 int *vlevel_out) 2527 { 2528 bool out = false; 2529 bool split[MAX_PIPES] = { false }; 2530 int pipe_cnt, i, pipe_idx, vlevel; 2531 2532 ASSERT(pipes); 2533 if (!pipes) 2534 return false; 2535 2536 dcn20_merge_pipes_for_validate(dc, context); 2537 2538 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, &context->res_ctx, pipes); 2539 2540 *pipe_cnt_out = pipe_cnt; 2541 2542 if (!pipe_cnt) { 2543 out = true; 2544 goto validate_out; 2545 } 2546 2547 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 2548 2549 if (vlevel > context->bw_ctx.dml.soc.num_states) 2550 goto validate_fail; 2551 2552 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split); 2553 2554 /*initialize pipe_just_split_from to invalid idx*/ 2555 for (i = 0; i < MAX_PIPES; i++) 2556 pipe_split_from[i] = -1; 2557 2558 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { 2559 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2560 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 2561 2562 if (!pipe->stream || pipe_split_from[i] >= 0) 2563 continue; 2564 2565 pipe_idx++; 2566 2567 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 2568 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 2569 ASSERT(hsplit_pipe); 2570 if (!dcn20_split_stream_for_odm( 2571 &context->res_ctx, dc->res_pool, 2572 pipe, hsplit_pipe)) 2573 goto validate_fail; 2574 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 2575 dcn20_build_mapped_resource(dc, context, pipe->stream); 2576 } 2577 2578 if (!pipe->plane_state) 2579 continue; 2580 /* Skip 2nd half of already split pipe */ 2581 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state) 2582 continue; 2583 2584 /* We do not support mpo + odm at the moment */ 2585 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state 2586 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) 2587 goto validate_fail; 2588 2589 if (split[i]) { 2590 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) { 2591 /* pipe not split previously needs split */ 2592 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 2593 ASSERT(hsplit_pipe); 2594 if (!hsplit_pipe) { 2595 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2; 2596 continue; 2597 } 2598 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 2599 if (!dcn20_split_stream_for_odm( 2600 &context->res_ctx, dc->res_pool, 2601 pipe, hsplit_pipe)) 2602 goto validate_fail; 2603 dcn20_build_mapped_resource(dc, context, pipe->stream); 2604 } else 2605 dcn20_split_stream_for_mpc( 2606 &context->res_ctx, dc->res_pool, 2607 pipe, hsplit_pipe); 2608 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 2609 } 2610 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { 2611 /* merge should already have been done */ 2612 ASSERT(0); 2613 } 2614 } 2615 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 2616 /* Actual dsc count per stream dsc validation*/ 2617 if (!dcn20_validate_dsc(dc, context)) { 2618 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = 2619 DML_FAIL_DSC_VALIDATION_FAILURE; 2620 goto validate_fail; 2621 } 2622 #endif 2623 2624 *vlevel_out = vlevel; 2625 2626 out = true; 2627 goto validate_out; 2628 2629 validate_fail: 2630 out = false; 2631 2632 validate_out: 2633 return out; 2634 } 2635 2636 static void dcn20_calculate_wm( 2637 struct dc *dc, struct dc_state *context, 2638 display_e2e_pipe_params_st *pipes, 2639 int *out_pipe_cnt, 2640 int *pipe_split_from, 2641 int vlevel) 2642 { 2643 int pipe_cnt, i, pipe_idx; 2644 2645 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 2646 if (!context->res_ctx.pipe_ctx[i].stream) 2647 continue; 2648 2649 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 2650 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 2651 2652 if (pipe_split_from[i] < 0) { 2653 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 2654 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; 2655 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) 2656 pipes[pipe_cnt].pipe.dest.odm_combine = 2657 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]; 2658 else 2659 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 2660 pipe_idx++; 2661 } else { 2662 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 2663 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; 2664 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) 2665 pipes[pipe_cnt].pipe.dest.odm_combine = 2666 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]]; 2667 else 2668 pipes[pipe_cnt].pipe.dest.odm_combine = 0; 2669 } 2670 2671 if (dc->config.forced_clocks) { 2672 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 2673 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 2674 } 2675 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000) 2676 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 2677 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000) 2678 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 2679 2680 pipe_cnt++; 2681 } 2682 2683 if (pipe_cnt != pipe_idx) { 2684 if (dc->res_pool->funcs->populate_dml_pipes) 2685 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, 2686 &context->res_ctx, pipes); 2687 else 2688 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, 2689 &context->res_ctx, pipes); 2690 } 2691 2692 *out_pipe_cnt = pipe_cnt; 2693 2694 pipes[0].clks_cfg.voltage = vlevel; 2695 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; 2696 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 2697 2698 /* only pipe 0 is read for voltage and dcf/soc clocks */ 2699 if (vlevel < 1) { 2700 pipes[0].clks_cfg.voltage = 1; 2701 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz; 2702 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz; 2703 } 2704 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2705 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2706 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2707 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2708 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2709 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 2710 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2711 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2712 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2713 #endif 2714 2715 if (vlevel < 2) { 2716 pipes[0].clks_cfg.voltage = 2; 2717 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; 2718 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; 2719 } 2720 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2721 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2722 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2723 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2724 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2725 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 2726 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2727 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2728 #endif 2729 2730 if (vlevel < 3) { 2731 pipes[0].clks_cfg.voltage = 3; 2732 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; 2733 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; 2734 } 2735 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2736 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2737 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2738 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2739 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2740 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 2741 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2742 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2743 #endif 2744 2745 pipes[0].clks_cfg.voltage = vlevel; 2746 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; 2747 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 2748 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2749 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2750 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2751 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2752 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2753 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 2754 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2755 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2756 #endif 2757 } 2758 2759 void dcn20_calculate_dlg_params( 2760 struct dc *dc, struct dc_state *context, 2761 display_e2e_pipe_params_st *pipes, 2762 int pipe_cnt, 2763 int vlevel) 2764 { 2765 int i, j, pipe_idx, pipe_idx_unsplit; 2766 bool visited[MAX_PIPES] = { 0 }; 2767 2768 /* Writeback MCIF_WB arbitration parameters */ 2769 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); 2770 2771 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; 2772 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; 2773 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; 2774 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; 2775 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; 2776 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; 2777 context->bw_ctx.bw.dcn.clk.p_state_change_support = 2778 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] 2779 != dm_dram_clock_change_unsupported; 2780 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 2781 2782 /* 2783 * An artifact of dml pipe split/odm is that pipes get merged back together for 2784 * calculation. Therefore we need to only extract for first pipe in ascending index order 2785 * and copy into the other split half. 2786 */ 2787 for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) { 2788 if (!context->res_ctx.pipe_ctx[i].stream) 2789 continue; 2790 2791 if (!visited[pipe_idx]) { 2792 display_pipe_source_params_st *src = &pipes[pipe_idx].pipe.src; 2793 display_pipe_dest_params_st *dst = &pipes[pipe_idx].pipe.dest; 2794 2795 dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit]; 2796 dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit]; 2797 dst->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit]; 2798 dst->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit]; 2799 /* 2800 * j iterates inside pipes array, unlike i which iterates inside 2801 * pipe_ctx array 2802 */ 2803 if (src->is_hsplit) 2804 for (j = pipe_idx + 1; j < pipe_cnt; j++) { 2805 display_pipe_source_params_st *src_j = &pipes[j].pipe.src; 2806 display_pipe_dest_params_st *dst_j = &pipes[j].pipe.dest; 2807 2808 if (src_j->is_hsplit && !visited[j] 2809 && src->hsplit_grp == src_j->hsplit_grp) { 2810 dst_j->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit]; 2811 dst_j->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit]; 2812 dst_j->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit]; 2813 dst_j->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit]; 2814 visited[j] = true; 2815 } 2816 } 2817 visited[pipe_idx] = true; 2818 pipe_idx_unsplit++; 2819 } 2820 pipe_idx++; 2821 } 2822 2823 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2824 if (!context->res_ctx.pipe_ctx[i].stream) 2825 continue; 2826 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 2827 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 2828 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 2829 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 2830 ASSERT(visited[pipe_idx]); 2831 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; 2832 pipe_idx++; 2833 } 2834 /*save a original dppclock copy*/ 2835 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; 2836 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; 2837 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000; 2838 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000; 2839 2840 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2841 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2; 2842 2843 if (!context->res_ctx.pipe_ctx[i].stream) 2844 continue; 2845 2846 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml, 2847 &context->res_ctx.pipe_ctx[i].dlg_regs, 2848 &context->res_ctx.pipe_ctx[i].ttu_regs, 2849 pipes, 2850 pipe_cnt, 2851 pipe_idx, 2852 cstate_en, 2853 context->bw_ctx.bw.dcn.clk.p_state_change_support, 2854 false, false, false); 2855 2856 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml, 2857 &context->res_ctx.pipe_ctx[i].rq_regs, 2858 pipes[pipe_idx].pipe); 2859 pipe_idx++; 2860 } 2861 } 2862 2863 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context, 2864 bool fast_validate) 2865 { 2866 bool out = false; 2867 2868 BW_VAL_TRACE_SETUP(); 2869 2870 int vlevel = 0; 2871 int pipe_split_from[MAX_PIPES]; 2872 int pipe_cnt = 0; 2873 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 2874 DC_LOGGER_INIT(dc->ctx->logger); 2875 2876 BW_VAL_TRACE_COUNT(); 2877 2878 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel); 2879 2880 if (pipe_cnt == 0) 2881 goto validate_out; 2882 2883 if (!out) 2884 goto validate_fail; 2885 2886 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 2887 2888 if (fast_validate) { 2889 BW_VAL_TRACE_SKIP(fast); 2890 goto validate_out; 2891 } 2892 2893 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel); 2894 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 2895 2896 BW_VAL_TRACE_END_WATERMARKS(); 2897 2898 goto validate_out; 2899 2900 validate_fail: 2901 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 2902 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 2903 2904 BW_VAL_TRACE_SKIP(fail); 2905 out = false; 2906 2907 validate_out: 2908 kfree(pipes); 2909 2910 BW_VAL_TRACE_FINISH(); 2911 2912 return out; 2913 } 2914 2915 2916 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, 2917 bool fast_validate) 2918 { 2919 bool voltage_supported = false; 2920 bool full_pstate_supported = false; 2921 bool dummy_pstate_supported = false; 2922 double p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us; 2923 2924 if (fast_validate) 2925 return dcn20_validate_bandwidth_internal(dc, context, true); 2926 2927 2928 // Best case, we support full UCLK switch latency 2929 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); 2930 full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; 2931 2932 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 || 2933 (voltage_supported && full_pstate_supported)) { 2934 context->bw_ctx.bw.dcn.clk.p_state_change_support = true; 2935 goto restore_dml_state; 2936 } 2937 2938 // Fallback: Try to only support G6 temperature read latency 2939 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us; 2940 2941 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); 2942 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; 2943 2944 if (voltage_supported && dummy_pstate_supported) { 2945 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; 2946 goto restore_dml_state; 2947 } 2948 2949 // ERROR: fallback is supposed to always work. 2950 ASSERT(false); 2951 2952 restore_dml_state: 2953 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us; 2954 2955 return voltage_supported; 2956 } 2957 2958 struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer( 2959 struct dc_state *state, 2960 const struct resource_pool *pool, 2961 struct dc_stream_state *stream) 2962 { 2963 struct resource_context *res_ctx = &state->res_ctx; 2964 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 2965 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe); 2966 2967 if (!head_pipe) 2968 ASSERT(0); 2969 2970 if (!idle_pipe) 2971 return NULL; 2972 2973 idle_pipe->stream = head_pipe->stream; 2974 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 2975 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 2976 2977 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 2978 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 2979 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 2980 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 2981 2982 return idle_pipe; 2983 } 2984 2985 bool dcn20_get_dcc_compression_cap(const struct dc *dc, 2986 const struct dc_dcc_surface_param *input, 2987 struct dc_surface_dcc_cap *output) 2988 { 2989 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 2990 dc->res_pool->hubbub, 2991 input, 2992 output); 2993 } 2994 2995 static void dcn20_destroy_resource_pool(struct resource_pool **pool) 2996 { 2997 struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool); 2998 2999 destruct(dcn20_pool); 3000 kfree(dcn20_pool); 3001 *pool = NULL; 3002 } 3003 3004 3005 static struct dc_cap_funcs cap_funcs = { 3006 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 3007 }; 3008 3009 3010 enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state) 3011 { 3012 enum dc_status result = DC_OK; 3013 3014 enum surface_pixel_format surf_pix_format = plane_state->format; 3015 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 3016 3017 enum swizzle_mode_values swizzle = DC_SW_LINEAR; 3018 3019 if (bpp == 64) 3020 swizzle = DC_SW_64KB_D; 3021 else 3022 swizzle = DC_SW_64KB_S; 3023 3024 plane_state->tiling_info.gfx9.swizzle = swizzle; 3025 return result; 3026 } 3027 3028 static struct resource_funcs dcn20_res_pool_funcs = { 3029 .destroy = dcn20_destroy_resource_pool, 3030 .link_enc_create = dcn20_link_encoder_create, 3031 .validate_bandwidth = dcn20_validate_bandwidth, 3032 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 3033 .add_stream_to_ctx = dcn20_add_stream_to_ctx, 3034 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 3035 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, 3036 .get_default_swizzle_mode = dcn20_get_default_swizzle_mode, 3037 .set_mcif_arb_params = dcn20_set_mcif_arb_params, 3038 .populate_dml_pipes = dcn20_populate_dml_pipes_from_context, 3039 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link 3040 }; 3041 3042 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 3043 { 3044 int i; 3045 uint32_t pipe_count = pool->res_cap->num_dwb; 3046 3047 for (i = 0; i < pipe_count; i++) { 3048 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc), 3049 GFP_KERNEL); 3050 3051 if (!dwbc20) { 3052 dm_error("DC: failed to create dwbc20!\n"); 3053 return false; 3054 } 3055 dcn20_dwbc_construct(dwbc20, ctx, 3056 &dwbc20_regs[i], 3057 &dwbc20_shift, 3058 &dwbc20_mask, 3059 i); 3060 pool->dwbc[i] = &dwbc20->base; 3061 } 3062 return true; 3063 } 3064 3065 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 3066 { 3067 int i; 3068 uint32_t pipe_count = pool->res_cap->num_dwb; 3069 3070 ASSERT(pipe_count > 0); 3071 3072 for (i = 0; i < pipe_count; i++) { 3073 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub), 3074 GFP_KERNEL); 3075 3076 if (!mcif_wb20) { 3077 dm_error("DC: failed to create mcif_wb20!\n"); 3078 return false; 3079 } 3080 3081 dcn20_mmhubbub_construct(mcif_wb20, ctx, 3082 &mcif_wb20_regs[i], 3083 &mcif_wb20_shift, 3084 &mcif_wb20_mask, 3085 i); 3086 3087 pool->mcif_wb[i] = &mcif_wb20->base; 3088 } 3089 return true; 3090 } 3091 3092 static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx) 3093 { 3094 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 3095 3096 if (!pp_smu) 3097 return pp_smu; 3098 3099 dm_pp_get_funcs(ctx, pp_smu); 3100 3101 if (pp_smu->ctx.ver != PP_SMU_VER_NV) 3102 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); 3103 3104 return pp_smu; 3105 } 3106 3107 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu) 3108 { 3109 if (pp_smu && *pp_smu) { 3110 kfree(*pp_smu); 3111 *pp_smu = NULL; 3112 } 3113 } 3114 3115 void dcn20_cap_soc_clocks( 3116 struct _vcs_dpi_soc_bounding_box_st *bb, 3117 struct pp_smu_nv_clock_table max_clocks) 3118 { 3119 int i; 3120 3121 // First pass - cap all clocks higher than the reported max 3122 for (i = 0; i < bb->num_states; i++) { 3123 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000)) 3124 && max_clocks.dcfClockInKhz != 0) 3125 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000); 3126 3127 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16) 3128 && max_clocks.uClockInKhz != 0) 3129 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16; 3130 3131 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000)) 3132 && max_clocks.fabricClockInKhz != 0) 3133 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000); 3134 3135 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000)) 3136 && max_clocks.displayClockInKhz != 0) 3137 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000); 3138 3139 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000)) 3140 && max_clocks.dppClockInKhz != 0) 3141 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000); 3142 3143 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000)) 3144 && max_clocks.phyClockInKhz != 0) 3145 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000); 3146 3147 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000)) 3148 && max_clocks.socClockInKhz != 0) 3149 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000); 3150 3151 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000)) 3152 && max_clocks.dscClockInKhz != 0) 3153 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000); 3154 } 3155 3156 // Second pass - remove all duplicate clock states 3157 for (i = bb->num_states - 1; i > 1; i--) { 3158 bool duplicate = true; 3159 3160 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz) 3161 duplicate = false; 3162 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz) 3163 duplicate = false; 3164 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz) 3165 duplicate = false; 3166 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts) 3167 duplicate = false; 3168 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz) 3169 duplicate = false; 3170 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz) 3171 duplicate = false; 3172 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz) 3173 duplicate = false; 3174 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz) 3175 duplicate = false; 3176 3177 if (duplicate) 3178 bb->num_states--; 3179 } 3180 } 3181 3182 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb, 3183 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) 3184 { 3185 struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES]; 3186 int i; 3187 int num_calculated_states = 0; 3188 int min_dcfclk = 0; 3189 3190 if (num_states == 0) 3191 return; 3192 3193 memset(calculated_states, 0, sizeof(calculated_states)); 3194 3195 if (dc->bb_overrides.min_dcfclk_mhz > 0) 3196 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz; 3197 else { 3198 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) 3199 min_dcfclk = 310; 3200 else 3201 // Accounting for SOC/DCF relationship, we can go as high as 3202 // 506Mhz in Vmin. 3203 min_dcfclk = 506; 3204 } 3205 3206 for (i = 0; i < num_states; i++) { 3207 int min_fclk_required_by_uclk; 3208 calculated_states[i].state = i; 3209 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000; 3210 3211 // FCLK:UCLK ratio is 1.08 3212 min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32); 3213 3214 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? 3215 min_dcfclk : min_fclk_required_by_uclk; 3216 3217 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ? 3218 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; 3219 3220 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ? 3221 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; 3222 3223 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000; 3224 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000; 3225 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3); 3226 3227 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000; 3228 3229 num_calculated_states++; 3230 } 3231 3232 calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000; 3233 calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000; 3234 calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000; 3235 3236 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits)); 3237 bb->num_states = num_calculated_states; 3238 3239 // Duplicate the last state, DML always an extra state identical to max state to work 3240 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st)); 3241 bb->clock_limits[num_calculated_states].state = bb->num_states; 3242 } 3243 3244 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) 3245 { 3246 kernel_fpu_begin(); 3247 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns 3248 && dc->bb_overrides.sr_exit_time_ns) { 3249 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; 3250 } 3251 3252 if ((int)(bb->sr_enter_plus_exit_time_us * 1000) 3253 != dc->bb_overrides.sr_enter_plus_exit_time_ns 3254 && dc->bb_overrides.sr_enter_plus_exit_time_ns) { 3255 bb->sr_enter_plus_exit_time_us = 3256 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 3257 } 3258 3259 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns 3260 && dc->bb_overrides.urgent_latency_ns) { 3261 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 3262 } 3263 3264 if ((int)(bb->dram_clock_change_latency_us * 1000) 3265 != dc->bb_overrides.dram_clock_change_latency_ns 3266 && dc->bb_overrides.dram_clock_change_latency_ns) { 3267 bb->dram_clock_change_latency_us = 3268 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 3269 } 3270 kernel_fpu_end(); 3271 } 3272 3273 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb( 3274 uint32_t hw_internal_rev) 3275 { 3276 if (ASICREV_IS_NAVI12_P(hw_internal_rev)) 3277 return &dcn2_0_nv12_soc; 3278 3279 return &dcn2_0_soc; 3280 } 3281 3282 static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params( 3283 uint32_t hw_internal_rev) 3284 { 3285 /* NV14 */ 3286 if (ASICREV_IS_NAVI14_M(hw_internal_rev)) 3287 return &dcn2_0_nv14_ip; 3288 3289 /* NV12 and NV10 */ 3290 return &dcn2_0_ip; 3291 } 3292 3293 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev) 3294 { 3295 return DML_PROJECT_NAVI10v2; 3296 } 3297 3298 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16))) 3299 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) 3300 3301 static bool init_soc_bounding_box(struct dc *dc, 3302 struct dcn20_resource_pool *pool) 3303 { 3304 const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box; 3305 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = 3306 get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev); 3307 struct _vcs_dpi_ip_params_st *loaded_ip = 3308 get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev); 3309 3310 DC_LOGGER_INIT(dc->ctx->logger); 3311 3312 if (!bb && !SOC_BOUNDING_BOX_VALID) { 3313 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); 3314 return false; 3315 } 3316 3317 if (bb && !SOC_BOUNDING_BOX_VALID) { 3318 int i; 3319 3320 dcn2_0_nv12_soc.sr_exit_time_us = 3321 fixed16_to_double_to_cpu(bb->sr_exit_time_us); 3322 dcn2_0_nv12_soc.sr_enter_plus_exit_time_us = 3323 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us); 3324 dcn2_0_nv12_soc.urgent_latency_us = 3325 fixed16_to_double_to_cpu(bb->urgent_latency_us); 3326 dcn2_0_nv12_soc.urgent_latency_pixel_data_only_us = 3327 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us); 3328 dcn2_0_nv12_soc.urgent_latency_pixel_mixed_with_vm_data_us = 3329 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us); 3330 dcn2_0_nv12_soc.urgent_latency_vm_data_only_us = 3331 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us); 3332 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes = 3333 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes); 3334 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 3335 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes); 3336 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_vm_only_bytes = 3337 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes); 3338 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 3339 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only); 3340 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 3341 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm); 3342 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 3343 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only); 3344 dcn2_0_nv12_soc.max_avg_sdp_bw_use_normal_percent = 3345 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent); 3346 dcn2_0_nv12_soc.max_avg_dram_bw_use_normal_percent = 3347 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent); 3348 dcn2_0_nv12_soc.writeback_latency_us = 3349 fixed16_to_double_to_cpu(bb->writeback_latency_us); 3350 dcn2_0_nv12_soc.ideal_dram_bw_after_urgent_percent = 3351 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent); 3352 dcn2_0_nv12_soc.max_request_size_bytes = 3353 le32_to_cpu(bb->max_request_size_bytes); 3354 dcn2_0_nv12_soc.dram_channel_width_bytes = 3355 le32_to_cpu(bb->dram_channel_width_bytes); 3356 dcn2_0_nv12_soc.fabric_datapath_to_dcn_data_return_bytes = 3357 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes); 3358 dcn2_0_nv12_soc.dcn_downspread_percent = 3359 fixed16_to_double_to_cpu(bb->dcn_downspread_percent); 3360 dcn2_0_nv12_soc.downspread_percent = 3361 fixed16_to_double_to_cpu(bb->downspread_percent); 3362 dcn2_0_nv12_soc.dram_page_open_time_ns = 3363 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns); 3364 dcn2_0_nv12_soc.dram_rw_turnaround_time_ns = 3365 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns); 3366 dcn2_0_nv12_soc.dram_return_buffer_per_channel_bytes = 3367 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes); 3368 dcn2_0_nv12_soc.round_trip_ping_latency_dcfclk_cycles = 3369 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles); 3370 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_bytes = 3371 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes); 3372 dcn2_0_nv12_soc.channel_interleave_bytes = 3373 le32_to_cpu(bb->channel_interleave_bytes); 3374 dcn2_0_nv12_soc.num_banks = 3375 le32_to_cpu(bb->num_banks); 3376 dcn2_0_nv12_soc.num_chans = 3377 le32_to_cpu(bb->num_chans); 3378 dcn2_0_nv12_soc.vmm_page_size_bytes = 3379 le32_to_cpu(bb->vmm_page_size_bytes); 3380 dcn2_0_nv12_soc.dram_clock_change_latency_us = 3381 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us); 3382 // HACK!! Lower uclock latency switch time so we don't switch 3383 dcn2_0_nv12_soc.dram_clock_change_latency_us = 10; 3384 dcn2_0_nv12_soc.writeback_dram_clock_change_latency_us = 3385 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us); 3386 dcn2_0_nv12_soc.return_bus_width_bytes = 3387 le32_to_cpu(bb->return_bus_width_bytes); 3388 dcn2_0_nv12_soc.dispclk_dppclk_vco_speed_mhz = 3389 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz); 3390 dcn2_0_nv12_soc.xfc_bus_transport_time_us = 3391 le32_to_cpu(bb->xfc_bus_transport_time_us); 3392 dcn2_0_nv12_soc.xfc_xbuf_latency_tolerance_us = 3393 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us); 3394 dcn2_0_nv12_soc.use_urgent_burst_bw = 3395 le32_to_cpu(bb->use_urgent_burst_bw); 3396 dcn2_0_nv12_soc.num_states = 3397 le32_to_cpu(bb->num_states); 3398 3399 for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) { 3400 dcn2_0_nv12_soc.clock_limits[i].state = 3401 le32_to_cpu(bb->clock_limits[i].state); 3402 dcn2_0_nv12_soc.clock_limits[i].dcfclk_mhz = 3403 fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz); 3404 dcn2_0_nv12_soc.clock_limits[i].fabricclk_mhz = 3405 fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz); 3406 dcn2_0_nv12_soc.clock_limits[i].dispclk_mhz = 3407 fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz); 3408 dcn2_0_nv12_soc.clock_limits[i].dppclk_mhz = 3409 fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz); 3410 dcn2_0_nv12_soc.clock_limits[i].phyclk_mhz = 3411 fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz); 3412 dcn2_0_nv12_soc.clock_limits[i].socclk_mhz = 3413 fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz); 3414 dcn2_0_nv12_soc.clock_limits[i].dscclk_mhz = 3415 fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz); 3416 dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts = 3417 fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts); 3418 } 3419 } 3420 3421 if (pool->base.pp_smu) { 3422 struct pp_smu_nv_clock_table max_clocks = {0}; 3423 unsigned int uclk_states[8] = {0}; 3424 unsigned int num_states = 0; 3425 enum pp_smu_status status; 3426 bool clock_limits_available = false; 3427 bool uclk_states_available = false; 3428 3429 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) { 3430 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) 3431 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); 3432 3433 uclk_states_available = (status == PP_SMU_RESULT_OK); 3434 } 3435 3436 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) { 3437 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) 3438 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks); 3439 /* SMU cannot set DCF clock to anything equal to or higher than SOC clock 3440 */ 3441 if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz) 3442 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000; 3443 clock_limits_available = (status == PP_SMU_RESULT_OK); 3444 } 3445 3446 if (clock_limits_available && uclk_states_available && num_states) 3447 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states); 3448 else if (clock_limits_available) 3449 dcn20_cap_soc_clocks(loaded_bb, max_clocks); 3450 } 3451 3452 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; 3453 loaded_ip->max_num_dpp = pool->base.pipe_count; 3454 dcn20_patch_bounding_box(dc, loaded_bb); 3455 3456 return true; 3457 } 3458 3459 static bool construct( 3460 uint8_t num_virtual_links, 3461 struct dc *dc, 3462 struct dcn20_resource_pool *pool) 3463 { 3464 int i; 3465 struct dc_context *ctx = dc->ctx; 3466 struct irq_service_init_data init_data; 3467 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = 3468 get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev); 3469 struct _vcs_dpi_ip_params_st *loaded_ip = 3470 get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev); 3471 enum dml_project dml_project_version = 3472 get_dml_project_version(ctx->asic_id.hw_internal_rev); 3473 3474 ctx->dc_bios->regs = &bios_regs; 3475 pool->base.funcs = &dcn20_res_pool_funcs; 3476 3477 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) { 3478 pool->base.res_cap = &res_cap_nv14; 3479 pool->base.pipe_count = 5; 3480 pool->base.mpcc_count = 5; 3481 } else { 3482 pool->base.res_cap = &res_cap_nv10; 3483 pool->base.pipe_count = 6; 3484 pool->base.mpcc_count = 6; 3485 } 3486 /************************************************* 3487 * Resource + asic cap harcoding * 3488 *************************************************/ 3489 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 3490 3491 dc->caps.max_downscale_ratio = 200; 3492 dc->caps.i2c_speed_in_khz = 100; 3493 dc->caps.max_cursor_size = 256; 3494 dc->caps.dmdata_alloc_size = 2048; 3495 3496 dc->caps.max_slave_planes = 1; 3497 dc->caps.post_blend_color_processing = true; 3498 dc->caps.force_dp_tps4_for_cp2520 = true; 3499 dc->caps.hw_3d_lut = true; 3500 dc->caps.extended_aux_timeout_support = true; 3501 3502 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) { 3503 dc->debug = debug_defaults_drv; 3504 } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 3505 pool->base.pipe_count = 4; 3506 pool->base.mpcc_count = pool->base.pipe_count; 3507 dc->debug = debug_defaults_diags; 3508 } else { 3509 dc->debug = debug_defaults_diags; 3510 } 3511 //dcn2.0x 3512 dc->work_arounds.dedcn20_305_wa = true; 3513 3514 // Init the vm_helper 3515 if (dc->vm_helper) 3516 vm_helper_init(dc->vm_helper, 16); 3517 3518 /************************************************* 3519 * Create resources * 3520 *************************************************/ 3521 3522 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = 3523 dcn20_clock_source_create(ctx, ctx->dc_bios, 3524 CLOCK_SOURCE_COMBO_PHY_PLL0, 3525 &clk_src_regs[0], false); 3526 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = 3527 dcn20_clock_source_create(ctx, ctx->dc_bios, 3528 CLOCK_SOURCE_COMBO_PHY_PLL1, 3529 &clk_src_regs[1], false); 3530 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = 3531 dcn20_clock_source_create(ctx, ctx->dc_bios, 3532 CLOCK_SOURCE_COMBO_PHY_PLL2, 3533 &clk_src_regs[2], false); 3534 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] = 3535 dcn20_clock_source_create(ctx, ctx->dc_bios, 3536 CLOCK_SOURCE_COMBO_PHY_PLL3, 3537 &clk_src_regs[3], false); 3538 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] = 3539 dcn20_clock_source_create(ctx, ctx->dc_bios, 3540 CLOCK_SOURCE_COMBO_PHY_PLL4, 3541 &clk_src_regs[4], false); 3542 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] = 3543 dcn20_clock_source_create(ctx, ctx->dc_bios, 3544 CLOCK_SOURCE_COMBO_PHY_PLL5, 3545 &clk_src_regs[5], false); 3546 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL; 3547 /* todo: not reuse phy_pll registers */ 3548 pool->base.dp_clock_source = 3549 dcn20_clock_source_create(ctx, ctx->dc_bios, 3550 CLOCK_SOURCE_ID_DP_DTO, 3551 &clk_src_regs[0], true); 3552 3553 for (i = 0; i < pool->base.clk_src_count; i++) { 3554 if (pool->base.clock_sources[i] == NULL) { 3555 dm_error("DC: failed to create clock sources!\n"); 3556 BREAK_TO_DEBUGGER(); 3557 goto create_fail; 3558 } 3559 } 3560 3561 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 3562 if (pool->base.dccg == NULL) { 3563 dm_error("DC: failed to create dccg!\n"); 3564 BREAK_TO_DEBUGGER(); 3565 goto create_fail; 3566 } 3567 3568 pool->base.dmcu = dcn20_dmcu_create(ctx, 3569 &dmcu_regs, 3570 &dmcu_shift, 3571 &dmcu_mask); 3572 if (pool->base.dmcu == NULL) { 3573 dm_error("DC: failed to create dmcu!\n"); 3574 BREAK_TO_DEBUGGER(); 3575 goto create_fail; 3576 } 3577 3578 pool->base.abm = dce_abm_create(ctx, 3579 &abm_regs, 3580 &abm_shift, 3581 &abm_mask); 3582 if (pool->base.abm == NULL) { 3583 dm_error("DC: failed to create abm!\n"); 3584 BREAK_TO_DEBUGGER(); 3585 goto create_fail; 3586 } 3587 3588 pool->base.pp_smu = dcn20_pp_smu_create(ctx); 3589 3590 3591 if (!init_soc_bounding_box(dc, pool)) { 3592 dm_error("DC: failed to initialize soc bounding box!\n"); 3593 BREAK_TO_DEBUGGER(); 3594 goto create_fail; 3595 } 3596 3597 dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version); 3598 3599 if (!dc->debug.disable_pplib_wm_range) { 3600 struct pp_smu_wm_range_sets ranges = {0}; 3601 int i = 0; 3602 3603 ranges.num_reader_wm_sets = 0; 3604 3605 if (loaded_bb->num_states == 1) { 3606 ranges.reader_wm_sets[0].wm_inst = i; 3607 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3608 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3609 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3610 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3611 3612 ranges.num_reader_wm_sets = 1; 3613 } else if (loaded_bb->num_states > 1) { 3614 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { 3615 ranges.reader_wm_sets[i].wm_inst = i; 3616 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3617 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3618 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; 3619 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; 3620 3621 ranges.num_reader_wm_sets = i + 1; 3622 } 3623 3624 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3625 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3626 } 3627 3628 ranges.num_writer_wm_sets = 1; 3629 3630 ranges.writer_wm_sets[0].wm_inst = 0; 3631 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3632 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3633 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 3634 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 3635 3636 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 3637 if (pool->base.pp_smu->nv_funcs.set_wm_ranges) 3638 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges); 3639 } 3640 3641 init_data.ctx = dc->ctx; 3642 pool->base.irqs = dal_irq_service_dcn20_create(&init_data); 3643 if (!pool->base.irqs) 3644 goto create_fail; 3645 3646 /* mem input -> ipp -> dpp -> opp -> TG */ 3647 for (i = 0; i < pool->base.pipe_count; i++) { 3648 pool->base.hubps[i] = dcn20_hubp_create(ctx, i); 3649 if (pool->base.hubps[i] == NULL) { 3650 BREAK_TO_DEBUGGER(); 3651 dm_error( 3652 "DC: failed to create memory input!\n"); 3653 goto create_fail; 3654 } 3655 3656 pool->base.ipps[i] = dcn20_ipp_create(ctx, i); 3657 if (pool->base.ipps[i] == NULL) { 3658 BREAK_TO_DEBUGGER(); 3659 dm_error( 3660 "DC: failed to create input pixel processor!\n"); 3661 goto create_fail; 3662 } 3663 3664 pool->base.dpps[i] = dcn20_dpp_create(ctx, i); 3665 if (pool->base.dpps[i] == NULL) { 3666 BREAK_TO_DEBUGGER(); 3667 dm_error( 3668 "DC: failed to create dpps!\n"); 3669 goto create_fail; 3670 } 3671 } 3672 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 3673 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i); 3674 if (pool->base.engines[i] == NULL) { 3675 BREAK_TO_DEBUGGER(); 3676 dm_error( 3677 "DC:failed to create aux engine!!\n"); 3678 goto create_fail; 3679 } 3680 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i); 3681 if (pool->base.hw_i2cs[i] == NULL) { 3682 BREAK_TO_DEBUGGER(); 3683 dm_error( 3684 "DC:failed to create hw i2c!!\n"); 3685 goto create_fail; 3686 } 3687 pool->base.sw_i2cs[i] = NULL; 3688 } 3689 3690 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 3691 pool->base.opps[i] = dcn20_opp_create(ctx, i); 3692 if (pool->base.opps[i] == NULL) { 3693 BREAK_TO_DEBUGGER(); 3694 dm_error( 3695 "DC: failed to create output pixel processor!\n"); 3696 goto create_fail; 3697 } 3698 } 3699 3700 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 3701 pool->base.timing_generators[i] = dcn20_timing_generator_create( 3702 ctx, i); 3703 if (pool->base.timing_generators[i] == NULL) { 3704 BREAK_TO_DEBUGGER(); 3705 dm_error("DC: failed to create tg!\n"); 3706 goto create_fail; 3707 } 3708 } 3709 3710 pool->base.timing_generator_count = i; 3711 3712 pool->base.mpc = dcn20_mpc_create(ctx); 3713 if (pool->base.mpc == NULL) { 3714 BREAK_TO_DEBUGGER(); 3715 dm_error("DC: failed to create mpc!\n"); 3716 goto create_fail; 3717 } 3718 3719 pool->base.hubbub = dcn20_hubbub_create(ctx); 3720 if (pool->base.hubbub == NULL) { 3721 BREAK_TO_DEBUGGER(); 3722 dm_error("DC: failed to create hubbub!\n"); 3723 goto create_fail; 3724 } 3725 3726 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 3727 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 3728 pool->base.dscs[i] = dcn20_dsc_create(ctx, i); 3729 if (pool->base.dscs[i] == NULL) { 3730 BREAK_TO_DEBUGGER(); 3731 dm_error("DC: failed to create display stream compressor %d!\n", i); 3732 goto create_fail; 3733 } 3734 } 3735 #endif 3736 3737 if (!dcn20_dwbc_create(ctx, &pool->base)) { 3738 BREAK_TO_DEBUGGER(); 3739 dm_error("DC: failed to create dwbc!\n"); 3740 goto create_fail; 3741 } 3742 if (!dcn20_mmhubbub_create(ctx, &pool->base)) { 3743 BREAK_TO_DEBUGGER(); 3744 dm_error("DC: failed to create mcif_wb!\n"); 3745 goto create_fail; 3746 } 3747 3748 if (!resource_construct(num_virtual_links, dc, &pool->base, 3749 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 3750 &res_create_funcs : &res_create_maximus_funcs))) 3751 goto create_fail; 3752 3753 dcn20_hw_sequencer_construct(dc); 3754 3755 dc->caps.max_planes = pool->base.pipe_count; 3756 3757 for (i = 0; i < dc->caps.max_planes; ++i) 3758 dc->caps.planes[i] = plane_cap; 3759 3760 dc->cap_funcs = cap_funcs; 3761 3762 return true; 3763 3764 create_fail: 3765 3766 destruct(pool); 3767 3768 return false; 3769 } 3770 3771 struct resource_pool *dcn20_create_resource_pool( 3772 const struct dc_init_data *init_data, 3773 struct dc *dc) 3774 { 3775 struct dcn20_resource_pool *pool = 3776 kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL); 3777 3778 if (!pool) 3779 return NULL; 3780 3781 if (construct(init_data->num_virtual_links, dc, pool)) 3782 return &pool->base; 3783 3784 BREAK_TO_DEBUGGER(); 3785 kfree(pool); 3786 return NULL; 3787 } 3788