1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "dcn20_optc.h" 28 #include "dc.h" 29 30 #define REG(reg)\ 31 optc1->tg_regs->reg 32 33 #define CTX \ 34 optc1->base.ctx 35 36 #undef FN 37 #define FN(reg_name, field_name) \ 38 optc1->tg_shift->field_name, optc1->tg_mask->field_name 39 40 /** 41 * optc2_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator. 42 * 43 * @optc: timing_generator instance. 44 * 45 * Return: If CRTC is enabled, return true. 46 * 47 */ 48 bool optc2_enable_crtc(struct timing_generator *optc) 49 { 50 /* TODO FPGA wait for answer 51 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE 52 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK 53 */ 54 struct optc *optc1 = DCN10TG_FROM_TG(optc); 55 56 /* opp instance for OTG. For DCN1.0, ODM is remoed. 57 * OPP and OPTC should 1:1 mapping 58 */ 59 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 60 OPTC_SEG0_SRC_SEL, optc->inst); 61 62 /* VTG enable first is for HW workaround */ 63 REG_UPDATE(CONTROL, 64 VTG0_ENABLE, 1); 65 66 REG_SEQ_START(); 67 68 /* Enable CRTC */ 69 REG_UPDATE_2(OTG_CONTROL, 70 OTG_DISABLE_POINT_CNTL, 3, 71 OTG_MASTER_EN, 1); 72 73 REG_SEQ_SUBMIT(); 74 REG_SEQ_WAIT_DONE(); 75 76 return true; 77 } 78 79 /** 80 * optc2_set_gsl() - Assign OTG to GSL groups, 81 * set one of the OTGs to be master & rest are slaves 82 * 83 * @optc: timing_generator instance. 84 * @params: pointer to gsl_params 85 */ 86 void optc2_set_gsl(struct timing_generator *optc, 87 const struct gsl_params *params) 88 { 89 struct optc *optc1 = DCN10TG_FROM_TG(optc); 90 91 /* 92 * There are (MAX_OPTC+1)/2 gsl groups available for use. 93 * In each group (assign an OTG to a group by setting OTG_GSLX_EN = 1, 94 * set one of the OTGs to be the master (OTG_GSL_MASTER_EN = 1) and the rest are slaves. 95 */ 96 REG_UPDATE_5(OTG_GSL_CONTROL, 97 OTG_GSL0_EN, params->gsl0_en, 98 OTG_GSL1_EN, params->gsl1_en, 99 OTG_GSL2_EN, params->gsl2_en, 100 OTG_GSL_MASTER_EN, params->gsl_master_en, 101 OTG_GSL_MASTER_MODE, params->gsl_master_mode); 102 } 103 104 105 void optc2_set_gsl_source_select( 106 struct timing_generator *optc, 107 int group_idx, 108 uint32_t gsl_ready_signal) 109 { 110 struct optc *optc1 = DCN10TG_FROM_TG(optc); 111 112 switch (group_idx) { 113 case 1: 114 REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal); 115 break; 116 case 2: 117 REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal); 118 break; 119 case 3: 120 REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal); 121 break; 122 default: 123 break; 124 } 125 } 126 127 /* Set DSC-related configuration. 128 * dsc_mode: 0 disables DSC, other values enable DSC in specified format 129 * sc_bytes_per_pixel: Bytes per pixel in u3.28 format 130 * dsc_slice_width: Slice width in pixels 131 */ 132 void optc2_set_dsc_config(struct timing_generator *optc, 133 enum optc_dsc_mode dsc_mode, 134 uint32_t dsc_bytes_per_pixel, 135 uint32_t dsc_slice_width) 136 { 137 struct optc *optc1 = DCN10TG_FROM_TG(optc); 138 139 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, 140 OPTC_DSC_MODE, dsc_mode); 141 142 REG_SET(OPTC_BYTES_PER_PIXEL, 0, 143 OPTC_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel); 144 145 REG_UPDATE(OPTC_WIDTH_CONTROL, 146 OPTC_DSC_SLICE_WIDTH, dsc_slice_width); 147 } 148 149 /* Get DSC-related configuration. 150 * dsc_mode: 0 disables DSC, other values enable DSC in specified format 151 */ 152 void optc2_get_dsc_status(struct timing_generator *optc, 153 uint32_t *dsc_mode) 154 { 155 struct optc *optc1 = DCN10TG_FROM_TG(optc); 156 157 REG_GET(OPTC_DATA_FORMAT_CONTROL, 158 OPTC_DSC_MODE, dsc_mode); 159 } 160 161 162 /*TEMP: Need to figure out inheritance model here.*/ 163 bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) 164 { 165 return optc1_is_two_pixels_per_containter(timing); 166 } 167 168 void optc2_set_odm_bypass(struct timing_generator *optc, 169 const struct dc_crtc_timing *dc_crtc_timing) 170 { 171 struct optc *optc1 = DCN10TG_FROM_TG(optc); 172 uint32_t h_div_2 = 0; 173 174 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, 175 OPTC_NUM_OF_INPUT_SEGMENT, 0, 176 OPTC_SEG0_SRC_SEL, optc->inst, 177 OPTC_SEG1_SRC_SEL, 0xf); 178 REG_WRITE(OTG_H_TIMING_CNTL, 0); 179 180 h_div_2 = optc2_is_two_pixels_per_containter(dc_crtc_timing); 181 REG_UPDATE(OTG_H_TIMING_CNTL, 182 OTG_H_TIMING_DIV_BY2, h_div_2); 183 REG_SET(OPTC_MEMORY_CONFIG, 0, 184 OPTC_MEM_SEL, 0); 185 optc1->opp_count = 1; 186 } 187 188 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 189 struct dc_crtc_timing *timing) 190 { 191 struct optc *optc1 = DCN10TG_FROM_TG(optc); 192 int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right) 193 / opp_cnt; 194 uint32_t memory_mask; 195 196 ASSERT(opp_cnt == 2); 197 198 /* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic 199 * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1); 200 * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start 201 * REG_SET_2(OTG_GLOBAL_CONTROL1, 0, 202 * MASTER_UPDATE_LOCK_DB_X, 160, 203 * MASTER_UPDATE_LOCK_DB_Y, 240); 204 */ 205 206 /* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192, 207 * however, for ODM combine we can simplify by always using 4. 208 * To make sure there's no overlap, each instance "reserves" 2 memories and 209 * they are uniquely combined here. 210 */ 211 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); 212 213 if (REG(OPTC_MEMORY_CONFIG)) 214 REG_SET(OPTC_MEMORY_CONFIG, 0, 215 OPTC_MEM_SEL, memory_mask); 216 217 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, 218 OPTC_NUM_OF_INPUT_SEGMENT, 1, 219 OPTC_SEG0_SRC_SEL, opp_id[0], 220 OPTC_SEG1_SRC_SEL, opp_id[1]); 221 222 REG_UPDATE(OPTC_WIDTH_CONTROL, 223 OPTC_SEGMENT_WIDTH, mpcc_hactive); 224 225 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1); 226 optc1->opp_count = opp_cnt; 227 } 228 229 void optc2_get_optc_source(struct timing_generator *optc, 230 uint32_t *num_of_src_opp, 231 uint32_t *src_opp_id_0, 232 uint32_t *src_opp_id_1) 233 { 234 uint32_t num_of_input_segments; 235 struct optc *optc1 = DCN10TG_FROM_TG(optc); 236 237 REG_GET_3(OPTC_DATA_SOURCE_SELECT, 238 OPTC_NUM_OF_INPUT_SEGMENT, &num_of_input_segments, 239 OPTC_SEG0_SRC_SEL, src_opp_id_0, 240 OPTC_SEG1_SRC_SEL, src_opp_id_1); 241 242 if (num_of_input_segments == 1) 243 *num_of_src_opp = 2; 244 else 245 *num_of_src_opp = 1; 246 247 /* Work around VBIOS not updating OPTC_NUM_OF_INPUT_SEGMENT */ 248 if (*src_opp_id_1 == 0xf) 249 *num_of_src_opp = 1; 250 } 251 252 static void optc2_set_dwb_source(struct timing_generator *optc, 253 uint32_t dwb_pipe_inst) 254 { 255 struct optc *optc1 = DCN10TG_FROM_TG(optc); 256 257 if (dwb_pipe_inst == 0) 258 REG_UPDATE(DWB_SOURCE_SELECT, 259 OPTC_DWB0_SOURCE_SELECT, optc->inst); 260 else if (dwb_pipe_inst == 1) 261 REG_UPDATE(DWB_SOURCE_SELECT, 262 OPTC_DWB1_SOURCE_SELECT, optc->inst); 263 } 264 265 static void optc2_align_vblanks( 266 struct timing_generator *optc_master, 267 struct timing_generator *optc_slave, 268 uint32_t master_pixel_clock_100Hz, 269 uint32_t slave_pixel_clock_100Hz, 270 uint8_t master_clock_divider, 271 uint8_t slave_clock_divider) 272 { 273 /* accessing slave OTG registers */ 274 struct optc *optc1 = DCN10TG_FROM_TG(optc_slave); 275 276 uint32_t master_v_active = 0; 277 uint32_t master_h_total = 0; 278 uint32_t slave_h_total = 0; 279 uint64_t L, XY; 280 uint32_t X, Y, p = 10000; 281 uint32_t master_update_lock; 282 283 /* disable slave OTG */ 284 REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0); 285 /* wait until disabled */ 286 REG_WAIT(OTG_CONTROL, 287 OTG_CURRENT_MASTER_EN_STATE, 288 0, 10, 5000); 289 290 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &slave_h_total); 291 292 /* assign slave OTG to be controlled by master update lock */ 293 REG_SET(OTG_GLOBAL_CONTROL0, 0, 294 OTG_MASTER_UPDATE_LOCK_SEL, optc_master->inst); 295 296 /* accessing master OTG registers */ 297 optc1 = DCN10TG_FROM_TG(optc_master); 298 299 /* saving update lock state, not sure if it's needed */ 300 REG_GET(OTG_MASTER_UPDATE_LOCK, 301 OTG_MASTER_UPDATE_LOCK, &master_update_lock); 302 /* unlocking master OTG */ 303 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 304 OTG_MASTER_UPDATE_LOCK, 0); 305 306 REG_GET(OTG_V_BLANK_START_END, 307 OTG_V_BLANK_START, &master_v_active); 308 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &master_h_total); 309 310 /* calculate when to enable slave OTG */ 311 L = (uint64_t)p * slave_h_total * master_pixel_clock_100Hz; 312 L = div_u64(L, master_h_total); 313 L = div_u64(L, slave_pixel_clock_100Hz); 314 XY = div_u64(L, p); 315 Y = master_v_active - XY - 1; 316 X = div_u64(((XY + 1) * p - L) * master_h_total, p * master_clock_divider); 317 318 /* 319 * set master OTG to unlock when V/H 320 * counters reach calculated values 321 */ 322 REG_UPDATE(OTG_GLOBAL_CONTROL1, 323 MASTER_UPDATE_LOCK_DB_EN, 1); 324 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, 325 MASTER_UPDATE_LOCK_DB_X, 326 X, 327 MASTER_UPDATE_LOCK_DB_Y, 328 Y); 329 330 /* lock master OTG */ 331 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 332 OTG_MASTER_UPDATE_LOCK, 1); 333 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 334 UPDATE_LOCK_STATUS, 1, 1, 10); 335 336 /* accessing slave OTG registers */ 337 optc1 = DCN10TG_FROM_TG(optc_slave); 338 339 /* 340 * enable slave OTG, the OTG is locked with 341 * master's update lock, so it will not run 342 */ 343 REG_UPDATE(OTG_CONTROL, 344 OTG_MASTER_EN, 1); 345 346 /* accessing master OTG registers */ 347 optc1 = DCN10TG_FROM_TG(optc_master); 348 349 /* 350 * unlock master OTG. When master H/V counters reach 351 * DB_XY point, slave OTG will start 352 */ 353 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 354 OTG_MASTER_UPDATE_LOCK, 0); 355 356 /* accessing slave OTG registers */ 357 optc1 = DCN10TG_FROM_TG(optc_slave); 358 359 /* wait for slave OTG to start running*/ 360 REG_WAIT(OTG_CONTROL, 361 OTG_CURRENT_MASTER_EN_STATE, 362 1, 10, 5000); 363 364 /* accessing master OTG registers */ 365 optc1 = DCN10TG_FROM_TG(optc_master); 366 367 /* disable the XY point*/ 368 REG_UPDATE(OTG_GLOBAL_CONTROL1, 369 MASTER_UPDATE_LOCK_DB_EN, 0); 370 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, 371 MASTER_UPDATE_LOCK_DB_X, 372 0, 373 MASTER_UPDATE_LOCK_DB_Y, 374 0); 375 376 /*restore master update lock*/ 377 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 378 OTG_MASTER_UPDATE_LOCK, master_update_lock); 379 380 /* accessing slave OTG registers */ 381 optc1 = DCN10TG_FROM_TG(optc_slave); 382 /* restore slave to be controlled by it's own */ 383 REG_SET(OTG_GLOBAL_CONTROL0, 0, 384 OTG_MASTER_UPDATE_LOCK_SEL, optc_slave->inst); 385 386 } 387 388 void optc2_triplebuffer_lock(struct timing_generator *optc) 389 { 390 struct optc *optc1 = DCN10TG_FROM_TG(optc); 391 392 REG_SET(OTG_GLOBAL_CONTROL0, 0, 393 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); 394 395 REG_SET(OTG_VUPDATE_KEEPOUT, 0, 396 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1); 397 398 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 399 OTG_MASTER_UPDATE_LOCK, 1); 400 401 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 402 UPDATE_LOCK_STATUS, 1, 403 1, 10); 404 } 405 406 void optc2_triplebuffer_unlock(struct timing_generator *optc) 407 { 408 struct optc *optc1 = DCN10TG_FROM_TG(optc); 409 410 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 411 OTG_MASTER_UPDATE_LOCK, 0); 412 413 REG_SET(OTG_VUPDATE_KEEPOUT, 0, 414 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 0); 415 416 } 417 418 void optc2_lock_doublebuffer_enable(struct timing_generator *optc) 419 { 420 struct optc *optc1 = DCN10TG_FROM_TG(optc); 421 uint32_t v_blank_start = 0; 422 uint32_t h_blank_start = 0; 423 424 REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 1); 425 426 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1, 427 DIG_UPDATE_LOCATION, 20); 428 429 REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start); 430 431 REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start); 432 433 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, 434 MASTER_UPDATE_LOCK_DB_X, 435 (h_blank_start - 200 - 1) / optc1->opp_count, 436 MASTER_UPDATE_LOCK_DB_Y, 437 v_blank_start - 1); 438 439 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0, 440 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 0, 441 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, 100, 442 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1); 443 } 444 445 void optc2_lock_doublebuffer_disable(struct timing_generator *optc) 446 { 447 struct optc *optc1 = DCN10TG_FROM_TG(optc); 448 449 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, 450 MASTER_UPDATE_LOCK_DB_X, 451 0, 452 MASTER_UPDATE_LOCK_DB_Y, 453 0); 454 455 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0, 456 DIG_UPDATE_LOCATION, 0); 457 458 REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 0); 459 } 460 461 void optc2_setup_manual_trigger(struct timing_generator *optc) 462 { 463 struct optc *optc1 = DCN10TG_FROM_TG(optc); 464 465 /* Set the min/max selectors unconditionally so that 466 * DMCUB fw may change OTG timings when necessary 467 * TODO: Remove the w/a after fixing the issue in DMCUB firmware 468 */ 469 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 470 OTG_V_TOTAL_MIN_SEL, 1, 471 OTG_V_TOTAL_MAX_SEL, 1, 472 OTG_FORCE_LOCK_ON_EVENT, 0, 473 OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */ 474 475 REG_SET_8(OTG_TRIGA_CNTL, 0, 476 OTG_TRIGA_SOURCE_SELECT, 21, 477 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst, 478 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1, 479 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0, 480 OTG_TRIGA_POLARITY_SELECT, 0, 481 OTG_TRIGA_FREQUENCY_SELECT, 0, 482 OTG_TRIGA_DELAY, 0, 483 OTG_TRIGA_CLEAR, 1); 484 } 485 486 void optc2_program_manual_trigger(struct timing_generator *optc) 487 { 488 struct optc *optc1 = DCN10TG_FROM_TG(optc); 489 490 REG_SET(OTG_TRIGA_MANUAL_TRIG, 0, 491 OTG_TRIGA_MANUAL_TRIG, 1); 492 } 493 494 bool optc2_configure_crc(struct timing_generator *optc, 495 const struct crc_params *params) 496 { 497 struct optc *optc1 = DCN10TG_FROM_TG(optc); 498 499 REG_SET_2(OTG_CRC_CNTL2, 0, 500 OTG_CRC_DSC_MODE, params->dsc_mode, 501 OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode); 502 503 return optc1_configure_crc(optc, params); 504 } 505 506 507 void optc2_get_last_used_drr_vtotal(struct timing_generator *optc, uint32_t *refresh_rate) 508 { 509 struct optc *optc1 = DCN10TG_FROM_TG(optc); 510 511 REG_GET(OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, refresh_rate); 512 } 513 514 static struct timing_generator_funcs dcn20_tg_funcs = { 515 .validate_timing = optc1_validate_timing, 516 .program_timing = optc1_program_timing, 517 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 518 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 519 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 520 .program_global_sync = optc1_program_global_sync, 521 .enable_crtc = optc2_enable_crtc, 522 .disable_crtc = optc1_disable_crtc, 523 /* used by enable_timing_synchronization. Not need for FPGA */ 524 .is_counter_moving = optc1_is_counter_moving, 525 .get_position = optc1_get_position, 526 .get_frame_count = optc1_get_vblank_counter, 527 .get_scanoutpos = optc1_get_crtc_scanoutpos, 528 .get_otg_active_size = optc1_get_otg_active_size, 529 .set_early_control = optc1_set_early_control, 530 /* used by enable_timing_synchronization. Not need for FPGA */ 531 .wait_for_state = optc1_wait_for_state, 532 .set_blank = optc1_set_blank, 533 .is_blanked = optc1_is_blanked, 534 .set_blank_color = optc1_program_blank_color, 535 .enable_reset_trigger = optc1_enable_reset_trigger, 536 .enable_crtc_reset = optc1_enable_crtc_reset, 537 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 538 .triplebuffer_lock = optc2_triplebuffer_lock, 539 .triplebuffer_unlock = optc2_triplebuffer_unlock, 540 .disable_reset_trigger = optc1_disable_reset_trigger, 541 .lock = optc1_lock, 542 .unlock = optc1_unlock, 543 .lock_doublebuffer_enable = optc2_lock_doublebuffer_enable, 544 .lock_doublebuffer_disable = optc2_lock_doublebuffer_disable, 545 .enable_optc_clock = optc1_enable_optc_clock, 546 .set_drr = optc1_set_drr, 547 .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal, 548 .set_vtotal_min_max = optc1_set_vtotal_min_max, 549 .set_static_screen_control = optc1_set_static_screen_control, 550 .program_stereo = optc1_program_stereo, 551 .is_stereo_left_eye = optc1_is_stereo_left_eye, 552 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer, 553 .tg_init = optc1_tg_init, 554 .is_tg_enabled = optc1_is_tg_enabled, 555 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 556 .clear_optc_underflow = optc1_clear_optc_underflow, 557 .setup_global_swap_lock = NULL, 558 .get_crc = optc1_get_crc, 559 .configure_crc = optc2_configure_crc, 560 .set_dsc_config = optc2_set_dsc_config, 561 .get_dsc_status = optc2_get_dsc_status, 562 .set_dwb_source = optc2_set_dwb_source, 563 .set_odm_bypass = optc2_set_odm_bypass, 564 .set_odm_combine = optc2_set_odm_combine, 565 .get_optc_source = optc2_get_optc_source, 566 .set_gsl = optc2_set_gsl, 567 .set_gsl_source_select = optc2_set_gsl_source_select, 568 .set_vtg_params = optc1_set_vtg_params, 569 .program_manual_trigger = optc2_program_manual_trigger, 570 .setup_manual_trigger = optc2_setup_manual_trigger, 571 .get_hw_timing = optc1_get_hw_timing, 572 .align_vblanks = optc2_align_vblanks, 573 }; 574 575 void dcn20_timing_generator_init(struct optc *optc1) 576 { 577 optc1->base.funcs = &dcn20_tg_funcs; 578 579 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 580 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 581 582 optc1->min_h_blank = 32; 583 optc1->min_v_blank = 3; 584 optc1->min_v_blank_interlace = 5; 585 optc1->min_h_sync_width = 4;// Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue. 586 optc1->min_v_sync_width = 1; 587 } 588