1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "dcn20_optc.h" 28 #include "dc.h" 29 30 #define REG(reg)\ 31 optc1->tg_regs->reg 32 33 #define CTX \ 34 optc1->base.ctx 35 36 #undef FN 37 #define FN(reg_name, field_name) \ 38 optc1->tg_shift->field_name, optc1->tg_mask->field_name 39 40 /** 41 * Enable CRTC 42 * Enable CRTC - call ASIC Control Object to enable Timing generator. 43 */ 44 bool optc2_enable_crtc(struct timing_generator *optc) 45 { 46 /* TODO FPGA wait for answer 47 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE 48 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK 49 */ 50 struct optc *optc1 = DCN10TG_FROM_TG(optc); 51 52 /* opp instance for OTG. For DCN1.0, ODM is remoed. 53 * OPP and OPTC should 1:1 mapping 54 */ 55 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 56 OPTC_SEG0_SRC_SEL, optc->inst); 57 58 /* VTG enable first is for HW workaround */ 59 REG_UPDATE(CONTROL, 60 VTG0_ENABLE, 1); 61 62 /* Enable CRTC */ 63 REG_UPDATE_2(OTG_CONTROL, 64 OTG_DISABLE_POINT_CNTL, 3, 65 OTG_MASTER_EN, 1); 66 67 return true; 68 } 69 70 /** 71 * DRR double buffering control to select buffer point 72 * for V_TOTAL, H_TOTAL, VTOTAL_MIN, VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers 73 * Options: anytime, start of frame, dp start of frame (range timing) 74 */ 75 void optc2_set_timing_db_mode(struct timing_generator *optc, bool enable) 76 { 77 struct optc *optc1 = DCN10TG_FROM_TG(optc); 78 79 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; 80 81 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 82 OTG_RANGE_TIMING_DBUF_UPDATE_MODE, blank_data_double_buffer_enable); 83 } 84 85 /** 86 *For the below, I'm not sure how your GSL parameters are stored in your env, 87 * so I will assume a gsl_params struct for now 88 */ 89 void optc2_set_gsl(struct timing_generator *optc, 90 const struct gsl_params *params) 91 { 92 struct optc *optc1 = DCN10TG_FROM_TG(optc); 93 94 /** 95 * There are (MAX_OPTC+1)/2 gsl groups available for use. 96 * In each group (assign an OTG to a group by setting OTG_GSLX_EN = 1, 97 * set one of the OTGs to be the master (OTG_GSL_MASTER_EN = 1) and the rest are slaves. 98 */ 99 REG_UPDATE_5(OTG_GSL_CONTROL, 100 OTG_GSL0_EN, params->gsl0_en, 101 OTG_GSL1_EN, params->gsl1_en, 102 OTG_GSL2_EN, params->gsl2_en, 103 OTG_GSL_MASTER_EN, params->gsl_master_en, 104 OTG_GSL_MASTER_MODE, params->gsl_master_mode); 105 } 106 107 108 /* Use the gsl allow flip as the master update lock */ 109 void optc2_use_gsl_as_master_update_lock(struct timing_generator *optc, 110 const struct gsl_params *params) 111 { 112 struct optc *optc1 = DCN10TG_FROM_TG(optc); 113 114 REG_UPDATE(OTG_GSL_CONTROL, 115 OTG_MASTER_UPDATE_LOCK_GSL_EN, params->master_update_lock_gsl_en); 116 } 117 118 /* You can control the GSL timing by limiting GSL to a window (X,Y) */ 119 void optc2_set_gsl_window(struct timing_generator *optc, 120 const struct gsl_params *params) 121 { 122 struct optc *optc1 = DCN10TG_FROM_TG(optc); 123 124 REG_SET_2(OTG_GSL_WINDOW_X, 0, 125 OTG_GSL_WINDOW_START_X, params->gsl_window_start_x, 126 OTG_GSL_WINDOW_END_X, params->gsl_window_end_x); 127 REG_SET_2(OTG_GSL_WINDOW_Y, 0, 128 OTG_GSL_WINDOW_START_Y, params->gsl_window_start_y, 129 OTG_GSL_WINDOW_END_Y, params->gsl_window_end_y); 130 } 131 132 /** 133 * Vupdate keepout can be set to a window to block the update lock for that pipe from changing. 134 * Start offset begins with vstartup and goes for x number of clocks, 135 * end offset starts from end of vupdate to x number of clocks. 136 */ 137 void optc2_set_vupdate_keepout(struct timing_generator *optc, 138 const struct vupdate_keepout_params *params) 139 { 140 struct optc *optc1 = DCN10TG_FROM_TG(optc); 141 142 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0, 143 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, params->start_offset, 144 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, params->end_offset, 145 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, params->enable); 146 } 147 148 void optc2_set_gsl_source_select( 149 struct timing_generator *optc, 150 int group_idx, 151 uint32_t gsl_ready_signal) 152 { 153 struct optc *optc1 = DCN10TG_FROM_TG(optc); 154 155 switch (group_idx) { 156 case 1: 157 REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal); 158 break; 159 case 2: 160 REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal); 161 break; 162 case 3: 163 REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal); 164 break; 165 default: 166 break; 167 } 168 } 169 170 /* DSC encoder frame start controls: x = h position, line_num = # of lines from vstartup */ 171 void optc2_set_dsc_encoder_frame_start(struct timing_generator *optc, 172 int x_position, 173 int line_num) 174 { 175 struct optc *optc1 = DCN10TG_FROM_TG(optc); 176 177 REG_SET_2(OTG_DSC_START_POSITION, 0, 178 OTG_DSC_START_POSITION_X, x_position, 179 OTG_DSC_START_POSITION_LINE_NUM, line_num); 180 } 181 182 /* Set DSC-related configuration. 183 * dsc_mode: 0 disables DSC, other values enable DSC in specified format 184 * sc_bytes_per_pixel: Bytes per pixel in u3.28 format 185 * dsc_slice_width: Slice width in pixels 186 */ 187 void optc2_set_dsc_config(struct timing_generator *optc, 188 enum optc_dsc_mode dsc_mode, 189 uint32_t dsc_bytes_per_pixel, 190 uint32_t dsc_slice_width) 191 { 192 struct optc *optc1 = DCN10TG_FROM_TG(optc); 193 194 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, 195 OPTC_DSC_MODE, dsc_mode); 196 197 REG_SET(OPTC_BYTES_PER_PIXEL, 0, 198 OPTC_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel); 199 200 REG_UPDATE(OPTC_WIDTH_CONTROL, 201 OPTC_DSC_SLICE_WIDTH, dsc_slice_width); 202 } 203 204 /*TEMP: Need to figure out inheritance model here.*/ 205 bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) 206 { 207 return optc1_is_two_pixels_per_containter(timing); 208 } 209 210 void optc2_set_odm_bypass(struct timing_generator *optc, 211 const struct dc_crtc_timing *dc_crtc_timing) 212 { 213 struct optc *optc1 = DCN10TG_FROM_TG(optc); 214 uint32_t h_div_2 = 0; 215 216 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, 217 OPTC_NUM_OF_INPUT_SEGMENT, 0, 218 OPTC_SEG0_SRC_SEL, optc->inst, 219 OPTC_SEG1_SRC_SEL, 0xf); 220 REG_WRITE(OTG_H_TIMING_CNTL, 0); 221 222 h_div_2 = optc2_is_two_pixels_per_containter(dc_crtc_timing); 223 REG_UPDATE(OTG_H_TIMING_CNTL, 224 OTG_H_TIMING_DIV_BY2, h_div_2); 225 REG_SET(OPTC_MEMORY_CONFIG, 0, 226 OPTC_MEM_SEL, 0); 227 optc1->opp_count = 1; 228 } 229 230 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 231 struct dc_crtc_timing *timing) 232 { 233 struct optc *optc1 = DCN10TG_FROM_TG(optc); 234 /* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192 */ 235 int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right) 236 / opp_cnt; 237 int memory_mask = mpcc_hactive <= 2560 ? 0x3 : 0xf; 238 uint32_t data_fmt = 0; 239 240 /* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic 241 * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1); 242 * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start 243 * REG_SET_2(OTG_GLOBAL_CONTROL1, 0, 244 * MASTER_UPDATE_LOCK_DB_X, 160, 245 * MASTER_UPDATE_LOCK_DB_Y, 240); 246 */ 247 if (REG(OPTC_MEMORY_CONFIG)) 248 REG_SET(OPTC_MEMORY_CONFIG, 0, 249 OPTC_MEM_SEL, memory_mask << (optc->inst * 4)); 250 251 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) 252 data_fmt = 1; 253 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 254 data_fmt = 2; 255 256 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt); 257 258 ASSERT(opp_cnt == 2); 259 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, 260 OPTC_NUM_OF_INPUT_SEGMENT, 1, 261 OPTC_SEG0_SRC_SEL, opp_id[0], 262 OPTC_SEG1_SRC_SEL, opp_id[1]); 263 264 REG_UPDATE(OPTC_WIDTH_CONTROL, 265 OPTC_SEGMENT_WIDTH, mpcc_hactive); 266 267 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1); 268 optc1->opp_count = opp_cnt; 269 } 270 271 void optc2_get_optc_source(struct timing_generator *optc, 272 uint32_t *num_of_src_opp, 273 uint32_t *src_opp_id_0, 274 uint32_t *src_opp_id_1) 275 { 276 uint32_t num_of_input_segments; 277 struct optc *optc1 = DCN10TG_FROM_TG(optc); 278 279 REG_GET_3(OPTC_DATA_SOURCE_SELECT, 280 OPTC_NUM_OF_INPUT_SEGMENT, &num_of_input_segments, 281 OPTC_SEG0_SRC_SEL, src_opp_id_0, 282 OPTC_SEG1_SRC_SEL, src_opp_id_1); 283 284 if (num_of_input_segments == 1) 285 *num_of_src_opp = 2; 286 else 287 *num_of_src_opp = 1; 288 289 /* Work around VBIOS not updating OPTC_NUM_OF_INPUT_SEGMENT */ 290 if (*src_opp_id_1 == 0xf) 291 *num_of_src_opp = 1; 292 } 293 294 void optc2_set_dwb_source(struct timing_generator *optc, 295 uint32_t dwb_pipe_inst) 296 { 297 struct optc *optc1 = DCN10TG_FROM_TG(optc); 298 299 if (dwb_pipe_inst == 0) 300 REG_UPDATE(DWB_SOURCE_SELECT, 301 OPTC_DWB0_SOURCE_SELECT, optc->inst); 302 else if (dwb_pipe_inst == 1) 303 REG_UPDATE(DWB_SOURCE_SELECT, 304 OPTC_DWB1_SOURCE_SELECT, optc->inst); 305 } 306 307 void optc2_triplebuffer_lock(struct timing_generator *optc) 308 { 309 struct optc *optc1 = DCN10TG_FROM_TG(optc); 310 311 REG_SET(OTG_GLOBAL_CONTROL0, 0, 312 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); 313 314 REG_SET(OTG_VUPDATE_KEEPOUT, 0, 315 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1); 316 317 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 318 OTG_MASTER_UPDATE_LOCK, 1); 319 320 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) 321 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 322 UPDATE_LOCK_STATUS, 1, 323 1, 10); 324 } 325 326 void optc2_triplebuffer_unlock(struct timing_generator *optc) 327 { 328 struct optc *optc1 = DCN10TG_FROM_TG(optc); 329 330 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 331 OTG_MASTER_UPDATE_LOCK, 0); 332 333 REG_SET(OTG_VUPDATE_KEEPOUT, 0, 334 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 0); 335 336 } 337 338 void optc2_lock_doublebuffer_enable(struct timing_generator *optc) 339 { 340 struct optc *optc1 = DCN10TG_FROM_TG(optc); 341 uint32_t v_blank_start = 0; 342 uint32_t h_blank_start = 0; 343 344 REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 1); 345 346 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1, 347 DIG_UPDATE_LOCATION, 20); 348 349 REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start); 350 351 REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start); 352 353 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, 354 MASTER_UPDATE_LOCK_DB_X, 355 h_blank_start - 200 - 1, 356 MASTER_UPDATE_LOCK_DB_Y, 357 v_blank_start - 1); 358 } 359 360 void optc2_lock_doublebuffer_disable(struct timing_generator *optc) 361 { 362 struct optc *optc1 = DCN10TG_FROM_TG(optc); 363 364 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, 365 MASTER_UPDATE_LOCK_DB_X, 366 0, 367 MASTER_UPDATE_LOCK_DB_Y, 368 0); 369 370 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0, 371 DIG_UPDATE_LOCATION, 0); 372 373 REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 0); 374 } 375 376 void optc2_setup_manual_trigger(struct timing_generator *optc) 377 { 378 struct optc *optc1 = DCN10TG_FROM_TG(optc); 379 380 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 381 MANUAL_FLOW_CONTROL, 1); 382 383 REG_SET(OTG_GLOBAL_CONTROL2, 0, 384 MANUAL_FLOW_CONTROL_SEL, optc->inst); 385 386 REG_SET_8(OTG_TRIGA_CNTL, 0, 387 OTG_TRIGA_SOURCE_SELECT, 22, 388 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst, 389 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1, 390 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0, 391 OTG_TRIGA_POLARITY_SELECT, 0, 392 OTG_TRIGA_FREQUENCY_SELECT, 0, 393 OTG_TRIGA_DELAY, 0, 394 OTG_TRIGA_CLEAR, 1); 395 } 396 397 void optc2_program_manual_trigger(struct timing_generator *optc) 398 { 399 struct optc *optc1 = DCN10TG_FROM_TG(optc); 400 401 REG_SET(OTG_TRIGA_MANUAL_TRIG, 0, 402 OTG_TRIGA_MANUAL_TRIG, 1); 403 } 404 405 static struct timing_generator_funcs dcn20_tg_funcs = { 406 .validate_timing = optc1_validate_timing, 407 .program_timing = optc1_program_timing, 408 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 409 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 410 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 411 .program_global_sync = optc1_program_global_sync, 412 .enable_crtc = optc2_enable_crtc, 413 .disable_crtc = optc1_disable_crtc, 414 /* used by enable_timing_synchronization. Not need for FPGA */ 415 .is_counter_moving = optc1_is_counter_moving, 416 .get_position = optc1_get_position, 417 .get_frame_count = optc1_get_vblank_counter, 418 .get_scanoutpos = optc1_get_crtc_scanoutpos, 419 .get_otg_active_size = optc1_get_otg_active_size, 420 .set_early_control = optc1_set_early_control, 421 /* used by enable_timing_synchronization. Not need for FPGA */ 422 .wait_for_state = optc1_wait_for_state, 423 .set_blank = optc1_set_blank, 424 .is_blanked = optc1_is_blanked, 425 .set_blank_color = optc1_program_blank_color, 426 .enable_reset_trigger = optc1_enable_reset_trigger, 427 .enable_crtc_reset = optc1_enable_crtc_reset, 428 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 429 .triplebuffer_lock = optc2_triplebuffer_lock, 430 .triplebuffer_unlock = optc2_triplebuffer_unlock, 431 .disable_reset_trigger = optc1_disable_reset_trigger, 432 .lock = optc1_lock, 433 .unlock = optc1_unlock, 434 .lock_doublebuffer_enable = optc2_lock_doublebuffer_enable, 435 .lock_doublebuffer_disable = optc2_lock_doublebuffer_disable, 436 .enable_optc_clock = optc1_enable_optc_clock, 437 .set_drr = optc1_set_drr, 438 .set_static_screen_control = optc1_set_static_screen_control, 439 .program_stereo = optc1_program_stereo, 440 .is_stereo_left_eye = optc1_is_stereo_left_eye, 441 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer, 442 .tg_init = optc1_tg_init, 443 .is_tg_enabled = optc1_is_tg_enabled, 444 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 445 .clear_optc_underflow = optc1_clear_optc_underflow, 446 .setup_global_swap_lock = NULL, 447 .get_crc = optc1_get_crc, 448 .configure_crc = optc1_configure_crc, 449 .set_dsc_config = optc2_set_dsc_config, 450 .set_dwb_source = optc2_set_dwb_source, 451 .set_odm_bypass = optc2_set_odm_bypass, 452 .set_odm_combine = optc2_set_odm_combine, 453 .get_optc_source = optc2_get_optc_source, 454 .set_gsl = optc2_set_gsl, 455 .set_gsl_source_select = optc2_set_gsl_source_select, 456 .set_vtg_params = optc1_set_vtg_params, 457 .program_manual_trigger = optc2_program_manual_trigger, 458 .setup_manual_trigger = optc2_setup_manual_trigger, 459 .get_hw_timing = optc1_get_hw_timing, 460 }; 461 462 void dcn20_timing_generator_init(struct optc *optc1) 463 { 464 optc1->base.funcs = &dcn20_tg_funcs; 465 466 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 467 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 468 469 optc1->min_h_blank = 32; 470 optc1->min_v_blank = 3; 471 optc1->min_v_blank_interlace = 5; 472 optc1->min_h_sync_width = 4;// Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue. 473 optc1->min_v_sync_width = 1; 474 } 475 476