1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dcn20_mpc.h"
27 
28 #include "reg_helper.h"
29 #include "dc.h"
30 #include "mem_input.h"
31 #include "dcn10/dcn10_cm_common.h"
32 
33 #define REG(reg)\
34 	mpc20->mpc_regs->reg
35 
36 #define CTX \
37 	mpc20->base.ctx
38 
39 #undef FN
40 #define FN(reg_name, field_name) \
41 	mpc20->mpc_shift->field_name, mpc20->mpc_mask->field_name
42 
43 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
44 
45 void mpc2_update_blending(
46 	struct mpc *mpc,
47 	struct mpcc_blnd_cfg *blnd_cfg,
48 	int mpcc_id)
49 {
50 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
51 
52 	struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);
53 
54 	REG_UPDATE_7(MPCC_CONTROL[mpcc_id],
55 			MPCC_ALPHA_BLND_MODE,		blnd_cfg->alpha_mode,
56 			MPCC_ALPHA_MULTIPLIED_MODE,	blnd_cfg->pre_multiplied_alpha,
57 			MPCC_BLND_ACTIVE_OVERLAP_ONLY,	blnd_cfg->overlap_only,
58 			MPCC_GLOBAL_ALPHA,		blnd_cfg->global_alpha,
59 			MPCC_GLOBAL_GAIN,		blnd_cfg->global_gain,
60 			MPCC_BG_BPC,			blnd_cfg->background_color_bpc,
61 			MPCC_BOT_GAIN_MODE,		blnd_cfg->bottom_gain_mode);
62 
63 	REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain);
64 	REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain);
65 	REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain);
66 
67 	mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id);
68 	mpcc->blnd_cfg = *blnd_cfg;
69 }
70 
71 void mpc2_set_denorm(
72 		struct mpc *mpc,
73 		int opp_id,
74 		enum dc_color_depth output_depth)
75 {
76 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
77 	int denorm_mode = 0;
78 
79 	switch (output_depth) {
80 	case COLOR_DEPTH_666:
81 		denorm_mode = 1;
82 		break;
83 	case COLOR_DEPTH_888:
84 		denorm_mode = 2;
85 		break;
86 	case COLOR_DEPTH_999:
87 		denorm_mode = 3;
88 		break;
89 	case COLOR_DEPTH_101010:
90 		denorm_mode = 4;
91 		break;
92 	case COLOR_DEPTH_111111:
93 		denorm_mode = 5;
94 		break;
95 	case COLOR_DEPTH_121212:
96 		denorm_mode = 6;
97 		break;
98 	case COLOR_DEPTH_141414:
99 	case COLOR_DEPTH_161616:
100 	default:
101 		/* not valid used case! */
102 		break;
103 	}
104 
105 	REG_UPDATE(DENORM_CONTROL[opp_id],
106 			MPC_OUT_DENORM_MODE, denorm_mode);
107 }
108 
109 void mpc2_set_denorm_clamp(
110 		struct mpc *mpc,
111 		int opp_id,
112 		struct mpc_denorm_clamp denorm_clamp)
113 {
114 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
115 
116 	REG_UPDATE_2(DENORM_CONTROL[opp_id],
117 			MPC_OUT_DENORM_CLAMP_MAX_R_CR, denorm_clamp.clamp_max_r_cr,
118 			MPC_OUT_DENORM_CLAMP_MIN_R_CR, denorm_clamp.clamp_min_r_cr);
119 	REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id],
120 			MPC_OUT_DENORM_CLAMP_MAX_G_Y, denorm_clamp.clamp_max_g_y,
121 			MPC_OUT_DENORM_CLAMP_MIN_G_Y, denorm_clamp.clamp_min_g_y);
122 	REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id],
123 			MPC_OUT_DENORM_CLAMP_MAX_B_CB, denorm_clamp.clamp_max_b_cb,
124 			MPC_OUT_DENORM_CLAMP_MIN_B_CB, denorm_clamp.clamp_min_b_cb);
125 }
126 
127 
128 
129 void mpc2_set_output_csc(
130 		struct mpc *mpc,
131 		int opp_id,
132 		const uint16_t *regval,
133 		enum mpc_output_csc_mode ocsc_mode)
134 {
135 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
136 	struct color_matrices_reg ocsc_regs;
137 
138 	REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
139 
140 	if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE)
141 		return;
142 
143 	if (regval == NULL) {
144 		BREAK_TO_DEBUGGER();
145 		return;
146 	}
147 
148 	ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A;
149 	ocsc_regs.masks.csc_c11  = mpc20->mpc_mask->MPC_OCSC_C11_A;
150 	ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A;
151 	ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A;
152 
153 	if (ocsc_mode == MPC_OUTPUT_CSC_COEF_A) {
154 		ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]);
155 		ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]);
156 	} else {
157 		ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]);
158 		ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]);
159 	}
160 	cm_helper_program_color_matrices(
161 			mpc20->base.ctx,
162 			regval,
163 			&ocsc_regs);
164 }
165 
166 void mpc2_set_ocsc_default(
167 		struct mpc *mpc,
168 		int opp_id,
169 		enum dc_color_space color_space,
170 		enum mpc_output_csc_mode ocsc_mode)
171 {
172 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
173 	uint32_t arr_size;
174 	struct color_matrices_reg ocsc_regs;
175 	const uint16_t *regval = NULL;
176 
177 	REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
178 	if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE)
179 		return;
180 
181 	regval = find_color_matrix(color_space, &arr_size);
182 
183 	if (regval == NULL) {
184 		BREAK_TO_DEBUGGER();
185 		return;
186 	}
187 
188 	ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A;
189 	ocsc_regs.masks.csc_c11  = mpc20->mpc_mask->MPC_OCSC_C11_A;
190 	ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A;
191 	ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A;
192 
193 
194 	if (ocsc_mode == MPC_OUTPUT_CSC_COEF_A) {
195 		ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]);
196 		ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]);
197 	} else {
198 		ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]);
199 		ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]);
200 	}
201 
202 	cm_helper_program_color_matrices(
203 			mpc20->base.ctx,
204 			regval,
205 			&ocsc_regs);
206 }
207 
208 static void mpc2_ogam_get_reg_field(
209 		struct mpc *mpc,
210 		struct xfer_func_reg *reg)
211 {
212 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
213 
214 	reg->shifts.exp_region0_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
215 	reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
216 	reg->shifts.exp_region0_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
217 	reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
218 	reg->shifts.exp_region1_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
219 	reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
220 	reg->shifts.exp_region1_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
221 	reg->masks.exp_region1_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
222 	reg->shifts.field_region_end = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_B;
223 	reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B;
224 	reg->shifts.field_region_end_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B;
225 	reg->masks.field_region_end_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B;
226 	reg->shifts.field_region_end_base = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B;
227 	reg->masks.field_region_end_base = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B;
228 	reg->shifts.field_region_linear_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;
229 	reg->masks.field_region_linear_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;
230 	reg->shifts.exp_region_start = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_B;
231 	reg->masks.exp_region_start = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_B;
232 	reg->shifts.exp_resion_start_segment = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
233 	reg->masks.exp_resion_start_segment = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
234 }
235 
236 static void mpc20_power_on_ogam_lut(
237 		struct mpc *mpc, int mpcc_id,
238 		bool power_on)
239 {
240 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
241 
242 	REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0,
243 			MPCC_OGAM_MEM_PWR_FORCE, power_on == true ? 0:1);
244 
245 }
246 
247 static void mpc20_configure_ogam_lut(
248 		struct mpc *mpc, int mpcc_id,
249 		bool is_ram_a)
250 {
251 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
252 
253 	REG_UPDATE_2(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id],
254 			MPCC_OGAM_LUT_WRITE_EN_MASK, 7,
255 			MPCC_OGAM_LUT_RAM_SEL, is_ram_a == true ? 0:1);
256 
257 	REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0);
258 }
259 
260 static enum dc_lut_mode mpc20_get_ogam_current(struct mpc *mpc, int mpcc_id)
261 {
262 	enum dc_lut_mode mode;
263 	uint32_t state_mode;
264 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
265 
266 	REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id],
267 			MPCC_OGAM_CONFIG_STATUS, &state_mode);
268 
269 		switch (state_mode) {
270 		case 0:
271 			mode = LUT_BYPASS;
272 			break;
273 		case 1:
274 			mode = LUT_RAM_A;
275 			break;
276 		case 2:
277 			mode = LUT_RAM_B;
278 			break;
279 		default:
280 			mode = LUT_BYPASS;
281 			break;
282 		}
283 		return mode;
284 }
285 
286 static void mpc2_program_lutb(struct mpc *mpc, int mpcc_id,
287 			const struct pwl_params *params)
288 {
289 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
290 	struct xfer_func_reg gam_regs;
291 
292 	mpc2_ogam_get_reg_field(mpc, &gam_regs);
293 
294 	gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMB_START_CNTL_B[mpcc_id]);
295 	gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMB_START_CNTL_G[mpcc_id]);
296 	gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMB_START_CNTL_R[mpcc_id]);
297 	gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_B[mpcc_id]);
298 	gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_G[mpcc_id]);
299 	gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_R[mpcc_id]);
300 	gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMB_END_CNTL1_B[mpcc_id]);
301 	gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMB_END_CNTL2_B[mpcc_id]);
302 	gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMB_END_CNTL1_G[mpcc_id]);
303 	gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMB_END_CNTL2_G[mpcc_id]);
304 	gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMB_END_CNTL1_R[mpcc_id]);
305 	gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMB_END_CNTL2_R[mpcc_id]);
306 	gam_regs.region_start = REG(MPCC_OGAM_RAMB_REGION_0_1[mpcc_id]);
307 	gam_regs.region_end = REG(MPCC_OGAM_RAMB_REGION_32_33[mpcc_id]);
308 
309 	cm_helper_program_xfer_func(mpc20->base.ctx, params, &gam_regs);
310 
311 }
312 
313 static void mpc2_program_luta(struct mpc *mpc, int mpcc_id,
314 		const struct pwl_params *params)
315 {
316 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
317 	struct xfer_func_reg gam_regs;
318 
319 	mpc2_ogam_get_reg_field(mpc, &gam_regs);
320 
321 	gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMA_START_CNTL_B[mpcc_id]);
322 	gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMA_START_CNTL_G[mpcc_id]);
323 	gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMA_START_CNTL_R[mpcc_id]);
324 	gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_B[mpcc_id]);
325 	gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_G[mpcc_id]);
326 	gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_R[mpcc_id]);
327 	gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMA_END_CNTL1_B[mpcc_id]);
328 	gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMA_END_CNTL2_B[mpcc_id]);
329 	gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMA_END_CNTL1_G[mpcc_id]);
330 	gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMA_END_CNTL2_G[mpcc_id]);
331 	gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMA_END_CNTL1_R[mpcc_id]);
332 	gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMA_END_CNTL2_R[mpcc_id]);
333 	gam_regs.region_start = REG(MPCC_OGAM_RAMA_REGION_0_1[mpcc_id]);
334 	gam_regs.region_end = REG(MPCC_OGAM_RAMA_REGION_32_33[mpcc_id]);
335 
336 	cm_helper_program_xfer_func(mpc20->base.ctx, params, &gam_regs);
337 
338 }
339 
340 static void mpc20_program_ogam_pwl(
341 		struct mpc *mpc, int mpcc_id,
342 		const struct pwl_result_data *rgb,
343 		uint32_t num)
344 {
345 	uint32_t i;
346 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
347 
348 	for (i = 0 ; i < num; i++) {
349 		REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg);
350 		REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].green_reg);
351 		REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].blue_reg);
352 
353 		REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0,
354 				MPCC_OGAM_LUT_DATA, rgb[i].delta_red_reg);
355 		REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0,
356 				MPCC_OGAM_LUT_DATA, rgb[i].delta_green_reg);
357 		REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0,
358 				MPCC_OGAM_LUT_DATA, rgb[i].delta_blue_reg);
359 
360 	}
361 
362 }
363 
364 void apply_DEDCN20_305_wa(
365 		struct mpc *mpc,
366 		int mpcc_id, enum dc_lut_mode current_mode,
367 		enum dc_lut_mode next_mode)
368 {
369 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
370 
371 	if (mpc->ctx->dc->work_arounds.dedcn20_305_wa == false) {
372 		/*hw fixed in new review*/
373 		return;
374 	}
375 	if (current_mode == LUT_BYPASS)
376 		/*this will only work if OTG is locked.
377 		 *if we were to support OTG unlock case,
378 		 *the workaround will be more complex
379 		 */
380 		REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE,
381 			next_mode == LUT_RAM_A ? 1:2);
382 }
383 
384 void mpc2_set_output_gamma(
385 		struct mpc *mpc,
386 		int mpcc_id,
387 		const struct pwl_params *params)
388 {
389 	enum dc_lut_mode current_mode;
390 	enum dc_lut_mode next_mode;
391 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
392 
393 	if (params == NULL) {
394 		REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);
395 		return;
396 	}
397 	current_mode = mpc20_get_ogam_current(mpc, mpcc_id);
398 	if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
399 		next_mode = LUT_RAM_B;
400 	else
401 		next_mode = LUT_RAM_A;
402 
403 	mpc20_power_on_ogam_lut(mpc, mpcc_id, true);
404 	mpc20_configure_ogam_lut(mpc, mpcc_id, next_mode == LUT_RAM_A ? true:false);
405 
406 	if (next_mode == LUT_RAM_A)
407 		mpc2_program_luta(mpc, mpcc_id, params);
408 	else
409 		mpc2_program_lutb(mpc, mpcc_id, params);
410 
411 	apply_DEDCN20_305_wa(mpc, mpcc_id, current_mode, next_mode);
412 
413 	mpc20_program_ogam_pwl(
414 			mpc, mpcc_id, params->rgb_resulted, params->hw_points_num);
415 
416 	REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE,
417 		next_mode == LUT_RAM_A ? 1:2);
418 }
419 void mpc2_assert_idle_mpcc(struct mpc *mpc, int id)
420 {
421 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
422 	unsigned int mpc_disabled;
423 
424 	ASSERT(!(mpc20->mpcc_in_use_mask & 1 << id));
425 	REG_GET(MPCC_STATUS[id], MPCC_DISABLED, &mpc_disabled);
426 	if (mpc_disabled)
427 		return;
428 
429 	REG_WAIT(MPCC_STATUS[id],
430 			MPCC_IDLE, 1,
431 			1, 100000);
432 }
433 
434 void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)
435 {
436 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
437 	unsigned int top_sel, mpc_busy, mpc_idle, mpc_disabled;
438 	REG_GET(MPCC_STATUS[mpcc_id], MPCC_DISABLED, &mpc_disabled);
439 
440 	if (mpc_disabled) {
441 		ASSERT(0);
442 		return;
443 	}
444 
445 	REG_GET(MPCC_TOP_SEL[mpcc_id],
446 			MPCC_TOP_SEL, &top_sel);
447 
448 	if (top_sel == 0xf) {
449 		REG_GET_2(MPCC_STATUS[mpcc_id],
450 				MPCC_BUSY, &mpc_busy,
451 				MPCC_IDLE, &mpc_idle);
452 
453 		ASSERT(mpc_busy == 0);
454 		ASSERT(mpc_idle == 1);
455 	}
456 }
457 
458 static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
459 {
460 	mpcc->mpcc_id = mpcc_inst;
461 	mpcc->dpp_id = 0xf;
462 	mpcc->mpcc_bot = NULL;
463 	mpcc->blnd_cfg.overlap_only = false;
464 	mpcc->blnd_cfg.global_alpha = 0xff;
465 	mpcc->blnd_cfg.global_gain = 0xff;
466 	mpcc->blnd_cfg.background_color_bpc = 4;
467 	mpcc->blnd_cfg.bottom_gain_mode = 0;
468 	mpcc->blnd_cfg.top_gain = 0x1f000;
469 	mpcc->blnd_cfg.bottom_inside_gain = 0x1f000;
470 	mpcc->blnd_cfg.bottom_outside_gain = 0x1f000;
471 	mpcc->sm_cfg.enable = false;
472 }
473 
474 struct mpcc *mpc2_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id)
475 {
476 	struct mpcc *tmp_mpcc = tree->opp_list;
477 
478 	while (tmp_mpcc != NULL) {
479 		if (tmp_mpcc->dpp_id == 0xf || tmp_mpcc->dpp_id == dpp_id)
480 			return tmp_mpcc;
481 		tmp_mpcc = tmp_mpcc->mpcc_bot;
482 	}
483 	return NULL;
484 }
485 
486 const struct mpc_funcs dcn20_mpc_funcs = {
487 	.read_mpcc_state = mpc1_read_mpcc_state,
488 	.insert_plane = mpc1_insert_plane,
489 	.remove_mpcc = mpc1_remove_mpcc,
490 	.mpc_init = mpc1_mpc_init,
491 	.update_blending = mpc2_update_blending,
492 	.get_mpcc_for_dpp = mpc2_get_mpcc_for_dpp,
493 	.wait_for_idle = mpc2_assert_idle_mpcc,
494 	.assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect,
495 	.init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
496 	.set_denorm = mpc2_set_denorm,
497 	.set_denorm_clamp = mpc2_set_denorm_clamp,
498 	.set_output_csc = mpc2_set_output_csc,
499 	.set_ocsc_default = mpc2_set_ocsc_default,
500 	.set_output_gamma = mpc2_set_output_gamma,
501 };
502 
503 void dcn20_mpc_construct(struct dcn20_mpc *mpc20,
504 	struct dc_context *ctx,
505 	const struct dcn20_mpc_registers *mpc_regs,
506 	const struct dcn20_mpc_shift *mpc_shift,
507 	const struct dcn20_mpc_mask *mpc_mask,
508 	int num_mpcc)
509 {
510 	int i;
511 
512 	mpc20->base.ctx = ctx;
513 
514 	mpc20->base.funcs = &dcn20_mpc_funcs;
515 
516 	mpc20->mpc_regs = mpc_regs;
517 	mpc20->mpc_shift = mpc_shift;
518 	mpc20->mpc_mask = mpc_mask;
519 
520 	mpc20->mpcc_in_use_mask = 0;
521 	mpc20->num_mpcc = num_mpcc;
522 
523 	for (i = 0; i < MAX_MPCC; i++)
524 		mpc2_init_mpcc(&mpc20->base.mpcc_array[i], i);
525 }
526 
527