1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef __DC_MCIF_WB_DCN20_H__
27 #define __DC_MCIF_WB_DCN20_H__
28 
29 #define TO_DCN20_MMHUBBUB(mcif_wb_base) \
30 	container_of(mcif_wb_base, struct dcn20_mmhubbub, base)
31 
32 /* DCN */
33 #define BASE_INNER(seg) \
34 	DCE_BASE__INST0_SEG ## seg
35 
36 #define BASE(seg) \
37 	BASE_INNER(seg)
38 
39 #define MCIF_WB_COMMON_REG_LIST_DCN2_0(inst) \
40 	SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
41 	SRI(MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB, inst),\
42 	SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
43 	SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
44 	SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
45 	SRI(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
46 	SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
47 	SRI(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
48 	SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
49 	SRI(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\
50 	SRI(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\
51 	SRI(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\
52 	SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
53 	SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
54 	SRI(MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB, inst),\
55 	SRI(MCIF_WB_TEST_DEBUG_DATA, MCIF_WB, inst),\
56 	SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
57 	SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\
58 	SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
59 	SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\
60 	SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
61 	SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\
62 	SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
63 	SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\
64 	SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
65 	SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\
66 	SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
67 	SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\
68 	SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
69 	SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\
70 	SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
71 	SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\
72 	SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
73 	SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\
74 	SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
75 	SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\
76 	SRI(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),\
77 	SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\
78 	SRI(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),\
79 	SRI(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),\
80 	SRI(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst),\
81 	SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
82 	SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\
83 	SRI(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),\
84 	SRI(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),\
85 	SRI(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),\
86 	SRI(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),\
87 	SRI(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),\
88 	SRI(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),\
89 	SRI(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),\
90 	SRI(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),\
91 	SRI(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),\
92 	SRI(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),\
93 	SRI(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),\
94 	SRI(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),\
95 	SRI(SMU_WM_CONTROL, WBIF, inst)
96 
97 #define MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \
98 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
99 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
100 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
101 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
102 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
103 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
104 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
105 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
106 	SF(MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB_BUFMGR_CUR_LINE_R, mask_sh),\
107 	SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_VCE_INT_STATUS, mask_sh),\
108 	SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\
109 	SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\
110 	SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_BUF, mask_sh),\
111 	SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_BUFTAG, mask_sh),\
112 	SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_LINE_L, mask_sh),\
113 	SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_NEXT_BUF, mask_sh),\
114 	SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
115 	SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\
116 	SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_ACTIVE, mask_sh),\
117 	SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_SW_LOCKED, mask_sh),\
118 	SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_VCE_LOCKED, mask_sh),\
119 	SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_OVERFLOW, mask_sh),\
120 	SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_DISABLE, mask_sh),\
121 	SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
122 	SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_BUFTAG, mask_sh),\
123 	SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_NXT_BUF, mask_sh),\
124 	SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_FIELD, mask_sh),\
125 	SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_CUR_LINE_L, mask_sh),\
126 	SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_LONG_LINE_ERROR, mask_sh),\
127 	SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_SHORT_LINE_ERROR, mask_sh),\
128 	SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_FRAME_LENGTH_ERROR, mask_sh),\
129 	SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_CUR_LINE_R, mask_sh),\
130 	SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_NEW_CONTENT, mask_sh),\
131 	SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_COLOR_DEPTH, mask_sh),\
132 	SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ_BLACK_PIXEL, mask_sh),\
133 	SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
134 	SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_Y_OVERRUN, mask_sh),\
135 	SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_C_OVERRUN, mask_sh),\
136 	SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_ACTIVE, mask_sh),\
137 	SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_SW_LOCKED, mask_sh),\
138 	SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_VCE_LOCKED, mask_sh),\
139 	SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_OVERFLOW, mask_sh),\
140 	SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_DISABLE, mask_sh),\
141 	SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
142 	SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_BUFTAG, mask_sh),\
143 	SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_NXT_BUF, mask_sh),\
144 	SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_FIELD, mask_sh),\
145 	SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_CUR_LINE_L, mask_sh),\
146 	SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_LONG_LINE_ERROR, mask_sh),\
147 	SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_SHORT_LINE_ERROR, mask_sh),\
148 	SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_FRAME_LENGTH_ERROR, mask_sh),\
149 	SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_CUR_LINE_R, mask_sh),\
150 	SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_NEW_CONTENT, mask_sh),\
151 	SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_COLOR_DEPTH, mask_sh),\
152 	SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ_BLACK_PIXEL, mask_sh),\
153 	SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
154 	SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_Y_OVERRUN, mask_sh),\
155 	SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_C_OVERRUN, mask_sh),\
156 	SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_ACTIVE, mask_sh),\
157 	SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_SW_LOCKED, mask_sh),\
158 	SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_VCE_LOCKED, mask_sh),\
159 	SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_OVERFLOW, mask_sh),\
160 	SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_DISABLE, mask_sh),\
161 	SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
162 	SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_BUFTAG, mask_sh),\
163 	SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_NXT_BUF, mask_sh),\
164 	SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_FIELD, mask_sh),\
165 	SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_CUR_LINE_L, mask_sh),\
166 	SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_LONG_LINE_ERROR, mask_sh),\
167 	SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_SHORT_LINE_ERROR, mask_sh),\
168 	SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_FRAME_LENGTH_ERROR, mask_sh),\
169 	SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_CUR_LINE_R, mask_sh),\
170 	SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_NEW_CONTENT, mask_sh),\
171 	SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_COLOR_DEPTH, mask_sh),\
172 	SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ_BLACK_PIXEL, mask_sh),\
173 	SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
174 	SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_Y_OVERRUN, mask_sh),\
175 	SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_C_OVERRUN, mask_sh),\
176 	SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_ACTIVE, mask_sh),\
177 	SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_SW_LOCKED, mask_sh),\
178 	SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_VCE_LOCKED, mask_sh),\
179 	SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_OVERFLOW, mask_sh),\
180 	SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_DISABLE, mask_sh),\
181 	SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\
182 	SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_BUFTAG, mask_sh),\
183 	SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_NXT_BUF, mask_sh),\
184 	SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_FIELD, mask_sh),\
185 	SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_CUR_LINE_L, mask_sh),\
186 	SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_LONG_LINE_ERROR, mask_sh),\
187 	SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_SHORT_LINE_ERROR, mask_sh),\
188 	SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_FRAME_LENGTH_ERROR, mask_sh),\
189 	SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_CUR_LINE_R, mask_sh),\
190 	SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_NEW_CONTENT, mask_sh),\
191 	SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_COLOR_DEPTH, mask_sh),\
192 	SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ_BLACK_PIXEL, mask_sh),\
193 	SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ, mask_sh),\
194 	SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_Y_OVERRUN, mask_sh),\
195 	SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_C_OVERRUN, mask_sh),\
196 	SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\
197 	SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\
198 	SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\
199 	SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\
200 	SF(MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB_TEST_DEBUG_INDEX, mask_sh),\
201 	SF(MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA, MCIF_WB_TEST_DEBUG_DATA, mask_sh),\
202 	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\
203 	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\
204 	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\
205 	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\
206 	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\
207 	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\
208 	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\
209 	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\
210 	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\
211 	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\
212 	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\
213 	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\
214 	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\
215 	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\
216 	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\
217 	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\
218 	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\
219 	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\
220 	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\
221 	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\
222 	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\
223 	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\
224 	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\
225 	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
226 	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\
227 	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\
228 	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
229 	SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
230 	SF(MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB_CLI_CLOCK_GATER_OVERRIDE, mask_sh),\
231 	SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\
232 	SF(MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL, DIS_REFRESH_UNDER_NBPREQ, mask_sh),\
233 	SF(MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL, PERFRAME_SELF_REFRESH, mask_sh),\
234 	SF(MCIF_WB0_MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, mask_sh),\
235 	SF(MCIF_WB0_MCIF_WB_SECURITY_LEVEL, MCIF_WB_SECURITY_LEVEL, mask_sh),\
236 	SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\
237 	SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh),\
238 	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, mask_sh),\
239 	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, mask_sh),\
240 	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, mask_sh),\
241 	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, mask_sh),\
242 	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, mask_sh),\
243 	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, mask_sh),\
244 	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, mask_sh),\
245 	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, mask_sh),\
246 	SF(MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_WIDTH, mask_sh),\
247 	SF(MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_HEIGHT, mask_sh),\
248 	SF(MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_WIDTH, mask_sh),\
249 	SF(MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_HEIGHT, mask_sh),\
250 	SF(MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_WIDTH, mask_sh),\
251 	SF(MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_HEIGHT, mask_sh),\
252 	SF(MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_WIDTH, mask_sh),\
253 	SF(MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_HEIGHT, mask_sh),\
254 	SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_SEL, mask_sh),\
255 	SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_REQ, mask_sh),\
256 	SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_DIS, mask_sh),\
257 	SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_STATUS, mask_sh)
258 
259 #define MCIF_WB_REG_FIELD_LIST_DCN2_0(type) \
260 	type MCIF_WB_BUFMGR_ENABLE;\
261 	type MCIF_WB_BUFMGR_SW_INT_EN;\
262 	type MCIF_WB_BUFMGR_SW_INT_ACK;\
263 	type MCIF_WB_BUFMGR_SW_SLICE_INT_EN;\
264 	type MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN;\
265 	type MCIF_WB_BUFMGR_SW_LOCK;\
266 	type MCIF_WB_P_VMID;\
267 	type MCIF_WB_BUF_ADDR_FENCE_EN;\
268 	type MCIF_WB_BUFMGR_CUR_LINE_R;\
269 	type MCIF_WB_BUFMGR_VCE_INT_STATUS;\
270 	type MCIF_WB_BUFMGR_SW_INT_STATUS;\
271 	type MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS;\
272 	type MCIF_WB_BUFMGR_CUR_BUF;\
273 	type MCIF_WB_BUFMGR_BUFTAG;\
274 	type MCIF_WB_BUFMGR_CUR_LINE_L;\
275 	type MCIF_WB_BUFMGR_NEXT_BUF;\
276 	type MCIF_WB_BUF_LUMA_PITCH;\
277 	type MCIF_WB_BUF_CHROMA_PITCH;\
278 	type MCIF_WB_BUF_1_ACTIVE;\
279 	type MCIF_WB_BUF_1_SW_LOCKED;\
280 	type MCIF_WB_BUF_1_VCE_LOCKED;\
281 	type MCIF_WB_BUF_1_OVERFLOW;\
282 	type MCIF_WB_BUF_1_DISABLE;\
283 	type MCIF_WB_BUF_1_MODE;\
284 	type MCIF_WB_BUF_1_BUFTAG;\
285 	type MCIF_WB_BUF_1_NXT_BUF;\
286 	type MCIF_WB_BUF_1_FIELD;\
287 	type MCIF_WB_BUF_1_CUR_LINE_L;\
288 	type MCIF_WB_BUF_1_LONG_LINE_ERROR;\
289 	type MCIF_WB_BUF_1_SHORT_LINE_ERROR;\
290 	type MCIF_WB_BUF_1_FRAME_LENGTH_ERROR;\
291 	type MCIF_WB_BUF_1_CUR_LINE_R;\
292 	type MCIF_WB_BUF_1_NEW_CONTENT;\
293 	type MCIF_WB_BUF_1_COLOR_DEPTH;\
294 	type MCIF_WB_BUF_1_TMZ_BLACK_PIXEL;\
295 	type MCIF_WB_BUF_1_TMZ;\
296 	type MCIF_WB_BUF_1_Y_OVERRUN;\
297 	type MCIF_WB_BUF_1_C_OVERRUN;\
298 	type MCIF_WB_BUF_2_ACTIVE;\
299 	type MCIF_WB_BUF_2_SW_LOCKED;\
300 	type MCIF_WB_BUF_2_VCE_LOCKED;\
301 	type MCIF_WB_BUF_2_OVERFLOW;\
302 	type MCIF_WB_BUF_2_DISABLE;\
303 	type MCIF_WB_BUF_2_MODE;\
304 	type MCIF_WB_BUF_2_BUFTAG;\
305 	type MCIF_WB_BUF_2_NXT_BUF;\
306 	type MCIF_WB_BUF_2_FIELD;\
307 	type MCIF_WB_BUF_2_CUR_LINE_L;\
308 	type MCIF_WB_BUF_2_LONG_LINE_ERROR;\
309 	type MCIF_WB_BUF_2_SHORT_LINE_ERROR;\
310 	type MCIF_WB_BUF_2_FRAME_LENGTH_ERROR;\
311 	type MCIF_WB_BUF_2_CUR_LINE_R;\
312 	type MCIF_WB_BUF_2_NEW_CONTENT;\
313 	type MCIF_WB_BUF_2_COLOR_DEPTH;\
314 	type MCIF_WB_BUF_2_TMZ_BLACK_PIXEL;\
315 	type MCIF_WB_BUF_2_TMZ;\
316 	type MCIF_WB_BUF_2_Y_OVERRUN;\
317 	type MCIF_WB_BUF_2_C_OVERRUN;\
318 	type MCIF_WB_BUF_3_ACTIVE;\
319 	type MCIF_WB_BUF_3_SW_LOCKED;\
320 	type MCIF_WB_BUF_3_VCE_LOCKED;\
321 	type MCIF_WB_BUF_3_OVERFLOW;\
322 	type MCIF_WB_BUF_3_DISABLE;\
323 	type MCIF_WB_BUF_3_MODE;\
324 	type MCIF_WB_BUF_3_BUFTAG;\
325 	type MCIF_WB_BUF_3_NXT_BUF;\
326 	type MCIF_WB_BUF_3_FIELD;\
327 	type MCIF_WB_BUF_3_CUR_LINE_L;\
328 	type MCIF_WB_BUF_3_LONG_LINE_ERROR;\
329 	type MCIF_WB_BUF_3_SHORT_LINE_ERROR;\
330 	type MCIF_WB_BUF_3_FRAME_LENGTH_ERROR;\
331 	type MCIF_WB_BUF_3_CUR_LINE_R;\
332 	type MCIF_WB_BUF_3_NEW_CONTENT;\
333 	type MCIF_WB_BUF_3_COLOR_DEPTH;\
334 	type MCIF_WB_BUF_3_TMZ_BLACK_PIXEL;\
335 	type MCIF_WB_BUF_3_TMZ;\
336 	type MCIF_WB_BUF_3_Y_OVERRUN;\
337 	type MCIF_WB_BUF_3_C_OVERRUN;\
338 	type MCIF_WB_BUF_4_ACTIVE;\
339 	type MCIF_WB_BUF_4_SW_LOCKED;\
340 	type MCIF_WB_BUF_4_VCE_LOCKED;\
341 	type MCIF_WB_BUF_4_OVERFLOW;\
342 	type MCIF_WB_BUF_4_DISABLE;\
343 	type MCIF_WB_BUF_4_MODE;\
344 	type MCIF_WB_BUF_4_BUFTAG;\
345 	type MCIF_WB_BUF_4_NXT_BUF;\
346 	type MCIF_WB_BUF_4_FIELD;\
347 	type MCIF_WB_BUF_4_CUR_LINE_L;\
348 	type MCIF_WB_BUF_4_LONG_LINE_ERROR;\
349 	type MCIF_WB_BUF_4_SHORT_LINE_ERROR;\
350 	type MCIF_WB_BUF_4_FRAME_LENGTH_ERROR;\
351 	type MCIF_WB_BUF_4_CUR_LINE_R;\
352 	type MCIF_WB_BUF_4_NEW_CONTENT;\
353 	type MCIF_WB_BUF_4_COLOR_DEPTH;\
354 	type MCIF_WB_BUF_4_TMZ_BLACK_PIXEL;\
355 	type MCIF_WB_BUF_4_TMZ;\
356 	type MCIF_WB_BUF_4_Y_OVERRUN;\
357 	type MCIF_WB_BUF_4_C_OVERRUN;\
358 	type MCIF_WB_CLIENT_ARBITRATION_SLICE;\
359 	type MCIF_WB_TIME_PER_PIXEL;\
360 	type WM_CHANGE_ACK_FORCE_ON;\
361 	type MCIF_WB_CLI_WATERMARK_MASK;\
362 	type MCIF_WB_TEST_DEBUG_INDEX;\
363 	type MCIF_WB_TEST_DEBUG_DATA;\
364 	type MCIF_WB_BUF_1_ADDR_Y;\
365 	type MCIF_WB_BUF_1_ADDR_Y_OFFSET;\
366 	type MCIF_WB_BUF_1_ADDR_C;\
367 	type MCIF_WB_BUF_1_ADDR_C_OFFSET;\
368 	type MCIF_WB_BUF_2_ADDR_Y;\
369 	type MCIF_WB_BUF_2_ADDR_Y_OFFSET;\
370 	type MCIF_WB_BUF_2_ADDR_C;\
371 	type MCIF_WB_BUF_2_ADDR_C_OFFSET;\
372 	type MCIF_WB_BUF_3_ADDR_Y;\
373 	type MCIF_WB_BUF_3_ADDR_Y_OFFSET;\
374 	type MCIF_WB_BUF_3_ADDR_C;\
375 	type MCIF_WB_BUF_3_ADDR_C_OFFSET;\
376 	type MCIF_WB_BUF_4_ADDR_Y;\
377 	type MCIF_WB_BUF_4_ADDR_Y_OFFSET;\
378 	type MCIF_WB_BUF_4_ADDR_C;\
379 	type MCIF_WB_BUF_4_ADDR_C_OFFSET;\
380 	type MCIF_WB_BUFMGR_VCE_LOCK_IGNORE;\
381 	type MCIF_WB_BUFMGR_VCE_INT_EN;\
382 	type MCIF_WB_BUFMGR_VCE_INT_ACK;\
383 	type MCIF_WB_BUFMGR_VCE_SLICE_INT_EN;\
384 	type MCIF_WB_BUFMGR_VCE_LOCK;\
385 	type MCIF_WB_BUFMGR_SLICE_SIZE;\
386 	type NB_PSTATE_CHANGE_REFRESH_WATERMARK;\
387 	type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST;\
388 	type NB_PSTATE_CHANGE_FORCE_ON;\
389 	type NB_PSTATE_ALLOW_FOR_URGENT;\
390 	type NB_PSTATE_CHANGE_WATERMARK_MASK;\
391 	type MCIF_WB_CLI_WATERMARK;\
392 	type MCIF_WB_CLI_CLOCK_GATER_OVERRIDE;\
393 	type MCIF_WB_PITCH_SIZE_WARMUP;\
394 	type DIS_REFRESH_UNDER_NBPREQ;\
395 	type PERFRAME_SELF_REFRESH;\
396 	type MAX_SCALED_TIME_TO_URGENT;\
397 	type MCIF_WB_SECURITY_LEVEL;\
398 	type MCIF_WB_BUF_LUMA_SIZE;\
399 	type MCIF_WB_BUF_CHROMA_SIZE;\
400 	type MCIF_WB_BUF_1_ADDR_Y_HIGH;\
401 	type MCIF_WB_BUF_1_ADDR_C_HIGH;\
402 	type MCIF_WB_BUF_2_ADDR_Y_HIGH;\
403 	type MCIF_WB_BUF_2_ADDR_C_HIGH;\
404 	type MCIF_WB_BUF_3_ADDR_Y_HIGH;\
405 	type MCIF_WB_BUF_3_ADDR_C_HIGH;\
406 	type MCIF_WB_BUF_4_ADDR_Y_HIGH;\
407 	type MCIF_WB_BUF_4_ADDR_C_HIGH;\
408 	type MCIF_WB_BUF_1_RESOLUTION_WIDTH;\
409 	type MCIF_WB_BUF_1_RESOLUTION_HEIGHT;\
410 	type MCIF_WB_BUF_2_RESOLUTION_WIDTH;\
411 	type MCIF_WB_BUF_2_RESOLUTION_HEIGHT;\
412 	type MCIF_WB_BUF_3_RESOLUTION_WIDTH;\
413 	type MCIF_WB_BUF_3_RESOLUTION_HEIGHT;\
414 	type MCIF_WB_BUF_4_RESOLUTION_WIDTH;\
415 	type MCIF_WB_BUF_4_RESOLUTION_HEIGHT;\
416 	type MCIF_WB0_WM_CHG_SEL;\
417 	type MCIF_WB0_WM_CHG_REQ;\
418 	type MCIF_WB0_WM_CHG_ACK_INT_DIS;\
419 	type MCIF_WB0_WM_CHG_ACK_INT_STATUS
420 
421 #define MCIF_WB_REG_VARIABLE_LIST_DCN2_0 \
422 	uint32_t MCIF_WB_BUFMGR_SW_CONTROL;\
423 	uint32_t MCIF_WB_BUFMGR_CUR_LINE_R;\
424 	uint32_t MCIF_WB_BUFMGR_STATUS;\
425 	uint32_t MCIF_WB_BUF_PITCH;\
426 	uint32_t MCIF_WB_BUF_1_STATUS;\
427 	uint32_t MCIF_WB_BUF_1_STATUS2;\
428 	uint32_t MCIF_WB_BUF_2_STATUS;\
429 	uint32_t MCIF_WB_BUF_2_STATUS2;\
430 	uint32_t MCIF_WB_BUF_3_STATUS;\
431 	uint32_t MCIF_WB_BUF_3_STATUS2;\
432 	uint32_t MCIF_WB_BUF_4_STATUS;\
433 	uint32_t MCIF_WB_BUF_4_STATUS2;\
434 	uint32_t MCIF_WB_ARBITRATION_CONTROL;\
435 	uint32_t MCIF_WB_SCLK_CHANGE;\
436 	uint32_t MCIF_WB_TEST_DEBUG_INDEX;\
437 	uint32_t MCIF_WB_TEST_DEBUG_DATA;\
438 	uint32_t MCIF_WB_BUF_1_ADDR_Y;\
439 	uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSET;\
440 	uint32_t MCIF_WB_BUF_1_ADDR_C;\
441 	uint32_t MCIF_WB_BUF_1_ADDR_C_OFFSET;\
442 	uint32_t MCIF_WB_BUF_2_ADDR_Y;\
443 	uint32_t MCIF_WB_BUF_2_ADDR_Y_OFFSET;\
444 	uint32_t MCIF_WB_BUF_2_ADDR_C;\
445 	uint32_t MCIF_WB_BUF_2_ADDR_C_OFFSET;\
446 	uint32_t MCIF_WB_BUF_3_ADDR_Y;\
447 	uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET;\
448 	uint32_t MCIF_WB_BUF_3_ADDR_C;\
449 	uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET;\
450 	uint32_t MCIF_WB_BUF_4_ADDR_Y;\
451 	uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET;\
452 	uint32_t MCIF_WB_BUF_4_ADDR_C;\
453 	uint32_t MCIF_WB_BUF_4_ADDR_C_OFFSET;\
454 	uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;\
455 	uint32_t MCIF_WB_NB_PSTATE_LATENCY_WATERMARK;\
456 	uint32_t MCIF_WB_NB_PSTATE_CONTROL;\
457 	uint32_t MCIF_WB_WATERMARK;\
458 	uint32_t MCIF_WB_CLOCK_GATER_CONTROL;\
459 	uint32_t MCIF_WB_WARM_UP_CNTL;\
460 	uint32_t MCIF_WB_SELF_REFRESH_CONTROL;\
461 	uint32_t MULTI_LEVEL_QOS_CTRL;\
462 	uint32_t MCIF_WB_SECURITY_LEVEL;\
463 	uint32_t MCIF_WB_BUF_LUMA_SIZE;\
464 	uint32_t MCIF_WB_BUF_CHROMA_SIZE;\
465 	uint32_t MCIF_WB_BUF_1_ADDR_Y_HIGH;\
466 	uint32_t MCIF_WB_BUF_1_ADDR_C_HIGH;\
467 	uint32_t MCIF_WB_BUF_2_ADDR_Y_HIGH;\
468 	uint32_t MCIF_WB_BUF_2_ADDR_C_HIGH;\
469 	uint32_t MCIF_WB_BUF_3_ADDR_Y_HIGH;\
470 	uint32_t MCIF_WB_BUF_3_ADDR_C_HIGH;\
471 	uint32_t MCIF_WB_BUF_4_ADDR_Y_HIGH;\
472 	uint32_t MCIF_WB_BUF_4_ADDR_C_HIGH;\
473 	uint32_t MCIF_WB_BUF_1_RESOLUTION;\
474 	uint32_t MCIF_WB_BUF_2_RESOLUTION;\
475 	uint32_t MCIF_WB_BUF_3_RESOLUTION;\
476 	uint32_t MCIF_WB_BUF_4_RESOLUTION;\
477 	uint32_t SMU_WM_CONTROL
478 
479 struct dcn20_mmhubbub_registers {
480 	MCIF_WB_REG_VARIABLE_LIST_DCN2_0;
481 };
482 
483 
484 struct dcn20_mmhubbub_mask {
485 	MCIF_WB_REG_FIELD_LIST_DCN2_0(uint32_t);
486 };
487 
488 struct dcn20_mmhubbub_shift {
489 	MCIF_WB_REG_FIELD_LIST_DCN2_0(uint8_t);
490 };
491 
492 struct dcn20_mmhubbub {
493 	struct mcif_wb base;
494 	const struct dcn20_mmhubbub_registers *mcif_wb_regs;
495 	const struct dcn20_mmhubbub_shift *mcif_wb_shift;
496 	const struct dcn20_mmhubbub_mask *mcif_wb_mask;
497 };
498 
499 void mmhubbub2_config_mcif_irq(struct mcif_wb *mcif_wb,
500 	struct mcif_irq_params *params);
501 
502 void mmhubbub2_enable_mcif(struct mcif_wb *mcif_wb);
503 
504 void mmhubbub2_disable_mcif(struct mcif_wb *mcif_wb);
505 
506 void mcifwb2_dump_frame(struct mcif_wb *mcif_wb,
507 	struct mcif_buf_params *mcif_params,
508 	enum dwb_scaler_mode out_format,
509 	unsigned int dest_width,
510 	unsigned int dest_height,
511 	struct mcif_wb_frame_dump_info *dump_info,
512 	unsigned char *luma_buffer,
513 	unsigned char *chroma_buffer,
514 	unsigned char *dest_luma_buffer,
515 	unsigned char *dest_chroma_buffer);
516 
517 void dcn20_mmhubbub_construct(struct dcn20_mmhubbub *mcif_wb20,
518 	struct dc_context *ctx,
519 	const struct dcn20_mmhubbub_registers *mcif_wb_regs,
520 	const struct dcn20_mmhubbub_shift *mcif_wb_shift,
521 	const struct dcn20_mmhubbub_mask *mcif_wb_mask,
522 	int inst);
523 
524 #endif
525