1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HWSS_DCN20_H__ 27 #define __DC_HWSS_DCN20_H__ 28 29 #include "hw_sequencer_private.h" 30 31 bool dcn20_set_blend_lut( 32 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state); 33 bool dcn20_set_shaper_3dlut( 34 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state); 35 void dcn20_program_front_end_for_ctx( 36 struct dc *dc, 37 struct dc_state *context); 38 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx); 39 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx); 40 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 41 const struct dc_plane_state *plane_state); 42 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 43 const struct dc_stream_state *stream); 44 void dcn20_program_output_csc(struct dc *dc, 45 struct pipe_ctx *pipe_ctx, 46 enum dc_color_space colorspace, 47 uint16_t *matrix, 48 int opp_id); 49 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx); 50 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, 51 struct dc_link_settings *link_settings); 52 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx); 53 void dcn20_blank_pixel_data( 54 struct dc *dc, 55 struct pipe_ctx *pipe_ctx, 56 bool blank); 57 void dcn20_pipe_control_lock( 58 struct dc *dc, 59 struct pipe_ctx *pipe, 60 bool lock); 61 void dcn20_pipe_control_lock_global( 62 struct dc *dc, 63 struct pipe_ctx *pipe, 64 bool lock); 65 void dcn20_prepare_bandwidth( 66 struct dc *dc, 67 struct dc_state *context); 68 void dcn20_optimize_bandwidth( 69 struct dc *dc, 70 struct dc_state *context); 71 bool dcn20_update_bandwidth( 72 struct dc *dc, 73 struct dc_state *context); 74 void dcn20_reset_hw_ctx_wrap( 75 struct dc *dc, 76 struct dc_state *context); 77 enum dc_status dcn20_enable_stream_timing( 78 struct pipe_ctx *pipe_ctx, 79 struct dc_state *context, 80 struct dc *dc); 81 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx); 82 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx); 83 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx); 84 void dcn20_init_blank( 85 struct dc *dc, 86 struct timing_generator *tg); 87 void dcn20_disable_vga( 88 struct dce_hwseq *hws); 89 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx); 90 void dcn20_enable_power_gating_plane( 91 struct dce_hwseq *hws, 92 bool enable); 93 void dcn20_dpp_pg_control( 94 struct dce_hwseq *hws, 95 unsigned int dpp_inst, 96 bool power_on); 97 void dcn20_hubp_pg_control( 98 struct dce_hwseq *hws, 99 unsigned int hubp_inst, 100 bool power_on); 101 void dcn20_program_triple_buffer( 102 const struct dc *dc, 103 struct pipe_ctx *pipe_ctx, 104 bool enable_triple_buffer); 105 void dcn20_enable_writeback( 106 struct dc *dc, 107 struct dc_writeback_info *wb_info, 108 struct dc_state *context); 109 void dcn20_disable_writeback( 110 struct dc *dc, 111 unsigned int dwb_pipe_inst); 112 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); 113 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx); 114 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx); 115 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx); 116 void dcn20_init_vm_ctx( 117 struct dce_hwseq *hws, 118 struct dc *dc, 119 struct dc_virtual_addr_space_config *va_config, 120 int vmid); 121 void dcn20_set_flip_control_gsl( 122 struct pipe_ctx *pipe_ctx, 123 bool flip_immediate); 124 void dcn20_dsc_pg_control( 125 struct dce_hwseq *hws, 126 unsigned int dsc_inst, 127 bool power_on); 128 void dcn20_fpga_init_hw(struct dc *dc); 129 bool dcn20_wait_for_blank_complete( 130 struct output_pixel_processor *opp); 131 void dcn20_dccg_init(struct dce_hwseq *hws); 132 int dcn20_init_sys_ctx(struct dce_hwseq *hws, 133 struct dc *dc, 134 struct dc_phy_addr_space_config *pa_config); 135 136 #endif /* __DC_HWSS_DCN20_H__ */ 137 138