1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include <linux/delay.h> 26 27 #include "dm_services.h" 28 #include "basics/dc_common.h" 29 #include "dm_helpers.h" 30 #include "core_types.h" 31 #include "resource.h" 32 #include "dcn20_resource.h" 33 #include "dcn20_hwseq.h" 34 #include "dce/dce_hwseq.h" 35 #include "dcn20_dsc.h" 36 #include "dcn20_optc.h" 37 #include "abm.h" 38 #include "clk_mgr.h" 39 #include "dmcu.h" 40 #include "hubp.h" 41 #include "timing_generator.h" 42 #include "opp.h" 43 #include "ipp.h" 44 #include "mpc.h" 45 #include "mcif_wb.h" 46 #include "dchubbub.h" 47 #include "reg_helper.h" 48 #include "dcn10/dcn10_cm_common.h" 49 #include "vm_helper.h" 50 #include "dccg.h" 51 #include "dc_dmub_srv.h" 52 #include "dce/dmub_hw_lock_mgr.h" 53 #include "hw_sequencer.h" 54 #include "dpcd_defs.h" 55 #include "inc/link_enc_cfg.h" 56 #include "link_hwss.h" 57 #include "link.h" 58 59 #define DC_LOGGER_INIT(logger) 60 61 #define CTX \ 62 hws->ctx 63 #define REG(reg)\ 64 hws->regs->reg 65 66 #undef FN 67 #define FN(reg_name, field_name) \ 68 hws->shifts->field_name, hws->masks->field_name 69 70 static int find_free_gsl_group(const struct dc *dc) 71 { 72 if (dc->res_pool->gsl_groups.gsl_0 == 0) 73 return 1; 74 if (dc->res_pool->gsl_groups.gsl_1 == 0) 75 return 2; 76 if (dc->res_pool->gsl_groups.gsl_2 == 0) 77 return 3; 78 79 return 0; 80 } 81 82 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock) 83 * This is only used to lock pipes in pipe splitting case with immediate flip 84 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate, 85 * so we get tearing with freesync since we cannot flip multiple pipes 86 * atomically. 87 * We use GSL for this: 88 * - immediate flip: find first available GSL group if not already assigned 89 * program gsl with that group, set current OTG as master 90 * and always us 0x4 = AND of flip_ready from all pipes 91 * - vsync flip: disable GSL if used 92 * 93 * Groups in stream_res are stored as +1 from HW registers, i.e. 94 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1 95 * Using a magic value like -1 would require tracking all inits/resets 96 */ 97 static void dcn20_setup_gsl_group_as_lock( 98 const struct dc *dc, 99 struct pipe_ctx *pipe_ctx, 100 bool enable) 101 { 102 struct gsl_params gsl; 103 int group_idx; 104 105 memset(&gsl, 0, sizeof(struct gsl_params)); 106 107 if (enable) { 108 /* return if group already assigned since GSL was set up 109 * for vsync flip, we would unassign so it can't be "left over" 110 */ 111 if (pipe_ctx->stream_res.gsl_group > 0) 112 return; 113 114 group_idx = find_free_gsl_group(dc); 115 ASSERT(group_idx != 0); 116 pipe_ctx->stream_res.gsl_group = group_idx; 117 118 /* set gsl group reg field and mark resource used */ 119 switch (group_idx) { 120 case 1: 121 gsl.gsl0_en = 1; 122 dc->res_pool->gsl_groups.gsl_0 = 1; 123 break; 124 case 2: 125 gsl.gsl1_en = 1; 126 dc->res_pool->gsl_groups.gsl_1 = 1; 127 break; 128 case 3: 129 gsl.gsl2_en = 1; 130 dc->res_pool->gsl_groups.gsl_2 = 1; 131 break; 132 default: 133 BREAK_TO_DEBUGGER(); 134 return; // invalid case 135 } 136 gsl.gsl_master_en = 1; 137 } else { 138 group_idx = pipe_ctx->stream_res.gsl_group; 139 if (group_idx == 0) 140 return; // if not in use, just return 141 142 pipe_ctx->stream_res.gsl_group = 0; 143 144 /* unset gsl group reg field and mark resource free */ 145 switch (group_idx) { 146 case 1: 147 gsl.gsl0_en = 0; 148 dc->res_pool->gsl_groups.gsl_0 = 0; 149 break; 150 case 2: 151 gsl.gsl1_en = 0; 152 dc->res_pool->gsl_groups.gsl_1 = 0; 153 break; 154 case 3: 155 gsl.gsl2_en = 0; 156 dc->res_pool->gsl_groups.gsl_2 = 0; 157 break; 158 default: 159 BREAK_TO_DEBUGGER(); 160 return; 161 } 162 gsl.gsl_master_en = 0; 163 } 164 165 /* at this point we want to program whether it's to enable or disable */ 166 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && 167 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { 168 pipe_ctx->stream_res.tg->funcs->set_gsl( 169 pipe_ctx->stream_res.tg, 170 &gsl); 171 172 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( 173 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); 174 } else 175 BREAK_TO_DEBUGGER(); 176 } 177 178 void dcn20_set_flip_control_gsl( 179 struct pipe_ctx *pipe_ctx, 180 bool flip_immediate) 181 { 182 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) 183 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( 184 pipe_ctx->plane_res.hubp, flip_immediate); 185 186 } 187 188 void dcn20_enable_power_gating_plane( 189 struct dce_hwseq *hws, 190 bool enable) 191 { 192 bool force_on = true; /* disable power gating */ 193 uint32_t org_ip_request_cntl = 0; 194 195 if (enable) 196 force_on = false; 197 198 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 199 if (org_ip_request_cntl == 0) 200 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 201 202 /* DCHUBP0/1/2/3/4/5 */ 203 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); 204 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); 205 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); 206 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); 207 if (REG(DOMAIN8_PG_CONFIG)) 208 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 209 if (REG(DOMAIN10_PG_CONFIG)) 210 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 211 212 /* DPP0/1/2/3/4/5 */ 213 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); 214 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); 215 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); 216 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); 217 if (REG(DOMAIN9_PG_CONFIG)) 218 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 219 if (REG(DOMAIN11_PG_CONFIG)) 220 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 221 222 /* DCS0/1/2/3/4/5 */ 223 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on); 224 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on); 225 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on); 226 if (REG(DOMAIN19_PG_CONFIG)) 227 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on); 228 if (REG(DOMAIN20_PG_CONFIG)) 229 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on); 230 if (REG(DOMAIN21_PG_CONFIG)) 231 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); 232 233 if (org_ip_request_cntl == 0) 234 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 235 236 } 237 238 void dcn20_dccg_init(struct dce_hwseq *hws) 239 { 240 /* 241 * set MICROSECOND_TIME_BASE_DIV 242 * 100Mhz refclk -> 0x120264 243 * 27Mhz refclk -> 0x12021b 244 * 48Mhz refclk -> 0x120230 245 * 246 */ 247 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); 248 249 /* 250 * set MILLISECOND_TIME_BASE_DIV 251 * 100Mhz refclk -> 0x1186a0 252 * 27Mhz refclk -> 0x106978 253 * 48Mhz refclk -> 0x10bb80 254 * 255 */ 256 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); 257 258 /* This value is dependent on the hardware pipeline delay so set once per SOC */ 259 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c); 260 } 261 262 void dcn20_disable_vga( 263 struct dce_hwseq *hws) 264 { 265 REG_WRITE(D1VGA_CONTROL, 0); 266 REG_WRITE(D2VGA_CONTROL, 0); 267 REG_WRITE(D3VGA_CONTROL, 0); 268 REG_WRITE(D4VGA_CONTROL, 0); 269 REG_WRITE(D5VGA_CONTROL, 0); 270 REG_WRITE(D6VGA_CONTROL, 0); 271 } 272 273 void dcn20_program_triple_buffer( 274 const struct dc *dc, 275 struct pipe_ctx *pipe_ctx, 276 bool enable_triple_buffer) 277 { 278 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { 279 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( 280 pipe_ctx->plane_res.hubp, 281 enable_triple_buffer); 282 } 283 } 284 285 /* Blank pixel data during initialization */ 286 void dcn20_init_blank( 287 struct dc *dc, 288 struct timing_generator *tg) 289 { 290 struct dce_hwseq *hws = dc->hwseq; 291 enum dc_color_space color_space; 292 struct tg_color black_color = {0}; 293 struct output_pixel_processor *opp = NULL; 294 struct output_pixel_processor *bottom_opp = NULL; 295 uint32_t num_opps, opp_id_src0, opp_id_src1; 296 uint32_t otg_active_width, otg_active_height; 297 298 /* program opp dpg blank color */ 299 color_space = COLOR_SPACE_SRGB; 300 color_space_to_black_color(dc, color_space, &black_color); 301 302 /* get the OTG active size */ 303 tg->funcs->get_otg_active_size(tg, 304 &otg_active_width, 305 &otg_active_height); 306 307 /* get the OPTC source */ 308 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 309 310 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { 311 ASSERT(false); 312 return; 313 } 314 opp = dc->res_pool->opps[opp_id_src0]; 315 316 if (num_opps == 2) { 317 otg_active_width = otg_active_width / 2; 318 319 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { 320 ASSERT(false); 321 return; 322 } 323 bottom_opp = dc->res_pool->opps[opp_id_src1]; 324 } 325 326 opp->funcs->opp_set_disp_pattern_generator( 327 opp, 328 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 329 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 330 COLOR_DEPTH_UNDEFINED, 331 &black_color, 332 otg_active_width, 333 otg_active_height, 334 0); 335 336 if (num_opps == 2) { 337 bottom_opp->funcs->opp_set_disp_pattern_generator( 338 bottom_opp, 339 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 340 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 341 COLOR_DEPTH_UNDEFINED, 342 &black_color, 343 otg_active_width, 344 otg_active_height, 345 0); 346 } 347 348 hws->funcs.wait_for_blank_complete(opp); 349 } 350 351 void dcn20_dsc_pg_control( 352 struct dce_hwseq *hws, 353 unsigned int dsc_inst, 354 bool power_on) 355 { 356 uint32_t power_gate = power_on ? 0 : 1; 357 uint32_t pwr_status = power_on ? 0 : 2; 358 uint32_t org_ip_request_cntl = 0; 359 360 if (hws->ctx->dc->debug.disable_dsc_power_gate) 361 return; 362 363 if (REG(DOMAIN16_PG_CONFIG) == 0) 364 return; 365 366 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 367 if (org_ip_request_cntl == 0) 368 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 369 370 switch (dsc_inst) { 371 case 0: /* DSC0 */ 372 REG_UPDATE(DOMAIN16_PG_CONFIG, 373 DOMAIN16_POWER_GATE, power_gate); 374 375 REG_WAIT(DOMAIN16_PG_STATUS, 376 DOMAIN16_PGFSM_PWR_STATUS, pwr_status, 377 1, 1000); 378 break; 379 case 1: /* DSC1 */ 380 REG_UPDATE(DOMAIN17_PG_CONFIG, 381 DOMAIN17_POWER_GATE, power_gate); 382 383 REG_WAIT(DOMAIN17_PG_STATUS, 384 DOMAIN17_PGFSM_PWR_STATUS, pwr_status, 385 1, 1000); 386 break; 387 case 2: /* DSC2 */ 388 REG_UPDATE(DOMAIN18_PG_CONFIG, 389 DOMAIN18_POWER_GATE, power_gate); 390 391 REG_WAIT(DOMAIN18_PG_STATUS, 392 DOMAIN18_PGFSM_PWR_STATUS, pwr_status, 393 1, 1000); 394 break; 395 case 3: /* DSC3 */ 396 REG_UPDATE(DOMAIN19_PG_CONFIG, 397 DOMAIN19_POWER_GATE, power_gate); 398 399 REG_WAIT(DOMAIN19_PG_STATUS, 400 DOMAIN19_PGFSM_PWR_STATUS, pwr_status, 401 1, 1000); 402 break; 403 case 4: /* DSC4 */ 404 REG_UPDATE(DOMAIN20_PG_CONFIG, 405 DOMAIN20_POWER_GATE, power_gate); 406 407 REG_WAIT(DOMAIN20_PG_STATUS, 408 DOMAIN20_PGFSM_PWR_STATUS, pwr_status, 409 1, 1000); 410 break; 411 case 5: /* DSC5 */ 412 REG_UPDATE(DOMAIN21_PG_CONFIG, 413 DOMAIN21_POWER_GATE, power_gate); 414 415 REG_WAIT(DOMAIN21_PG_STATUS, 416 DOMAIN21_PGFSM_PWR_STATUS, pwr_status, 417 1, 1000); 418 break; 419 default: 420 BREAK_TO_DEBUGGER(); 421 break; 422 } 423 424 if (org_ip_request_cntl == 0) 425 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 426 } 427 428 void dcn20_dpp_pg_control( 429 struct dce_hwseq *hws, 430 unsigned int dpp_inst, 431 bool power_on) 432 { 433 uint32_t power_gate = power_on ? 0 : 1; 434 uint32_t pwr_status = power_on ? 0 : 2; 435 436 if (hws->ctx->dc->debug.disable_dpp_power_gate) 437 return; 438 if (REG(DOMAIN1_PG_CONFIG) == 0) 439 return; 440 441 switch (dpp_inst) { 442 case 0: /* DPP0 */ 443 REG_UPDATE(DOMAIN1_PG_CONFIG, 444 DOMAIN1_POWER_GATE, power_gate); 445 446 REG_WAIT(DOMAIN1_PG_STATUS, 447 DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 448 1, 1000); 449 break; 450 case 1: /* DPP1 */ 451 REG_UPDATE(DOMAIN3_PG_CONFIG, 452 DOMAIN3_POWER_GATE, power_gate); 453 454 REG_WAIT(DOMAIN3_PG_STATUS, 455 DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 456 1, 1000); 457 break; 458 case 2: /* DPP2 */ 459 REG_UPDATE(DOMAIN5_PG_CONFIG, 460 DOMAIN5_POWER_GATE, power_gate); 461 462 REG_WAIT(DOMAIN5_PG_STATUS, 463 DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 464 1, 1000); 465 break; 466 case 3: /* DPP3 */ 467 REG_UPDATE(DOMAIN7_PG_CONFIG, 468 DOMAIN7_POWER_GATE, power_gate); 469 470 REG_WAIT(DOMAIN7_PG_STATUS, 471 DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 472 1, 1000); 473 break; 474 case 4: /* DPP4 */ 475 REG_UPDATE(DOMAIN9_PG_CONFIG, 476 DOMAIN9_POWER_GATE, power_gate); 477 478 REG_WAIT(DOMAIN9_PG_STATUS, 479 DOMAIN9_PGFSM_PWR_STATUS, pwr_status, 480 1, 1000); 481 break; 482 case 5: /* DPP5 */ 483 /* 484 * Do not power gate DPP5, should be left at HW default, power on permanently. 485 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 486 * reset. 487 * REG_UPDATE(DOMAIN11_PG_CONFIG, 488 * DOMAIN11_POWER_GATE, power_gate); 489 * 490 * REG_WAIT(DOMAIN11_PG_STATUS, 491 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, 492 * 1, 1000); 493 */ 494 break; 495 default: 496 BREAK_TO_DEBUGGER(); 497 break; 498 } 499 } 500 501 502 void dcn20_hubp_pg_control( 503 struct dce_hwseq *hws, 504 unsigned int hubp_inst, 505 bool power_on) 506 { 507 uint32_t power_gate = power_on ? 0 : 1; 508 uint32_t pwr_status = power_on ? 0 : 2; 509 510 if (hws->ctx->dc->debug.disable_hubp_power_gate) 511 return; 512 if (REG(DOMAIN0_PG_CONFIG) == 0) 513 return; 514 515 switch (hubp_inst) { 516 case 0: /* DCHUBP0 */ 517 REG_UPDATE(DOMAIN0_PG_CONFIG, 518 DOMAIN0_POWER_GATE, power_gate); 519 520 REG_WAIT(DOMAIN0_PG_STATUS, 521 DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 522 1, 1000); 523 break; 524 case 1: /* DCHUBP1 */ 525 REG_UPDATE(DOMAIN2_PG_CONFIG, 526 DOMAIN2_POWER_GATE, power_gate); 527 528 REG_WAIT(DOMAIN2_PG_STATUS, 529 DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 530 1, 1000); 531 break; 532 case 2: /* DCHUBP2 */ 533 REG_UPDATE(DOMAIN4_PG_CONFIG, 534 DOMAIN4_POWER_GATE, power_gate); 535 536 REG_WAIT(DOMAIN4_PG_STATUS, 537 DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 538 1, 1000); 539 break; 540 case 3: /* DCHUBP3 */ 541 REG_UPDATE(DOMAIN6_PG_CONFIG, 542 DOMAIN6_POWER_GATE, power_gate); 543 544 REG_WAIT(DOMAIN6_PG_STATUS, 545 DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 546 1, 1000); 547 break; 548 case 4: /* DCHUBP4 */ 549 REG_UPDATE(DOMAIN8_PG_CONFIG, 550 DOMAIN8_POWER_GATE, power_gate); 551 552 REG_WAIT(DOMAIN8_PG_STATUS, 553 DOMAIN8_PGFSM_PWR_STATUS, pwr_status, 554 1, 1000); 555 break; 556 case 5: /* DCHUBP5 */ 557 /* 558 * Do not power gate DCHUB5, should be left at HW default, power on permanently. 559 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 560 * reset. 561 * REG_UPDATE(DOMAIN10_PG_CONFIG, 562 * DOMAIN10_POWER_GATE, power_gate); 563 * 564 * REG_WAIT(DOMAIN10_PG_STATUS, 565 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status, 566 * 1, 1000); 567 */ 568 break; 569 default: 570 BREAK_TO_DEBUGGER(); 571 break; 572 } 573 } 574 575 576 /* disable HW used by plane. 577 * note: cannot disable until disconnect is complete 578 */ 579 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 580 { 581 struct dce_hwseq *hws = dc->hwseq; 582 struct hubp *hubp = pipe_ctx->plane_res.hubp; 583 struct dpp *dpp = pipe_ctx->plane_res.dpp; 584 585 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); 586 587 /* In flip immediate with pipe splitting case GSL is used for 588 * synchronization so we must disable it when the plane is disabled. 589 */ 590 if (pipe_ctx->stream_res.gsl_group != 0) 591 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false); 592 593 if (hubp->funcs->hubp_update_mall_sel) 594 hubp->funcs->hubp_update_mall_sel(hubp, 0, false); 595 596 dc->hwss.set_flip_control_gsl(pipe_ctx, false); 597 598 hubp->funcs->hubp_clk_cntl(hubp, false); 599 600 dpp->funcs->dpp_dppclk_control(dpp, false, false); 601 602 hubp->power_gated = true; 603 604 hws->funcs.plane_atomic_power_down(dc, 605 pipe_ctx->plane_res.dpp, 606 pipe_ctx->plane_res.hubp); 607 608 pipe_ctx->stream = NULL; 609 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); 610 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); 611 pipe_ctx->top_pipe = NULL; 612 pipe_ctx->bottom_pipe = NULL; 613 pipe_ctx->plane_state = NULL; 614 } 615 616 617 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) 618 { 619 bool is_phantom = pipe_ctx->plane_state && pipe_ctx->plane_state->is_phantom; 620 struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL; 621 622 DC_LOGGER_INIT(dc->ctx->logger); 623 624 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) 625 return; 626 627 dcn20_plane_atomic_disable(dc, pipe_ctx); 628 629 /* Turn back off the phantom OTG after the phantom plane is fully disabled 630 */ 631 if (is_phantom) 632 if (tg && tg->funcs->disable_phantom_crtc) 633 tg->funcs->disable_phantom_crtc(tg); 634 635 DC_LOG_DC("Power down front end %d\n", 636 pipe_ctx->pipe_idx); 637 } 638 639 void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank) 640 { 641 dcn20_blank_pixel_data(dc, pipe_ctx, blank); 642 } 643 644 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 645 int opp_cnt) 646 { 647 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 648 int flow_ctrl_cnt; 649 650 if (opp_cnt >= 2) 651 hblank_halved = true; 652 653 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 654 stream->timing.h_border_left - 655 stream->timing.h_border_right; 656 657 if (hblank_halved) 658 flow_ctrl_cnt /= 2; 659 660 /* ODM combine 4:1 case */ 661 if (opp_cnt == 4) 662 flow_ctrl_cnt /= 2; 663 664 return flow_ctrl_cnt; 665 } 666 667 enum dc_status dcn20_enable_stream_timing( 668 struct pipe_ctx *pipe_ctx, 669 struct dc_state *context, 670 struct dc *dc) 671 { 672 struct dce_hwseq *hws = dc->hwseq; 673 struct dc_stream_state *stream = pipe_ctx->stream; 674 struct drr_params params = {0}; 675 unsigned int event_triggers = 0; 676 struct pipe_ctx *odm_pipe; 677 int opp_cnt = 1; 678 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 679 bool interlace = stream->timing.flags.INTERLACE; 680 int i; 681 struct mpc_dwb_flow_control flow_control; 682 struct mpc *mpc = dc->res_pool->mpc; 683 bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing)); 684 unsigned int k1_div = PIXEL_RATE_DIV_NA; 685 unsigned int k2_div = PIXEL_RATE_DIV_NA; 686 687 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { 688 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); 689 690 dc->res_pool->dccg->funcs->set_pixel_rate_div( 691 dc->res_pool->dccg, 692 pipe_ctx->stream_res.tg->inst, 693 k1_div, k2_div); 694 } 695 /* by upper caller loop, pipe0 is parent pipe and be called first. 696 * back end is set up by for pipe0. Other children pipe share back end 697 * with pipe 0. No program is needed. 698 */ 699 if (pipe_ctx->top_pipe != NULL) 700 return DC_OK; 701 702 /* TODO check if timing_changed, disable stream if timing changed */ 703 704 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 705 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 706 opp_cnt++; 707 } 708 709 if (opp_cnt > 1) 710 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 711 pipe_ctx->stream_res.tg, 712 opp_inst, opp_cnt, 713 &pipe_ctx->stream->timing); 714 715 /* HW program guide assume display already disable 716 * by unplug sequence. OTG assume stop. 717 */ 718 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); 719 720 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 721 pipe_ctx->clock_source, 722 &pipe_ctx->stream_res.pix_clk_params, 723 dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings), 724 &pipe_ctx->pll_settings)) { 725 BREAK_TO_DEBUGGER(); 726 return DC_ERROR_UNEXPECTED; 727 } 728 729 if (dc_is_hdmi_tmds_signal(stream->signal)) { 730 stream->link->phy_state.symclk_ref_cnts.otg = 1; 731 if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF) 732 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; 733 else 734 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 735 } 736 737 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal))) 738 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx); 739 740 pipe_ctx->stream_res.tg->funcs->program_timing( 741 pipe_ctx->stream_res.tg, 742 &stream->timing, 743 pipe_ctx->pipe_dlg_param.vready_offset, 744 pipe_ctx->pipe_dlg_param.vstartup_start, 745 pipe_ctx->pipe_dlg_param.vupdate_offset, 746 pipe_ctx->pipe_dlg_param.vupdate_width, 747 pipe_ctx->stream->signal, 748 true); 749 750 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 751 flow_control.flow_ctrl_mode = 0; 752 flow_control.flow_ctrl_cnt0 = 0x80; 753 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt); 754 if (mpc->funcs->set_out_rate_control) { 755 for (i = 0; i < opp_cnt; ++i) { 756 mpc->funcs->set_out_rate_control( 757 mpc, opp_inst[i], 758 true, 759 rate_control_2x_pclk, 760 &flow_control); 761 } 762 } 763 764 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 765 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 766 odm_pipe->stream_res.opp, 767 true); 768 769 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 770 pipe_ctx->stream_res.opp, 771 true); 772 773 hws->funcs.blank_pixel_data(dc, pipe_ctx, true); 774 775 /* VTG is within DCHUB command block. DCFCLK is always on */ 776 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { 777 BREAK_TO_DEBUGGER(); 778 return DC_ERROR_UNEXPECTED; 779 } 780 781 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp); 782 783 params.vertical_total_min = stream->adjust.v_total_min; 784 params.vertical_total_max = stream->adjust.v_total_max; 785 params.vertical_total_mid = stream->adjust.v_total_mid; 786 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num; 787 if (pipe_ctx->stream_res.tg->funcs->set_drr) 788 pipe_ctx->stream_res.tg->funcs->set_drr( 789 pipe_ctx->stream_res.tg, ¶ms); 790 791 // DRR should set trigger event to monitor surface update event 792 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 793 event_triggers = 0x80; 794 /* Event triggers and num frames initialized for DRR, but can be 795 * later updated for PSR use. Note DRR trigger events are generated 796 * regardless of whether num frames met. 797 */ 798 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 799 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 800 pipe_ctx->stream_res.tg, event_triggers, 2); 801 802 /* TODO program crtc source select for non-virtual signal*/ 803 /* TODO program FMT */ 804 /* TODO setup link_enc */ 805 /* TODO set stream attributes */ 806 /* TODO program audio */ 807 /* TODO enable stream if timing changed */ 808 /* TODO unblank stream if DP */ 809 810 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) { 811 if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable) 812 pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg); 813 } 814 return DC_OK; 815 } 816 817 void dcn20_program_output_csc(struct dc *dc, 818 struct pipe_ctx *pipe_ctx, 819 enum dc_color_space colorspace, 820 uint16_t *matrix, 821 int opp_id) 822 { 823 struct mpc *mpc = dc->res_pool->mpc; 824 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; 825 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 826 827 if (mpc->funcs->power_on_mpc_mem_pwr) 828 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 829 830 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 831 if (mpc->funcs->set_output_csc != NULL) 832 mpc->funcs->set_output_csc(mpc, 833 opp_id, 834 matrix, 835 ocsc_mode); 836 } else { 837 if (mpc->funcs->set_ocsc_default != NULL) 838 mpc->funcs->set_ocsc_default(mpc, 839 opp_id, 840 colorspace, 841 ocsc_mode); 842 } 843 } 844 845 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 846 const struct dc_stream_state *stream) 847 { 848 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 849 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 850 struct pwl_params *params = NULL; 851 /* 852 * program OGAM only for the top pipe 853 * if there is a pipe split then fix diagnostic is required: 854 * how to pass OGAM parameter for stream. 855 * if programming for all pipes is required then remove condition 856 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic. 857 */ 858 if (mpc->funcs->power_on_mpc_mem_pwr) 859 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 860 if (pipe_ctx->top_pipe == NULL 861 && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 862 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 863 params = &stream->out_transfer_func->pwl; 864 else if (pipe_ctx->stream->out_transfer_func->type == 865 TF_TYPE_DISTRIBUTED_POINTS && 866 cm_helper_translate_curve_to_hw_format( 867 stream->out_transfer_func, 868 &mpc->blender_params, false)) 869 params = &mpc->blender_params; 870 /* 871 * there is no ROM 872 */ 873 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 874 BREAK_TO_DEBUGGER(); 875 } 876 /* 877 * if above if is not executed then 'params' equal to 0 and set in bypass 878 */ 879 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 880 881 return true; 882 } 883 884 bool dcn20_set_blend_lut( 885 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 886 { 887 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 888 bool result = true; 889 struct pwl_params *blend_lut = NULL; 890 891 if (plane_state->blend_tf) { 892 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 893 blend_lut = &plane_state->blend_tf->pwl; 894 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 895 cm_helper_translate_curve_to_hw_format( 896 plane_state->blend_tf, 897 &dpp_base->regamma_params, false); 898 blend_lut = &dpp_base->regamma_params; 899 } 900 } 901 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); 902 903 return result; 904 } 905 906 bool dcn20_set_shaper_3dlut( 907 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 908 { 909 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 910 bool result = true; 911 struct pwl_params *shaper_lut = NULL; 912 913 if (plane_state->in_shaper_func) { 914 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 915 shaper_lut = &plane_state->in_shaper_func->pwl; 916 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 917 cm_helper_translate_curve_to_hw_format( 918 plane_state->in_shaper_func, 919 &dpp_base->shaper_params, true); 920 shaper_lut = &dpp_base->shaper_params; 921 } 922 } 923 924 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); 925 if (plane_state->lut3d_func && 926 plane_state->lut3d_func->state.bits.initialized == 1) 927 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, 928 &plane_state->lut3d_func->lut_3d); 929 else 930 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); 931 932 return result; 933 } 934 935 bool dcn20_set_input_transfer_func(struct dc *dc, 936 struct pipe_ctx *pipe_ctx, 937 const struct dc_plane_state *plane_state) 938 { 939 struct dce_hwseq *hws = dc->hwseq; 940 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 941 const struct dc_transfer_func *tf = NULL; 942 bool result = true; 943 bool use_degamma_ram = false; 944 945 if (dpp_base == NULL || plane_state == NULL) 946 return false; 947 948 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); 949 hws->funcs.set_blend_lut(pipe_ctx, plane_state); 950 951 if (plane_state->in_transfer_func) 952 tf = plane_state->in_transfer_func; 953 954 955 if (tf == NULL) { 956 dpp_base->funcs->dpp_set_degamma(dpp_base, 957 IPP_DEGAMMA_MODE_BYPASS); 958 return true; 959 } 960 961 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS) 962 use_degamma_ram = true; 963 964 if (use_degamma_ram == true) { 965 if (tf->type == TF_TYPE_HWPWL) 966 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 967 &tf->pwl); 968 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 969 cm_helper_translate_curve_to_degamma_hw_format(tf, 970 &dpp_base->degamma_params); 971 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 972 &dpp_base->degamma_params); 973 } 974 return true; 975 } 976 /* handle here the optimized cases when de-gamma ROM could be used. 977 * 978 */ 979 if (tf->type == TF_TYPE_PREDEFINED) { 980 switch (tf->tf) { 981 case TRANSFER_FUNCTION_SRGB: 982 dpp_base->funcs->dpp_set_degamma(dpp_base, 983 IPP_DEGAMMA_MODE_HW_sRGB); 984 break; 985 case TRANSFER_FUNCTION_BT709: 986 dpp_base->funcs->dpp_set_degamma(dpp_base, 987 IPP_DEGAMMA_MODE_HW_xvYCC); 988 break; 989 case TRANSFER_FUNCTION_LINEAR: 990 dpp_base->funcs->dpp_set_degamma(dpp_base, 991 IPP_DEGAMMA_MODE_BYPASS); 992 break; 993 case TRANSFER_FUNCTION_PQ: 994 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL); 995 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params); 996 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params); 997 result = true; 998 break; 999 default: 1000 result = false; 1001 break; 1002 } 1003 } else if (tf->type == TF_TYPE_BYPASS) 1004 dpp_base->funcs->dpp_set_degamma(dpp_base, 1005 IPP_DEGAMMA_MODE_BYPASS); 1006 else { 1007 /* 1008 * if we are here, we did not handle correctly. 1009 * fix is required for this use case 1010 */ 1011 BREAK_TO_DEBUGGER(); 1012 dpp_base->funcs->dpp_set_degamma(dpp_base, 1013 IPP_DEGAMMA_MODE_BYPASS); 1014 } 1015 1016 return result; 1017 } 1018 1019 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1020 { 1021 struct pipe_ctx *odm_pipe; 1022 int opp_cnt = 1; 1023 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 1024 1025 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1026 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 1027 opp_cnt++; 1028 } 1029 1030 if (opp_cnt > 1) 1031 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 1032 pipe_ctx->stream_res.tg, 1033 opp_inst, opp_cnt, 1034 &pipe_ctx->stream->timing); 1035 else 1036 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1037 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1038 } 1039 1040 void dcn20_blank_pixel_data( 1041 struct dc *dc, 1042 struct pipe_ctx *pipe_ctx, 1043 bool blank) 1044 { 1045 struct tg_color black_color = {0}; 1046 struct stream_resource *stream_res = &pipe_ctx->stream_res; 1047 struct dc_stream_state *stream = pipe_ctx->stream; 1048 enum dc_color_space color_space = stream->output_color_space; 1049 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; 1050 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; 1051 struct pipe_ctx *odm_pipe; 1052 int odm_cnt = 1; 1053 1054 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 1055 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; 1056 1057 if (stream->link->test_pattern_enabled) 1058 return; 1059 1060 /* get opp dpg blank color */ 1061 color_space_to_black_color(dc, color_space, &black_color); 1062 1063 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1064 odm_cnt++; 1065 1066 width = width / odm_cnt; 1067 1068 if (blank) { 1069 dc->hwss.set_abm_immediate_disable(pipe_ctx); 1070 1071 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { 1072 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; 1073 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; 1074 } 1075 } else { 1076 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; 1077 } 1078 1079 dc->hwss.set_disp_pattern_generator(dc, 1080 pipe_ctx, 1081 test_pattern, 1082 test_pattern_color_space, 1083 stream->timing.display_color_depth, 1084 &black_color, 1085 width, 1086 height, 1087 0); 1088 1089 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1090 dc->hwss.set_disp_pattern_generator(dc, 1091 odm_pipe, 1092 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ? 1093 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern, 1094 test_pattern_color_space, 1095 stream->timing.display_color_depth, 1096 &black_color, 1097 width, 1098 height, 1099 0); 1100 } 1101 1102 if (!blank && dc->debug.enable_single_display_2to1_odm_policy) { 1103 /* when exiting dynamic ODM need to reinit DPG state for unused pipes */ 1104 struct pipe_ctx *old_odm_pipe = dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx].next_odm_pipe; 1105 1106 odm_pipe = pipe_ctx->next_odm_pipe; 1107 1108 while (old_odm_pipe) { 1109 if (!odm_pipe || old_odm_pipe->pipe_idx != odm_pipe->pipe_idx) 1110 dc->hwss.set_disp_pattern_generator(dc, 1111 old_odm_pipe, 1112 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 1113 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 1114 COLOR_DEPTH_888, 1115 NULL, 1116 0, 1117 0, 1118 0); 1119 old_odm_pipe = old_odm_pipe->next_odm_pipe; 1120 if (odm_pipe) 1121 odm_pipe = odm_pipe->next_odm_pipe; 1122 } 1123 } 1124 1125 if (!blank) 1126 if (stream_res->abm) { 1127 dc->hwss.set_pipe(pipe_ctx); 1128 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level); 1129 } 1130 } 1131 1132 1133 static void dcn20_power_on_plane_resources( 1134 struct dce_hwseq *hws, 1135 struct pipe_ctx *pipe_ctx) 1136 { 1137 DC_LOGGER_INIT(hws->ctx->logger); 1138 1139 if (hws->funcs.dpp_root_clock_control) 1140 hws->funcs.dpp_root_clock_control(hws, pipe_ctx->plane_res.dpp->inst, true); 1141 1142 if (REG(DC_IP_REQUEST_CNTL)) { 1143 REG_SET(DC_IP_REQUEST_CNTL, 0, 1144 IP_REQUEST_EN, 1); 1145 1146 if (hws->funcs.dpp_pg_control) 1147 hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); 1148 1149 if (hws->funcs.hubp_pg_control) 1150 hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true); 1151 1152 REG_SET(DC_IP_REQUEST_CNTL, 0, 1153 IP_REQUEST_EN, 0); 1154 DC_LOG_DEBUG( 1155 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst); 1156 } 1157 } 1158 1159 static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx, 1160 struct dc_state *context) 1161 { 1162 //if (dc->debug.sanity_checks) { 1163 // dcn10_verify_allow_pstate_change_high(dc); 1164 //} 1165 dcn20_power_on_plane_resources(dc->hwseq, pipe_ctx); 1166 1167 /* enable DCFCLK current DCHUB */ 1168 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); 1169 1170 /* initialize HUBP on power up */ 1171 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); 1172 1173 /* make sure OPP_PIPE_CLOCK_EN = 1 */ 1174 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 1175 pipe_ctx->stream_res.opp, 1176 true); 1177 1178 /* TODO: enable/disable in dm as per update type. 1179 if (plane_state) { 1180 DC_LOG_DC(dc->ctx->logger, 1181 "Pipe:%d 0x%x: addr hi:0x%x, " 1182 "addr low:0x%x, " 1183 "src: %d, %d, %d," 1184 " %d; dst: %d, %d, %d, %d;\n", 1185 pipe_ctx->pipe_idx, 1186 plane_state, 1187 plane_state->address.grph.addr.high_part, 1188 plane_state->address.grph.addr.low_part, 1189 plane_state->src_rect.x, 1190 plane_state->src_rect.y, 1191 plane_state->src_rect.width, 1192 plane_state->src_rect.height, 1193 plane_state->dst_rect.x, 1194 plane_state->dst_rect.y, 1195 plane_state->dst_rect.width, 1196 plane_state->dst_rect.height); 1197 1198 DC_LOG_DC(dc->ctx->logger, 1199 "Pipe %d: width, height, x, y format:%d\n" 1200 "viewport:%d, %d, %d, %d\n" 1201 "recout: %d, %d, %d, %d\n", 1202 pipe_ctx->pipe_idx, 1203 plane_state->format, 1204 pipe_ctx->plane_res.scl_data.viewport.width, 1205 pipe_ctx->plane_res.scl_data.viewport.height, 1206 pipe_ctx->plane_res.scl_data.viewport.x, 1207 pipe_ctx->plane_res.scl_data.viewport.y, 1208 pipe_ctx->plane_res.scl_data.recout.width, 1209 pipe_ctx->plane_res.scl_data.recout.height, 1210 pipe_ctx->plane_res.scl_data.recout.x, 1211 pipe_ctx->plane_res.scl_data.recout.y); 1212 print_rq_dlg_ttu(dc, pipe_ctx); 1213 } 1214 */ 1215 if (dc->vm_pa_config.valid) { 1216 struct vm_system_aperture_param apt; 1217 1218 apt.sys_default.quad_part = 0; 1219 1220 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr; 1221 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr; 1222 1223 // Program system aperture settings 1224 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); 1225 } 1226 1227 if (!pipe_ctx->top_pipe 1228 && pipe_ctx->plane_state 1229 && pipe_ctx->plane_state->flip_int_enabled 1230 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) 1231 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); 1232 1233 // if (dc->debug.sanity_checks) { 1234 // dcn10_verify_allow_pstate_change_high(dc); 1235 // } 1236 } 1237 1238 void dcn20_pipe_control_lock( 1239 struct dc *dc, 1240 struct pipe_ctx *pipe, 1241 bool lock) 1242 { 1243 struct pipe_ctx *temp_pipe; 1244 bool flip_immediate = false; 1245 1246 /* use TG master update lock to lock everything on the TG 1247 * therefore only top pipe need to lock 1248 */ 1249 if (!pipe || pipe->top_pipe) 1250 return; 1251 1252 if (pipe->plane_state != NULL) 1253 flip_immediate = pipe->plane_state->flip_immediate; 1254 1255 if (pipe->stream_res.gsl_group > 0) { 1256 temp_pipe = pipe->bottom_pipe; 1257 while (!flip_immediate && temp_pipe) { 1258 if (temp_pipe->plane_state != NULL) 1259 flip_immediate = temp_pipe->plane_state->flip_immediate; 1260 temp_pipe = temp_pipe->bottom_pipe; 1261 } 1262 } 1263 1264 if (flip_immediate && lock) { 1265 const int TIMEOUT_FOR_FLIP_PENDING = 100000; 1266 int i; 1267 1268 temp_pipe = pipe; 1269 while (temp_pipe) { 1270 if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) { 1271 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) { 1272 if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp)) 1273 break; 1274 udelay(1); 1275 } 1276 1277 /* no reason it should take this long for immediate flips */ 1278 ASSERT(i != TIMEOUT_FOR_FLIP_PENDING); 1279 } 1280 temp_pipe = temp_pipe->bottom_pipe; 1281 } 1282 } 1283 1284 /* In flip immediate and pipe splitting case, we need to use GSL 1285 * for synchronization. Only do setup on locking and on flip type change. 1286 */ 1287 if (lock && (pipe->bottom_pipe != NULL || !flip_immediate)) 1288 if ((flip_immediate && pipe->stream_res.gsl_group == 0) || 1289 (!flip_immediate && pipe->stream_res.gsl_group > 0)) 1290 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate); 1291 1292 if (pipe->plane_state != NULL) 1293 flip_immediate = pipe->plane_state->flip_immediate; 1294 1295 temp_pipe = pipe->bottom_pipe; 1296 while (flip_immediate && temp_pipe) { 1297 if (temp_pipe->plane_state != NULL) 1298 flip_immediate = temp_pipe->plane_state->flip_immediate; 1299 temp_pipe = temp_pipe->bottom_pipe; 1300 } 1301 1302 if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state && 1303 !flip_immediate) 1304 dcn20_setup_gsl_group_as_lock(dc, pipe, false); 1305 1306 if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) { 1307 union dmub_hw_lock_flags hw_locks = { 0 }; 1308 struct dmub_hw_lock_inst_flags inst_flags = { 0 }; 1309 1310 hw_locks.bits.lock_pipe = 1; 1311 inst_flags.otg_inst = pipe->stream_res.tg->inst; 1312 1313 if (pipe->plane_state != NULL) 1314 hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips; 1315 1316 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, 1317 lock, 1318 &hw_locks, 1319 &inst_flags); 1320 } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) { 1321 if (lock) 1322 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); 1323 else 1324 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); 1325 } else { 1326 if (lock) 1327 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1328 else 1329 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1330 } 1331 } 1332 1333 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe) 1334 { 1335 new_pipe->update_flags.raw = 0; 1336 1337 /* If non-phantom pipe is being transitioned to a phantom pipe, 1338 * set disable and return immediately. This is because the pipe 1339 * that was previously in use must be fully disabled before we 1340 * can "enable" it as a phantom pipe (since the OTG will certainly 1341 * be different). The post_unlock sequence will set the correct 1342 * update flags to enable the phantom pipe. 1343 */ 1344 if (old_pipe->plane_state && !old_pipe->plane_state->is_phantom && 1345 new_pipe->plane_state && new_pipe->plane_state->is_phantom) { 1346 new_pipe->update_flags.bits.disable = 1; 1347 return; 1348 } 1349 1350 /* Exit on unchanged, unused pipe */ 1351 if (!old_pipe->plane_state && !new_pipe->plane_state) 1352 return; 1353 /* Detect pipe enable/disable */ 1354 if (!old_pipe->plane_state && new_pipe->plane_state) { 1355 new_pipe->update_flags.bits.enable = 1; 1356 new_pipe->update_flags.bits.mpcc = 1; 1357 new_pipe->update_flags.bits.dppclk = 1; 1358 new_pipe->update_flags.bits.hubp_interdependent = 1; 1359 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1360 new_pipe->update_flags.bits.gamut_remap = 1; 1361 new_pipe->update_flags.bits.scaler = 1; 1362 new_pipe->update_flags.bits.viewport = 1; 1363 new_pipe->update_flags.bits.det_size = 1; 1364 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1365 new_pipe->update_flags.bits.odm = 1; 1366 new_pipe->update_flags.bits.global_sync = 1; 1367 } 1368 return; 1369 } 1370 1371 /* For SubVP we need to unconditionally enable because any phantom pipes are 1372 * always removed then newly added for every full updates whenever SubVP is in use. 1373 * The remove-add sequence of the phantom pipe always results in the pipe 1374 * being blanked in enable_stream_timing (DPG). 1375 */ 1376 if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) 1377 new_pipe->update_flags.bits.enable = 1; 1378 1379 /* Phantom pipes are effectively disabled, if the pipe was previously phantom 1380 * we have to enable 1381 */ 1382 if (old_pipe->plane_state && old_pipe->plane_state->is_phantom && 1383 new_pipe->plane_state && !new_pipe->plane_state->is_phantom) 1384 new_pipe->update_flags.bits.enable = 1; 1385 1386 if (old_pipe->plane_state && !new_pipe->plane_state) { 1387 new_pipe->update_flags.bits.disable = 1; 1388 return; 1389 } 1390 1391 /* Detect plane change */ 1392 if (old_pipe->plane_state != new_pipe->plane_state) { 1393 new_pipe->update_flags.bits.plane_changed = true; 1394 } 1395 1396 /* Detect top pipe only changes */ 1397 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1398 /* Detect odm changes */ 1399 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe 1400 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx) 1401 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe) 1402 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe) 1403 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1404 new_pipe->update_flags.bits.odm = 1; 1405 1406 /* Detect global sync changes */ 1407 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset 1408 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start 1409 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset 1410 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) 1411 new_pipe->update_flags.bits.global_sync = 1; 1412 } 1413 1414 if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb) 1415 new_pipe->update_flags.bits.det_size = 1; 1416 1417 /* 1418 * Detect opp / tg change, only set on change, not on enable 1419 * Assume mpcc inst = pipe index, if not this code needs to be updated 1420 * since mpcc is what is affected by these. In fact all of our sequence 1421 * makes this assumption at the moment with how hubp reset is matched to 1422 * same index mpcc reset. 1423 */ 1424 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1425 new_pipe->update_flags.bits.opp_changed = 1; 1426 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg) 1427 new_pipe->update_flags.bits.tg_changed = 1; 1428 1429 /* 1430 * Detect mpcc blending changes, only dpp inst and opp matter here, 1431 * mpccs getting removed/inserted update connected ones during their own 1432 * programming 1433 */ 1434 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp 1435 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1436 new_pipe->update_flags.bits.mpcc = 1; 1437 1438 /* Detect dppclk change */ 1439 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) 1440 new_pipe->update_flags.bits.dppclk = 1; 1441 1442 /* Check for scl update */ 1443 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data))) 1444 new_pipe->update_flags.bits.scaler = 1; 1445 /* Check for vp update */ 1446 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect)) 1447 || memcmp(&old_pipe->plane_res.scl_data.viewport_c, 1448 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect))) 1449 new_pipe->update_flags.bits.viewport = 1; 1450 1451 /* Detect dlg/ttu/rq updates */ 1452 { 1453 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs; 1454 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs; 1455 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs; 1456 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs; 1457 1458 /* Detect pipe interdependent updates */ 1459 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch || 1460 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch || 1461 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c || 1462 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank || 1463 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank || 1464 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip || 1465 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip || 1466 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l || 1467 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c || 1468 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l || 1469 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l || 1470 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c || 1471 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l || 1472 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c || 1473 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 || 1474 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 || 1475 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank || 1476 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) { 1477 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch; 1478 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch; 1479 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c; 1480 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank; 1481 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank; 1482 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip; 1483 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip; 1484 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l; 1485 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c; 1486 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l; 1487 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l; 1488 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c; 1489 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l; 1490 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c; 1491 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0; 1492 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1; 1493 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank; 1494 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip; 1495 new_pipe->update_flags.bits.hubp_interdependent = 1; 1496 } 1497 /* Detect any other updates to ttu/rq/dlg */ 1498 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) || 1499 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) || 1500 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs))) 1501 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1502 } 1503 } 1504 1505 static void dcn20_update_dchubp_dpp( 1506 struct dc *dc, 1507 struct pipe_ctx *pipe_ctx, 1508 struct dc_state *context) 1509 { 1510 struct dce_hwseq *hws = dc->hwseq; 1511 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1512 struct dpp *dpp = pipe_ctx->plane_res.dpp; 1513 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1514 struct dccg *dccg = dc->res_pool->dccg; 1515 bool viewport_changed = false; 1516 1517 if (pipe_ctx->update_flags.bits.dppclk) 1518 dpp->funcs->dpp_dppclk_control(dpp, false, true); 1519 1520 if (pipe_ctx->update_flags.bits.enable) 1521 dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz); 1522 1523 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG 1524 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. 1525 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG 1526 */ 1527 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) { 1528 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst); 1529 1530 hubp->funcs->hubp_setup( 1531 hubp, 1532 &pipe_ctx->dlg_regs, 1533 &pipe_ctx->ttu_regs, 1534 &pipe_ctx->rq_regs, 1535 &pipe_ctx->pipe_dlg_param); 1536 1537 if (hubp->funcs->set_unbounded_requesting) 1538 hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req); 1539 } 1540 if (pipe_ctx->update_flags.bits.hubp_interdependent) 1541 hubp->funcs->hubp_setup_interdependent( 1542 hubp, 1543 &pipe_ctx->dlg_regs, 1544 &pipe_ctx->ttu_regs); 1545 1546 if (pipe_ctx->update_flags.bits.enable || 1547 pipe_ctx->update_flags.bits.plane_changed || 1548 plane_state->update_flags.bits.bpp_change || 1549 plane_state->update_flags.bits.input_csc_change || 1550 plane_state->update_flags.bits.color_space_change || 1551 plane_state->update_flags.bits.coeff_reduction_change) { 1552 struct dc_bias_and_scale bns_params = {0}; 1553 1554 // program the input csc 1555 dpp->funcs->dpp_setup(dpp, 1556 plane_state->format, 1557 EXPANSION_MODE_ZERO, 1558 plane_state->input_csc_color_matrix, 1559 plane_state->color_space, 1560 NULL); 1561 1562 if (dpp->funcs->dpp_program_bias_and_scale) { 1563 //TODO :for CNVC set scale and bias registers if necessary 1564 build_prescale_params(&bns_params, plane_state); 1565 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); 1566 } 1567 } 1568 1569 if (pipe_ctx->update_flags.bits.mpcc 1570 || pipe_ctx->update_flags.bits.plane_changed 1571 || plane_state->update_flags.bits.global_alpha_change 1572 || plane_state->update_flags.bits.per_pixel_alpha_change) { 1573 // MPCC inst is equal to pipe index in practice 1574 int mpcc_inst = hubp->inst; 1575 int opp_inst; 1576 int opp_count = dc->res_pool->pipe_count; 1577 1578 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) { 1579 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) { 1580 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); 1581 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; 1582 break; 1583 } 1584 } 1585 hws->funcs.update_mpcc(dc, pipe_ctx); 1586 } 1587 1588 if (pipe_ctx->update_flags.bits.scaler || 1589 plane_state->update_flags.bits.scaling_change || 1590 plane_state->update_flags.bits.position_change || 1591 plane_state->update_flags.bits.per_pixel_alpha_change || 1592 pipe_ctx->stream->update_flags.bits.scaling) { 1593 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; 1594 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP); 1595 /* scaler configuration */ 1596 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( 1597 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); 1598 } 1599 1600 if (pipe_ctx->update_flags.bits.viewport || 1601 (context == dc->current_state && plane_state->update_flags.bits.position_change) || 1602 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) || 1603 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) { 1604 1605 hubp->funcs->mem_program_viewport( 1606 hubp, 1607 &pipe_ctx->plane_res.scl_data.viewport, 1608 &pipe_ctx->plane_res.scl_data.viewport_c); 1609 viewport_changed = true; 1610 } 1611 1612 /* Any updates are handled in dc interface, just need to apply existing for plane enable */ 1613 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || 1614 pipe_ctx->update_flags.bits.scaler || viewport_changed == true) && 1615 pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { 1616 dc->hwss.set_cursor_position(pipe_ctx); 1617 dc->hwss.set_cursor_attribute(pipe_ctx); 1618 1619 if (dc->hwss.set_cursor_sdr_white_level) 1620 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 1621 } 1622 1623 /* Any updates are handled in dc interface, just need 1624 * to apply existing for plane enable / opp change */ 1625 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed 1626 || pipe_ctx->update_flags.bits.plane_changed 1627 || pipe_ctx->stream->update_flags.bits.gamut_remap 1628 || pipe_ctx->stream->update_flags.bits.out_csc) { 1629 /* dpp/cm gamut remap*/ 1630 dc->hwss.program_gamut_remap(pipe_ctx); 1631 1632 /*call the dcn2 method which uses mpc csc*/ 1633 dc->hwss.program_output_csc(dc, 1634 pipe_ctx, 1635 pipe_ctx->stream->output_color_space, 1636 pipe_ctx->stream->csc_color_matrix.matrix, 1637 hubp->opp_id); 1638 } 1639 1640 if (pipe_ctx->update_flags.bits.enable || 1641 pipe_ctx->update_flags.bits.plane_changed || 1642 pipe_ctx->update_flags.bits.opp_changed || 1643 plane_state->update_flags.bits.pixel_format_change || 1644 plane_state->update_flags.bits.horizontal_mirror_change || 1645 plane_state->update_flags.bits.rotation_change || 1646 plane_state->update_flags.bits.swizzle_change || 1647 plane_state->update_flags.bits.dcc_change || 1648 plane_state->update_flags.bits.bpp_change || 1649 plane_state->update_flags.bits.scaling_change || 1650 plane_state->update_flags.bits.plane_size_change) { 1651 struct plane_size size = plane_state->plane_size; 1652 1653 size.surface_size = pipe_ctx->plane_res.scl_data.viewport; 1654 hubp->funcs->hubp_program_surface_config( 1655 hubp, 1656 plane_state->format, 1657 &plane_state->tiling_info, 1658 &size, 1659 plane_state->rotation, 1660 &plane_state->dcc, 1661 plane_state->horizontal_mirror, 1662 0); 1663 hubp->power_gated = false; 1664 } 1665 1666 if (pipe_ctx->update_flags.bits.enable || 1667 pipe_ctx->update_flags.bits.plane_changed || 1668 plane_state->update_flags.bits.addr_update) 1669 hws->funcs.update_plane_addr(dc, pipe_ctx); 1670 1671 if (pipe_ctx->update_flags.bits.enable) 1672 hubp->funcs->set_blank(hubp, false); 1673 /* If the stream paired with this plane is phantom, the plane is also phantom */ 1674 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM 1675 && hubp->funcs->phantom_hubp_post_enable) 1676 hubp->funcs->phantom_hubp_post_enable(hubp); 1677 } 1678 1679 static int calculate_vready_offset_for_group(struct pipe_ctx *pipe) 1680 { 1681 struct pipe_ctx *other_pipe; 1682 int vready_offset = pipe->pipe_dlg_param.vready_offset; 1683 1684 /* Always use the largest vready_offset of all connected pipes */ 1685 for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) { 1686 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1687 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1688 } 1689 for (other_pipe = pipe->top_pipe; other_pipe != NULL; other_pipe = other_pipe->top_pipe) { 1690 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1691 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1692 } 1693 for (other_pipe = pipe->next_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->next_odm_pipe) { 1694 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1695 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1696 } 1697 for (other_pipe = pipe->prev_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->prev_odm_pipe) { 1698 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1699 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1700 } 1701 1702 return vready_offset; 1703 } 1704 1705 static void dcn20_program_pipe( 1706 struct dc *dc, 1707 struct pipe_ctx *pipe_ctx, 1708 struct dc_state *context) 1709 { 1710 struct dce_hwseq *hws = dc->hwseq; 1711 /* Only need to unblank on top pipe */ 1712 1713 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level) 1714 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) 1715 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible); 1716 1717 /* Only update TG on top pipe */ 1718 if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe 1719 && !pipe_ctx->prev_odm_pipe) { 1720 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1721 pipe_ctx->stream_res.tg, 1722 calculate_vready_offset_for_group(pipe_ctx), 1723 pipe_ctx->pipe_dlg_param.vstartup_start, 1724 pipe_ctx->pipe_dlg_param.vupdate_offset, 1725 pipe_ctx->pipe_dlg_param.vupdate_width); 1726 1727 if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) 1728 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); 1729 1730 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1731 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true); 1732 1733 if (hws->funcs.setup_vupdate_interrupt) 1734 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1735 } 1736 1737 if (pipe_ctx->update_flags.bits.odm) 1738 hws->funcs.update_odm(dc, context, pipe_ctx); 1739 1740 if (pipe_ctx->update_flags.bits.enable) { 1741 dcn20_enable_plane(dc, pipe_ctx, context); 1742 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes) 1743 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub); 1744 } 1745 1746 if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size) 1747 dc->res_pool->hubbub->funcs->program_det_size( 1748 dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb); 1749 1750 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) 1751 dcn20_update_dchubp_dpp(dc, pipe_ctx, context); 1752 1753 if (pipe_ctx->update_flags.bits.enable 1754 || pipe_ctx->plane_state->update_flags.bits.hdr_mult) 1755 hws->funcs.set_hdr_multiplier(pipe_ctx); 1756 1757 if (pipe_ctx->update_flags.bits.enable || 1758 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 1759 pipe_ctx->plane_state->update_flags.bits.gamma_change) 1760 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 1761 1762 /* dcn10_translate_regamma_to_hw_format takes 750us to finish 1763 * only do gamma programming for powering on, internal memcmp to avoid 1764 * updating on slave planes 1765 */ 1766 if (pipe_ctx->update_flags.bits.enable || 1767 pipe_ctx->update_flags.bits.plane_changed || 1768 pipe_ctx->stream->update_flags.bits.out_tf || 1769 pipe_ctx->plane_state->update_flags.bits.output_tf_change) 1770 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 1771 1772 /* If the pipe has been enabled or has a different opp, we 1773 * should reprogram the fmt. This deals with cases where 1774 * interation between mpc and odm combine on different streams 1775 * causes a different pipe to be chosen to odm combine with. 1776 */ 1777 if (pipe_ctx->update_flags.bits.enable 1778 || pipe_ctx->update_flags.bits.opp_changed) { 1779 1780 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1781 pipe_ctx->stream_res.opp, 1782 COLOR_SPACE_YCBCR601, 1783 pipe_ctx->stream->timing.display_color_depth, 1784 pipe_ctx->stream->signal); 1785 1786 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1787 pipe_ctx->stream_res.opp, 1788 &pipe_ctx->stream->bit_depth_params, 1789 &pipe_ctx->stream->clamping); 1790 } 1791 1792 /* Set ABM pipe after other pipe configurations done */ 1793 if (pipe_ctx->plane_state->visible) { 1794 if (pipe_ctx->stream_res.abm) { 1795 dc->hwss.set_pipe(pipe_ctx); 1796 pipe_ctx->stream_res.abm->funcs->set_abm_level(pipe_ctx->stream_res.abm, 1797 pipe_ctx->stream->abm_level); 1798 } 1799 } 1800 } 1801 1802 void dcn20_program_front_end_for_ctx( 1803 struct dc *dc, 1804 struct dc_state *context) 1805 { 1806 int i; 1807 struct dce_hwseq *hws = dc->hwseq; 1808 DC_LOGGER_INIT(dc->ctx->logger); 1809 1810 /* Carry over GSL groups in case the context is changing. */ 1811 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1812 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1813 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 1814 1815 if (pipe_ctx->stream == old_pipe_ctx->stream) 1816 pipe_ctx->stream_res.gsl_group = old_pipe_ctx->stream_res.gsl_group; 1817 } 1818 1819 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) { 1820 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1821 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1822 1823 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) { 1824 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips); 1825 /*turn off triple buffer for full update*/ 1826 dc->hwss.program_triplebuffer( 1827 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); 1828 } 1829 } 1830 } 1831 1832 /* Set pipe update flags and lock pipes */ 1833 for (i = 0; i < dc->res_pool->pipe_count; i++) 1834 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i], 1835 &context->res_ctx.pipe_ctx[i]); 1836 1837 /* When disabling phantom pipes, turn on phantom OTG first (so we can get double 1838 * buffer updates properly) 1839 */ 1840 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1841 struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream; 1842 1843 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream && 1844 dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { 1845 struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg; 1846 1847 if (tg->funcs->enable_crtc) 1848 tg->funcs->enable_crtc(tg); 1849 } 1850 } 1851 /* OTG blank before disabling all front ends */ 1852 for (i = 0; i < dc->res_pool->pipe_count; i++) 1853 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1854 && !context->res_ctx.pipe_ctx[i].top_pipe 1855 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe 1856 && context->res_ctx.pipe_ctx[i].stream) 1857 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); 1858 1859 1860 /* Disconnect mpcc */ 1861 for (i = 0; i < dc->res_pool->pipe_count; i++) 1862 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1863 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) { 1864 struct hubbub *hubbub = dc->res_pool->hubbub; 1865 1866 /* Phantom pipe DET should be 0, but if a pipe in use is being transitioned to phantom 1867 * then we want to do the programming here (effectively it's being disabled). If we do 1868 * the programming later the DET won't be updated until the OTG for the phantom pipe is 1869 * turned on (i.e. in an MCLK switch) which can come in too late and cause issues with 1870 * DET allocation. 1871 */ 1872 if (hubbub->funcs->program_det_size && (context->res_ctx.pipe_ctx[i].update_flags.bits.disable || 1873 (context->res_ctx.pipe_ctx[i].plane_state && context->res_ctx.pipe_ctx[i].plane_state->is_phantom))) 1874 hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0); 1875 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1876 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); 1877 } 1878 1879 /* 1880 * Program all updated pipes, order matters for mpcc setup. Start with 1881 * top pipe and program all pipes that follow in order 1882 */ 1883 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1884 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1885 1886 if (pipe->plane_state && !pipe->top_pipe) { 1887 while (pipe) { 1888 if (hws->funcs.program_pipe) 1889 hws->funcs.program_pipe(dc, pipe, context); 1890 else { 1891 /* Don't program phantom pipes in the regular front end programming sequence. 1892 * There is an MPO transition case where a pipe being used by a video plane is 1893 * transitioned directly to be a phantom pipe when closing the MPO video. However 1894 * the phantom pipe will program a new HUBP_VTG_SEL (update takes place right away), 1895 * but the MPO still exists until the double buffered update of the main pipe so we 1896 * will get a frame of underflow if the phantom pipe is programmed here. 1897 */ 1898 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) 1899 dcn20_program_pipe(dc, pipe, context); 1900 } 1901 1902 pipe = pipe->bottom_pipe; 1903 } 1904 } 1905 /* Program secondary blending tree and writeback pipes */ 1906 pipe = &context->res_ctx.pipe_ctx[i]; 1907 if (!pipe->top_pipe && !pipe->prev_odm_pipe 1908 && pipe->stream && pipe->stream->num_wb_info > 0 1909 && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw) 1910 || pipe->stream->update_flags.raw) 1911 && hws->funcs.program_all_writeback_pipes_in_tree) 1912 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context); 1913 1914 /* Avoid underflow by check of pipe line read when adding 2nd plane. */ 1915 if (hws->wa.wait_hubpret_read_start_during_mpo_transition && 1916 !pipe->top_pipe && 1917 pipe->stream && 1918 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start && 1919 dc->current_state->stream_status[0].plane_count == 1 && 1920 context->stream_status[0].plane_count > 1) { 1921 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp); 1922 } 1923 1924 /* when dynamic ODM is active, pipes must be reconfigured when all planes are 1925 * disabled, as some transitions will leave software and hardware state 1926 * mismatched. 1927 */ 1928 if (dc->debug.enable_single_display_2to1_odm_policy && 1929 pipe->stream && 1930 pipe->update_flags.bits.disable && 1931 !pipe->prev_odm_pipe && 1932 hws->funcs.update_odm) 1933 hws->funcs.update_odm(dc, context, pipe); 1934 } 1935 } 1936 1937 void dcn20_post_unlock_program_front_end( 1938 struct dc *dc, 1939 struct dc_state *context) 1940 { 1941 int i; 1942 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100; 1943 struct dce_hwseq *hwseq = dc->hwseq; 1944 1945 DC_LOGGER_INIT(dc->ctx->logger); 1946 1947 for (i = 0; i < dc->res_pool->pipe_count; i++) 1948 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1949 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1950 1951 /* 1952 * If we are enabling a pipe, we need to wait for pending clear as this is a critical 1953 * part of the enable operation otherwise, DM may request an immediate flip which 1954 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which 1955 * is unsupported on DCN. 1956 */ 1957 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1958 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1959 // Don't check flip pending on phantom pipes 1960 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable && 1961 pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1962 struct hubp *hubp = pipe->plane_res.hubp; 1963 int j = 0; 1964 1965 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000 1966 && hubp->funcs->hubp_is_flip_pending(hubp); j++) 1967 udelay(1); 1968 } 1969 } 1970 1971 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1972 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1973 1974 if (pipe->plane_state && !pipe->top_pipe) { 1975 /* Program phantom pipe here to prevent a frame of underflow in the MPO transition 1976 * case (if a pipe being used for a video plane transitions to a phantom pipe, it 1977 * can underflow due to HUBP_VTG_SEL programming if done in the regular front end 1978 * programming sequence). 1979 */ 1980 while (pipe) { 1981 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1982 /* When turning on the phantom pipe we want to run through the 1983 * entire enable sequence, so apply all the "enable" flags. 1984 */ 1985 if (dc->hwss.apply_update_flags_for_phantom) 1986 dc->hwss.apply_update_flags_for_phantom(pipe); 1987 if (dc->hwss.update_phantom_vp_position) 1988 dc->hwss.update_phantom_vp_position(dc, context, pipe); 1989 dcn20_program_pipe(dc, pipe, context); 1990 } 1991 pipe = pipe->bottom_pipe; 1992 } 1993 } 1994 } 1995 1996 /* P-State support transitions: 1997 * Natural -> FPO: P-State disabled in prepare, force disallow anytime is safe 1998 * FPO -> Natural: Unforce anytime after FW disable is safe (P-State will assert naturally) 1999 * Unsupported -> FPO: P-State enabled in optimize, force disallow anytime is safe 2000 * FPO -> Unsupported: P-State disabled in prepare, unforce disallow anytime is safe 2001 * FPO <-> SubVP: Force disallow is maintained on the FPO / SubVP pipes 2002 */ 2003 if (hwseq && hwseq->funcs.update_force_pstate) 2004 dc->hwseq->funcs.update_force_pstate(dc, context); 2005 2006 /* Only program the MALL registers after all the main and phantom pipes 2007 * are done programming. 2008 */ 2009 if (hwseq->funcs.program_mall_pipe_config) 2010 hwseq->funcs.program_mall_pipe_config(dc, context); 2011 2012 /* WA to apply WM setting*/ 2013 if (hwseq->wa.DEGVIDCN21) 2014 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub); 2015 2016 2017 /* WA for stutter underflow during MPO transitions when adding 2nd plane */ 2018 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) { 2019 2020 if (dc->current_state->stream_status[0].plane_count == 1 && 2021 context->stream_status[0].plane_count > 1) { 2022 2023 struct timing_generator *tg = dc->res_pool->timing_generators[0]; 2024 2025 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false); 2026 2027 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true; 2028 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg); 2029 } 2030 } 2031 } 2032 2033 void dcn20_prepare_bandwidth( 2034 struct dc *dc, 2035 struct dc_state *context) 2036 { 2037 struct hubbub *hubbub = dc->res_pool->hubbub; 2038 unsigned int compbuf_size_kb = 0; 2039 unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns; 2040 unsigned int i; 2041 2042 dc->clk_mgr->funcs->update_clocks( 2043 dc->clk_mgr, 2044 context, 2045 false); 2046 2047 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2048 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2049 2050 // At optimize don't restore the original watermark value 2051 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) { 2052 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; 2053 break; 2054 } 2055 } 2056 2057 /* program dchubbub watermarks: 2058 * For assigning wm_optimized_required, use |= operator since we don't want 2059 * to clear the value if the optimize has not happened yet 2060 */ 2061 dc->wm_optimized_required |= hubbub->funcs->program_watermarks(hubbub, 2062 &context->bw_ctx.bw.dcn.watermarks, 2063 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 2064 false); 2065 2066 // Restore the real watermark so we can commit the value to DMCUB 2067 // DMCUB uses the "original" watermark value in SubVP MCLK switch 2068 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a; 2069 2070 /* decrease compbuf size */ 2071 if (hubbub->funcs->program_compbuf_size) { 2072 if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes) { 2073 compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes; 2074 dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.dml.ip.min_comp_buffer_size_kbytes); 2075 } else { 2076 compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb; 2077 dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.bw.dcn.compbuf_size_kb); 2078 } 2079 2080 hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false); 2081 } 2082 } 2083 2084 void dcn20_optimize_bandwidth( 2085 struct dc *dc, 2086 struct dc_state *context) 2087 { 2088 struct hubbub *hubbub = dc->res_pool->hubbub; 2089 int i; 2090 2091 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2092 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2093 2094 // At optimize don't need to restore the original watermark value 2095 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) { 2096 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; 2097 break; 2098 } 2099 } 2100 2101 /* program dchubbub watermarks */ 2102 hubbub->funcs->program_watermarks(hubbub, 2103 &context->bw_ctx.bw.dcn.watermarks, 2104 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 2105 true); 2106 2107 if (dc->clk_mgr->dc_mode_softmax_enabled) 2108 if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && 2109 context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) 2110 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk); 2111 2112 /* increase compbuf size */ 2113 if (hubbub->funcs->program_compbuf_size) 2114 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true); 2115 2116 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { 2117 dc_dmub_srv_p_state_delegate(dc, 2118 true, context); 2119 context->bw_ctx.bw.dcn.clk.p_state_change_support = true; 2120 dc->clk_mgr->clks.fw_based_mclk_switching = true; 2121 } else { 2122 dc->clk_mgr->clks.fw_based_mclk_switching = false; 2123 } 2124 2125 dc->clk_mgr->funcs->update_clocks( 2126 dc->clk_mgr, 2127 context, 2128 true); 2129 if (dc_extended_blank_supported(dc) && context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) { 2130 for (i = 0; i < dc->res_pool->pipe_count; ++i) { 2131 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2132 2133 if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank 2134 && pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max 2135 && pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total) 2136 pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp, 2137 pipe_ctx->dlg_regs.optimized_min_dst_y_next_start); 2138 } 2139 } 2140 } 2141 2142 bool dcn20_update_bandwidth( 2143 struct dc *dc, 2144 struct dc_state *context) 2145 { 2146 int i; 2147 struct dce_hwseq *hws = dc->hwseq; 2148 2149 /* recalculate DML parameters */ 2150 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) 2151 return false; 2152 2153 /* apply updated bandwidth parameters */ 2154 dc->hwss.prepare_bandwidth(dc, context); 2155 2156 /* update hubp configs for all pipes */ 2157 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2158 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2159 2160 if (pipe_ctx->plane_state == NULL) 2161 continue; 2162 2163 if (pipe_ctx->top_pipe == NULL) { 2164 bool blank = !is_pipe_tree_visible(pipe_ctx); 2165 2166 pipe_ctx->stream_res.tg->funcs->program_global_sync( 2167 pipe_ctx->stream_res.tg, 2168 calculate_vready_offset_for_group(pipe_ctx), 2169 pipe_ctx->pipe_dlg_param.vstartup_start, 2170 pipe_ctx->pipe_dlg_param.vupdate_offset, 2171 pipe_ctx->pipe_dlg_param.vupdate_width); 2172 2173 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 2174 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false); 2175 2176 if (pipe_ctx->prev_odm_pipe == NULL) 2177 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank); 2178 2179 if (hws->funcs.setup_vupdate_interrupt) 2180 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 2181 } 2182 2183 pipe_ctx->plane_res.hubp->funcs->hubp_setup( 2184 pipe_ctx->plane_res.hubp, 2185 &pipe_ctx->dlg_regs, 2186 &pipe_ctx->ttu_regs, 2187 &pipe_ctx->rq_regs, 2188 &pipe_ctx->pipe_dlg_param); 2189 } 2190 2191 return true; 2192 } 2193 2194 void dcn20_enable_writeback( 2195 struct dc *dc, 2196 struct dc_writeback_info *wb_info, 2197 struct dc_state *context) 2198 { 2199 struct dwbc *dwb; 2200 struct mcif_wb *mcif_wb; 2201 struct timing_generator *optc; 2202 2203 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 2204 ASSERT(wb_info->wb_enabled); 2205 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 2206 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 2207 2208 /* set the OPTC source mux */ 2209 optc = dc->res_pool->timing_generators[dwb->otg_inst]; 2210 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); 2211 /* set MCIF_WB buffer and arbitration configuration */ 2212 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 2213 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 2214 /* Enable MCIF_WB */ 2215 mcif_wb->funcs->enable_mcif(mcif_wb); 2216 /* Enable DWB */ 2217 dwb->funcs->enable(dwb, &wb_info->dwb_params); 2218 /* TODO: add sequence to enable/disable warmup */ 2219 } 2220 2221 void dcn20_disable_writeback( 2222 struct dc *dc, 2223 unsigned int dwb_pipe_inst) 2224 { 2225 struct dwbc *dwb; 2226 struct mcif_wb *mcif_wb; 2227 2228 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); 2229 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; 2230 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; 2231 2232 dwb->funcs->disable(dwb); 2233 mcif_wb->funcs->disable_mcif(mcif_wb); 2234 } 2235 2236 bool dcn20_wait_for_blank_complete( 2237 struct output_pixel_processor *opp) 2238 { 2239 int counter; 2240 2241 for (counter = 0; counter < 1000; counter++) { 2242 if (opp->funcs->dpg_is_blanked(opp)) 2243 break; 2244 2245 udelay(100); 2246 } 2247 2248 if (counter == 1000) { 2249 dm_error("DC: failed to blank crtc!\n"); 2250 return false; 2251 } 2252 2253 return true; 2254 } 2255 2256 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) 2257 { 2258 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2259 2260 if (!hubp) 2261 return false; 2262 return hubp->funcs->dmdata_status_done(hubp); 2263 } 2264 2265 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 2266 { 2267 struct dce_hwseq *hws = dc->hwseq; 2268 2269 if (pipe_ctx->stream_res.dsc) { 2270 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2271 2272 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); 2273 while (odm_pipe) { 2274 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true); 2275 odm_pipe = odm_pipe->next_odm_pipe; 2276 } 2277 } 2278 } 2279 2280 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 2281 { 2282 struct dce_hwseq *hws = dc->hwseq; 2283 2284 if (pipe_ctx->stream_res.dsc) { 2285 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2286 2287 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false); 2288 while (odm_pipe) { 2289 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false); 2290 odm_pipe = odm_pipe->next_odm_pipe; 2291 } 2292 } 2293 } 2294 2295 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) 2296 { 2297 struct dc_dmdata_attributes attr = { 0 }; 2298 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2299 2300 attr.dmdata_mode = DMDATA_HW_MODE; 2301 attr.dmdata_size = 2302 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; 2303 attr.address.quad_part = 2304 pipe_ctx->stream->dmdata_address.quad_part; 2305 attr.dmdata_dl_delta = 0; 2306 attr.dmdata_qos_mode = 0; 2307 attr.dmdata_qos_level = 0; 2308 attr.dmdata_repeat = 1; /* always repeat */ 2309 attr.dmdata_updated = 1; 2310 attr.dmdata_sw_data = NULL; 2311 2312 hubp->funcs->dmdata_set_attributes(hubp, &attr); 2313 } 2314 2315 void dcn20_init_vm_ctx( 2316 struct dce_hwseq *hws, 2317 struct dc *dc, 2318 struct dc_virtual_addr_space_config *va_config, 2319 int vmid) 2320 { 2321 struct dcn_hubbub_virt_addr_config config; 2322 2323 if (vmid == 0) { 2324 ASSERT(0); /* VMID cannot be 0 for vm context */ 2325 return; 2326 } 2327 2328 config.page_table_start_addr = va_config->page_table_start_addr; 2329 config.page_table_end_addr = va_config->page_table_end_addr; 2330 config.page_table_block_size = va_config->page_table_block_size_in_bytes; 2331 config.page_table_depth = va_config->page_table_depth; 2332 config.page_table_base_addr = va_config->page_table_base_addr; 2333 2334 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); 2335 } 2336 2337 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 2338 { 2339 struct dcn_hubbub_phys_addr_config config; 2340 2341 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 2342 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 2343 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 2344 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 2345 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 2346 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 2347 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 2348 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 2349 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 2350 config.page_table_default_page_addr = pa_config->page_table_default_page_addr; 2351 2352 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 2353 } 2354 2355 static bool patch_address_for_sbs_tb_stereo( 2356 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) 2357 { 2358 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2359 bool sec_split = pipe_ctx->top_pipe && 2360 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; 2361 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && 2362 (pipe_ctx->stream->timing.timing_3d_format == 2363 TIMING_3D_FORMAT_SIDE_BY_SIDE || 2364 pipe_ctx->stream->timing.timing_3d_format == 2365 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { 2366 *addr = plane_state->address.grph_stereo.left_addr; 2367 plane_state->address.grph_stereo.left_addr = 2368 plane_state->address.grph_stereo.right_addr; 2369 return true; 2370 } 2371 2372 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && 2373 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { 2374 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; 2375 plane_state->address.grph_stereo.right_addr = 2376 plane_state->address.grph_stereo.left_addr; 2377 plane_state->address.grph_stereo.right_meta_addr = 2378 plane_state->address.grph_stereo.left_meta_addr; 2379 } 2380 return false; 2381 } 2382 2383 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) 2384 { 2385 bool addr_patched = false; 2386 PHYSICAL_ADDRESS_LOC addr; 2387 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2388 2389 if (plane_state == NULL) 2390 return; 2391 2392 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); 2393 2394 // Call Helper to track VMID use 2395 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); 2396 2397 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( 2398 pipe_ctx->plane_res.hubp, 2399 &plane_state->address, 2400 plane_state->flip_immediate); 2401 2402 plane_state->status.requested_address = plane_state->address; 2403 2404 if (plane_state->flip_immediate) 2405 plane_state->status.current_address = plane_state->address; 2406 2407 if (addr_patched) 2408 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; 2409 } 2410 2411 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, 2412 struct dc_link_settings *link_settings) 2413 { 2414 struct encoder_unblank_param params = {0}; 2415 struct dc_stream_state *stream = pipe_ctx->stream; 2416 struct dc_link *link = stream->link; 2417 struct dce_hwseq *hws = link->dc->hwseq; 2418 struct pipe_ctx *odm_pipe; 2419 2420 params.opp_cnt = 1; 2421 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 2422 params.opp_cnt++; 2423 } 2424 /* only 3 items below are used by unblank */ 2425 params.timing = pipe_ctx->stream->timing; 2426 2427 params.link_settings.link_rate = link_settings->link_rate; 2428 2429 if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 2430 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 2431 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 2432 pipe_ctx->stream_res.hpo_dp_stream_enc, 2433 pipe_ctx->stream_res.tg->inst); 2434 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 2435 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1) 2436 params.timing.pix_clk_100hz /= 2; 2437 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 2438 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1); 2439 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 2440 } 2441 2442 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 2443 hws->funcs.edp_backlight_control(link, true); 2444 } 2445 } 2446 2447 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx) 2448 { 2449 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2450 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx); 2451 2452 if (start_line < 0) 2453 start_line = 0; 2454 2455 if (tg->funcs->setup_vertical_interrupt2) 2456 tg->funcs->setup_vertical_interrupt2(tg, start_line); 2457 } 2458 2459 static void dcn20_reset_back_end_for_pipe( 2460 struct dc *dc, 2461 struct pipe_ctx *pipe_ctx, 2462 struct dc_state *context) 2463 { 2464 int i; 2465 struct dc_link *link = pipe_ctx->stream->link; 2466 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2467 2468 DC_LOGGER_INIT(dc->ctx->logger); 2469 if (pipe_ctx->stream_res.stream_enc == NULL) { 2470 pipe_ctx->stream = NULL; 2471 return; 2472 } 2473 2474 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 2475 /* DPMS may already disable or */ 2476 /* dpms_off status is incorrect due to fastboot 2477 * feature. When system resume from S4 with second 2478 * screen only, the dpms_off would be true but 2479 * VBIOS lit up eDP, so check link status too. 2480 */ 2481 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 2482 dc->link_srv->set_dpms_off(pipe_ctx); 2483 else if (pipe_ctx->stream_res.audio) 2484 dc->hwss.disable_audio_stream(pipe_ctx); 2485 2486 /* free acquired resources */ 2487 if (pipe_ctx->stream_res.audio) { 2488 /*disable az_endpoint*/ 2489 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 2490 2491 /*free audio*/ 2492 if (dc->caps.dynamic_audio == true) { 2493 /*we have to dynamic arbitrate the audio endpoints*/ 2494 /*we free the resource, need reset is_audio_acquired*/ 2495 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 2496 pipe_ctx->stream_res.audio, false); 2497 pipe_ctx->stream_res.audio = NULL; 2498 } 2499 } 2500 } 2501 else if (pipe_ctx->stream_res.dsc) { 2502 dc->link_srv->set_dsc_enable(pipe_ctx, false); 2503 } 2504 2505 /* by upper caller loop, parent pipe: pipe0, will be reset last. 2506 * back end share by all pipes and will be disable only when disable 2507 * parent pipe. 2508 */ 2509 if (pipe_ctx->top_pipe == NULL) { 2510 2511 dc->hwss.set_abm_immediate_disable(pipe_ctx); 2512 2513 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 2514 2515 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 2516 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 2517 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 2518 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 2519 2520 if (pipe_ctx->stream_res.tg->funcs->set_drr) 2521 pipe_ctx->stream_res.tg->funcs->set_drr( 2522 pipe_ctx->stream_res.tg, NULL); 2523 /* TODO - convert symclk_ref_cnts for otg to a bit map to solve 2524 * the case where the same symclk is shared across multiple otg 2525 * instances 2526 */ 2527 link->phy_state.symclk_ref_cnts.otg = 0; 2528 if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) { 2529 link_hwss->disable_link_output(link, 2530 &pipe_ctx->link_res, pipe_ctx->stream->signal); 2531 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 2532 } 2533 } 2534 2535 for (i = 0; i < dc->res_pool->pipe_count; i++) 2536 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) 2537 break; 2538 2539 if (i == dc->res_pool->pipe_count) 2540 return; 2541 2542 pipe_ctx->stream = NULL; 2543 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 2544 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 2545 } 2546 2547 void dcn20_reset_hw_ctx_wrap( 2548 struct dc *dc, 2549 struct dc_state *context) 2550 { 2551 int i; 2552 struct dce_hwseq *hws = dc->hwseq; 2553 2554 /* Reset Back End*/ 2555 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 2556 struct pipe_ctx *pipe_ctx_old = 2557 &dc->current_state->res_ctx.pipe_ctx[i]; 2558 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2559 2560 if (!pipe_ctx_old->stream) 2561 continue; 2562 2563 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 2564 continue; 2565 2566 if (!pipe_ctx->stream || 2567 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 2568 struct clock_source *old_clk = pipe_ctx_old->clock_source; 2569 2570 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 2571 if (hws->funcs.enable_stream_gating) 2572 hws->funcs.enable_stream_gating(dc, pipe_ctx_old); 2573 if (old_clk) 2574 old_clk->funcs->cs_power_down(old_clk); 2575 } 2576 } 2577 } 2578 2579 void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id) 2580 { 2581 struct mpc *mpc = dc->res_pool->mpc; 2582 2583 // input to MPCC is always RGB, by default leave black_color at 0 2584 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) 2585 get_hdr_visual_confirm_color(pipe_ctx, color); 2586 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) 2587 get_surface_visual_confirm_color(pipe_ctx, color); 2588 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) 2589 get_mpctree_visual_confirm_color(pipe_ctx, color); 2590 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE) 2591 get_surface_tile_visual_confirm_color(pipe_ctx, color); 2592 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP) 2593 get_subvp_visual_confirm_color(dc, pipe_ctx, color); 2594 2595 if (mpc->funcs->set_bg_color) { 2596 memcpy(&pipe_ctx->plane_state->visual_confirm_color, color, sizeof(struct tg_color)); 2597 mpc->funcs->set_bg_color(mpc, color, mpcc_id); 2598 } 2599 } 2600 2601 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 2602 { 2603 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2604 struct mpcc_blnd_cfg blnd_cfg = {0}; 2605 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; 2606 int mpcc_id; 2607 struct mpcc *new_mpcc; 2608 struct mpc *mpc = dc->res_pool->mpc; 2609 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); 2610 2611 blnd_cfg.overlap_only = false; 2612 blnd_cfg.global_gain = 0xff; 2613 2614 if (per_pixel_alpha) { 2615 blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha; 2616 if (pipe_ctx->plane_state->global_alpha) { 2617 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; 2618 blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value; 2619 } else { 2620 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2621 } 2622 } else { 2623 blnd_cfg.pre_multiplied_alpha = false; 2624 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 2625 } 2626 2627 if (pipe_ctx->plane_state->global_alpha) 2628 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; 2629 else 2630 blnd_cfg.global_alpha = 0xff; 2631 2632 blnd_cfg.background_color_bpc = 4; 2633 blnd_cfg.bottom_gain_mode = 0; 2634 blnd_cfg.top_gain = 0x1f000; 2635 blnd_cfg.bottom_inside_gain = 0x1f000; 2636 blnd_cfg.bottom_outside_gain = 0x1f000; 2637 2638 if (pipe_ctx->plane_state->format 2639 == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA) 2640 blnd_cfg.pre_multiplied_alpha = false; 2641 2642 /* 2643 * TODO: remove hack 2644 * Note: currently there is a bug in init_hw such that 2645 * on resume from hibernate, BIOS sets up MPCC0, and 2646 * we do mpcc_remove but the mpcc cannot go to idle 2647 * after remove. This cause us to pick mpcc1 here, 2648 * which causes a pstate hang for yet unknown reason. 2649 */ 2650 mpcc_id = hubp->inst; 2651 2652 /* If there is no full update, don't need to touch MPC tree*/ 2653 if (!pipe_ctx->plane_state->update_flags.bits.full_update && 2654 !pipe_ctx->update_flags.bits.mpcc) { 2655 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); 2656 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); 2657 return; 2658 } 2659 2660 /* check if this MPCC is already being used */ 2661 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 2662 /* remove MPCC if being used */ 2663 if (new_mpcc != NULL) 2664 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); 2665 else 2666 if (dc->debug.sanity_checks) 2667 mpc->funcs->assert_mpcc_idle_before_connect( 2668 dc->res_pool->mpc, mpcc_id); 2669 2670 /* Call MPC to insert new plane */ 2671 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, 2672 mpc_tree_params, 2673 &blnd_cfg, 2674 NULL, 2675 NULL, 2676 hubp->inst, 2677 mpcc_id); 2678 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); 2679 2680 ASSERT(new_mpcc != NULL); 2681 hubp->opp_id = pipe_ctx->stream_res.opp->inst; 2682 hubp->mpcc_id = mpcc_id; 2683 } 2684 2685 static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link) 2686 { 2687 switch (link->link_enc->transmitter) { 2688 case TRANSMITTER_UNIPHY_A: 2689 return PHYD32CLKA; 2690 case TRANSMITTER_UNIPHY_B: 2691 return PHYD32CLKB; 2692 case TRANSMITTER_UNIPHY_C: 2693 return PHYD32CLKC; 2694 case TRANSMITTER_UNIPHY_D: 2695 return PHYD32CLKD; 2696 case TRANSMITTER_UNIPHY_E: 2697 return PHYD32CLKE; 2698 default: 2699 return PHYD32CLKA; 2700 } 2701 } 2702 2703 static int get_odm_segment_count(struct pipe_ctx *pipe_ctx) 2704 { 2705 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2706 int count = 1; 2707 2708 while (odm_pipe != NULL) { 2709 count++; 2710 odm_pipe = odm_pipe->next_odm_pipe; 2711 } 2712 2713 return count; 2714 } 2715 2716 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 2717 { 2718 enum dc_lane_count lane_count = 2719 pipe_ctx->stream->link->cur_link_settings.lane_count; 2720 2721 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 2722 struct dc_link *link = pipe_ctx->stream->link; 2723 2724 uint32_t active_total_with_borders; 2725 uint32_t early_control = 0; 2726 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2727 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2728 struct dc *dc = pipe_ctx->stream->ctx->dc; 2729 struct dtbclk_dto_params dto_params = {0}; 2730 struct dccg *dccg = dc->res_pool->dccg; 2731 enum phyd32clk_clock_source phyd32clk; 2732 int dp_hpo_inst; 2733 struct dce_hwseq *hws = dc->hwseq; 2734 unsigned int k1_div = PIXEL_RATE_DIV_NA; 2735 unsigned int k2_div = PIXEL_RATE_DIV_NA; 2736 2737 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 2738 if (dc->hwseq->funcs.setup_hpo_hw_control) 2739 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, true); 2740 } 2741 2742 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 2743 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; 2744 dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst); 2745 2746 phyd32clk = get_phyd32clk_src(link); 2747 dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); 2748 2749 dto_params.otg_inst = tg->inst; 2750 dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10; 2751 dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx); 2752 dto_params.timing = &pipe_ctx->stream->timing; 2753 dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); 2754 dccg->funcs->set_dtbclk_dto(dccg, &dto_params); 2755 } 2756 2757 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { 2758 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); 2759 2760 dc->res_pool->dccg->funcs->set_pixel_rate_div( 2761 dc->res_pool->dccg, 2762 pipe_ctx->stream_res.tg->inst, 2763 k1_div, k2_div); 2764 } 2765 2766 link_hwss->setup_stream_encoder(pipe_ctx); 2767 2768 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) { 2769 if (dc->hwss.program_dmdata_engine) 2770 dc->hwss.program_dmdata_engine(pipe_ctx); 2771 } 2772 2773 dc->hwss.update_info_frame(pipe_ctx); 2774 2775 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2776 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2777 2778 /* enable early control to avoid corruption on DP monitor*/ 2779 active_total_with_borders = 2780 timing->h_addressable 2781 + timing->h_border_left 2782 + timing->h_border_right; 2783 2784 if (lane_count != 0) 2785 early_control = active_total_with_borders % lane_count; 2786 2787 if (early_control == 0) 2788 early_control = lane_count; 2789 2790 tg->funcs->set_early_control(tg, early_control); 2791 2792 if (dc->hwseq->funcs.set_pixels_per_cycle) 2793 dc->hwseq->funcs.set_pixels_per_cycle(pipe_ctx); 2794 } 2795 2796 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx) 2797 { 2798 struct dc_stream_state *stream = pipe_ctx->stream; 2799 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2800 bool enable = false; 2801 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2802 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) 2803 ? dmdata_dp 2804 : dmdata_hdmi; 2805 2806 /* if using dynamic meta, don't set up generic infopackets */ 2807 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { 2808 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; 2809 enable = true; 2810 } 2811 2812 if (!hubp) 2813 return; 2814 2815 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) 2816 return; 2817 2818 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, 2819 hubp->inst, mode); 2820 } 2821 2822 void dcn20_fpga_init_hw(struct dc *dc) 2823 { 2824 int i, j; 2825 struct dce_hwseq *hws = dc->hwseq; 2826 struct resource_pool *res_pool = dc->res_pool; 2827 struct dc_state *context = dc->current_state; 2828 2829 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 2830 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 2831 2832 // Initialize the dccg 2833 if (res_pool->dccg->funcs->dccg_init) 2834 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 2835 2836 //Enable ability to power gate / don't force power on permanently 2837 hws->funcs.enable_power_gating_plane(hws, true); 2838 2839 // Specific to FPGA dccg and registers 2840 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); 2841 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 2842 2843 hws->funcs.dccg_init(hws); 2844 2845 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); 2846 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 2847 if (REG(REFCLK_CNTL)) 2848 REG_WRITE(REFCLK_CNTL, 0); 2849 // 2850 2851 2852 /* Blank pixel data with OPP DPG */ 2853 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2854 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2855 2856 if (tg->funcs->is_tg_enabled(tg)) 2857 dcn20_init_blank(dc, tg); 2858 } 2859 2860 for (i = 0; i < res_pool->timing_generator_count; i++) { 2861 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2862 2863 if (tg->funcs->is_tg_enabled(tg)) 2864 tg->funcs->lock(tg); 2865 } 2866 2867 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2868 struct dpp *dpp = res_pool->dpps[i]; 2869 2870 dpp->funcs->dpp_reset(dpp); 2871 } 2872 2873 /* Reset all MPCC muxes */ 2874 res_pool->mpc->funcs->mpc_init(res_pool->mpc); 2875 2876 /* initialize OPP mpc_tree parameter */ 2877 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 2878 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; 2879 res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2880 for (j = 0; j < MAX_PIPES; j++) 2881 res_pool->opps[i]->mpcc_disconnect_pending[j] = false; 2882 } 2883 2884 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2885 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2886 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2887 struct hubp *hubp = dc->res_pool->hubps[i]; 2888 struct dpp *dpp = dc->res_pool->dpps[i]; 2889 2890 pipe_ctx->stream_res.tg = tg; 2891 pipe_ctx->pipe_idx = i; 2892 2893 pipe_ctx->plane_res.hubp = hubp; 2894 pipe_ctx->plane_res.dpp = dpp; 2895 pipe_ctx->plane_res.mpcc_inst = dpp->inst; 2896 hubp->mpcc_id = dpp->inst; 2897 hubp->opp_id = OPP_ID_INVALID; 2898 hubp->power_gated = false; 2899 pipe_ctx->stream_res.opp = NULL; 2900 2901 hubp->funcs->hubp_init(hubp); 2902 2903 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; 2904 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2905 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; 2906 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; 2907 /*to do*/ 2908 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx); 2909 } 2910 2911 /* initialize DWB pointer to MCIF_WB */ 2912 for (i = 0; i < res_pool->res_cap->num_dwb; i++) 2913 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; 2914 2915 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2916 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2917 2918 if (tg->funcs->is_tg_enabled(tg)) 2919 tg->funcs->unlock(tg); 2920 } 2921 2922 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2923 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2924 2925 dc->hwss.disable_plane(dc, pipe_ctx); 2926 2927 pipe_ctx->stream_res.tg = NULL; 2928 pipe_ctx->plane_res.hubp = NULL; 2929 } 2930 2931 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2932 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2933 2934 tg->funcs->tg_init(tg); 2935 } 2936 2937 if (dc->res_pool->hubbub->funcs->init_crb) 2938 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 2939 } 2940 #ifndef TRIM_FSFT 2941 bool dcn20_optimize_timing_for_fsft(struct dc *dc, 2942 struct dc_crtc_timing *timing, 2943 unsigned int max_input_rate_in_khz) 2944 { 2945 unsigned int old_v_front_porch; 2946 unsigned int old_v_total; 2947 unsigned int max_input_rate_in_100hz; 2948 unsigned long long new_v_total; 2949 2950 max_input_rate_in_100hz = max_input_rate_in_khz * 10; 2951 if (max_input_rate_in_100hz < timing->pix_clk_100hz) 2952 return false; 2953 2954 old_v_total = timing->v_total; 2955 old_v_front_porch = timing->v_front_porch; 2956 2957 timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz; 2958 timing->pix_clk_100hz = max_input_rate_in_100hz; 2959 2960 new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz); 2961 2962 timing->v_total = new_v_total; 2963 timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total); 2964 return true; 2965 } 2966 #endif 2967 2968 void dcn20_set_disp_pattern_generator(const struct dc *dc, 2969 struct pipe_ctx *pipe_ctx, 2970 enum controller_dp_test_pattern test_pattern, 2971 enum controller_dp_color_space color_space, 2972 enum dc_color_depth color_depth, 2973 const struct tg_color *solid_color, 2974 int width, int height, int offset) 2975 { 2976 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern, 2977 color_space, color_depth, solid_color, width, height, offset); 2978 } 2979