1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include <linux/delay.h> 26 27 #include "dm_services.h" 28 #include "basics/dc_common.h" 29 #include "dm_helpers.h" 30 #include "core_types.h" 31 #include "resource.h" 32 #include "dcn20_resource.h" 33 #include "dcn20_hwseq.h" 34 #include "dce/dce_hwseq.h" 35 #include "dcn20_dsc.h" 36 #include "dcn20_optc.h" 37 #include "abm.h" 38 #include "clk_mgr.h" 39 #include "dmcu.h" 40 #include "hubp.h" 41 #include "timing_generator.h" 42 #include "opp.h" 43 #include "ipp.h" 44 #include "mpc.h" 45 #include "mcif_wb.h" 46 #include "dchubbub.h" 47 #include "reg_helper.h" 48 #include "dcn10/dcn10_cm_common.h" 49 #include "dc_link_dp.h" 50 #include "vm_helper.h" 51 #include "dccg.h" 52 #include "dc_dmub_srv.h" 53 #include "dce/dmub_hw_lock_mgr.h" 54 #include "hw_sequencer.h" 55 #include "inc/link_dpcd.h" 56 #include "dpcd_defs.h" 57 #include "inc/link_enc_cfg.h" 58 #include "link_hwss.h" 59 60 #define DC_LOGGER_INIT(logger) 61 62 #define CTX \ 63 hws->ctx 64 #define REG(reg)\ 65 hws->regs->reg 66 67 #undef FN 68 #define FN(reg_name, field_name) \ 69 hws->shifts->field_name, hws->masks->field_name 70 71 static int find_free_gsl_group(const struct dc *dc) 72 { 73 if (dc->res_pool->gsl_groups.gsl_0 == 0) 74 return 1; 75 if (dc->res_pool->gsl_groups.gsl_1 == 0) 76 return 2; 77 if (dc->res_pool->gsl_groups.gsl_2 == 0) 78 return 3; 79 80 return 0; 81 } 82 83 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock) 84 * This is only used to lock pipes in pipe splitting case with immediate flip 85 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate, 86 * so we get tearing with freesync since we cannot flip multiple pipes 87 * atomically. 88 * We use GSL for this: 89 * - immediate flip: find first available GSL group if not already assigned 90 * program gsl with that group, set current OTG as master 91 * and always us 0x4 = AND of flip_ready from all pipes 92 * - vsync flip: disable GSL if used 93 * 94 * Groups in stream_res are stored as +1 from HW registers, i.e. 95 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1 96 * Using a magic value like -1 would require tracking all inits/resets 97 */ 98 static void dcn20_setup_gsl_group_as_lock( 99 const struct dc *dc, 100 struct pipe_ctx *pipe_ctx, 101 bool enable) 102 { 103 struct gsl_params gsl; 104 int group_idx; 105 106 memset(&gsl, 0, sizeof(struct gsl_params)); 107 108 if (enable) { 109 /* return if group already assigned since GSL was set up 110 * for vsync flip, we would unassign so it can't be "left over" 111 */ 112 if (pipe_ctx->stream_res.gsl_group > 0) 113 return; 114 115 group_idx = find_free_gsl_group(dc); 116 ASSERT(group_idx != 0); 117 pipe_ctx->stream_res.gsl_group = group_idx; 118 119 /* set gsl group reg field and mark resource used */ 120 switch (group_idx) { 121 case 1: 122 gsl.gsl0_en = 1; 123 dc->res_pool->gsl_groups.gsl_0 = 1; 124 break; 125 case 2: 126 gsl.gsl1_en = 1; 127 dc->res_pool->gsl_groups.gsl_1 = 1; 128 break; 129 case 3: 130 gsl.gsl2_en = 1; 131 dc->res_pool->gsl_groups.gsl_2 = 1; 132 break; 133 default: 134 BREAK_TO_DEBUGGER(); 135 return; // invalid case 136 } 137 gsl.gsl_master_en = 1; 138 } else { 139 group_idx = pipe_ctx->stream_res.gsl_group; 140 if (group_idx == 0) 141 return; // if not in use, just return 142 143 pipe_ctx->stream_res.gsl_group = 0; 144 145 /* unset gsl group reg field and mark resource free */ 146 switch (group_idx) { 147 case 1: 148 gsl.gsl0_en = 0; 149 dc->res_pool->gsl_groups.gsl_0 = 0; 150 break; 151 case 2: 152 gsl.gsl1_en = 0; 153 dc->res_pool->gsl_groups.gsl_1 = 0; 154 break; 155 case 3: 156 gsl.gsl2_en = 0; 157 dc->res_pool->gsl_groups.gsl_2 = 0; 158 break; 159 default: 160 BREAK_TO_DEBUGGER(); 161 return; 162 } 163 gsl.gsl_master_en = 0; 164 } 165 166 /* at this point we want to program whether it's to enable or disable */ 167 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && 168 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { 169 pipe_ctx->stream_res.tg->funcs->set_gsl( 170 pipe_ctx->stream_res.tg, 171 &gsl); 172 173 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( 174 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); 175 } else 176 BREAK_TO_DEBUGGER(); 177 } 178 179 void dcn20_set_flip_control_gsl( 180 struct pipe_ctx *pipe_ctx, 181 bool flip_immediate) 182 { 183 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) 184 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( 185 pipe_ctx->plane_res.hubp, flip_immediate); 186 187 } 188 189 void dcn20_enable_power_gating_plane( 190 struct dce_hwseq *hws, 191 bool enable) 192 { 193 bool force_on = true; /* disable power gating */ 194 195 if (enable) 196 force_on = false; 197 198 /* DCHUBP0/1/2/3/4/5 */ 199 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); 200 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); 201 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); 202 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); 203 if (REG(DOMAIN8_PG_CONFIG)) 204 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 205 if (REG(DOMAIN10_PG_CONFIG)) 206 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 207 208 /* DPP0/1/2/3/4/5 */ 209 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); 210 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); 211 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); 212 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); 213 if (REG(DOMAIN9_PG_CONFIG)) 214 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 215 if (REG(DOMAIN11_PG_CONFIG)) 216 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 217 218 /* DCS0/1/2/3/4/5 */ 219 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on); 220 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on); 221 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on); 222 if (REG(DOMAIN19_PG_CONFIG)) 223 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on); 224 if (REG(DOMAIN20_PG_CONFIG)) 225 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on); 226 if (REG(DOMAIN21_PG_CONFIG)) 227 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); 228 } 229 230 void dcn20_dccg_init(struct dce_hwseq *hws) 231 { 232 /* 233 * set MICROSECOND_TIME_BASE_DIV 234 * 100Mhz refclk -> 0x120264 235 * 27Mhz refclk -> 0x12021b 236 * 48Mhz refclk -> 0x120230 237 * 238 */ 239 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); 240 241 /* 242 * set MILLISECOND_TIME_BASE_DIV 243 * 100Mhz refclk -> 0x1186a0 244 * 27Mhz refclk -> 0x106978 245 * 48Mhz refclk -> 0x10bb80 246 * 247 */ 248 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); 249 250 /* This value is dependent on the hardware pipeline delay so set once per SOC */ 251 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c); 252 } 253 254 void dcn20_disable_vga( 255 struct dce_hwseq *hws) 256 { 257 REG_WRITE(D1VGA_CONTROL, 0); 258 REG_WRITE(D2VGA_CONTROL, 0); 259 REG_WRITE(D3VGA_CONTROL, 0); 260 REG_WRITE(D4VGA_CONTROL, 0); 261 REG_WRITE(D5VGA_CONTROL, 0); 262 REG_WRITE(D6VGA_CONTROL, 0); 263 } 264 265 void dcn20_program_triple_buffer( 266 const struct dc *dc, 267 struct pipe_ctx *pipe_ctx, 268 bool enable_triple_buffer) 269 { 270 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { 271 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( 272 pipe_ctx->plane_res.hubp, 273 enable_triple_buffer); 274 } 275 } 276 277 /* Blank pixel data during initialization */ 278 void dcn20_init_blank( 279 struct dc *dc, 280 struct timing_generator *tg) 281 { 282 struct dce_hwseq *hws = dc->hwseq; 283 enum dc_color_space color_space; 284 struct tg_color black_color = {0}; 285 struct output_pixel_processor *opp = NULL; 286 struct output_pixel_processor *bottom_opp = NULL; 287 uint32_t num_opps, opp_id_src0, opp_id_src1; 288 uint32_t otg_active_width, otg_active_height; 289 290 /* program opp dpg blank color */ 291 color_space = COLOR_SPACE_SRGB; 292 color_space_to_black_color(dc, color_space, &black_color); 293 294 /* get the OTG active size */ 295 tg->funcs->get_otg_active_size(tg, 296 &otg_active_width, 297 &otg_active_height); 298 299 /* get the OPTC source */ 300 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 301 302 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { 303 ASSERT(false); 304 return; 305 } 306 opp = dc->res_pool->opps[opp_id_src0]; 307 308 if (num_opps == 2) { 309 otg_active_width = otg_active_width / 2; 310 311 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { 312 ASSERT(false); 313 return; 314 } 315 bottom_opp = dc->res_pool->opps[opp_id_src1]; 316 } 317 318 opp->funcs->opp_set_disp_pattern_generator( 319 opp, 320 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 321 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 322 COLOR_DEPTH_UNDEFINED, 323 &black_color, 324 otg_active_width, 325 otg_active_height, 326 0); 327 328 if (num_opps == 2) { 329 bottom_opp->funcs->opp_set_disp_pattern_generator( 330 bottom_opp, 331 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 332 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 333 COLOR_DEPTH_UNDEFINED, 334 &black_color, 335 otg_active_width, 336 otg_active_height, 337 0); 338 } 339 340 hws->funcs.wait_for_blank_complete(opp); 341 } 342 343 void dcn20_dsc_pg_control( 344 struct dce_hwseq *hws, 345 unsigned int dsc_inst, 346 bool power_on) 347 { 348 uint32_t power_gate = power_on ? 0 : 1; 349 uint32_t pwr_status = power_on ? 0 : 2; 350 uint32_t org_ip_request_cntl = 0; 351 352 if (hws->ctx->dc->debug.disable_dsc_power_gate) 353 return; 354 355 if (REG(DOMAIN16_PG_CONFIG) == 0) 356 return; 357 358 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 359 if (org_ip_request_cntl == 0) 360 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 361 362 switch (dsc_inst) { 363 case 0: /* DSC0 */ 364 REG_UPDATE(DOMAIN16_PG_CONFIG, 365 DOMAIN16_POWER_GATE, power_gate); 366 367 REG_WAIT(DOMAIN16_PG_STATUS, 368 DOMAIN16_PGFSM_PWR_STATUS, pwr_status, 369 1, 1000); 370 break; 371 case 1: /* DSC1 */ 372 REG_UPDATE(DOMAIN17_PG_CONFIG, 373 DOMAIN17_POWER_GATE, power_gate); 374 375 REG_WAIT(DOMAIN17_PG_STATUS, 376 DOMAIN17_PGFSM_PWR_STATUS, pwr_status, 377 1, 1000); 378 break; 379 case 2: /* DSC2 */ 380 REG_UPDATE(DOMAIN18_PG_CONFIG, 381 DOMAIN18_POWER_GATE, power_gate); 382 383 REG_WAIT(DOMAIN18_PG_STATUS, 384 DOMAIN18_PGFSM_PWR_STATUS, pwr_status, 385 1, 1000); 386 break; 387 case 3: /* DSC3 */ 388 REG_UPDATE(DOMAIN19_PG_CONFIG, 389 DOMAIN19_POWER_GATE, power_gate); 390 391 REG_WAIT(DOMAIN19_PG_STATUS, 392 DOMAIN19_PGFSM_PWR_STATUS, pwr_status, 393 1, 1000); 394 break; 395 case 4: /* DSC4 */ 396 REG_UPDATE(DOMAIN20_PG_CONFIG, 397 DOMAIN20_POWER_GATE, power_gate); 398 399 REG_WAIT(DOMAIN20_PG_STATUS, 400 DOMAIN20_PGFSM_PWR_STATUS, pwr_status, 401 1, 1000); 402 break; 403 case 5: /* DSC5 */ 404 REG_UPDATE(DOMAIN21_PG_CONFIG, 405 DOMAIN21_POWER_GATE, power_gate); 406 407 REG_WAIT(DOMAIN21_PG_STATUS, 408 DOMAIN21_PGFSM_PWR_STATUS, pwr_status, 409 1, 1000); 410 break; 411 default: 412 BREAK_TO_DEBUGGER(); 413 break; 414 } 415 416 if (org_ip_request_cntl == 0) 417 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 418 } 419 420 void dcn20_dpp_pg_control( 421 struct dce_hwseq *hws, 422 unsigned int dpp_inst, 423 bool power_on) 424 { 425 uint32_t power_gate = power_on ? 0 : 1; 426 uint32_t pwr_status = power_on ? 0 : 2; 427 428 if (hws->ctx->dc->debug.disable_dpp_power_gate) 429 return; 430 if (REG(DOMAIN1_PG_CONFIG) == 0) 431 return; 432 433 switch (dpp_inst) { 434 case 0: /* DPP0 */ 435 REG_UPDATE(DOMAIN1_PG_CONFIG, 436 DOMAIN1_POWER_GATE, power_gate); 437 438 REG_WAIT(DOMAIN1_PG_STATUS, 439 DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 440 1, 1000); 441 break; 442 case 1: /* DPP1 */ 443 REG_UPDATE(DOMAIN3_PG_CONFIG, 444 DOMAIN3_POWER_GATE, power_gate); 445 446 REG_WAIT(DOMAIN3_PG_STATUS, 447 DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 448 1, 1000); 449 break; 450 case 2: /* DPP2 */ 451 REG_UPDATE(DOMAIN5_PG_CONFIG, 452 DOMAIN5_POWER_GATE, power_gate); 453 454 REG_WAIT(DOMAIN5_PG_STATUS, 455 DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 456 1, 1000); 457 break; 458 case 3: /* DPP3 */ 459 REG_UPDATE(DOMAIN7_PG_CONFIG, 460 DOMAIN7_POWER_GATE, power_gate); 461 462 REG_WAIT(DOMAIN7_PG_STATUS, 463 DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 464 1, 1000); 465 break; 466 case 4: /* DPP4 */ 467 REG_UPDATE(DOMAIN9_PG_CONFIG, 468 DOMAIN9_POWER_GATE, power_gate); 469 470 REG_WAIT(DOMAIN9_PG_STATUS, 471 DOMAIN9_PGFSM_PWR_STATUS, pwr_status, 472 1, 1000); 473 break; 474 case 5: /* DPP5 */ 475 /* 476 * Do not power gate DPP5, should be left at HW default, power on permanently. 477 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 478 * reset. 479 * REG_UPDATE(DOMAIN11_PG_CONFIG, 480 * DOMAIN11_POWER_GATE, power_gate); 481 * 482 * REG_WAIT(DOMAIN11_PG_STATUS, 483 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, 484 * 1, 1000); 485 */ 486 break; 487 default: 488 BREAK_TO_DEBUGGER(); 489 break; 490 } 491 } 492 493 494 void dcn20_hubp_pg_control( 495 struct dce_hwseq *hws, 496 unsigned int hubp_inst, 497 bool power_on) 498 { 499 uint32_t power_gate = power_on ? 0 : 1; 500 uint32_t pwr_status = power_on ? 0 : 2; 501 502 if (hws->ctx->dc->debug.disable_hubp_power_gate) 503 return; 504 if (REG(DOMAIN0_PG_CONFIG) == 0) 505 return; 506 507 switch (hubp_inst) { 508 case 0: /* DCHUBP0 */ 509 REG_UPDATE(DOMAIN0_PG_CONFIG, 510 DOMAIN0_POWER_GATE, power_gate); 511 512 REG_WAIT(DOMAIN0_PG_STATUS, 513 DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 514 1, 1000); 515 break; 516 case 1: /* DCHUBP1 */ 517 REG_UPDATE(DOMAIN2_PG_CONFIG, 518 DOMAIN2_POWER_GATE, power_gate); 519 520 REG_WAIT(DOMAIN2_PG_STATUS, 521 DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 522 1, 1000); 523 break; 524 case 2: /* DCHUBP2 */ 525 REG_UPDATE(DOMAIN4_PG_CONFIG, 526 DOMAIN4_POWER_GATE, power_gate); 527 528 REG_WAIT(DOMAIN4_PG_STATUS, 529 DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 530 1, 1000); 531 break; 532 case 3: /* DCHUBP3 */ 533 REG_UPDATE(DOMAIN6_PG_CONFIG, 534 DOMAIN6_POWER_GATE, power_gate); 535 536 REG_WAIT(DOMAIN6_PG_STATUS, 537 DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 538 1, 1000); 539 break; 540 case 4: /* DCHUBP4 */ 541 REG_UPDATE(DOMAIN8_PG_CONFIG, 542 DOMAIN8_POWER_GATE, power_gate); 543 544 REG_WAIT(DOMAIN8_PG_STATUS, 545 DOMAIN8_PGFSM_PWR_STATUS, pwr_status, 546 1, 1000); 547 break; 548 case 5: /* DCHUBP5 */ 549 /* 550 * Do not power gate DCHUB5, should be left at HW default, power on permanently. 551 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 552 * reset. 553 * REG_UPDATE(DOMAIN10_PG_CONFIG, 554 * DOMAIN10_POWER_GATE, power_gate); 555 * 556 * REG_WAIT(DOMAIN10_PG_STATUS, 557 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status, 558 * 1, 1000); 559 */ 560 break; 561 default: 562 BREAK_TO_DEBUGGER(); 563 break; 564 } 565 } 566 567 568 /* disable HW used by plane. 569 * note: cannot disable until disconnect is complete 570 */ 571 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 572 { 573 struct dce_hwseq *hws = dc->hwseq; 574 struct hubp *hubp = pipe_ctx->plane_res.hubp; 575 struct dpp *dpp = pipe_ctx->plane_res.dpp; 576 577 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); 578 579 /* In flip immediate with pipe splitting case GSL is used for 580 * synchronization so we must disable it when the plane is disabled. 581 */ 582 if (pipe_ctx->stream_res.gsl_group != 0) 583 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false); 584 585 dc->hwss.set_flip_control_gsl(pipe_ctx, false); 586 587 hubp->funcs->hubp_clk_cntl(hubp, false); 588 589 dpp->funcs->dpp_dppclk_control(dpp, false, false); 590 591 hubp->power_gated = true; 592 593 hws->funcs.plane_atomic_power_down(dc, 594 pipe_ctx->plane_res.dpp, 595 pipe_ctx->plane_res.hubp); 596 597 pipe_ctx->stream = NULL; 598 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); 599 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); 600 pipe_ctx->top_pipe = NULL; 601 pipe_ctx->bottom_pipe = NULL; 602 pipe_ctx->plane_state = NULL; 603 } 604 605 606 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) 607 { 608 DC_LOGGER_INIT(dc->ctx->logger); 609 610 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) 611 return; 612 613 dcn20_plane_atomic_disable(dc, pipe_ctx); 614 615 DC_LOG_DC("Power down front end %d\n", 616 pipe_ctx->pipe_idx); 617 } 618 619 void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank) 620 { 621 dcn20_blank_pixel_data(dc, pipe_ctx, blank); 622 } 623 624 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 625 int opp_cnt) 626 { 627 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 628 int flow_ctrl_cnt; 629 630 if (opp_cnt >= 2) 631 hblank_halved = true; 632 633 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 634 stream->timing.h_border_left - 635 stream->timing.h_border_right; 636 637 if (hblank_halved) 638 flow_ctrl_cnt /= 2; 639 640 /* ODM combine 4:1 case */ 641 if (opp_cnt == 4) 642 flow_ctrl_cnt /= 2; 643 644 return flow_ctrl_cnt; 645 } 646 647 enum dc_status dcn20_enable_stream_timing( 648 struct pipe_ctx *pipe_ctx, 649 struct dc_state *context, 650 struct dc *dc) 651 { 652 struct dce_hwseq *hws = dc->hwseq; 653 struct dc_stream_state *stream = pipe_ctx->stream; 654 struct drr_params params = {0}; 655 unsigned int event_triggers = 0; 656 struct pipe_ctx *odm_pipe; 657 int opp_cnt = 1; 658 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 659 bool interlace = stream->timing.flags.INTERLACE; 660 int i; 661 struct mpc_dwb_flow_control flow_control; 662 struct mpc *mpc = dc->res_pool->mpc; 663 bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing)); 664 665 /* by upper caller loop, pipe0 is parent pipe and be called first. 666 * back end is set up by for pipe0. Other children pipe share back end 667 * with pipe 0. No program is needed. 668 */ 669 if (pipe_ctx->top_pipe != NULL) 670 return DC_OK; 671 672 /* TODO check if timing_changed, disable stream if timing changed */ 673 674 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 675 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 676 opp_cnt++; 677 } 678 679 if (opp_cnt > 1) 680 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 681 pipe_ctx->stream_res.tg, 682 opp_inst, opp_cnt, 683 &pipe_ctx->stream->timing); 684 685 /* HW program guide assume display already disable 686 * by unplug sequence. OTG assume stop. 687 */ 688 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); 689 690 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 691 pipe_ctx->clock_source, 692 &pipe_ctx->stream_res.pix_clk_params, 693 &pipe_ctx->pll_settings)) { 694 BREAK_TO_DEBUGGER(); 695 return DC_ERROR_UNEXPECTED; 696 } 697 698 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal))) 699 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx); 700 701 pipe_ctx->stream_res.tg->funcs->program_timing( 702 pipe_ctx->stream_res.tg, 703 &stream->timing, 704 pipe_ctx->pipe_dlg_param.vready_offset, 705 pipe_ctx->pipe_dlg_param.vstartup_start, 706 pipe_ctx->pipe_dlg_param.vupdate_offset, 707 pipe_ctx->pipe_dlg_param.vupdate_width, 708 pipe_ctx->stream->signal, 709 true); 710 711 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 712 flow_control.flow_ctrl_mode = 0; 713 flow_control.flow_ctrl_cnt0 = 0x80; 714 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt); 715 if (mpc->funcs->set_out_rate_control) { 716 for (i = 0; i < opp_cnt; ++i) { 717 mpc->funcs->set_out_rate_control( 718 mpc, opp_inst[i], 719 true, 720 rate_control_2x_pclk, 721 &flow_control); 722 } 723 } 724 725 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 726 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 727 odm_pipe->stream_res.opp, 728 true); 729 730 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 731 pipe_ctx->stream_res.opp, 732 true); 733 734 hws->funcs.blank_pixel_data(dc, pipe_ctx, true); 735 736 /* VTG is within DCHUB command block. DCFCLK is always on */ 737 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { 738 BREAK_TO_DEBUGGER(); 739 return DC_ERROR_UNEXPECTED; 740 } 741 742 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp); 743 744 params.vertical_total_min = stream->adjust.v_total_min; 745 params.vertical_total_max = stream->adjust.v_total_max; 746 params.vertical_total_mid = stream->adjust.v_total_mid; 747 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num; 748 if (pipe_ctx->stream_res.tg->funcs->set_drr) 749 pipe_ctx->stream_res.tg->funcs->set_drr( 750 pipe_ctx->stream_res.tg, ¶ms); 751 752 // DRR should set trigger event to monitor surface update event 753 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 754 event_triggers = 0x80; 755 /* Event triggers and num frames initialized for DRR, but can be 756 * later updated for PSR use. Note DRR trigger events are generated 757 * regardless of whether num frames met. 758 */ 759 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 760 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 761 pipe_ctx->stream_res.tg, event_triggers, 2); 762 763 /* TODO program crtc source select for non-virtual signal*/ 764 /* TODO program FMT */ 765 /* TODO setup link_enc */ 766 /* TODO set stream attributes */ 767 /* TODO program audio */ 768 /* TODO enable stream if timing changed */ 769 /* TODO unblank stream if DP */ 770 771 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) { 772 if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable) 773 pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg); 774 } 775 return DC_OK; 776 } 777 778 void dcn20_program_output_csc(struct dc *dc, 779 struct pipe_ctx *pipe_ctx, 780 enum dc_color_space colorspace, 781 uint16_t *matrix, 782 int opp_id) 783 { 784 struct mpc *mpc = dc->res_pool->mpc; 785 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; 786 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 787 788 if (mpc->funcs->power_on_mpc_mem_pwr) 789 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 790 791 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 792 if (mpc->funcs->set_output_csc != NULL) 793 mpc->funcs->set_output_csc(mpc, 794 opp_id, 795 matrix, 796 ocsc_mode); 797 } else { 798 if (mpc->funcs->set_ocsc_default != NULL) 799 mpc->funcs->set_ocsc_default(mpc, 800 opp_id, 801 colorspace, 802 ocsc_mode); 803 } 804 } 805 806 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 807 const struct dc_stream_state *stream) 808 { 809 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 810 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 811 struct pwl_params *params = NULL; 812 /* 813 * program OGAM only for the top pipe 814 * if there is a pipe split then fix diagnostic is required: 815 * how to pass OGAM parameter for stream. 816 * if programming for all pipes is required then remove condition 817 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic. 818 */ 819 if (mpc->funcs->power_on_mpc_mem_pwr) 820 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 821 if (pipe_ctx->top_pipe == NULL 822 && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 823 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 824 params = &stream->out_transfer_func->pwl; 825 else if (pipe_ctx->stream->out_transfer_func->type == 826 TF_TYPE_DISTRIBUTED_POINTS && 827 cm_helper_translate_curve_to_hw_format( 828 stream->out_transfer_func, 829 &mpc->blender_params, false)) 830 params = &mpc->blender_params; 831 /* 832 * there is no ROM 833 */ 834 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 835 BREAK_TO_DEBUGGER(); 836 } 837 /* 838 * if above if is not executed then 'params' equal to 0 and set in bypass 839 */ 840 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 841 842 return true; 843 } 844 845 bool dcn20_set_blend_lut( 846 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 847 { 848 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 849 bool result = true; 850 struct pwl_params *blend_lut = NULL; 851 852 if (plane_state->blend_tf) { 853 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 854 blend_lut = &plane_state->blend_tf->pwl; 855 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 856 cm_helper_translate_curve_to_hw_format( 857 plane_state->blend_tf, 858 &dpp_base->regamma_params, false); 859 blend_lut = &dpp_base->regamma_params; 860 } 861 } 862 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); 863 864 return result; 865 } 866 867 bool dcn20_set_shaper_3dlut( 868 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 869 { 870 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 871 bool result = true; 872 struct pwl_params *shaper_lut = NULL; 873 874 if (plane_state->in_shaper_func) { 875 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 876 shaper_lut = &plane_state->in_shaper_func->pwl; 877 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 878 cm_helper_translate_curve_to_hw_format( 879 plane_state->in_shaper_func, 880 &dpp_base->shaper_params, true); 881 shaper_lut = &dpp_base->shaper_params; 882 } 883 } 884 885 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); 886 if (plane_state->lut3d_func && 887 plane_state->lut3d_func->state.bits.initialized == 1) 888 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, 889 &plane_state->lut3d_func->lut_3d); 890 else 891 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); 892 893 return result; 894 } 895 896 bool dcn20_set_input_transfer_func(struct dc *dc, 897 struct pipe_ctx *pipe_ctx, 898 const struct dc_plane_state *plane_state) 899 { 900 struct dce_hwseq *hws = dc->hwseq; 901 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 902 const struct dc_transfer_func *tf = NULL; 903 bool result = true; 904 bool use_degamma_ram = false; 905 906 if (dpp_base == NULL || plane_state == NULL) 907 return false; 908 909 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); 910 hws->funcs.set_blend_lut(pipe_ctx, plane_state); 911 912 if (plane_state->in_transfer_func) 913 tf = plane_state->in_transfer_func; 914 915 916 if (tf == NULL) { 917 dpp_base->funcs->dpp_set_degamma(dpp_base, 918 IPP_DEGAMMA_MODE_BYPASS); 919 return true; 920 } 921 922 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS) 923 use_degamma_ram = true; 924 925 if (use_degamma_ram == true) { 926 if (tf->type == TF_TYPE_HWPWL) 927 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 928 &tf->pwl); 929 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 930 cm_helper_translate_curve_to_degamma_hw_format(tf, 931 &dpp_base->degamma_params); 932 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 933 &dpp_base->degamma_params); 934 } 935 return true; 936 } 937 /* handle here the optimized cases when de-gamma ROM could be used. 938 * 939 */ 940 if (tf->type == TF_TYPE_PREDEFINED) { 941 switch (tf->tf) { 942 case TRANSFER_FUNCTION_SRGB: 943 dpp_base->funcs->dpp_set_degamma(dpp_base, 944 IPP_DEGAMMA_MODE_HW_sRGB); 945 break; 946 case TRANSFER_FUNCTION_BT709: 947 dpp_base->funcs->dpp_set_degamma(dpp_base, 948 IPP_DEGAMMA_MODE_HW_xvYCC); 949 break; 950 case TRANSFER_FUNCTION_LINEAR: 951 dpp_base->funcs->dpp_set_degamma(dpp_base, 952 IPP_DEGAMMA_MODE_BYPASS); 953 break; 954 case TRANSFER_FUNCTION_PQ: 955 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL); 956 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params); 957 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params); 958 result = true; 959 break; 960 default: 961 result = false; 962 break; 963 } 964 } else if (tf->type == TF_TYPE_BYPASS) 965 dpp_base->funcs->dpp_set_degamma(dpp_base, 966 IPP_DEGAMMA_MODE_BYPASS); 967 else { 968 /* 969 * if we are here, we did not handle correctly. 970 * fix is required for this use case 971 */ 972 BREAK_TO_DEBUGGER(); 973 dpp_base->funcs->dpp_set_degamma(dpp_base, 974 IPP_DEGAMMA_MODE_BYPASS); 975 } 976 977 return result; 978 } 979 980 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 981 { 982 struct pipe_ctx *odm_pipe; 983 int opp_cnt = 1; 984 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 985 986 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 987 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 988 opp_cnt++; 989 } 990 991 if (opp_cnt > 1) 992 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 993 pipe_ctx->stream_res.tg, 994 opp_inst, opp_cnt, 995 &pipe_ctx->stream->timing); 996 else 997 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 998 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 999 } 1000 1001 void dcn20_blank_pixel_data( 1002 struct dc *dc, 1003 struct pipe_ctx *pipe_ctx, 1004 bool blank) 1005 { 1006 struct tg_color black_color = {0}; 1007 struct stream_resource *stream_res = &pipe_ctx->stream_res; 1008 struct dc_stream_state *stream = pipe_ctx->stream; 1009 enum dc_color_space color_space = stream->output_color_space; 1010 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; 1011 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; 1012 struct pipe_ctx *odm_pipe; 1013 int odm_cnt = 1; 1014 1015 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 1016 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; 1017 1018 if (stream->link->test_pattern_enabled) 1019 return; 1020 1021 /* get opp dpg blank color */ 1022 color_space_to_black_color(dc, color_space, &black_color); 1023 1024 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1025 odm_cnt++; 1026 1027 width = width / odm_cnt; 1028 1029 if (blank) { 1030 dc->hwss.set_abm_immediate_disable(pipe_ctx); 1031 1032 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { 1033 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; 1034 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; 1035 } 1036 } else { 1037 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; 1038 } 1039 1040 dc->hwss.set_disp_pattern_generator(dc, 1041 pipe_ctx, 1042 test_pattern, 1043 test_pattern_color_space, 1044 stream->timing.display_color_depth, 1045 &black_color, 1046 width, 1047 height, 1048 0); 1049 1050 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1051 dc->hwss.set_disp_pattern_generator(dc, 1052 odm_pipe, 1053 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ? 1054 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern, 1055 test_pattern_color_space, 1056 stream->timing.display_color_depth, 1057 &black_color, 1058 width, 1059 height, 1060 0); 1061 } 1062 1063 if (!blank) 1064 if (stream_res->abm) { 1065 dc->hwss.set_pipe(pipe_ctx); 1066 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level); 1067 } 1068 } 1069 1070 1071 static void dcn20_power_on_plane( 1072 struct dce_hwseq *hws, 1073 struct pipe_ctx *pipe_ctx) 1074 { 1075 DC_LOGGER_INIT(hws->ctx->logger); 1076 if (REG(DC_IP_REQUEST_CNTL)) { 1077 REG_SET(DC_IP_REQUEST_CNTL, 0, 1078 IP_REQUEST_EN, 1); 1079 1080 if (hws->funcs.dpp_pg_control) 1081 hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); 1082 1083 if (hws->funcs.hubp_pg_control) 1084 hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true); 1085 1086 REG_SET(DC_IP_REQUEST_CNTL, 0, 1087 IP_REQUEST_EN, 0); 1088 DC_LOG_DEBUG( 1089 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst); 1090 } 1091 } 1092 1093 static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx, 1094 struct dc_state *context) 1095 { 1096 //if (dc->debug.sanity_checks) { 1097 // dcn10_verify_allow_pstate_change_high(dc); 1098 //} 1099 dcn20_power_on_plane(dc->hwseq, pipe_ctx); 1100 1101 /* enable DCFCLK current DCHUB */ 1102 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); 1103 1104 /* initialize HUBP on power up */ 1105 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); 1106 1107 /* make sure OPP_PIPE_CLOCK_EN = 1 */ 1108 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 1109 pipe_ctx->stream_res.opp, 1110 true); 1111 1112 /* TODO: enable/disable in dm as per update type. 1113 if (plane_state) { 1114 DC_LOG_DC(dc->ctx->logger, 1115 "Pipe:%d 0x%x: addr hi:0x%x, " 1116 "addr low:0x%x, " 1117 "src: %d, %d, %d," 1118 " %d; dst: %d, %d, %d, %d;\n", 1119 pipe_ctx->pipe_idx, 1120 plane_state, 1121 plane_state->address.grph.addr.high_part, 1122 plane_state->address.grph.addr.low_part, 1123 plane_state->src_rect.x, 1124 plane_state->src_rect.y, 1125 plane_state->src_rect.width, 1126 plane_state->src_rect.height, 1127 plane_state->dst_rect.x, 1128 plane_state->dst_rect.y, 1129 plane_state->dst_rect.width, 1130 plane_state->dst_rect.height); 1131 1132 DC_LOG_DC(dc->ctx->logger, 1133 "Pipe %d: width, height, x, y format:%d\n" 1134 "viewport:%d, %d, %d, %d\n" 1135 "recout: %d, %d, %d, %d\n", 1136 pipe_ctx->pipe_idx, 1137 plane_state->format, 1138 pipe_ctx->plane_res.scl_data.viewport.width, 1139 pipe_ctx->plane_res.scl_data.viewport.height, 1140 pipe_ctx->plane_res.scl_data.viewport.x, 1141 pipe_ctx->plane_res.scl_data.viewport.y, 1142 pipe_ctx->plane_res.scl_data.recout.width, 1143 pipe_ctx->plane_res.scl_data.recout.height, 1144 pipe_ctx->plane_res.scl_data.recout.x, 1145 pipe_ctx->plane_res.scl_data.recout.y); 1146 print_rq_dlg_ttu(dc, pipe_ctx); 1147 } 1148 */ 1149 if (dc->vm_pa_config.valid) { 1150 struct vm_system_aperture_param apt; 1151 1152 apt.sys_default.quad_part = 0; 1153 1154 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr; 1155 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr; 1156 1157 // Program system aperture settings 1158 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); 1159 } 1160 1161 if (!pipe_ctx->top_pipe 1162 && pipe_ctx->plane_state 1163 && pipe_ctx->plane_state->flip_int_enabled 1164 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) 1165 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); 1166 1167 // if (dc->debug.sanity_checks) { 1168 // dcn10_verify_allow_pstate_change_high(dc); 1169 // } 1170 } 1171 1172 void dcn20_pipe_control_lock( 1173 struct dc *dc, 1174 struct pipe_ctx *pipe, 1175 bool lock) 1176 { 1177 struct pipe_ctx *temp_pipe; 1178 bool flip_immediate = false; 1179 1180 /* use TG master update lock to lock everything on the TG 1181 * therefore only top pipe need to lock 1182 */ 1183 if (!pipe || pipe->top_pipe) 1184 return; 1185 1186 if (pipe->plane_state != NULL) 1187 flip_immediate = pipe->plane_state->flip_immediate; 1188 1189 if (pipe->stream_res.gsl_group > 0) { 1190 temp_pipe = pipe->bottom_pipe; 1191 while (!flip_immediate && temp_pipe) { 1192 if (temp_pipe->plane_state != NULL) 1193 flip_immediate = temp_pipe->plane_state->flip_immediate; 1194 temp_pipe = temp_pipe->bottom_pipe; 1195 } 1196 } 1197 1198 if (flip_immediate && lock) { 1199 const int TIMEOUT_FOR_FLIP_PENDING = 100000; 1200 int i; 1201 1202 temp_pipe = pipe; 1203 while (temp_pipe) { 1204 if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) { 1205 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) { 1206 if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp)) 1207 break; 1208 udelay(1); 1209 } 1210 1211 /* no reason it should take this long for immediate flips */ 1212 ASSERT(i != TIMEOUT_FOR_FLIP_PENDING); 1213 } 1214 temp_pipe = temp_pipe->bottom_pipe; 1215 } 1216 } 1217 1218 /* In flip immediate and pipe splitting case, we need to use GSL 1219 * for synchronization. Only do setup on locking and on flip type change. 1220 */ 1221 if (lock && (pipe->bottom_pipe != NULL || !flip_immediate)) 1222 if ((flip_immediate && pipe->stream_res.gsl_group == 0) || 1223 (!flip_immediate && pipe->stream_res.gsl_group > 0)) 1224 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate); 1225 1226 if (pipe->plane_state != NULL) 1227 flip_immediate = pipe->plane_state->flip_immediate; 1228 1229 temp_pipe = pipe->bottom_pipe; 1230 while (flip_immediate && temp_pipe) { 1231 if (temp_pipe->plane_state != NULL) 1232 flip_immediate = temp_pipe->plane_state->flip_immediate; 1233 temp_pipe = temp_pipe->bottom_pipe; 1234 } 1235 1236 if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state && 1237 !flip_immediate) 1238 dcn20_setup_gsl_group_as_lock(dc, pipe, false); 1239 1240 if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) { 1241 union dmub_hw_lock_flags hw_locks = { 0 }; 1242 struct dmub_hw_lock_inst_flags inst_flags = { 0 }; 1243 1244 hw_locks.bits.lock_pipe = 1; 1245 inst_flags.otg_inst = pipe->stream_res.tg->inst; 1246 1247 if (pipe->plane_state != NULL) 1248 hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips; 1249 1250 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, 1251 lock, 1252 &hw_locks, 1253 &inst_flags); 1254 } else if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 1255 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; 1256 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; 1257 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; 1258 hw_lock_cmd.bits.lock_pipe = 1; 1259 hw_lock_cmd.bits.otg_inst = pipe->stream_res.tg->inst; 1260 hw_lock_cmd.bits.lock = lock; 1261 if (!lock) 1262 hw_lock_cmd.bits.should_release = 1; 1263 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); 1264 } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) { 1265 if (lock) 1266 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); 1267 else 1268 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); 1269 } else { 1270 if (lock) 1271 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1272 else 1273 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1274 } 1275 } 1276 1277 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe) 1278 { 1279 new_pipe->update_flags.raw = 0; 1280 1281 /* Exit on unchanged, unused pipe */ 1282 if (!old_pipe->plane_state && !new_pipe->plane_state) 1283 return; 1284 /* Detect pipe enable/disable */ 1285 if (!old_pipe->plane_state && new_pipe->plane_state) { 1286 new_pipe->update_flags.bits.enable = 1; 1287 new_pipe->update_flags.bits.mpcc = 1; 1288 new_pipe->update_flags.bits.dppclk = 1; 1289 new_pipe->update_flags.bits.hubp_interdependent = 1; 1290 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1291 new_pipe->update_flags.bits.gamut_remap = 1; 1292 new_pipe->update_flags.bits.scaler = 1; 1293 new_pipe->update_flags.bits.viewport = 1; 1294 new_pipe->update_flags.bits.det_size = 1; 1295 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1296 new_pipe->update_flags.bits.odm = 1; 1297 new_pipe->update_flags.bits.global_sync = 1; 1298 } 1299 return; 1300 } 1301 if (old_pipe->plane_state && !new_pipe->plane_state) { 1302 new_pipe->update_flags.bits.disable = 1; 1303 return; 1304 } 1305 1306 /* Detect plane change */ 1307 if (old_pipe->plane_state != new_pipe->plane_state) { 1308 new_pipe->update_flags.bits.plane_changed = true; 1309 } 1310 1311 /* Detect top pipe only changes */ 1312 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1313 /* Detect odm changes */ 1314 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe 1315 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx) 1316 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe) 1317 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe) 1318 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1319 new_pipe->update_flags.bits.odm = 1; 1320 1321 /* Detect global sync changes */ 1322 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset 1323 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start 1324 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset 1325 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) 1326 new_pipe->update_flags.bits.global_sync = 1; 1327 } 1328 1329 if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb) 1330 new_pipe->update_flags.bits.det_size = 1; 1331 1332 /* 1333 * Detect opp / tg change, only set on change, not on enable 1334 * Assume mpcc inst = pipe index, if not this code needs to be updated 1335 * since mpcc is what is affected by these. In fact all of our sequence 1336 * makes this assumption at the moment with how hubp reset is matched to 1337 * same index mpcc reset. 1338 */ 1339 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1340 new_pipe->update_flags.bits.opp_changed = 1; 1341 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg) 1342 new_pipe->update_flags.bits.tg_changed = 1; 1343 1344 /* 1345 * Detect mpcc blending changes, only dpp inst and opp matter here, 1346 * mpccs getting removed/inserted update connected ones during their own 1347 * programming 1348 */ 1349 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp 1350 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1351 new_pipe->update_flags.bits.mpcc = 1; 1352 1353 /* Detect dppclk change */ 1354 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) 1355 new_pipe->update_flags.bits.dppclk = 1; 1356 1357 /* Check for scl update */ 1358 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data))) 1359 new_pipe->update_flags.bits.scaler = 1; 1360 /* Check for vp update */ 1361 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect)) 1362 || memcmp(&old_pipe->plane_res.scl_data.viewport_c, 1363 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect))) 1364 new_pipe->update_flags.bits.viewport = 1; 1365 1366 /* Detect dlg/ttu/rq updates */ 1367 { 1368 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs; 1369 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs; 1370 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs; 1371 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs; 1372 1373 /* Detect pipe interdependent updates */ 1374 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch || 1375 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch || 1376 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c || 1377 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank || 1378 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank || 1379 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip || 1380 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip || 1381 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l || 1382 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c || 1383 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l || 1384 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l || 1385 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c || 1386 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l || 1387 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c || 1388 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 || 1389 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 || 1390 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank || 1391 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) { 1392 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch; 1393 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch; 1394 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c; 1395 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank; 1396 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank; 1397 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip; 1398 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip; 1399 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l; 1400 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c; 1401 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l; 1402 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l; 1403 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c; 1404 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l; 1405 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c; 1406 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0; 1407 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1; 1408 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank; 1409 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip; 1410 new_pipe->update_flags.bits.hubp_interdependent = 1; 1411 } 1412 /* Detect any other updates to ttu/rq/dlg */ 1413 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) || 1414 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) || 1415 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs))) 1416 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1417 } 1418 } 1419 1420 static void dcn20_update_dchubp_dpp( 1421 struct dc *dc, 1422 struct pipe_ctx *pipe_ctx, 1423 struct dc_state *context) 1424 { 1425 struct dce_hwseq *hws = dc->hwseq; 1426 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1427 struct dpp *dpp = pipe_ctx->plane_res.dpp; 1428 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1429 bool viewport_changed = false; 1430 1431 if (pipe_ctx->update_flags.bits.dppclk) 1432 dpp->funcs->dpp_dppclk_control(dpp, false, true); 1433 1434 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG 1435 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. 1436 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG 1437 */ 1438 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) { 1439 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst); 1440 1441 hubp->funcs->hubp_setup( 1442 hubp, 1443 &pipe_ctx->dlg_regs, 1444 &pipe_ctx->ttu_regs, 1445 &pipe_ctx->rq_regs, 1446 &pipe_ctx->pipe_dlg_param); 1447 1448 if (hubp->funcs->set_unbounded_requesting) 1449 hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req); 1450 } 1451 if (pipe_ctx->update_flags.bits.hubp_interdependent) 1452 hubp->funcs->hubp_setup_interdependent( 1453 hubp, 1454 &pipe_ctx->dlg_regs, 1455 &pipe_ctx->ttu_regs); 1456 1457 if (pipe_ctx->update_flags.bits.enable || 1458 pipe_ctx->update_flags.bits.plane_changed || 1459 plane_state->update_flags.bits.bpp_change || 1460 plane_state->update_flags.bits.input_csc_change || 1461 plane_state->update_flags.bits.color_space_change || 1462 plane_state->update_flags.bits.coeff_reduction_change) { 1463 struct dc_bias_and_scale bns_params = {0}; 1464 1465 // program the input csc 1466 dpp->funcs->dpp_setup(dpp, 1467 plane_state->format, 1468 EXPANSION_MODE_ZERO, 1469 plane_state->input_csc_color_matrix, 1470 plane_state->color_space, 1471 NULL); 1472 1473 if (dpp->funcs->dpp_program_bias_and_scale) { 1474 //TODO :for CNVC set scale and bias registers if necessary 1475 build_prescale_params(&bns_params, plane_state); 1476 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); 1477 } 1478 } 1479 1480 if (pipe_ctx->update_flags.bits.mpcc 1481 || pipe_ctx->update_flags.bits.plane_changed 1482 || plane_state->update_flags.bits.global_alpha_change 1483 || plane_state->update_flags.bits.per_pixel_alpha_change) { 1484 // MPCC inst is equal to pipe index in practice 1485 int mpcc_inst = hubp->inst; 1486 int opp_inst; 1487 int opp_count = dc->res_pool->pipe_count; 1488 1489 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) { 1490 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) { 1491 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); 1492 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; 1493 break; 1494 } 1495 } 1496 hws->funcs.update_mpcc(dc, pipe_ctx); 1497 } 1498 1499 if (pipe_ctx->update_flags.bits.scaler || 1500 plane_state->update_flags.bits.scaling_change || 1501 plane_state->update_flags.bits.position_change || 1502 plane_state->update_flags.bits.per_pixel_alpha_change || 1503 pipe_ctx->stream->update_flags.bits.scaling) { 1504 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; 1505 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP); 1506 /* scaler configuration */ 1507 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( 1508 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); 1509 } 1510 1511 if (pipe_ctx->update_flags.bits.viewport || 1512 (context == dc->current_state && plane_state->update_flags.bits.position_change) || 1513 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) || 1514 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) { 1515 1516 hubp->funcs->mem_program_viewport( 1517 hubp, 1518 &pipe_ctx->plane_res.scl_data.viewport, 1519 &pipe_ctx->plane_res.scl_data.viewport_c); 1520 viewport_changed = true; 1521 } 1522 1523 /* Any updates are handled in dc interface, just need to apply existing for plane enable */ 1524 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || 1525 pipe_ctx->update_flags.bits.scaler || viewport_changed == true) && 1526 pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { 1527 dc->hwss.set_cursor_position(pipe_ctx); 1528 dc->hwss.set_cursor_attribute(pipe_ctx); 1529 1530 if (dc->hwss.set_cursor_sdr_white_level) 1531 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 1532 } 1533 1534 /* Any updates are handled in dc interface, just need 1535 * to apply existing for plane enable / opp change */ 1536 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed 1537 || pipe_ctx->stream->update_flags.bits.gamut_remap 1538 || pipe_ctx->stream->update_flags.bits.out_csc) { 1539 /* dpp/cm gamut remap*/ 1540 dc->hwss.program_gamut_remap(pipe_ctx); 1541 1542 /*call the dcn2 method which uses mpc csc*/ 1543 dc->hwss.program_output_csc(dc, 1544 pipe_ctx, 1545 pipe_ctx->stream->output_color_space, 1546 pipe_ctx->stream->csc_color_matrix.matrix, 1547 hubp->opp_id); 1548 } 1549 1550 if (pipe_ctx->update_flags.bits.enable || 1551 pipe_ctx->update_flags.bits.plane_changed || 1552 pipe_ctx->update_flags.bits.opp_changed || 1553 plane_state->update_flags.bits.pixel_format_change || 1554 plane_state->update_flags.bits.horizontal_mirror_change || 1555 plane_state->update_flags.bits.rotation_change || 1556 plane_state->update_flags.bits.swizzle_change || 1557 plane_state->update_flags.bits.dcc_change || 1558 plane_state->update_flags.bits.bpp_change || 1559 plane_state->update_flags.bits.scaling_change || 1560 plane_state->update_flags.bits.plane_size_change) { 1561 struct plane_size size = plane_state->plane_size; 1562 1563 size.surface_size = pipe_ctx->plane_res.scl_data.viewport; 1564 hubp->funcs->hubp_program_surface_config( 1565 hubp, 1566 plane_state->format, 1567 &plane_state->tiling_info, 1568 &size, 1569 plane_state->rotation, 1570 &plane_state->dcc, 1571 plane_state->horizontal_mirror, 1572 0); 1573 hubp->power_gated = false; 1574 } 1575 1576 if (pipe_ctx->update_flags.bits.enable || 1577 pipe_ctx->update_flags.bits.plane_changed || 1578 plane_state->update_flags.bits.addr_update) 1579 hws->funcs.update_plane_addr(dc, pipe_ctx); 1580 1581 if (pipe_ctx->update_flags.bits.enable) 1582 hubp->funcs->set_blank(hubp, false); 1583 /* If the stream paired with this plane is phantom, the plane is also phantom */ 1584 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM 1585 && hubp->funcs->phantom_hubp_post_enable) 1586 hubp->funcs->phantom_hubp_post_enable(hubp); 1587 } 1588 1589 1590 static void dcn20_program_pipe( 1591 struct dc *dc, 1592 struct pipe_ctx *pipe_ctx, 1593 struct dc_state *context) 1594 { 1595 struct dce_hwseq *hws = dc->hwseq; 1596 /* Only need to unblank on top pipe */ 1597 1598 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level) 1599 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) 1600 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible); 1601 1602 /* Only update TG on top pipe */ 1603 if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe 1604 && !pipe_ctx->prev_odm_pipe) { 1605 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1606 pipe_ctx->stream_res.tg, 1607 pipe_ctx->pipe_dlg_param.vready_offset, 1608 pipe_ctx->pipe_dlg_param.vstartup_start, 1609 pipe_ctx->pipe_dlg_param.vupdate_offset, 1610 pipe_ctx->pipe_dlg_param.vupdate_width); 1611 1612 if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1613 pipe_ctx->stream_res.tg->funcs->wait_for_state( 1614 pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); 1615 pipe_ctx->stream_res.tg->funcs->wait_for_state( 1616 pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); 1617 } 1618 1619 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1620 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true); 1621 1622 if (hws->funcs.setup_vupdate_interrupt) 1623 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1624 } 1625 1626 if (pipe_ctx->update_flags.bits.odm) 1627 hws->funcs.update_odm(dc, context, pipe_ctx); 1628 1629 if (pipe_ctx->update_flags.bits.enable) { 1630 dcn20_enable_plane(dc, pipe_ctx, context); 1631 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes) 1632 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub); 1633 } 1634 1635 if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size) 1636 dc->res_pool->hubbub->funcs->program_det_size( 1637 dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb); 1638 1639 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) 1640 dcn20_update_dchubp_dpp(dc, pipe_ctx, context); 1641 1642 if (pipe_ctx->update_flags.bits.enable 1643 || pipe_ctx->plane_state->update_flags.bits.hdr_mult) 1644 hws->funcs.set_hdr_multiplier(pipe_ctx); 1645 1646 if (pipe_ctx->update_flags.bits.enable || 1647 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 1648 pipe_ctx->plane_state->update_flags.bits.gamma_change) 1649 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 1650 1651 /* dcn10_translate_regamma_to_hw_format takes 750us to finish 1652 * only do gamma programming for powering on, internal memcmp to avoid 1653 * updating on slave planes 1654 */ 1655 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf) 1656 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 1657 1658 /* If the pipe has been enabled or has a different opp, we 1659 * should reprogram the fmt. This deals with cases where 1660 * interation between mpc and odm combine on different streams 1661 * causes a different pipe to be chosen to odm combine with. 1662 */ 1663 if (pipe_ctx->update_flags.bits.enable 1664 || pipe_ctx->update_flags.bits.opp_changed) { 1665 1666 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1667 pipe_ctx->stream_res.opp, 1668 COLOR_SPACE_YCBCR601, 1669 pipe_ctx->stream->timing.display_color_depth, 1670 pipe_ctx->stream->signal); 1671 1672 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1673 pipe_ctx->stream_res.opp, 1674 &pipe_ctx->stream->bit_depth_params, 1675 &pipe_ctx->stream->clamping); 1676 } 1677 } 1678 1679 void dcn20_program_front_end_for_ctx( 1680 struct dc *dc, 1681 struct dc_state *context) 1682 { 1683 int i; 1684 struct dce_hwseq *hws = dc->hwseq; 1685 DC_LOGGER_INIT(dc->ctx->logger); 1686 1687 /* Carry over GSL groups in case the context is changing. */ 1688 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1689 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1690 struct pipe_ctx *old_pipe_ctx = 1691 &dc->current_state->res_ctx.pipe_ctx[i]; 1692 1693 if (pipe_ctx->stream == old_pipe_ctx->stream) 1694 pipe_ctx->stream_res.gsl_group = 1695 old_pipe_ctx->stream_res.gsl_group; 1696 } 1697 1698 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) { 1699 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1700 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1701 1702 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) { 1703 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips); 1704 /*turn off triple buffer for full update*/ 1705 dc->hwss.program_triplebuffer( 1706 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); 1707 } 1708 } 1709 } 1710 1711 /* Set pipe update flags and lock pipes */ 1712 for (i = 0; i < dc->res_pool->pipe_count; i++) 1713 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i], 1714 &context->res_ctx.pipe_ctx[i]); 1715 1716 /* OTG blank before disabling all front ends */ 1717 for (i = 0; i < dc->res_pool->pipe_count; i++) 1718 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1719 && !context->res_ctx.pipe_ctx[i].top_pipe 1720 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe 1721 && context->res_ctx.pipe_ctx[i].stream) 1722 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); 1723 1724 1725 /* Disconnect mpcc */ 1726 for (i = 0; i < dc->res_pool->pipe_count; i++) 1727 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1728 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) { 1729 struct hubbub *hubbub = dc->res_pool->hubbub; 1730 1731 if (hubbub->funcs->program_det_size && context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1732 hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0); 1733 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1734 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); 1735 } 1736 1737 /* 1738 * Program all updated pipes, order matters for mpcc setup. Start with 1739 * top pipe and program all pipes that follow in order 1740 */ 1741 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1742 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1743 1744 if (pipe->plane_state && !pipe->top_pipe) { 1745 while (pipe) { 1746 if (hws->funcs.program_pipe) 1747 hws->funcs.program_pipe(dc, pipe, context); 1748 else 1749 dcn20_program_pipe(dc, pipe, context); 1750 1751 pipe = pipe->bottom_pipe; 1752 } 1753 } 1754 /* Program secondary blending tree and writeback pipes */ 1755 pipe = &context->res_ctx.pipe_ctx[i]; 1756 if (!pipe->top_pipe && !pipe->prev_odm_pipe 1757 && pipe->stream && pipe->stream->num_wb_info > 0 1758 && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw) 1759 || pipe->stream->update_flags.raw) 1760 && hws->funcs.program_all_writeback_pipes_in_tree) 1761 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context); 1762 1763 /* Avoid underflow by check of pipe line read when adding 2nd plane. */ 1764 if (hws->wa.wait_hubpret_read_start_during_mpo_transition && 1765 !pipe->top_pipe && 1766 pipe->stream && 1767 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start && 1768 dc->current_state->stream_status[0].plane_count == 1 && 1769 context->stream_status[0].plane_count > 1) { 1770 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp); 1771 } 1772 } 1773 if (hws->funcs.program_mall_pipe_config) 1774 hws->funcs.program_mall_pipe_config(dc, context); 1775 } 1776 1777 void dcn20_post_unlock_program_front_end( 1778 struct dc *dc, 1779 struct dc_state *context) 1780 { 1781 int i; 1782 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100; 1783 struct dce_hwseq *hwseq = dc->hwseq; 1784 1785 DC_LOGGER_INIT(dc->ctx->logger); 1786 1787 for (i = 0; i < dc->res_pool->pipe_count; i++) 1788 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1789 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1790 1791 /* 1792 * If we are enabling a pipe, we need to wait for pending clear as this is a critical 1793 * part of the enable operation otherwise, DM may request an immediate flip which 1794 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which 1795 * is unsupported on DCN. 1796 */ 1797 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1798 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1799 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable) { 1800 struct hubp *hubp = pipe->plane_res.hubp; 1801 int j = 0; 1802 1803 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000 1804 && hubp->funcs->hubp_is_flip_pending(hubp); j++) 1805 mdelay(1); 1806 } 1807 } 1808 1809 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1810 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1811 struct pipe_ctx *mpcc_pipe; 1812 1813 if (pipe->vtp_locked) { 1814 dc->hwseq->funcs.wait_for_blank_complete(pipe->stream_res.opp); 1815 pipe->plane_res.hubp->funcs->set_blank(pipe->plane_res.hubp, true); 1816 pipe->vtp_locked = false; 1817 1818 for (mpcc_pipe = pipe->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe) 1819 mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true); 1820 1821 for (i = 0; i < dc->res_pool->pipe_count; i++) 1822 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1823 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1824 } 1825 } 1826 /* WA to apply WM setting*/ 1827 if (hwseq->wa.DEGVIDCN21) 1828 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub); 1829 1830 1831 /* WA for stutter underflow during MPO transitions when adding 2nd plane */ 1832 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) { 1833 1834 if (dc->current_state->stream_status[0].plane_count == 1 && 1835 context->stream_status[0].plane_count > 1) { 1836 1837 struct timing_generator *tg = dc->res_pool->timing_generators[0]; 1838 1839 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false); 1840 1841 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true; 1842 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg); 1843 } 1844 } 1845 } 1846 1847 void dcn20_prepare_bandwidth( 1848 struct dc *dc, 1849 struct dc_state *context) 1850 { 1851 struct hubbub *hubbub = dc->res_pool->hubbub; 1852 unsigned int compbuf_size_kb = 0; 1853 1854 dc->clk_mgr->funcs->update_clocks( 1855 dc->clk_mgr, 1856 context, 1857 false); 1858 1859 /* program dchubbub watermarks */ 1860 dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub, 1861 &context->bw_ctx.bw.dcn.watermarks, 1862 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1863 false); 1864 1865 /* decrease compbuf size */ 1866 if (hubbub->funcs->program_compbuf_size) { 1867 if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes) 1868 compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes; 1869 else 1870 compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb; 1871 1872 hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false); 1873 } 1874 } 1875 1876 void dcn20_optimize_bandwidth( 1877 struct dc *dc, 1878 struct dc_state *context) 1879 { 1880 struct hubbub *hubbub = dc->res_pool->hubbub; 1881 int i; 1882 1883 /* program dchubbub watermarks */ 1884 hubbub->funcs->program_watermarks(hubbub, 1885 &context->bw_ctx.bw.dcn.watermarks, 1886 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1887 true); 1888 1889 if (dc->clk_mgr->dc_mode_softmax_enabled) 1890 if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && 1891 context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) 1892 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk); 1893 1894 dc->clk_mgr->funcs->update_clocks( 1895 dc->clk_mgr, 1896 context, 1897 true); 1898 if (dc_extended_blank_supported(dc) && context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) { 1899 for (i = 0; i < dc->res_pool->pipe_count; ++i) { 1900 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1901 1902 if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank 1903 && pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max 1904 && pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total) 1905 pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp, 1906 pipe_ctx->dlg_regs.optimized_min_dst_y_next_start); 1907 } 1908 } 1909 /* increase compbuf size */ 1910 if (hubbub->funcs->program_compbuf_size) 1911 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true); 1912 } 1913 1914 bool dcn20_update_bandwidth( 1915 struct dc *dc, 1916 struct dc_state *context) 1917 { 1918 int i; 1919 struct dce_hwseq *hws = dc->hwseq; 1920 1921 /* recalculate DML parameters */ 1922 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) 1923 return false; 1924 1925 /* apply updated bandwidth parameters */ 1926 dc->hwss.prepare_bandwidth(dc, context); 1927 1928 /* update hubp configs for all pipes */ 1929 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1930 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1931 1932 if (pipe_ctx->plane_state == NULL) 1933 continue; 1934 1935 if (pipe_ctx->top_pipe == NULL) { 1936 bool blank = !is_pipe_tree_visible(pipe_ctx); 1937 1938 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1939 pipe_ctx->stream_res.tg, 1940 pipe_ctx->pipe_dlg_param.vready_offset, 1941 pipe_ctx->pipe_dlg_param.vstartup_start, 1942 pipe_ctx->pipe_dlg_param.vupdate_offset, 1943 pipe_ctx->pipe_dlg_param.vupdate_width); 1944 1945 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1946 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false); 1947 1948 if (pipe_ctx->prev_odm_pipe == NULL) 1949 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank); 1950 1951 if (hws->funcs.setup_vupdate_interrupt) 1952 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1953 } 1954 1955 pipe_ctx->plane_res.hubp->funcs->hubp_setup( 1956 pipe_ctx->plane_res.hubp, 1957 &pipe_ctx->dlg_regs, 1958 &pipe_ctx->ttu_regs, 1959 &pipe_ctx->rq_regs, 1960 &pipe_ctx->pipe_dlg_param); 1961 } 1962 1963 return true; 1964 } 1965 1966 void dcn20_enable_writeback( 1967 struct dc *dc, 1968 struct dc_writeback_info *wb_info, 1969 struct dc_state *context) 1970 { 1971 struct dwbc *dwb; 1972 struct mcif_wb *mcif_wb; 1973 struct timing_generator *optc; 1974 1975 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 1976 ASSERT(wb_info->wb_enabled); 1977 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 1978 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 1979 1980 /* set the OPTC source mux */ 1981 optc = dc->res_pool->timing_generators[dwb->otg_inst]; 1982 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); 1983 /* set MCIF_WB buffer and arbitration configuration */ 1984 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 1985 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 1986 /* Enable MCIF_WB */ 1987 mcif_wb->funcs->enable_mcif(mcif_wb); 1988 /* Enable DWB */ 1989 dwb->funcs->enable(dwb, &wb_info->dwb_params); 1990 /* TODO: add sequence to enable/disable warmup */ 1991 } 1992 1993 void dcn20_disable_writeback( 1994 struct dc *dc, 1995 unsigned int dwb_pipe_inst) 1996 { 1997 struct dwbc *dwb; 1998 struct mcif_wb *mcif_wb; 1999 2000 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); 2001 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; 2002 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; 2003 2004 dwb->funcs->disable(dwb); 2005 mcif_wb->funcs->disable_mcif(mcif_wb); 2006 } 2007 2008 bool dcn20_wait_for_blank_complete( 2009 struct output_pixel_processor *opp) 2010 { 2011 int counter; 2012 2013 for (counter = 0; counter < 1000; counter++) { 2014 if (opp->funcs->dpg_is_blanked(opp)) 2015 break; 2016 2017 udelay(100); 2018 } 2019 2020 if (counter == 1000) { 2021 dm_error("DC: failed to blank crtc!\n"); 2022 return false; 2023 } 2024 2025 return true; 2026 } 2027 2028 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) 2029 { 2030 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2031 2032 if (!hubp) 2033 return false; 2034 return hubp->funcs->dmdata_status_done(hubp); 2035 } 2036 2037 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 2038 { 2039 struct dce_hwseq *hws = dc->hwseq; 2040 2041 if (pipe_ctx->stream_res.dsc) { 2042 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2043 2044 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); 2045 while (odm_pipe) { 2046 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true); 2047 odm_pipe = odm_pipe->next_odm_pipe; 2048 } 2049 } 2050 } 2051 2052 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 2053 { 2054 struct dce_hwseq *hws = dc->hwseq; 2055 2056 if (pipe_ctx->stream_res.dsc) { 2057 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2058 2059 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false); 2060 while (odm_pipe) { 2061 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false); 2062 odm_pipe = odm_pipe->next_odm_pipe; 2063 } 2064 } 2065 } 2066 2067 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) 2068 { 2069 struct dc_dmdata_attributes attr = { 0 }; 2070 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2071 2072 attr.dmdata_mode = DMDATA_HW_MODE; 2073 attr.dmdata_size = 2074 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; 2075 attr.address.quad_part = 2076 pipe_ctx->stream->dmdata_address.quad_part; 2077 attr.dmdata_dl_delta = 0; 2078 attr.dmdata_qos_mode = 0; 2079 attr.dmdata_qos_level = 0; 2080 attr.dmdata_repeat = 1; /* always repeat */ 2081 attr.dmdata_updated = 1; 2082 attr.dmdata_sw_data = NULL; 2083 2084 hubp->funcs->dmdata_set_attributes(hubp, &attr); 2085 } 2086 2087 void dcn20_init_vm_ctx( 2088 struct dce_hwseq *hws, 2089 struct dc *dc, 2090 struct dc_virtual_addr_space_config *va_config, 2091 int vmid) 2092 { 2093 struct dcn_hubbub_virt_addr_config config; 2094 2095 if (vmid == 0) { 2096 ASSERT(0); /* VMID cannot be 0 for vm context */ 2097 return; 2098 } 2099 2100 config.page_table_start_addr = va_config->page_table_start_addr; 2101 config.page_table_end_addr = va_config->page_table_end_addr; 2102 config.page_table_block_size = va_config->page_table_block_size_in_bytes; 2103 config.page_table_depth = va_config->page_table_depth; 2104 config.page_table_base_addr = va_config->page_table_base_addr; 2105 2106 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); 2107 } 2108 2109 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 2110 { 2111 struct dcn_hubbub_phys_addr_config config; 2112 2113 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 2114 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 2115 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 2116 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 2117 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 2118 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 2119 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 2120 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 2121 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 2122 config.page_table_default_page_addr = pa_config->page_table_default_page_addr; 2123 2124 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 2125 } 2126 2127 static bool patch_address_for_sbs_tb_stereo( 2128 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) 2129 { 2130 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2131 bool sec_split = pipe_ctx->top_pipe && 2132 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; 2133 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && 2134 (pipe_ctx->stream->timing.timing_3d_format == 2135 TIMING_3D_FORMAT_SIDE_BY_SIDE || 2136 pipe_ctx->stream->timing.timing_3d_format == 2137 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { 2138 *addr = plane_state->address.grph_stereo.left_addr; 2139 plane_state->address.grph_stereo.left_addr = 2140 plane_state->address.grph_stereo.right_addr; 2141 return true; 2142 } 2143 2144 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && 2145 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { 2146 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; 2147 plane_state->address.grph_stereo.right_addr = 2148 plane_state->address.grph_stereo.left_addr; 2149 plane_state->address.grph_stereo.right_meta_addr = 2150 plane_state->address.grph_stereo.left_meta_addr; 2151 } 2152 return false; 2153 } 2154 2155 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) 2156 { 2157 bool addr_patched = false; 2158 PHYSICAL_ADDRESS_LOC addr; 2159 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2160 2161 if (plane_state == NULL) 2162 return; 2163 2164 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); 2165 2166 // Call Helper to track VMID use 2167 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); 2168 2169 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( 2170 pipe_ctx->plane_res.hubp, 2171 &plane_state->address, 2172 plane_state->flip_immediate); 2173 2174 plane_state->status.requested_address = plane_state->address; 2175 2176 if (plane_state->flip_immediate) 2177 plane_state->status.current_address = plane_state->address; 2178 2179 if (addr_patched) 2180 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; 2181 } 2182 2183 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, 2184 struct dc_link_settings *link_settings) 2185 { 2186 struct encoder_unblank_param params = {0}; 2187 struct dc_stream_state *stream = pipe_ctx->stream; 2188 struct dc_link *link = stream->link; 2189 struct dce_hwseq *hws = link->dc->hwseq; 2190 struct pipe_ctx *odm_pipe; 2191 2192 params.opp_cnt = 1; 2193 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 2194 params.opp_cnt++; 2195 } 2196 /* only 3 items below are used by unblank */ 2197 params.timing = pipe_ctx->stream->timing; 2198 2199 params.link_settings.link_rate = link_settings->link_rate; 2200 2201 if (is_dp_128b_132b_signal(pipe_ctx)) { 2202 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 2203 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 2204 pipe_ctx->stream_res.hpo_dp_stream_enc, 2205 pipe_ctx->stream_res.tg->inst); 2206 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 2207 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1) 2208 params.timing.pix_clk_100hz /= 2; 2209 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 2210 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1); 2211 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 2212 } 2213 2214 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 2215 hws->funcs.edp_backlight_control(link, true); 2216 } 2217 } 2218 2219 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx) 2220 { 2221 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2222 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx); 2223 2224 if (start_line < 0) 2225 start_line = 0; 2226 2227 if (tg->funcs->setup_vertical_interrupt2) 2228 tg->funcs->setup_vertical_interrupt2(tg, start_line); 2229 } 2230 2231 static void dcn20_reset_back_end_for_pipe( 2232 struct dc *dc, 2233 struct pipe_ctx *pipe_ctx, 2234 struct dc_state *context) 2235 { 2236 int i; 2237 struct dc_link *link; 2238 DC_LOGGER_INIT(dc->ctx->logger); 2239 if (pipe_ctx->stream_res.stream_enc == NULL) { 2240 pipe_ctx->stream = NULL; 2241 return; 2242 } 2243 2244 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 2245 link = pipe_ctx->stream->link; 2246 /* DPMS may already disable or */ 2247 /* dpms_off status is incorrect due to fastboot 2248 * feature. When system resume from S4 with second 2249 * screen only, the dpms_off would be true but 2250 * VBIOS lit up eDP, so check link status too. 2251 */ 2252 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 2253 core_link_disable_stream(pipe_ctx); 2254 else if (pipe_ctx->stream_res.audio) 2255 dc->hwss.disable_audio_stream(pipe_ctx); 2256 2257 /* free acquired resources */ 2258 if (pipe_ctx->stream_res.audio) { 2259 /*disable az_endpoint*/ 2260 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 2261 2262 /*free audio*/ 2263 if (dc->caps.dynamic_audio == true) { 2264 /*we have to dynamic arbitrate the audio endpoints*/ 2265 /*we free the resource, need reset is_audio_acquired*/ 2266 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 2267 pipe_ctx->stream_res.audio, false); 2268 pipe_ctx->stream_res.audio = NULL; 2269 } 2270 } 2271 } 2272 else if (pipe_ctx->stream_res.dsc) { 2273 dp_set_dsc_enable(pipe_ctx, false); 2274 } 2275 2276 /* by upper caller loop, parent pipe: pipe0, will be reset last. 2277 * back end share by all pipes and will be disable only when disable 2278 * parent pipe. 2279 */ 2280 if (pipe_ctx->top_pipe == NULL) { 2281 2282 dc->hwss.set_abm_immediate_disable(pipe_ctx); 2283 2284 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 2285 2286 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 2287 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 2288 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 2289 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 2290 2291 if (pipe_ctx->stream_res.tg->funcs->set_drr) 2292 pipe_ctx->stream_res.tg->funcs->set_drr( 2293 pipe_ctx->stream_res.tg, NULL); 2294 } 2295 2296 for (i = 0; i < dc->res_pool->pipe_count; i++) 2297 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) 2298 break; 2299 2300 if (i == dc->res_pool->pipe_count) 2301 return; 2302 2303 pipe_ctx->stream = NULL; 2304 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 2305 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 2306 } 2307 2308 void dcn20_reset_hw_ctx_wrap( 2309 struct dc *dc, 2310 struct dc_state *context) 2311 { 2312 int i; 2313 struct dce_hwseq *hws = dc->hwseq; 2314 2315 /* Reset Back End*/ 2316 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 2317 struct pipe_ctx *pipe_ctx_old = 2318 &dc->current_state->res_ctx.pipe_ctx[i]; 2319 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2320 2321 if (!pipe_ctx_old->stream) 2322 continue; 2323 2324 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 2325 continue; 2326 2327 if (!pipe_ctx->stream || 2328 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 2329 struct clock_source *old_clk = pipe_ctx_old->clock_source; 2330 2331 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 2332 if (hws->funcs.enable_stream_gating) 2333 hws->funcs.enable_stream_gating(dc, pipe_ctx_old); 2334 if (old_clk) 2335 old_clk->funcs->cs_power_down(old_clk); 2336 } 2337 } 2338 } 2339 2340 void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id) 2341 { 2342 struct mpc *mpc = dc->res_pool->mpc; 2343 2344 // input to MPCC is always RGB, by default leave black_color at 0 2345 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) 2346 get_hdr_visual_confirm_color(pipe_ctx, color); 2347 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) 2348 get_surface_visual_confirm_color(pipe_ctx, color); 2349 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) 2350 get_mpctree_visual_confirm_color(pipe_ctx, color); 2351 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE) 2352 get_surface_tile_visual_confirm_color(pipe_ctx, color); 2353 2354 if (mpc->funcs->set_bg_color) 2355 mpc->funcs->set_bg_color(mpc, color, mpcc_id); 2356 } 2357 2358 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 2359 { 2360 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2361 struct mpcc_blnd_cfg blnd_cfg = {0}; 2362 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; 2363 int mpcc_id; 2364 struct mpcc *new_mpcc; 2365 struct mpc *mpc = dc->res_pool->mpc; 2366 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); 2367 2368 blnd_cfg.overlap_only = false; 2369 blnd_cfg.global_gain = 0xff; 2370 2371 if (per_pixel_alpha) { 2372 blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha; 2373 if (pipe_ctx->plane_state->global_alpha) { 2374 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; 2375 blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value; 2376 } else { 2377 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2378 } 2379 } else { 2380 blnd_cfg.pre_multiplied_alpha = false; 2381 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 2382 } 2383 2384 if (pipe_ctx->plane_state->global_alpha) 2385 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; 2386 else 2387 blnd_cfg.global_alpha = 0xff; 2388 2389 blnd_cfg.background_color_bpc = 4; 2390 blnd_cfg.bottom_gain_mode = 0; 2391 blnd_cfg.top_gain = 0x1f000; 2392 blnd_cfg.bottom_inside_gain = 0x1f000; 2393 blnd_cfg.bottom_outside_gain = 0x1f000; 2394 2395 if (pipe_ctx->plane_state->format 2396 == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA) 2397 blnd_cfg.pre_multiplied_alpha = false; 2398 2399 /* 2400 * TODO: remove hack 2401 * Note: currently there is a bug in init_hw such that 2402 * on resume from hibernate, BIOS sets up MPCC0, and 2403 * we do mpcc_remove but the mpcc cannot go to idle 2404 * after remove. This cause us to pick mpcc1 here, 2405 * which causes a pstate hang for yet unknown reason. 2406 */ 2407 mpcc_id = hubp->inst; 2408 2409 /* If there is no full update, don't need to touch MPC tree*/ 2410 if (!pipe_ctx->plane_state->update_flags.bits.full_update && 2411 !pipe_ctx->update_flags.bits.mpcc) { 2412 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); 2413 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); 2414 return; 2415 } 2416 2417 /* check if this MPCC is already being used */ 2418 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 2419 /* remove MPCC if being used */ 2420 if (new_mpcc != NULL) 2421 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); 2422 else 2423 if (dc->debug.sanity_checks) 2424 mpc->funcs->assert_mpcc_idle_before_connect( 2425 dc->res_pool->mpc, mpcc_id); 2426 2427 /* Call MPC to insert new plane */ 2428 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, 2429 mpc_tree_params, 2430 &blnd_cfg, 2431 NULL, 2432 NULL, 2433 hubp->inst, 2434 mpcc_id); 2435 2436 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); 2437 2438 ASSERT(new_mpcc != NULL); 2439 hubp->opp_id = pipe_ctx->stream_res.opp->inst; 2440 hubp->mpcc_id = mpcc_id; 2441 } 2442 2443 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 2444 { 2445 enum dc_lane_count lane_count = 2446 pipe_ctx->stream->link->cur_link_settings.lane_count; 2447 2448 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 2449 struct dc_link *link = pipe_ctx->stream->link; 2450 2451 uint32_t active_total_with_borders; 2452 uint32_t early_control = 0; 2453 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2454 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2455 struct dc *dc = pipe_ctx->stream->ctx->dc; 2456 2457 if (is_dp_128b_132b_signal(pipe_ctx)) { 2458 if (dc->hwseq->funcs.setup_hpo_hw_control) 2459 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, true); 2460 } 2461 2462 link_hwss->setup_stream_encoder(pipe_ctx); 2463 2464 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) { 2465 if (dc->hwss.program_dmdata_engine) 2466 dc->hwss.program_dmdata_engine(pipe_ctx); 2467 } 2468 2469 dc->hwss.update_info_frame(pipe_ctx); 2470 2471 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2472 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2473 2474 /* enable early control to avoid corruption on DP monitor*/ 2475 active_total_with_borders = 2476 timing->h_addressable 2477 + timing->h_border_left 2478 + timing->h_border_right; 2479 2480 if (lane_count != 0) 2481 early_control = active_total_with_borders % lane_count; 2482 2483 if (early_control == 0) 2484 early_control = lane_count; 2485 2486 tg->funcs->set_early_control(tg, early_control); 2487 2488 /* enable audio only within mode set */ 2489 if (pipe_ctx->stream_res.audio != NULL) { 2490 if (is_dp_128b_132b_signal(pipe_ctx)) 2491 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.hpo_dp_stream_enc); 2492 else if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2493 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 2494 } 2495 } 2496 2497 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx) 2498 { 2499 struct dc_stream_state *stream = pipe_ctx->stream; 2500 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2501 bool enable = false; 2502 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2503 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) 2504 ? dmdata_dp 2505 : dmdata_hdmi; 2506 2507 /* if using dynamic meta, don't set up generic infopackets */ 2508 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { 2509 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; 2510 enable = true; 2511 } 2512 2513 if (!hubp) 2514 return; 2515 2516 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) 2517 return; 2518 2519 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, 2520 hubp->inst, mode); 2521 } 2522 2523 void dcn20_fpga_init_hw(struct dc *dc) 2524 { 2525 int i, j; 2526 struct dce_hwseq *hws = dc->hwseq; 2527 struct resource_pool *res_pool = dc->res_pool; 2528 struct dc_state *context = dc->current_state; 2529 2530 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 2531 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 2532 2533 // Initialize the dccg 2534 if (res_pool->dccg->funcs->dccg_init) 2535 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 2536 2537 //Enable ability to power gate / don't force power on permanently 2538 hws->funcs.enable_power_gating_plane(hws, true); 2539 2540 // Specific to FPGA dccg and registers 2541 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); 2542 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 2543 2544 hws->funcs.dccg_init(hws); 2545 2546 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); 2547 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 2548 if (REG(REFCLK_CNTL)) 2549 REG_WRITE(REFCLK_CNTL, 0); 2550 // 2551 2552 2553 /* Blank pixel data with OPP DPG */ 2554 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2555 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2556 2557 if (tg->funcs->is_tg_enabled(tg)) 2558 dcn20_init_blank(dc, tg); 2559 } 2560 2561 for (i = 0; i < res_pool->timing_generator_count; i++) { 2562 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2563 2564 if (tg->funcs->is_tg_enabled(tg)) 2565 tg->funcs->lock(tg); 2566 } 2567 2568 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2569 struct dpp *dpp = res_pool->dpps[i]; 2570 2571 dpp->funcs->dpp_reset(dpp); 2572 } 2573 2574 /* Reset all MPCC muxes */ 2575 res_pool->mpc->funcs->mpc_init(res_pool->mpc); 2576 2577 /* initialize OPP mpc_tree parameter */ 2578 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 2579 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; 2580 res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2581 for (j = 0; j < MAX_PIPES; j++) 2582 res_pool->opps[i]->mpcc_disconnect_pending[j] = false; 2583 } 2584 2585 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2586 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2587 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2588 struct hubp *hubp = dc->res_pool->hubps[i]; 2589 struct dpp *dpp = dc->res_pool->dpps[i]; 2590 2591 pipe_ctx->stream_res.tg = tg; 2592 pipe_ctx->pipe_idx = i; 2593 2594 pipe_ctx->plane_res.hubp = hubp; 2595 pipe_ctx->plane_res.dpp = dpp; 2596 pipe_ctx->plane_res.mpcc_inst = dpp->inst; 2597 hubp->mpcc_id = dpp->inst; 2598 hubp->opp_id = OPP_ID_INVALID; 2599 hubp->power_gated = false; 2600 pipe_ctx->stream_res.opp = NULL; 2601 2602 hubp->funcs->hubp_init(hubp); 2603 2604 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; 2605 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2606 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; 2607 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; 2608 /*to do*/ 2609 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx); 2610 } 2611 2612 /* initialize DWB pointer to MCIF_WB */ 2613 for (i = 0; i < res_pool->res_cap->num_dwb; i++) 2614 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; 2615 2616 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2617 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2618 2619 if (tg->funcs->is_tg_enabled(tg)) 2620 tg->funcs->unlock(tg); 2621 } 2622 2623 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2624 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2625 2626 dc->hwss.disable_plane(dc, pipe_ctx); 2627 2628 pipe_ctx->stream_res.tg = NULL; 2629 pipe_ctx->plane_res.hubp = NULL; 2630 } 2631 2632 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2633 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2634 2635 tg->funcs->tg_init(tg); 2636 } 2637 2638 if (dc->res_pool->hubbub->funcs->init_crb) 2639 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 2640 } 2641 #ifndef TRIM_FSFT 2642 bool dcn20_optimize_timing_for_fsft(struct dc *dc, 2643 struct dc_crtc_timing *timing, 2644 unsigned int max_input_rate_in_khz) 2645 { 2646 unsigned int old_v_front_porch; 2647 unsigned int old_v_total; 2648 unsigned int max_input_rate_in_100hz; 2649 unsigned long long new_v_total; 2650 2651 max_input_rate_in_100hz = max_input_rate_in_khz * 10; 2652 if (max_input_rate_in_100hz < timing->pix_clk_100hz) 2653 return false; 2654 2655 old_v_total = timing->v_total; 2656 old_v_front_porch = timing->v_front_porch; 2657 2658 timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz; 2659 timing->pix_clk_100hz = max_input_rate_in_100hz; 2660 2661 new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz); 2662 2663 timing->v_total = new_v_total; 2664 timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total); 2665 return true; 2666 } 2667 #endif 2668 2669 void dcn20_set_disp_pattern_generator(const struct dc *dc, 2670 struct pipe_ctx *pipe_ctx, 2671 enum controller_dp_test_pattern test_pattern, 2672 enum controller_dp_color_space color_space, 2673 enum dc_color_depth color_depth, 2674 const struct tg_color *solid_color, 2675 int width, int height, int offset) 2676 { 2677 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern, 2678 color_space, color_depth, solid_color, width, height, offset); 2679 } 2680