1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include <linux/delay.h> 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dcn20/dcn20_resource.h" 32 #include "dce110/dce110_hw_sequencer.h" 33 #include "dcn10/dcn10_hw_sequencer.h" 34 #include "dcn20_hwseq.h" 35 #include "dce/dce_hwseq.h" 36 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 37 #include "dcn20/dcn20_dsc.h" 38 #endif 39 #include "abm.h" 40 #include "clk_mgr.h" 41 #include "dmcu.h" 42 #include "hubp.h" 43 #include "timing_generator.h" 44 #include "opp.h" 45 #include "ipp.h" 46 #include "mpc.h" 47 #include "mcif_wb.h" 48 #include "reg_helper.h" 49 #include "dcn10/dcn10_cm_common.h" 50 #include "dcn10/dcn10_hubbub.h" 51 #include "dcn10/dcn10_optc.h" 52 #include "dc_link_dp.h" 53 #include "vm_helper.h" 54 #include "dccg.h" 55 56 #define DC_LOGGER_INIT(logger) 57 58 #define CTX \ 59 hws->ctx 60 #define REG(reg)\ 61 hws->regs->reg 62 63 #undef FN 64 #define FN(reg_name, field_name) \ 65 hws->shifts->field_name, hws->masks->field_name 66 67 static void bios_golden_init(struct dc *dc) 68 { 69 struct dc_bios *bp = dc->ctx->dc_bios; 70 int i; 71 72 /* initialize dcn global */ 73 bp->funcs->enable_disp_power_gating(bp, 74 CONTROLLER_ID_D0, ASIC_PIPE_INIT); 75 76 for (i = 0; i < dc->res_pool->pipe_count; i++) { 77 /* initialize dcn per pipe */ 78 bp->funcs->enable_disp_power_gating(bp, 79 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE); 80 } 81 } 82 83 static void enable_power_gating_plane( 84 struct dce_hwseq *hws, 85 bool enable) 86 { 87 bool force_on = 1; /* disable power gating */ 88 89 if (enable) 90 force_on = 0; 91 92 /* DCHUBP0/1/2/3/4/5 */ 93 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); 94 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); 95 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); 96 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); 97 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 98 /*Do not power gate DCHUB5, should be left at HW default, power on permanently*/ 99 /*REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, force_on);*/ 100 101 /* DPP0/1/2/3/4/5 */ 102 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); 103 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); 104 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); 105 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); 106 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 107 /*Do not power gate DPP5, should be left at HW default, power on permanently*/ 108 /*REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, force_on);*/ 109 110 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on); 111 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on); 112 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on); 113 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on); 114 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on); 115 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); 116 } 117 118 void dcn20_dccg_init(struct dce_hwseq *hws) 119 { 120 /* 121 * set MICROSECOND_TIME_BASE_DIV 122 * 100Mhz refclk -> 0x120264 123 * 27Mhz refclk -> 0x12021b 124 * 48Mhz refclk -> 0x120230 125 * 126 */ 127 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); 128 129 /* 130 * set MILLISECOND_TIME_BASE_DIV 131 * 100Mhz refclk -> 0x1186a0 132 * 27Mhz refclk -> 0x106978 133 * 48Mhz refclk -> 0x10bb80 134 * 135 */ 136 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); 137 138 /* This value is dependent on the hardware pipeline delay so set once per SOC */ 139 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c); 140 } 141 void dcn20_display_init(struct dc *dc) 142 { 143 struct dce_hwseq *hws = dc->hwseq; 144 145 /* RBBMIF 146 * disable RBBMIF timeout detection for all clients 147 * Ensure RBBMIF does not drop register accesses due to the per-client timeout 148 */ 149 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); 150 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 151 152 /* DCCG */ 153 dcn20_dccg_init(hws); 154 155 /* Disable all memory low power mode. All memories are enabled. */ 156 REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 1); 157 158 /* DCHUB/MMHUBBUB 159 * set global timer refclk divider 160 * 100Mhz refclk -> 2 161 * 27Mhz refclk -> 1 162 * 48Mhz refclk -> 1 163 */ 164 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); 165 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 166 REG_WRITE(REFCLK_CNTL, 0); 167 168 /* OPTC 169 * OTG_CONTROL.OTG_DISABLE_POINT_CNTL = 0x3; will be set during optc2_enable_crtc 170 */ 171 172 /* AZ 173 * default value is 0x64 for 100Mhz ref clock, if the ref clock is 100Mhz, no need to program this regiser, 174 * if not, it should be programmed according to the ref clock 175 */ 176 REG_UPDATE(AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, 0x64); 177 /* Enable controller clock gating */ 178 REG_WRITE(AZALIA_CONTROLLER_CLOCK_GATING, 0x1); 179 } 180 181 static void disable_vga( 182 struct dce_hwseq *hws) 183 { 184 REG_WRITE(D1VGA_CONTROL, 0); 185 REG_WRITE(D2VGA_CONTROL, 0); 186 REG_WRITE(D3VGA_CONTROL, 0); 187 REG_WRITE(D4VGA_CONTROL, 0); 188 REG_WRITE(D5VGA_CONTROL, 0); 189 REG_WRITE(D6VGA_CONTROL, 0); 190 } 191 192 void dcn20_program_tripleBuffer( 193 const struct dc *dc, 194 struct pipe_ctx *pipe_ctx, 195 bool enableTripleBuffer) 196 { 197 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { 198 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( 199 pipe_ctx->plane_res.hubp, 200 enableTripleBuffer); 201 } 202 } 203 204 /* Blank pixel data during initialization */ 205 void dcn20_init_blank( 206 struct dc *dc, 207 struct timing_generator *tg) 208 { 209 enum dc_color_space color_space; 210 struct tg_color black_color = {0}; 211 struct output_pixel_processor *opp = NULL; 212 struct output_pixel_processor *bottom_opp = NULL; 213 uint32_t num_opps, opp_id_src0, opp_id_src1; 214 uint32_t otg_active_width, otg_active_height; 215 216 /* program opp dpg blank color */ 217 color_space = COLOR_SPACE_SRGB; 218 color_space_to_black_color(dc, color_space, &black_color); 219 220 /* get the OTG active size */ 221 tg->funcs->get_otg_active_size(tg, 222 &otg_active_width, 223 &otg_active_height); 224 225 /* get the OPTC source */ 226 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 227 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); 228 opp = dc->res_pool->opps[opp_id_src0]; 229 230 if (num_opps == 2) { 231 otg_active_width = otg_active_width / 2; 232 ASSERT(opp_id_src1 < dc->res_pool->res_cap->num_opp); 233 bottom_opp = dc->res_pool->opps[opp_id_src1]; 234 } 235 236 opp->funcs->opp_set_disp_pattern_generator( 237 opp, 238 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 239 COLOR_DEPTH_UNDEFINED, 240 &black_color, 241 otg_active_width, 242 otg_active_height); 243 244 if (num_opps == 2) { 245 bottom_opp->funcs->opp_set_disp_pattern_generator( 246 bottom_opp, 247 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 248 COLOR_DEPTH_UNDEFINED, 249 &black_color, 250 otg_active_width, 251 otg_active_height); 252 } 253 254 dcn20_hwss_wait_for_blank_complete(opp); 255 } 256 257 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 258 static void dcn20_dsc_pg_control( 259 struct dce_hwseq *hws, 260 unsigned int dsc_inst, 261 bool power_on) 262 { 263 uint32_t power_gate = power_on ? 0 : 1; 264 uint32_t pwr_status = power_on ? 0 : 2; 265 uint32_t org_ip_request_cntl = 0; 266 267 if (hws->ctx->dc->debug.disable_dsc_power_gate) 268 return; 269 270 if (REG(DOMAIN16_PG_CONFIG) == 0) 271 return; 272 273 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 274 if (org_ip_request_cntl == 0) 275 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 276 277 switch (dsc_inst) { 278 case 0: /* DSC0 */ 279 REG_UPDATE(DOMAIN16_PG_CONFIG, 280 DOMAIN16_POWER_GATE, power_gate); 281 282 REG_WAIT(DOMAIN16_PG_STATUS, 283 DOMAIN16_PGFSM_PWR_STATUS, pwr_status, 284 1, 1000); 285 break; 286 case 1: /* DSC1 */ 287 REG_UPDATE(DOMAIN17_PG_CONFIG, 288 DOMAIN17_POWER_GATE, power_gate); 289 290 REG_WAIT(DOMAIN17_PG_STATUS, 291 DOMAIN17_PGFSM_PWR_STATUS, pwr_status, 292 1, 1000); 293 break; 294 case 2: /* DSC2 */ 295 REG_UPDATE(DOMAIN18_PG_CONFIG, 296 DOMAIN18_POWER_GATE, power_gate); 297 298 REG_WAIT(DOMAIN18_PG_STATUS, 299 DOMAIN18_PGFSM_PWR_STATUS, pwr_status, 300 1, 1000); 301 break; 302 case 3: /* DSC3 */ 303 REG_UPDATE(DOMAIN19_PG_CONFIG, 304 DOMAIN19_POWER_GATE, power_gate); 305 306 REG_WAIT(DOMAIN19_PG_STATUS, 307 DOMAIN19_PGFSM_PWR_STATUS, pwr_status, 308 1, 1000); 309 break; 310 case 4: /* DSC4 */ 311 REG_UPDATE(DOMAIN20_PG_CONFIG, 312 DOMAIN20_POWER_GATE, power_gate); 313 314 REG_WAIT(DOMAIN20_PG_STATUS, 315 DOMAIN20_PGFSM_PWR_STATUS, pwr_status, 316 1, 1000); 317 break; 318 case 5: /* DSC5 */ 319 REG_UPDATE(DOMAIN21_PG_CONFIG, 320 DOMAIN21_POWER_GATE, power_gate); 321 322 REG_WAIT(DOMAIN21_PG_STATUS, 323 DOMAIN21_PGFSM_PWR_STATUS, pwr_status, 324 1, 1000); 325 break; 326 default: 327 BREAK_TO_DEBUGGER(); 328 break; 329 } 330 331 if (org_ip_request_cntl == 0) 332 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 333 } 334 #endif 335 336 static void dcn20_dpp_pg_control( 337 struct dce_hwseq *hws, 338 unsigned int dpp_inst, 339 bool power_on) 340 { 341 uint32_t power_gate = power_on ? 0 : 1; 342 uint32_t pwr_status = power_on ? 0 : 2; 343 344 if (hws->ctx->dc->debug.disable_dpp_power_gate) 345 return; 346 if (REG(DOMAIN1_PG_CONFIG) == 0) 347 return; 348 349 switch (dpp_inst) { 350 case 0: /* DPP0 */ 351 REG_UPDATE(DOMAIN1_PG_CONFIG, 352 DOMAIN1_POWER_GATE, power_gate); 353 354 REG_WAIT(DOMAIN1_PG_STATUS, 355 DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 356 1, 1000); 357 break; 358 case 1: /* DPP1 */ 359 REG_UPDATE(DOMAIN3_PG_CONFIG, 360 DOMAIN3_POWER_GATE, power_gate); 361 362 REG_WAIT(DOMAIN3_PG_STATUS, 363 DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 364 1, 1000); 365 break; 366 case 2: /* DPP2 */ 367 REG_UPDATE(DOMAIN5_PG_CONFIG, 368 DOMAIN5_POWER_GATE, power_gate); 369 370 REG_WAIT(DOMAIN5_PG_STATUS, 371 DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 372 1, 1000); 373 break; 374 case 3: /* DPP3 */ 375 REG_UPDATE(DOMAIN7_PG_CONFIG, 376 DOMAIN7_POWER_GATE, power_gate); 377 378 REG_WAIT(DOMAIN7_PG_STATUS, 379 DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 380 1, 1000); 381 break; 382 case 4: /* DPP4 */ 383 REG_UPDATE(DOMAIN9_PG_CONFIG, 384 DOMAIN9_POWER_GATE, power_gate); 385 386 REG_WAIT(DOMAIN9_PG_STATUS, 387 DOMAIN9_PGFSM_PWR_STATUS, pwr_status, 388 1, 1000); 389 break; 390 case 5: /* DPP5 */ 391 /* 392 * Do not power gate DPP5, should be left at HW default, power on permanently. 393 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 394 * reset. 395 * REG_UPDATE(DOMAIN11_PG_CONFIG, 396 * DOMAIN11_POWER_GATE, power_gate); 397 * 398 * REG_WAIT(DOMAIN11_PG_STATUS, 399 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, 400 * 1, 1000); 401 */ 402 break; 403 default: 404 BREAK_TO_DEBUGGER(); 405 break; 406 } 407 } 408 409 410 static void dcn20_hubp_pg_control( 411 struct dce_hwseq *hws, 412 unsigned int hubp_inst, 413 bool power_on) 414 { 415 uint32_t power_gate = power_on ? 0 : 1; 416 uint32_t pwr_status = power_on ? 0 : 2; 417 418 if (hws->ctx->dc->debug.disable_hubp_power_gate) 419 return; 420 if (REG(DOMAIN0_PG_CONFIG) == 0) 421 return; 422 423 switch (hubp_inst) { 424 case 0: /* DCHUBP0 */ 425 REG_UPDATE(DOMAIN0_PG_CONFIG, 426 DOMAIN0_POWER_GATE, power_gate); 427 428 REG_WAIT(DOMAIN0_PG_STATUS, 429 DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 430 1, 1000); 431 break; 432 case 1: /* DCHUBP1 */ 433 REG_UPDATE(DOMAIN2_PG_CONFIG, 434 DOMAIN2_POWER_GATE, power_gate); 435 436 REG_WAIT(DOMAIN2_PG_STATUS, 437 DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 438 1, 1000); 439 break; 440 case 2: /* DCHUBP2 */ 441 REG_UPDATE(DOMAIN4_PG_CONFIG, 442 DOMAIN4_POWER_GATE, power_gate); 443 444 REG_WAIT(DOMAIN4_PG_STATUS, 445 DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 446 1, 1000); 447 break; 448 case 3: /* DCHUBP3 */ 449 REG_UPDATE(DOMAIN6_PG_CONFIG, 450 DOMAIN6_POWER_GATE, power_gate); 451 452 REG_WAIT(DOMAIN6_PG_STATUS, 453 DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 454 1, 1000); 455 break; 456 case 4: /* DCHUBP4 */ 457 REG_UPDATE(DOMAIN8_PG_CONFIG, 458 DOMAIN8_POWER_GATE, power_gate); 459 460 REG_WAIT(DOMAIN8_PG_STATUS, 461 DOMAIN8_PGFSM_PWR_STATUS, pwr_status, 462 1, 1000); 463 break; 464 case 5: /* DCHUBP5 */ 465 /* 466 * Do not power gate DCHUB5, should be left at HW default, power on permanently. 467 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 468 * reset. 469 * REG_UPDATE(DOMAIN10_PG_CONFIG, 470 * DOMAIN10_POWER_GATE, power_gate); 471 * 472 * REG_WAIT(DOMAIN10_PG_STATUS, 473 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status, 474 * 1, 1000); 475 */ 476 break; 477 default: 478 BREAK_TO_DEBUGGER(); 479 break; 480 } 481 } 482 483 484 485 static void dcn20_plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx) 486 { 487 struct dce_hwseq *hws = dc->hwseq; 488 struct dpp *dpp = pipe_ctx->plane_res.dpp; 489 490 DC_LOGGER_INIT(dc->ctx->logger); 491 492 if (REG(DC_IP_REQUEST_CNTL)) { 493 REG_SET(DC_IP_REQUEST_CNTL, 0, 494 IP_REQUEST_EN, 1); 495 dcn20_dpp_pg_control(hws, dpp->inst, false); 496 dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, false); 497 dpp->funcs->dpp_reset(dpp); 498 REG_SET(DC_IP_REQUEST_CNTL, 0, 499 IP_REQUEST_EN, 0); 500 DC_LOG_DEBUG( 501 "Power gated front end %d\n", pipe_ctx->pipe_idx); 502 } 503 } 504 505 506 507 /* disable HW used by plane. 508 * note: cannot disable until disconnect is complete 509 */ 510 static void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 511 { 512 struct hubp *hubp = pipe_ctx->plane_res.hubp; 513 struct dpp *dpp = pipe_ctx->plane_res.dpp; 514 515 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); 516 517 /* In flip immediate with pipe splitting case GSL is used for 518 * synchronization so we must disable it when the plane is disabled. 519 */ 520 if (pipe_ctx->stream_res.gsl_group != 0) 521 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false); 522 523 dc->hwss.set_flip_control_gsl(pipe_ctx, false); 524 525 hubp->funcs->hubp_clk_cntl(hubp, false); 526 527 dpp->funcs->dpp_dppclk_control(dpp, false, false); 528 529 hubp->power_gated = true; 530 dc->optimized_required = false; /* We're powering off, no need to optimize */ 531 532 dcn20_plane_atomic_power_down(dc, pipe_ctx); 533 534 pipe_ctx->stream = NULL; 535 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); 536 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); 537 pipe_ctx->top_pipe = NULL; 538 pipe_ctx->bottom_pipe = NULL; 539 pipe_ctx->plane_state = NULL; 540 } 541 542 543 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) 544 { 545 DC_LOGGER_INIT(dc->ctx->logger); 546 547 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) 548 return; 549 550 dcn20_plane_atomic_disable(dc, pipe_ctx); 551 552 DC_LOG_DC("Power down front end %d\n", 553 pipe_ctx->pipe_idx); 554 } 555 556 static void dcn20_init_hw(struct dc *dc) 557 { 558 int i, j; 559 struct abm *abm = dc->res_pool->abm; 560 struct dmcu *dmcu = dc->res_pool->dmcu; 561 struct dce_hwseq *hws = dc->hwseq; 562 struct dc_bios *dcb = dc->ctx->dc_bios; 563 struct resource_pool *res_pool = dc->res_pool; 564 struct dc_state *context = dc->current_state; 565 struct dc_firmware_info fw_info = { { 0 } }; 566 567 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 568 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 569 570 // Initialize the dccg 571 if (res_pool->dccg->funcs->dccg_init) 572 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 573 574 //Enable ability to power gate / don't force power on permanently 575 enable_power_gating_plane(dc->hwseq, true); 576 577 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 578 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); 579 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 580 581 dcn20_dccg_init(hws); 582 583 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); 584 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 585 REG_WRITE(REFCLK_CNTL, 0); 586 } else { 587 if (!dcb->funcs->is_accelerated_mode(dcb)) { 588 bios_golden_init(dc); 589 if (dc->ctx->dc_bios->funcs->get_firmware_info( 590 dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) { 591 res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency; 592 593 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 594 if (res_pool->dccg && res_pool->hubbub) { 595 596 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 597 fw_info.pll_info.crystal_frequency, 598 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 599 600 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 601 res_pool->ref_clocks.dccg_ref_clock_inKhz, 602 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 603 } else { 604 // Not all ASICs have DCCG sw component 605 res_pool->ref_clocks.dccg_ref_clock_inKhz = 606 res_pool->ref_clocks.xtalin_clock_inKhz; 607 res_pool->ref_clocks.dchub_ref_clock_inKhz = 608 res_pool->ref_clocks.xtalin_clock_inKhz; 609 } 610 } 611 } else 612 ASSERT_CRITICAL(false); 613 disable_vga(dc->hwseq); 614 } 615 616 for (i = 0; i < dc->link_count; i++) { 617 /* Power up AND update implementation according to the 618 * required signal (which may be different from the 619 * default signal on connector). 620 */ 621 struct dc_link *link = dc->links[i]; 622 623 link->link_enc->funcs->hw_init(link->link_enc); 624 } 625 } 626 627 /* Power gate DSCs */ 628 for (i = 0; i < res_pool->res_cap->num_dsc; i++) 629 dcn20_dsc_pg_control(hws, res_pool->dscs[i]->inst, false); 630 631 /* Blank pixel data with OPP DPG */ 632 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 633 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 634 635 if (tg->funcs->is_tg_enabled(tg)) { 636 dcn20_init_blank(dc, tg); 637 } 638 } 639 640 for (i = 0; i < res_pool->timing_generator_count; i++) { 641 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 642 643 if (tg->funcs->is_tg_enabled(tg)) 644 tg->funcs->lock(tg); 645 } 646 647 for (i = 0; i < dc->res_pool->pipe_count; i++) { 648 struct dpp *dpp = res_pool->dpps[i]; 649 650 dpp->funcs->dpp_reset(dpp); 651 } 652 653 /* Reset all MPCC muxes */ 654 res_pool->mpc->funcs->mpc_init(res_pool->mpc); 655 656 /* initialize OPP mpc_tree parameter */ 657 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 658 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; 659 res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 660 for (j = 0; j < MAX_PIPES; j++) 661 res_pool->opps[i]->mpcc_disconnect_pending[j] = false; 662 } 663 664 for (i = 0; i < dc->res_pool->pipe_count; i++) { 665 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 666 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 667 struct hubp *hubp = dc->res_pool->hubps[i]; 668 struct dpp *dpp = dc->res_pool->dpps[i]; 669 670 pipe_ctx->stream_res.tg = tg; 671 pipe_ctx->pipe_idx = i; 672 673 pipe_ctx->plane_res.hubp = hubp; 674 pipe_ctx->plane_res.dpp = dpp; 675 pipe_ctx->plane_res.mpcc_inst = dpp->inst; 676 hubp->mpcc_id = dpp->inst; 677 hubp->opp_id = OPP_ID_INVALID; 678 hubp->power_gated = false; 679 pipe_ctx->stream_res.opp = NULL; 680 681 hubp->funcs->hubp_init(hubp); 682 683 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; 684 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 685 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; 686 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; 687 /*to do*/ 688 hwss1_plane_atomic_disconnect(dc, pipe_ctx); 689 } 690 691 /* initialize DWB pointer to MCIF_WB */ 692 for (i = 0; i < res_pool->res_cap->num_dwb; i++) 693 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; 694 695 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 696 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 697 698 if (tg->funcs->is_tg_enabled(tg)) 699 tg->funcs->unlock(tg); 700 } 701 702 for (i = 0; i < dc->res_pool->pipe_count; i++) { 703 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 704 705 dc->hwss.disable_plane(dc, pipe_ctx); 706 707 pipe_ctx->stream_res.tg = NULL; 708 pipe_ctx->plane_res.hubp = NULL; 709 } 710 711 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 712 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 713 714 tg->funcs->tg_init(tg); 715 } 716 717 /* end of FPGA. Below if real ASIC */ 718 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 719 return; 720 721 722 for (i = 0; i < res_pool->audio_count; i++) { 723 struct audio *audio = res_pool->audios[i]; 724 725 audio->funcs->hw_init(audio); 726 } 727 728 if (abm != NULL) { 729 abm->funcs->init_backlight(abm); 730 abm->funcs->abm_init(abm); 731 } 732 733 if (dmcu != NULL) 734 dmcu->funcs->dmcu_init(dmcu); 735 736 if (abm != NULL && dmcu != NULL) 737 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 738 739 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 740 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 741 742 if (!dc->debug.disable_clock_gate) { 743 /* enable all DCN clock gating */ 744 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 745 746 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 747 748 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 749 } 750 751 } 752 753 enum dc_status dcn20_enable_stream_timing( 754 struct pipe_ctx *pipe_ctx, 755 struct dc_state *context, 756 struct dc *dc) 757 { 758 struct dc_stream_state *stream = pipe_ctx->stream; 759 struct drr_params params = {0}; 760 unsigned int event_triggers = 0; 761 762 763 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 764 struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); 765 #endif 766 767 /* by upper caller loop, pipe0 is parent pipe and be called first. 768 * back end is set up by for pipe0. Other children pipe share back end 769 * with pipe 0. No program is needed. 770 */ 771 if (pipe_ctx->top_pipe != NULL) 772 return DC_OK; 773 774 /* TODO check if timing_changed, disable stream if timing changed */ 775 776 if (odm_pipe) 777 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 778 pipe_ctx->stream_res.tg, 779 odm_pipe->stream_res.opp->inst, 780 pipe_ctx->stream->timing.h_addressable/2, 781 pipe_ctx->stream->timing.pixel_encoding); 782 /* HW program guide assume display already disable 783 * by unplug sequence. OTG assume stop. 784 */ 785 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); 786 787 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 788 pipe_ctx->clock_source, 789 &pipe_ctx->stream_res.pix_clk_params, 790 &pipe_ctx->pll_settings)) { 791 BREAK_TO_DEBUGGER(); 792 return DC_ERROR_UNEXPECTED; 793 } 794 795 pipe_ctx->stream_res.tg->funcs->program_timing( 796 pipe_ctx->stream_res.tg, 797 &stream->timing, 798 pipe_ctx->pipe_dlg_param.vready_offset, 799 pipe_ctx->pipe_dlg_param.vstartup_start, 800 pipe_ctx->pipe_dlg_param.vupdate_offset, 801 pipe_ctx->pipe_dlg_param.vupdate_width, 802 pipe_ctx->stream->signal, 803 true); 804 805 if (pipe_ctx->stream_res.tg->funcs->setup_global_lock) 806 pipe_ctx->stream_res.tg->funcs->setup_global_lock( 807 pipe_ctx->stream_res.tg); 808 809 if (odm_pipe) 810 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 811 odm_pipe->stream_res.opp, 812 true); 813 814 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 815 pipe_ctx->stream_res.opp, 816 true); 817 818 dc->hwss.blank_pixel_data(dc, pipe_ctx, true); 819 820 /* VTG is within DCHUB command block. DCFCLK is always on */ 821 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { 822 BREAK_TO_DEBUGGER(); 823 return DC_ERROR_UNEXPECTED; 824 } 825 826 dcn20_hwss_wait_for_blank_complete(pipe_ctx->stream_res.opp); 827 828 params.vertical_total_min = stream->adjust.v_total_min; 829 params.vertical_total_max = stream->adjust.v_total_max; 830 if (pipe_ctx->stream_res.tg->funcs->set_drr) 831 pipe_ctx->stream_res.tg->funcs->set_drr( 832 pipe_ctx->stream_res.tg, ¶ms); 833 834 // DRR should set trigger event to monitor surface update event 835 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 836 event_triggers = 0x80; 837 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 838 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 839 pipe_ctx->stream_res.tg, event_triggers); 840 841 /* TODO program crtc source select for non-virtual signal*/ 842 /* TODO program FMT */ 843 /* TODO setup link_enc */ 844 /* TODO set stream attributes */ 845 /* TODO program audio */ 846 /* TODO enable stream if timing changed */ 847 /* TODO unblank stream if DP */ 848 849 return DC_OK; 850 } 851 852 void dcn20_program_output_csc(struct dc *dc, 853 struct pipe_ctx *pipe_ctx, 854 enum dc_color_space colorspace, 855 uint16_t *matrix, 856 int opp_id) 857 { 858 struct mpc *mpc = dc->res_pool->mpc; 859 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; 860 861 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 862 if (mpc->funcs->set_output_csc != NULL) 863 mpc->funcs->set_output_csc(mpc, 864 opp_id, 865 matrix, 866 ocsc_mode); 867 } else { 868 if (mpc->funcs->set_ocsc_default != NULL) 869 mpc->funcs->set_ocsc_default(mpc, 870 opp_id, 871 colorspace, 872 ocsc_mode); 873 } 874 } 875 876 bool dcn20_set_output_transfer_func(struct pipe_ctx *pipe_ctx, 877 const struct dc_stream_state *stream) 878 { 879 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 880 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 881 struct pwl_params *params = NULL; 882 /* 883 * program OGAM only for the top pipe 884 * if there is a pipe split then fix diagnostic is required: 885 * how to pass OGAM parameter for stream. 886 * if programming for all pipes is required then remove condition 887 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic. 888 */ 889 if ((pipe_ctx->top_pipe == NULL || dc_res_is_odm_head_pipe(pipe_ctx)) 890 && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 891 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 892 params = &stream->out_transfer_func->pwl; 893 else if (pipe_ctx->stream->out_transfer_func->type == 894 TF_TYPE_DISTRIBUTED_POINTS && 895 cm_helper_translate_curve_to_hw_format( 896 stream->out_transfer_func, 897 &mpc->blender_params, false)) 898 params = &mpc->blender_params; 899 /* 900 * there is no ROM 901 */ 902 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 903 BREAK_TO_DEBUGGER(); 904 } 905 /* 906 * if above if is not executed then 'params' equal to 0 and set in bypass 907 */ 908 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 909 910 return true; 911 } 912 913 static bool dcn20_set_blend_lut( 914 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 915 { 916 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 917 bool result = true; 918 struct pwl_params *blend_lut = NULL; 919 920 if (plane_state->blend_tf) { 921 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 922 blend_lut = &plane_state->blend_tf->pwl; 923 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 924 cm_helper_translate_curve_to_hw_format( 925 plane_state->blend_tf, 926 &dpp_base->regamma_params, false); 927 blend_lut = &dpp_base->regamma_params; 928 } 929 } 930 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); 931 932 return result; 933 } 934 935 static bool dcn20_set_shaper_3dlut( 936 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 937 { 938 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 939 bool result = true; 940 struct pwl_params *shaper_lut = NULL; 941 942 if (plane_state->in_shaper_func) { 943 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 944 shaper_lut = &plane_state->in_shaper_func->pwl; 945 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 946 cm_helper_translate_curve_to_hw_format( 947 plane_state->in_shaper_func, 948 &dpp_base->shaper_params, true); 949 shaper_lut = &dpp_base->shaper_params; 950 } 951 } 952 953 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); 954 if (plane_state->lut3d_func && 955 plane_state->lut3d_func->state.bits.initialized == 1) 956 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, 957 &plane_state->lut3d_func->lut_3d); 958 else 959 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); 960 961 if (plane_state->lut3d_func && 962 plane_state->lut3d_func->state.bits.initialized == 1 && 963 plane_state->lut3d_func->hdr_multiplier != 0) 964 dpp_base->funcs->dpp_set_hdr_multiplier(dpp_base, 965 plane_state->lut3d_func->hdr_multiplier); 966 else 967 dpp_base->funcs->dpp_set_hdr_multiplier(dpp_base, 0x1f000); 968 969 return result; 970 } 971 972 bool dcn20_set_input_transfer_func(struct pipe_ctx *pipe_ctx, 973 const struct dc_plane_state *plane_state) 974 { 975 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 976 const struct dc_transfer_func *tf = NULL; 977 bool result = true; 978 bool use_degamma_ram = false; 979 980 if (dpp_base == NULL || plane_state == NULL) 981 return false; 982 983 dcn20_set_shaper_3dlut(pipe_ctx, plane_state); 984 dcn20_set_blend_lut(pipe_ctx, plane_state); 985 986 if (plane_state->in_transfer_func) 987 tf = plane_state->in_transfer_func; 988 989 990 if (tf == NULL) { 991 dpp_base->funcs->dpp_set_degamma(dpp_base, 992 IPP_DEGAMMA_MODE_BYPASS); 993 return true; 994 } 995 996 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS) 997 use_degamma_ram = true; 998 999 if (use_degamma_ram == true) { 1000 if (tf->type == TF_TYPE_HWPWL) 1001 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 1002 &tf->pwl); 1003 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 1004 cm_helper_translate_curve_to_degamma_hw_format(tf, 1005 &dpp_base->degamma_params); 1006 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 1007 &dpp_base->degamma_params); 1008 } 1009 return true; 1010 } 1011 /* handle here the optimized cases when de-gamma ROM could be used. 1012 * 1013 */ 1014 if (tf->type == TF_TYPE_PREDEFINED) { 1015 switch (tf->tf) { 1016 case TRANSFER_FUNCTION_SRGB: 1017 dpp_base->funcs->dpp_set_degamma(dpp_base, 1018 IPP_DEGAMMA_MODE_HW_sRGB); 1019 break; 1020 case TRANSFER_FUNCTION_BT709: 1021 dpp_base->funcs->dpp_set_degamma(dpp_base, 1022 IPP_DEGAMMA_MODE_HW_xvYCC); 1023 break; 1024 case TRANSFER_FUNCTION_LINEAR: 1025 dpp_base->funcs->dpp_set_degamma(dpp_base, 1026 IPP_DEGAMMA_MODE_BYPASS); 1027 break; 1028 case TRANSFER_FUNCTION_PQ: 1029 default: 1030 result = false; 1031 break; 1032 } 1033 } else if (tf->type == TF_TYPE_BYPASS) 1034 dpp_base->funcs->dpp_set_degamma(dpp_base, 1035 IPP_DEGAMMA_MODE_BYPASS); 1036 else { 1037 /* 1038 * if we are here, we did not handle correctly. 1039 * fix is required for this use case 1040 */ 1041 BREAK_TO_DEBUGGER(); 1042 dpp_base->funcs->dpp_set_degamma(dpp_base, 1043 IPP_DEGAMMA_MODE_BYPASS); 1044 } 1045 1046 return result; 1047 } 1048 1049 static void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1050 { 1051 struct pipe_ctx *combine_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); 1052 1053 if (combine_pipe) 1054 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 1055 pipe_ctx->stream_res.tg, 1056 combine_pipe->stream_res.opp->inst, 1057 pipe_ctx->plane_res.scl_data.h_active, 1058 pipe_ctx->stream->timing.pixel_encoding); 1059 else 1060 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1061 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1062 } 1063 1064 void dcn20_blank_pixel_data( 1065 struct dc *dc, 1066 struct pipe_ctx *pipe_ctx, 1067 bool blank) 1068 { 1069 struct tg_color black_color = {0}; 1070 struct stream_resource *stream_res = &pipe_ctx->stream_res; 1071 struct dc_stream_state *stream = pipe_ctx->stream; 1072 enum dc_color_space color_space = stream->output_color_space; 1073 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; 1074 struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); 1075 1076 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 1077 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; 1078 1079 /* get opp dpg blank color */ 1080 color_space_to_black_color(dc, color_space, &black_color); 1081 1082 if (bot_odm_pipe) 1083 width = width / 2; 1084 1085 if (blank) { 1086 if (stream_res->abm) 1087 stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm); 1088 1089 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) 1090 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; 1091 } else { 1092 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; 1093 } 1094 1095 stream_res->opp->funcs->opp_set_disp_pattern_generator( 1096 stream_res->opp, 1097 test_pattern, 1098 stream->timing.display_color_depth, 1099 &black_color, 1100 width, 1101 height); 1102 1103 if (bot_odm_pipe) { 1104 bot_odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator( 1105 bot_odm_pipe->stream_res.opp, 1106 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE ? 1107 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern, 1108 stream->timing.display_color_depth, 1109 &black_color, 1110 width, 1111 height); 1112 } 1113 1114 if (!blank) 1115 if (stream_res->abm) { 1116 stream_res->abm->funcs->set_pipe(stream_res->abm, stream_res->tg->inst + 1); 1117 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level); 1118 } 1119 } 1120 1121 1122 static void dcn20_power_on_plane( 1123 struct dce_hwseq *hws, 1124 struct pipe_ctx *pipe_ctx) 1125 { 1126 DC_LOGGER_INIT(hws->ctx->logger); 1127 if (REG(DC_IP_REQUEST_CNTL)) { 1128 REG_SET(DC_IP_REQUEST_CNTL, 0, 1129 IP_REQUEST_EN, 1); 1130 dcn20_dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); 1131 dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true); 1132 REG_SET(DC_IP_REQUEST_CNTL, 0, 1133 IP_REQUEST_EN, 0); 1134 DC_LOG_DEBUG( 1135 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst); 1136 } 1137 } 1138 1139 void dcn20_enable_plane( 1140 struct dc *dc, 1141 struct pipe_ctx *pipe_ctx, 1142 struct dc_state *context) 1143 { 1144 //if (dc->debug.sanity_checks) { 1145 // dcn10_verify_allow_pstate_change_high(dc); 1146 //} 1147 dcn20_power_on_plane(dc->hwseq, pipe_ctx); 1148 1149 /* enable DCFCLK current DCHUB */ 1150 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); 1151 1152 /* make sure OPP_PIPE_CLOCK_EN = 1 */ 1153 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 1154 pipe_ctx->stream_res.opp, 1155 true); 1156 1157 /* TODO: enable/disable in dm as per update type. 1158 if (plane_state) { 1159 DC_LOG_DC(dc->ctx->logger, 1160 "Pipe:%d 0x%x: addr hi:0x%x, " 1161 "addr low:0x%x, " 1162 "src: %d, %d, %d," 1163 " %d; dst: %d, %d, %d, %d;\n", 1164 pipe_ctx->pipe_idx, 1165 plane_state, 1166 plane_state->address.grph.addr.high_part, 1167 plane_state->address.grph.addr.low_part, 1168 plane_state->src_rect.x, 1169 plane_state->src_rect.y, 1170 plane_state->src_rect.width, 1171 plane_state->src_rect.height, 1172 plane_state->dst_rect.x, 1173 plane_state->dst_rect.y, 1174 plane_state->dst_rect.width, 1175 plane_state->dst_rect.height); 1176 1177 DC_LOG_DC(dc->ctx->logger, 1178 "Pipe %d: width, height, x, y format:%d\n" 1179 "viewport:%d, %d, %d, %d\n" 1180 "recout: %d, %d, %d, %d\n", 1181 pipe_ctx->pipe_idx, 1182 plane_state->format, 1183 pipe_ctx->plane_res.scl_data.viewport.width, 1184 pipe_ctx->plane_res.scl_data.viewport.height, 1185 pipe_ctx->plane_res.scl_data.viewport.x, 1186 pipe_ctx->plane_res.scl_data.viewport.y, 1187 pipe_ctx->plane_res.scl_data.recout.width, 1188 pipe_ctx->plane_res.scl_data.recout.height, 1189 pipe_ctx->plane_res.scl_data.recout.x, 1190 pipe_ctx->plane_res.scl_data.recout.y); 1191 print_rq_dlg_ttu(dc, pipe_ctx); 1192 } 1193 */ 1194 if (dc->vm_pa_config.valid) { 1195 struct vm_system_aperture_param apt; 1196 1197 apt.sys_default.quad_part = 0; 1198 1199 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr; 1200 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr; 1201 1202 // Program system aperture settings 1203 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); 1204 } 1205 1206 // if (dc->debug.sanity_checks) { 1207 // dcn10_verify_allow_pstate_change_high(dc); 1208 // } 1209 } 1210 1211 1212 static void dcn20_program_pipe( 1213 struct dc *dc, 1214 struct pipe_ctx *pipe_ctx, 1215 struct dc_state *context) 1216 { 1217 pipe_ctx->plane_state->update_flags.bits.full_update = 1218 context->commit_hints.full_update_needed ? 1 : pipe_ctx->plane_state->update_flags.bits.full_update; 1219 1220 if (pipe_ctx->plane_state->update_flags.bits.full_update) 1221 dcn20_enable_plane(dc, pipe_ctx, context); 1222 1223 update_dchubp_dpp(dc, pipe_ctx, context); 1224 1225 set_hdr_multiplier(pipe_ctx); 1226 1227 if (pipe_ctx->plane_state->update_flags.bits.full_update || 1228 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 1229 pipe_ctx->plane_state->update_flags.bits.gamma_change) 1230 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); 1231 1232 /* dcn10_translate_regamma_to_hw_format takes 750us to finish 1233 * only do gamma programming for full update. 1234 * TODO: This can be further optimized/cleaned up 1235 * Always call this for now since it does memcmp inside before 1236 * doing heavy calculation and programming 1237 */ 1238 if (pipe_ctx->plane_state->update_flags.bits.full_update) 1239 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); 1240 } 1241 1242 static void dcn20_program_all_pipe_in_tree( 1243 struct dc *dc, 1244 struct pipe_ctx *pipe_ctx, 1245 struct dc_state *context) 1246 { 1247 if (pipe_ctx->top_pipe == NULL) { 1248 bool blank = !is_pipe_tree_visible(pipe_ctx); 1249 1250 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1251 pipe_ctx->stream_res.tg, 1252 pipe_ctx->pipe_dlg_param.vready_offset, 1253 pipe_ctx->pipe_dlg_param.vstartup_start, 1254 pipe_ctx->pipe_dlg_param.vupdate_offset, 1255 pipe_ctx->pipe_dlg_param.vupdate_width); 1256 1257 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1258 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1259 1260 dc->hwss.blank_pixel_data(dc, pipe_ctx, blank); 1261 1262 if (dc->hwss.update_odm) 1263 dc->hwss.update_odm(dc, context, pipe_ctx); 1264 } 1265 1266 if (pipe_ctx->plane_state != NULL) 1267 dcn20_program_pipe(dc, pipe_ctx, context); 1268 1269 if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx) 1270 dcn20_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context); 1271 } 1272 1273 void dcn20_pipe_control_lock_global( 1274 struct dc *dc, 1275 struct pipe_ctx *pipe, 1276 bool lock) 1277 { 1278 if (lock) { 1279 pipe->stream_res.tg->funcs->lock_doublebuffer_enable( 1280 pipe->stream_res.tg); 1281 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1282 } else { 1283 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1284 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, 1285 CRTC_STATE_VACTIVE); 1286 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, 1287 CRTC_STATE_VBLANK); 1288 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, 1289 CRTC_STATE_VACTIVE); 1290 pipe->stream_res.tg->funcs->lock_doublebuffer_disable( 1291 pipe->stream_res.tg); 1292 } 1293 } 1294 1295 void dcn20_pipe_control_lock( 1296 struct dc *dc, 1297 struct pipe_ctx *pipe, 1298 bool lock) 1299 { 1300 bool flip_immediate = false; 1301 1302 /* use TG master update lock to lock everything on the TG 1303 * therefore only top pipe need to lock 1304 */ 1305 if (pipe->top_pipe) 1306 return; 1307 1308 if (pipe->plane_state != NULL) 1309 flip_immediate = pipe->plane_state->flip_immediate; 1310 1311 if (flip_immediate && lock) { 1312 while (pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp)) { 1313 udelay(1); 1314 } 1315 1316 if (pipe->bottom_pipe != NULL) 1317 while (pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp)) { 1318 udelay(1); 1319 } 1320 } 1321 1322 /* In flip immediate and pipe splitting case, we need to use GSL 1323 * for synchronization. Only do setup on locking and on flip type change. 1324 */ 1325 if (lock && pipe->bottom_pipe != NULL) 1326 if ((flip_immediate && pipe->stream_res.gsl_group == 0) || 1327 (!flip_immediate && pipe->stream_res.gsl_group > 0)) 1328 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate); 1329 1330 if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) { 1331 if (lock) 1332 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); 1333 else 1334 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); 1335 } else { 1336 if (lock) 1337 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1338 else 1339 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1340 } 1341 } 1342 1343 static void dcn20_apply_ctx_for_surface( 1344 struct dc *dc, 1345 const struct dc_stream_state *stream, 1346 int num_planes, 1347 struct dc_state *context) 1348 { 1349 1350 int i; 1351 struct timing_generator *tg; 1352 bool removed_pipe[6] = { false }; 1353 bool interdependent_update = false; 1354 struct pipe_ctx *top_pipe_to_program = 1355 find_top_pipe_for_stream(dc, context, stream); 1356 DC_LOGGER_INIT(dc->ctx->logger); 1357 1358 if (!top_pipe_to_program) 1359 return; 1360 1361 tg = top_pipe_to_program->stream_res.tg; 1362 1363 interdependent_update = top_pipe_to_program->plane_state && 1364 top_pipe_to_program->plane_state->update_flags.bits.full_update; 1365 1366 if (interdependent_update) 1367 lock_all_pipes(dc, context, true); 1368 else 1369 dcn20_pipe_control_lock(dc, top_pipe_to_program, true); 1370 1371 if (num_planes == 0) { 1372 /* OTG blank before remove all front end */ 1373 dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true); 1374 } 1375 1376 /* Disconnect unused mpcc */ 1377 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1378 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1379 struct pipe_ctx *old_pipe_ctx = 1380 &dc->current_state->res_ctx.pipe_ctx[i]; 1381 /* 1382 * Powergate reused pipes that are not powergated 1383 * fairly hacky right now, using opp_id as indicator 1384 * TODO: After move dc_post to dc_update, this will 1385 * be removed. 1386 */ 1387 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) { 1388 if (old_pipe_ctx->stream_res.tg == tg && 1389 old_pipe_ctx->plane_res.hubp && 1390 old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID) 1391 dcn20_disable_plane(dc, old_pipe_ctx); 1392 } 1393 1394 if ((!pipe_ctx->plane_state || 1395 pipe_ctx->stream_res.tg != old_pipe_ctx->stream_res.tg) && 1396 old_pipe_ctx->plane_state && 1397 old_pipe_ctx->stream_res.tg == tg) { 1398 1399 dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx); 1400 removed_pipe[i] = true; 1401 1402 DC_LOG_DC("Reset mpcc for pipe %d\n", 1403 old_pipe_ctx->pipe_idx); 1404 } 1405 } 1406 1407 if (num_planes > 0) 1408 dcn20_program_all_pipe_in_tree(dc, top_pipe_to_program, context); 1409 1410 /* Program secondary blending tree and writeback pipes */ 1411 if ((stream->num_wb_info > 0) && (dc->hwss.program_all_writeback_pipes_in_tree)) 1412 dc->hwss.program_all_writeback_pipes_in_tree(dc, stream, context); 1413 1414 if (interdependent_update) 1415 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1416 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1417 1418 /* Skip inactive pipes and ones already updated */ 1419 if (!pipe_ctx->stream || pipe_ctx->stream == stream || 1420 !pipe_ctx->plane_state || !tg->funcs->is_tg_enabled(tg)) 1421 continue; 1422 1423 pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent( 1424 pipe_ctx->plane_res.hubp, 1425 &pipe_ctx->dlg_regs, 1426 &pipe_ctx->ttu_regs); 1427 } 1428 1429 if (interdependent_update) 1430 lock_all_pipes(dc, context, false); 1431 else 1432 dcn20_pipe_control_lock(dc, top_pipe_to_program, false); 1433 1434 for (i = 0; i < dc->res_pool->pipe_count; i++) 1435 if (removed_pipe[i]) 1436 dcn20_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1437 } 1438 1439 1440 void dcn20_prepare_bandwidth( 1441 struct dc *dc, 1442 struct dc_state *context) 1443 { 1444 struct hubbub *hubbub = dc->res_pool->hubbub; 1445 1446 /* program dchubbub watermarks */ 1447 hubbub->funcs->program_watermarks(hubbub, 1448 &context->bw_ctx.bw.dcn.watermarks, 1449 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1450 false); 1451 1452 dc->clk_mgr->funcs->update_clocks( 1453 dc->clk_mgr, 1454 context, 1455 false); 1456 } 1457 1458 void dcn20_optimize_bandwidth( 1459 struct dc *dc, 1460 struct dc_state *context) 1461 { 1462 struct hubbub *hubbub = dc->res_pool->hubbub; 1463 1464 /* program dchubbub watermarks */ 1465 hubbub->funcs->program_watermarks(hubbub, 1466 &context->bw_ctx.bw.dcn.watermarks, 1467 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1468 true); 1469 1470 dc->clk_mgr->funcs->update_clocks( 1471 dc->clk_mgr, 1472 context, 1473 true); 1474 } 1475 1476 bool dcn20_update_bandwidth( 1477 struct dc *dc, 1478 struct dc_state *context) 1479 { 1480 int i; 1481 1482 /* recalculate DML parameters */ 1483 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) 1484 return false; 1485 1486 /* apply updated bandwidth parameters */ 1487 dc->hwss.prepare_bandwidth(dc, context); 1488 1489 /* update hubp configs for all pipes */ 1490 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1491 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1492 1493 if (pipe_ctx->plane_state == NULL) 1494 continue; 1495 1496 if (pipe_ctx->top_pipe == NULL) { 1497 bool blank = !is_pipe_tree_visible(pipe_ctx); 1498 1499 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1500 pipe_ctx->stream_res.tg, 1501 pipe_ctx->pipe_dlg_param.vready_offset, 1502 pipe_ctx->pipe_dlg_param.vstartup_start, 1503 pipe_ctx->pipe_dlg_param.vupdate_offset, 1504 pipe_ctx->pipe_dlg_param.vupdate_width); 1505 1506 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1507 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1508 1509 dc->hwss.blank_pixel_data(dc, pipe_ctx, blank); 1510 } 1511 1512 pipe_ctx->plane_res.hubp->funcs->hubp_setup( 1513 pipe_ctx->plane_res.hubp, 1514 &pipe_ctx->dlg_regs, 1515 &pipe_ctx->ttu_regs, 1516 &pipe_ctx->rq_regs, 1517 &pipe_ctx->pipe_dlg_param); 1518 } 1519 1520 return true; 1521 } 1522 1523 static void dcn20_enable_writeback( 1524 struct dc *dc, 1525 const struct dc_stream_status *stream_status, 1526 struct dc_writeback_info *wb_info) 1527 { 1528 struct dwbc *dwb; 1529 struct mcif_wb *mcif_wb; 1530 struct timing_generator *optc; 1531 1532 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 1533 ASSERT(wb_info->wb_enabled); 1534 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 1535 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 1536 1537 /* set the OPTC source mux */ 1538 ASSERT(stream_status->primary_otg_inst < MAX_PIPES); 1539 optc = dc->res_pool->timing_generators[stream_status->primary_otg_inst]; 1540 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); 1541 /* set MCIF_WB buffer and arbitration configuration */ 1542 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 1543 mcif_wb->funcs->config_mcif_arb(mcif_wb, &dc->current_state->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 1544 /* Enable MCIF_WB */ 1545 mcif_wb->funcs->enable_mcif(mcif_wb); 1546 /* Enable DWB */ 1547 dwb->funcs->enable(dwb, &wb_info->dwb_params); 1548 /* TODO: add sequence to enable/disable warmup */ 1549 } 1550 1551 void dcn20_disable_writeback( 1552 struct dc *dc, 1553 unsigned int dwb_pipe_inst) 1554 { 1555 struct dwbc *dwb; 1556 struct mcif_wb *mcif_wb; 1557 1558 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); 1559 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; 1560 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; 1561 1562 dwb->funcs->disable(dwb); 1563 mcif_wb->funcs->disable_mcif(mcif_wb); 1564 } 1565 1566 bool dcn20_hwss_wait_for_blank_complete( 1567 struct output_pixel_processor *opp) 1568 { 1569 int counter; 1570 1571 for (counter = 0; counter < 1000; counter++) { 1572 if (opp->funcs->dpg_is_blanked(opp)) 1573 break; 1574 1575 udelay(100); 1576 } 1577 1578 if (counter == 1000) { 1579 dm_error("DC: failed to blank crtc!\n"); 1580 return false; 1581 } 1582 1583 return true; 1584 } 1585 1586 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) 1587 { 1588 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1589 1590 if (!hubp) 1591 return false; 1592 return hubp->funcs->dmdata_status_done(hubp); 1593 } 1594 1595 static void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 1596 { 1597 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1598 struct dce_hwseq *hws = dc->hwseq; 1599 struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); 1600 1601 if (pipe_ctx->stream_res.dsc) { 1602 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); 1603 if (bot_odm_pipe) 1604 dcn20_dsc_pg_control(hws, bot_odm_pipe->stream_res.dsc->inst, true); 1605 } 1606 #endif 1607 } 1608 1609 static void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 1610 { 1611 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1612 struct dce_hwseq *hws = dc->hwseq; 1613 struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); 1614 1615 if (pipe_ctx->stream_res.dsc) { 1616 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false); 1617 if (bot_odm_pipe) 1618 dcn20_dsc_pg_control(hws, bot_odm_pipe->stream_res.dsc->inst, false); 1619 } 1620 #endif 1621 } 1622 1623 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) 1624 { 1625 struct dc_dmdata_attributes attr = { 0 }; 1626 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1627 1628 attr.dmdata_mode = DMDATA_HW_MODE; 1629 attr.dmdata_size = 1630 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; 1631 attr.address.quad_part = 1632 pipe_ctx->stream->dmdata_address.quad_part; 1633 attr.dmdata_dl_delta = 0; 1634 attr.dmdata_qos_mode = 0; 1635 attr.dmdata_qos_level = 0; 1636 attr.dmdata_repeat = 1; /* always repeat */ 1637 attr.dmdata_updated = 1; 1638 attr.dmdata_sw_data = NULL; 1639 1640 hubp->funcs->dmdata_set_attributes(hubp, &attr); 1641 } 1642 1643 void dcn20_disable_stream(struct pipe_ctx *pipe_ctx, int option) 1644 { 1645 dce110_disable_stream(pipe_ctx, option); 1646 } 1647 1648 static void dcn20_init_vm_ctx( 1649 struct dce_hwseq *hws, 1650 struct dc *dc, 1651 struct dc_virtual_addr_space_config *va_config, 1652 int vmid) 1653 { 1654 struct dcn_hubbub_virt_addr_config config; 1655 1656 if (vmid == 0) { 1657 ASSERT(0); /* VMID cannot be 0 for vm context */ 1658 return; 1659 } 1660 1661 config.page_table_start_addr = va_config->page_table_start_addr; 1662 config.page_table_end_addr = va_config->page_table_end_addr; 1663 config.page_table_block_size = va_config->page_table_block_size_in_bytes; 1664 config.page_table_depth = va_config->page_table_depth; 1665 config.page_table_base_addr = va_config->page_table_base_addr; 1666 1667 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); 1668 } 1669 1670 static int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 1671 { 1672 struct dcn_hubbub_phys_addr_config config; 1673 1674 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 1675 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 1676 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 1677 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 1678 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 1679 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 1680 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 1681 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 1682 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 1683 1684 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 1685 } 1686 1687 static bool patch_address_for_sbs_tb_stereo( 1688 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) 1689 { 1690 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1691 bool sec_split = pipe_ctx->top_pipe && 1692 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; 1693 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && 1694 (pipe_ctx->stream->timing.timing_3d_format == 1695 TIMING_3D_FORMAT_SIDE_BY_SIDE || 1696 pipe_ctx->stream->timing.timing_3d_format == 1697 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { 1698 *addr = plane_state->address.grph_stereo.left_addr; 1699 plane_state->address.grph_stereo.left_addr = 1700 plane_state->address.grph_stereo.right_addr; 1701 return true; 1702 } 1703 1704 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && 1705 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { 1706 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; 1707 plane_state->address.grph_stereo.right_addr = 1708 plane_state->address.grph_stereo.left_addr; 1709 } 1710 return false; 1711 } 1712 1713 1714 static void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) 1715 { 1716 bool addr_patched = false; 1717 PHYSICAL_ADDRESS_LOC addr; 1718 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1719 1720 if (plane_state == NULL) 1721 return; 1722 1723 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); 1724 1725 // Call Helper to track VMID use 1726 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); 1727 1728 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( 1729 pipe_ctx->plane_res.hubp, 1730 &plane_state->address, 1731 plane_state->flip_immediate); 1732 1733 plane_state->status.requested_address = plane_state->address; 1734 1735 if (plane_state->flip_immediate) 1736 plane_state->status.current_address = plane_state->address; 1737 1738 if (addr_patched) 1739 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; 1740 } 1741 1742 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, 1743 struct dc_link_settings *link_settings) 1744 { 1745 struct encoder_unblank_param params = { { 0 } }; 1746 struct dc_stream_state *stream = pipe_ctx->stream; 1747 struct dc_link *link = stream->link; 1748 params.odm = dc_res_get_odm_bottom_pipe(pipe_ctx); 1749 1750 /* only 3 items below are used by unblank */ 1751 params.timing = pipe_ctx->stream->timing; 1752 1753 params.link_settings.link_rate = link_settings->link_rate; 1754 1755 if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1756 if (optc1_is_two_pixels_per_containter(&stream->timing) || params.odm) 1757 params.timing.pix_clk_100hz /= 2; 1758 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 1759 pipe_ctx->stream_res.stream_enc, params.odm); 1760 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); 1761 } 1762 1763 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1764 link->dc->hwss.edp_backlight_control(link, true); 1765 } 1766 } 1767 1768 void dcn20_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx) 1769 { 1770 struct timing_generator *tg = pipe_ctx->stream_res.tg; 1771 int start_line = get_vupdate_offset_from_vsync(pipe_ctx); 1772 1773 if (start_line < 0) 1774 start_line = 0; 1775 1776 if (tg->funcs->setup_vertical_interrupt2) 1777 tg->funcs->setup_vertical_interrupt2(tg, start_line); 1778 } 1779 1780 static void dcn20_reset_back_end_for_pipe( 1781 struct dc *dc, 1782 struct pipe_ctx *pipe_ctx, 1783 struct dc_state *context) 1784 { 1785 int i; 1786 DC_LOGGER_INIT(dc->ctx->logger); 1787 if (pipe_ctx->stream_res.stream_enc == NULL) { 1788 pipe_ctx->stream = NULL; 1789 return; 1790 } 1791 1792 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 1793 /* DPMS may already disable */ 1794 if (!pipe_ctx->stream->dpms_off) 1795 core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE); 1796 else if (pipe_ctx->stream_res.audio) { 1797 dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE); 1798 } 1799 } 1800 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1801 else if (pipe_ctx->stream_res.dsc) { 1802 dp_set_dsc_enable(pipe_ctx, false); 1803 } 1804 #endif 1805 1806 /* by upper caller loop, parent pipe: pipe0, will be reset last. 1807 * back end share by all pipes and will be disable only when disable 1808 * parent pipe. 1809 */ 1810 if (pipe_ctx->top_pipe == NULL) { 1811 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 1812 1813 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 1814 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 1815 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1816 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1817 } 1818 1819 for (i = 0; i < dc->res_pool->pipe_count; i++) 1820 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) 1821 break; 1822 1823 if (i == dc->res_pool->pipe_count) 1824 return; 1825 1826 pipe_ctx->stream = NULL; 1827 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 1828 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 1829 } 1830 1831 static void dcn20_reset_hw_ctx_wrap( 1832 struct dc *dc, 1833 struct dc_state *context) 1834 { 1835 int i; 1836 1837 /* Reset Back End*/ 1838 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 1839 struct pipe_ctx *pipe_ctx_old = 1840 &dc->current_state->res_ctx.pipe_ctx[i]; 1841 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1842 1843 if (!pipe_ctx_old->stream) 1844 continue; 1845 1846 if (pipe_ctx_old->top_pipe) 1847 continue; 1848 1849 if (!pipe_ctx->stream || 1850 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 1851 struct clock_source *old_clk = pipe_ctx_old->clock_source; 1852 1853 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 1854 if (dc->hwss.enable_stream_gating) 1855 dc->hwss.enable_stream_gating(dc, pipe_ctx); 1856 if (old_clk) 1857 old_clk->funcs->cs_power_down(old_clk); 1858 } 1859 } 1860 } 1861 1862 static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 1863 { 1864 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1865 struct mpcc_blnd_cfg blnd_cfg = { {0} }; 1866 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; 1867 int mpcc_id; 1868 struct mpcc *new_mpcc; 1869 struct mpc *mpc = dc->res_pool->mpc; 1870 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); 1871 1872 // input to MPCC is always RGB, by default leave black_color at 0 1873 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) { 1874 dcn10_get_hdr_visual_confirm_color( 1875 pipe_ctx, &blnd_cfg.black_color); 1876 } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) { 1877 dcn10_get_surface_visual_confirm_color( 1878 pipe_ctx, &blnd_cfg.black_color); 1879 } 1880 1881 if (per_pixel_alpha) 1882 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 1883 else 1884 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 1885 1886 blnd_cfg.overlap_only = false; 1887 blnd_cfg.global_gain = 0xff; 1888 1889 if (pipe_ctx->plane_state->global_alpha) 1890 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; 1891 else 1892 blnd_cfg.global_alpha = 0xff; 1893 1894 blnd_cfg.background_color_bpc = 4; 1895 blnd_cfg.bottom_gain_mode = 0; 1896 blnd_cfg.top_gain = 0x1f000; 1897 blnd_cfg.bottom_inside_gain = 0x1f000; 1898 blnd_cfg.bottom_outside_gain = 0x1f000; 1899 blnd_cfg.pre_multiplied_alpha = per_pixel_alpha; 1900 1901 /* 1902 * TODO: remove hack 1903 * Note: currently there is a bug in init_hw such that 1904 * on resume from hibernate, BIOS sets up MPCC0, and 1905 * we do mpcc_remove but the mpcc cannot go to idle 1906 * after remove. This cause us to pick mpcc1 here, 1907 * which causes a pstate hang for yet unknown reason. 1908 */ 1909 mpcc_id = hubp->inst; 1910 1911 /* If there is no full update, don't need to touch MPC tree*/ 1912 if (!pipe_ctx->plane_state->update_flags.bits.full_update) { 1913 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); 1914 return; 1915 } 1916 1917 /* check if this MPCC is already being used */ 1918 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 1919 /* remove MPCC if being used */ 1920 if (new_mpcc != NULL) 1921 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); 1922 else 1923 if (dc->debug.sanity_checks) 1924 mpc->funcs->assert_mpcc_idle_before_connect( 1925 dc->res_pool->mpc, mpcc_id); 1926 1927 /* Call MPC to insert new plane */ 1928 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, 1929 mpc_tree_params, 1930 &blnd_cfg, 1931 NULL, 1932 NULL, 1933 hubp->inst, 1934 mpcc_id); 1935 1936 ASSERT(new_mpcc != NULL); 1937 hubp->opp_id = pipe_ctx->stream_res.opp->inst; 1938 hubp->mpcc_id = mpcc_id; 1939 } 1940 1941 static int find_free_gsl_group(const struct dc *dc) 1942 { 1943 if (dc->res_pool->gsl_groups.gsl_0 == 0) 1944 return 1; 1945 if (dc->res_pool->gsl_groups.gsl_1 == 0) 1946 return 2; 1947 if (dc->res_pool->gsl_groups.gsl_2 == 0) 1948 return 3; 1949 1950 return 0; 1951 } 1952 1953 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock) 1954 * This is only used to lock pipes in pipe splitting case with immediate flip 1955 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate, 1956 * so we get tearing with freesync since we cannot flip multiple pipes 1957 * atomically. 1958 * We use GSL for this: 1959 * - immediate flip: find first available GSL group if not already assigned 1960 * program gsl with that group, set current OTG as master 1961 * and always us 0x4 = AND of flip_ready from all pipes 1962 * - vsync flip: disable GSL if used 1963 * 1964 * Groups in stream_res are stored as +1 from HW registers, i.e. 1965 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1 1966 * Using a magic value like -1 would require tracking all inits/resets 1967 */ 1968 void dcn20_setup_gsl_group_as_lock( 1969 const struct dc *dc, 1970 struct pipe_ctx *pipe_ctx, 1971 bool enable) 1972 { 1973 struct gsl_params gsl; 1974 int group_idx; 1975 1976 memset(&gsl, 0, sizeof(struct gsl_params)); 1977 1978 if (enable) { 1979 /* return if group already assigned since GSL was set up 1980 * for vsync flip, we would unassign so it can't be "left over" 1981 */ 1982 if (pipe_ctx->stream_res.gsl_group > 0) 1983 return; 1984 1985 group_idx = find_free_gsl_group(dc); 1986 ASSERT(group_idx != 0); 1987 pipe_ctx->stream_res.gsl_group = group_idx; 1988 1989 /* set gsl group reg field and mark resource used */ 1990 switch (group_idx) { 1991 case 1: 1992 gsl.gsl0_en = 1; 1993 dc->res_pool->gsl_groups.gsl_0 = 1; 1994 break; 1995 case 2: 1996 gsl.gsl1_en = 1; 1997 dc->res_pool->gsl_groups.gsl_1 = 1; 1998 break; 1999 case 3: 2000 gsl.gsl2_en = 1; 2001 dc->res_pool->gsl_groups.gsl_2 = 1; 2002 break; 2003 default: 2004 BREAK_TO_DEBUGGER(); 2005 return; // invalid case 2006 } 2007 gsl.gsl_master_en = 1; 2008 } else { 2009 group_idx = pipe_ctx->stream_res.gsl_group; 2010 if (group_idx == 0) 2011 return; // if not in use, just return 2012 2013 pipe_ctx->stream_res.gsl_group = 0; 2014 2015 /* unset gsl group reg field and mark resource free */ 2016 switch (group_idx) { 2017 case 1: 2018 gsl.gsl0_en = 0; 2019 dc->res_pool->gsl_groups.gsl_0 = 0; 2020 break; 2021 case 2: 2022 gsl.gsl1_en = 0; 2023 dc->res_pool->gsl_groups.gsl_1 = 0; 2024 break; 2025 case 3: 2026 gsl.gsl2_en = 0; 2027 dc->res_pool->gsl_groups.gsl_2 = 0; 2028 break; 2029 default: 2030 BREAK_TO_DEBUGGER(); 2031 return; 2032 } 2033 gsl.gsl_master_en = 0; 2034 } 2035 2036 /* at this point we want to program whether it's to enable or disable */ 2037 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && 2038 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { 2039 pipe_ctx->stream_res.tg->funcs->set_gsl( 2040 pipe_ctx->stream_res.tg, 2041 &gsl); 2042 2043 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( 2044 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); 2045 } else 2046 BREAK_TO_DEBUGGER(); 2047 } 2048 2049 static void dcn20_set_flip_control_gsl( 2050 struct pipe_ctx *pipe_ctx, 2051 bool flip_immediate) 2052 { 2053 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) 2054 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( 2055 pipe_ctx->plane_res.hubp, flip_immediate); 2056 2057 } 2058 2059 void dcn20_hw_sequencer_construct(struct dc *dc) 2060 { 2061 dcn10_hw_sequencer_construct(dc); 2062 dc->hwss.init_hw = dcn20_init_hw; 2063 dc->hwss.init_pipes = NULL; 2064 dc->hwss.unblank_stream = dcn20_unblank_stream; 2065 dc->hwss.update_plane_addr = dcn20_update_plane_addr; 2066 dc->hwss.disable_plane = dcn20_disable_plane, 2067 dc->hwss.enable_stream_timing = dcn20_enable_stream_timing; 2068 dc->hwss.program_triplebuffer = dcn20_program_tripleBuffer; 2069 dc->hwss.set_input_transfer_func = dcn20_set_input_transfer_func; 2070 dc->hwss.set_output_transfer_func = dcn20_set_output_transfer_func; 2071 dc->hwss.apply_ctx_for_surface = dcn20_apply_ctx_for_surface; 2072 dc->hwss.pipe_control_lock = dcn20_pipe_control_lock; 2073 dc->hwss.pipe_control_lock_global = dcn20_pipe_control_lock_global; 2074 dc->hwss.optimize_bandwidth = dcn20_optimize_bandwidth; 2075 dc->hwss.prepare_bandwidth = dcn20_prepare_bandwidth; 2076 dc->hwss.update_bandwidth = dcn20_update_bandwidth; 2077 dc->hwss.enable_writeback = dcn20_enable_writeback; 2078 dc->hwss.disable_writeback = dcn20_disable_writeback; 2079 dc->hwss.program_output_csc = dcn20_program_output_csc; 2080 dc->hwss.update_odm = dcn20_update_odm; 2081 dc->hwss.blank_pixel_data = dcn20_blank_pixel_data; 2082 dc->hwss.dmdata_status_done = dcn20_dmdata_status_done; 2083 dc->hwss.disable_stream = dcn20_disable_stream; 2084 dc->hwss.init_sys_ctx = dcn20_init_sys_ctx; 2085 dc->hwss.init_vm_ctx = dcn20_init_vm_ctx; 2086 dc->hwss.disable_stream_gating = dcn20_disable_stream_gating; 2087 dc->hwss.enable_stream_gating = dcn20_enable_stream_gating; 2088 dc->hwss.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt; 2089 dc->hwss.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap; 2090 dc->hwss.update_mpcc = dcn20_update_mpcc; 2091 dc->hwss.set_flip_control_gsl = dcn20_set_flip_control_gsl; 2092 dc->hwss.did_underflow_occur = dcn10_did_underflow_occur; 2093 } 2094