1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include <linux/delay.h> 26 27 #include "dm_services.h" 28 #include "basics/dc_common.h" 29 #include "dm_helpers.h" 30 #include "core_types.h" 31 #include "resource.h" 32 #include "dcn20_resource.h" 33 #include "dcn20_hwseq.h" 34 #include "dce/dce_hwseq.h" 35 #include "dcn20_dsc.h" 36 #include "dcn20_optc.h" 37 #include "abm.h" 38 #include "clk_mgr.h" 39 #include "dmcu.h" 40 #include "hubp.h" 41 #include "timing_generator.h" 42 #include "opp.h" 43 #include "ipp.h" 44 #include "mpc.h" 45 #include "mcif_wb.h" 46 #include "dchubbub.h" 47 #include "reg_helper.h" 48 #include "dcn10/dcn10_cm_common.h" 49 #include "dc_link_dp.h" 50 #include "vm_helper.h" 51 #include "dccg.h" 52 #include "dc_dmub_srv.h" 53 #include "dce/dmub_hw_lock_mgr.h" 54 #include "hw_sequencer.h" 55 #include "inc/link_dpcd.h" 56 #include "dpcd_defs.h" 57 #include "inc/link_enc_cfg.h" 58 #include "link_hwss.h" 59 60 #define DC_LOGGER_INIT(logger) 61 62 #define CTX \ 63 hws->ctx 64 #define REG(reg)\ 65 hws->regs->reg 66 67 #undef FN 68 #define FN(reg_name, field_name) \ 69 hws->shifts->field_name, hws->masks->field_name 70 71 static int find_free_gsl_group(const struct dc *dc) 72 { 73 if (dc->res_pool->gsl_groups.gsl_0 == 0) 74 return 1; 75 if (dc->res_pool->gsl_groups.gsl_1 == 0) 76 return 2; 77 if (dc->res_pool->gsl_groups.gsl_2 == 0) 78 return 3; 79 80 return 0; 81 } 82 83 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock) 84 * This is only used to lock pipes in pipe splitting case with immediate flip 85 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate, 86 * so we get tearing with freesync since we cannot flip multiple pipes 87 * atomically. 88 * We use GSL for this: 89 * - immediate flip: find first available GSL group if not already assigned 90 * program gsl with that group, set current OTG as master 91 * and always us 0x4 = AND of flip_ready from all pipes 92 * - vsync flip: disable GSL if used 93 * 94 * Groups in stream_res are stored as +1 from HW registers, i.e. 95 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1 96 * Using a magic value like -1 would require tracking all inits/resets 97 */ 98 static void dcn20_setup_gsl_group_as_lock( 99 const struct dc *dc, 100 struct pipe_ctx *pipe_ctx, 101 bool enable) 102 { 103 struct gsl_params gsl; 104 int group_idx; 105 106 memset(&gsl, 0, sizeof(struct gsl_params)); 107 108 if (enable) { 109 /* return if group already assigned since GSL was set up 110 * for vsync flip, we would unassign so it can't be "left over" 111 */ 112 if (pipe_ctx->stream_res.gsl_group > 0) 113 return; 114 115 group_idx = find_free_gsl_group(dc); 116 ASSERT(group_idx != 0); 117 pipe_ctx->stream_res.gsl_group = group_idx; 118 119 /* set gsl group reg field and mark resource used */ 120 switch (group_idx) { 121 case 1: 122 gsl.gsl0_en = 1; 123 dc->res_pool->gsl_groups.gsl_0 = 1; 124 break; 125 case 2: 126 gsl.gsl1_en = 1; 127 dc->res_pool->gsl_groups.gsl_1 = 1; 128 break; 129 case 3: 130 gsl.gsl2_en = 1; 131 dc->res_pool->gsl_groups.gsl_2 = 1; 132 break; 133 default: 134 BREAK_TO_DEBUGGER(); 135 return; // invalid case 136 } 137 gsl.gsl_master_en = 1; 138 } else { 139 group_idx = pipe_ctx->stream_res.gsl_group; 140 if (group_idx == 0) 141 return; // if not in use, just return 142 143 pipe_ctx->stream_res.gsl_group = 0; 144 145 /* unset gsl group reg field and mark resource free */ 146 switch (group_idx) { 147 case 1: 148 gsl.gsl0_en = 0; 149 dc->res_pool->gsl_groups.gsl_0 = 0; 150 break; 151 case 2: 152 gsl.gsl1_en = 0; 153 dc->res_pool->gsl_groups.gsl_1 = 0; 154 break; 155 case 3: 156 gsl.gsl2_en = 0; 157 dc->res_pool->gsl_groups.gsl_2 = 0; 158 break; 159 default: 160 BREAK_TO_DEBUGGER(); 161 return; 162 } 163 gsl.gsl_master_en = 0; 164 } 165 166 /* at this point we want to program whether it's to enable or disable */ 167 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && 168 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { 169 pipe_ctx->stream_res.tg->funcs->set_gsl( 170 pipe_ctx->stream_res.tg, 171 &gsl); 172 173 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( 174 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); 175 } else 176 BREAK_TO_DEBUGGER(); 177 } 178 179 void dcn20_set_flip_control_gsl( 180 struct pipe_ctx *pipe_ctx, 181 bool flip_immediate) 182 { 183 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) 184 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( 185 pipe_ctx->plane_res.hubp, flip_immediate); 186 187 } 188 189 void dcn20_enable_power_gating_plane( 190 struct dce_hwseq *hws, 191 bool enable) 192 { 193 bool force_on = true; /* disable power gating */ 194 195 if (enable) 196 force_on = false; 197 198 /* DCHUBP0/1/2/3/4/5 */ 199 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); 200 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); 201 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); 202 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); 203 if (REG(DOMAIN8_PG_CONFIG)) 204 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 205 if (REG(DOMAIN10_PG_CONFIG)) 206 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 207 208 /* DPP0/1/2/3/4/5 */ 209 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); 210 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); 211 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); 212 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); 213 if (REG(DOMAIN9_PG_CONFIG)) 214 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 215 if (REG(DOMAIN11_PG_CONFIG)) 216 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 217 218 /* DCS0/1/2/3/4/5 */ 219 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on); 220 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on); 221 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on); 222 if (REG(DOMAIN19_PG_CONFIG)) 223 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on); 224 if (REG(DOMAIN20_PG_CONFIG)) 225 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on); 226 if (REG(DOMAIN21_PG_CONFIG)) 227 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); 228 } 229 230 void dcn20_dccg_init(struct dce_hwseq *hws) 231 { 232 /* 233 * set MICROSECOND_TIME_BASE_DIV 234 * 100Mhz refclk -> 0x120264 235 * 27Mhz refclk -> 0x12021b 236 * 48Mhz refclk -> 0x120230 237 * 238 */ 239 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); 240 241 /* 242 * set MILLISECOND_TIME_BASE_DIV 243 * 100Mhz refclk -> 0x1186a0 244 * 27Mhz refclk -> 0x106978 245 * 48Mhz refclk -> 0x10bb80 246 * 247 */ 248 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); 249 250 /* This value is dependent on the hardware pipeline delay so set once per SOC */ 251 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c); 252 } 253 254 void dcn20_disable_vga( 255 struct dce_hwseq *hws) 256 { 257 REG_WRITE(D1VGA_CONTROL, 0); 258 REG_WRITE(D2VGA_CONTROL, 0); 259 REG_WRITE(D3VGA_CONTROL, 0); 260 REG_WRITE(D4VGA_CONTROL, 0); 261 REG_WRITE(D5VGA_CONTROL, 0); 262 REG_WRITE(D6VGA_CONTROL, 0); 263 } 264 265 void dcn20_program_triple_buffer( 266 const struct dc *dc, 267 struct pipe_ctx *pipe_ctx, 268 bool enable_triple_buffer) 269 { 270 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { 271 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( 272 pipe_ctx->plane_res.hubp, 273 enable_triple_buffer); 274 } 275 } 276 277 /* Blank pixel data during initialization */ 278 void dcn20_init_blank( 279 struct dc *dc, 280 struct timing_generator *tg) 281 { 282 struct dce_hwseq *hws = dc->hwseq; 283 enum dc_color_space color_space; 284 struct tg_color black_color = {0}; 285 struct output_pixel_processor *opp = NULL; 286 struct output_pixel_processor *bottom_opp = NULL; 287 uint32_t num_opps, opp_id_src0, opp_id_src1; 288 uint32_t otg_active_width, otg_active_height; 289 290 /* program opp dpg blank color */ 291 color_space = COLOR_SPACE_SRGB; 292 color_space_to_black_color(dc, color_space, &black_color); 293 294 /* get the OTG active size */ 295 tg->funcs->get_otg_active_size(tg, 296 &otg_active_width, 297 &otg_active_height); 298 299 /* get the OPTC source */ 300 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 301 302 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { 303 ASSERT(false); 304 return; 305 } 306 opp = dc->res_pool->opps[opp_id_src0]; 307 308 if (num_opps == 2) { 309 otg_active_width = otg_active_width / 2; 310 311 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { 312 ASSERT(false); 313 return; 314 } 315 bottom_opp = dc->res_pool->opps[opp_id_src1]; 316 } 317 318 opp->funcs->opp_set_disp_pattern_generator( 319 opp, 320 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 321 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 322 COLOR_DEPTH_UNDEFINED, 323 &black_color, 324 otg_active_width, 325 otg_active_height, 326 0); 327 328 if (num_opps == 2) { 329 bottom_opp->funcs->opp_set_disp_pattern_generator( 330 bottom_opp, 331 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 332 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 333 COLOR_DEPTH_UNDEFINED, 334 &black_color, 335 otg_active_width, 336 otg_active_height, 337 0); 338 } 339 340 hws->funcs.wait_for_blank_complete(opp); 341 } 342 343 void dcn20_dsc_pg_control( 344 struct dce_hwseq *hws, 345 unsigned int dsc_inst, 346 bool power_on) 347 { 348 uint32_t power_gate = power_on ? 0 : 1; 349 uint32_t pwr_status = power_on ? 0 : 2; 350 uint32_t org_ip_request_cntl = 0; 351 352 if (hws->ctx->dc->debug.disable_dsc_power_gate) 353 return; 354 355 if (REG(DOMAIN16_PG_CONFIG) == 0) 356 return; 357 358 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 359 if (org_ip_request_cntl == 0) 360 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 361 362 switch (dsc_inst) { 363 case 0: /* DSC0 */ 364 REG_UPDATE(DOMAIN16_PG_CONFIG, 365 DOMAIN16_POWER_GATE, power_gate); 366 367 REG_WAIT(DOMAIN16_PG_STATUS, 368 DOMAIN16_PGFSM_PWR_STATUS, pwr_status, 369 1, 1000); 370 break; 371 case 1: /* DSC1 */ 372 REG_UPDATE(DOMAIN17_PG_CONFIG, 373 DOMAIN17_POWER_GATE, power_gate); 374 375 REG_WAIT(DOMAIN17_PG_STATUS, 376 DOMAIN17_PGFSM_PWR_STATUS, pwr_status, 377 1, 1000); 378 break; 379 case 2: /* DSC2 */ 380 REG_UPDATE(DOMAIN18_PG_CONFIG, 381 DOMAIN18_POWER_GATE, power_gate); 382 383 REG_WAIT(DOMAIN18_PG_STATUS, 384 DOMAIN18_PGFSM_PWR_STATUS, pwr_status, 385 1, 1000); 386 break; 387 case 3: /* DSC3 */ 388 REG_UPDATE(DOMAIN19_PG_CONFIG, 389 DOMAIN19_POWER_GATE, power_gate); 390 391 REG_WAIT(DOMAIN19_PG_STATUS, 392 DOMAIN19_PGFSM_PWR_STATUS, pwr_status, 393 1, 1000); 394 break; 395 case 4: /* DSC4 */ 396 REG_UPDATE(DOMAIN20_PG_CONFIG, 397 DOMAIN20_POWER_GATE, power_gate); 398 399 REG_WAIT(DOMAIN20_PG_STATUS, 400 DOMAIN20_PGFSM_PWR_STATUS, pwr_status, 401 1, 1000); 402 break; 403 case 5: /* DSC5 */ 404 REG_UPDATE(DOMAIN21_PG_CONFIG, 405 DOMAIN21_POWER_GATE, power_gate); 406 407 REG_WAIT(DOMAIN21_PG_STATUS, 408 DOMAIN21_PGFSM_PWR_STATUS, pwr_status, 409 1, 1000); 410 break; 411 default: 412 BREAK_TO_DEBUGGER(); 413 break; 414 } 415 416 if (org_ip_request_cntl == 0) 417 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 418 } 419 420 void dcn20_dpp_pg_control( 421 struct dce_hwseq *hws, 422 unsigned int dpp_inst, 423 bool power_on) 424 { 425 uint32_t power_gate = power_on ? 0 : 1; 426 uint32_t pwr_status = power_on ? 0 : 2; 427 428 if (hws->ctx->dc->debug.disable_dpp_power_gate) 429 return; 430 if (REG(DOMAIN1_PG_CONFIG) == 0) 431 return; 432 433 switch (dpp_inst) { 434 case 0: /* DPP0 */ 435 REG_UPDATE(DOMAIN1_PG_CONFIG, 436 DOMAIN1_POWER_GATE, power_gate); 437 438 REG_WAIT(DOMAIN1_PG_STATUS, 439 DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 440 1, 1000); 441 break; 442 case 1: /* DPP1 */ 443 REG_UPDATE(DOMAIN3_PG_CONFIG, 444 DOMAIN3_POWER_GATE, power_gate); 445 446 REG_WAIT(DOMAIN3_PG_STATUS, 447 DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 448 1, 1000); 449 break; 450 case 2: /* DPP2 */ 451 REG_UPDATE(DOMAIN5_PG_CONFIG, 452 DOMAIN5_POWER_GATE, power_gate); 453 454 REG_WAIT(DOMAIN5_PG_STATUS, 455 DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 456 1, 1000); 457 break; 458 case 3: /* DPP3 */ 459 REG_UPDATE(DOMAIN7_PG_CONFIG, 460 DOMAIN7_POWER_GATE, power_gate); 461 462 REG_WAIT(DOMAIN7_PG_STATUS, 463 DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 464 1, 1000); 465 break; 466 case 4: /* DPP4 */ 467 REG_UPDATE(DOMAIN9_PG_CONFIG, 468 DOMAIN9_POWER_GATE, power_gate); 469 470 REG_WAIT(DOMAIN9_PG_STATUS, 471 DOMAIN9_PGFSM_PWR_STATUS, pwr_status, 472 1, 1000); 473 break; 474 case 5: /* DPP5 */ 475 /* 476 * Do not power gate DPP5, should be left at HW default, power on permanently. 477 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 478 * reset. 479 * REG_UPDATE(DOMAIN11_PG_CONFIG, 480 * DOMAIN11_POWER_GATE, power_gate); 481 * 482 * REG_WAIT(DOMAIN11_PG_STATUS, 483 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, 484 * 1, 1000); 485 */ 486 break; 487 default: 488 BREAK_TO_DEBUGGER(); 489 break; 490 } 491 } 492 493 494 void dcn20_hubp_pg_control( 495 struct dce_hwseq *hws, 496 unsigned int hubp_inst, 497 bool power_on) 498 { 499 uint32_t power_gate = power_on ? 0 : 1; 500 uint32_t pwr_status = power_on ? 0 : 2; 501 502 if (hws->ctx->dc->debug.disable_hubp_power_gate) 503 return; 504 if (REG(DOMAIN0_PG_CONFIG) == 0) 505 return; 506 507 switch (hubp_inst) { 508 case 0: /* DCHUBP0 */ 509 REG_UPDATE(DOMAIN0_PG_CONFIG, 510 DOMAIN0_POWER_GATE, power_gate); 511 512 REG_WAIT(DOMAIN0_PG_STATUS, 513 DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 514 1, 1000); 515 break; 516 case 1: /* DCHUBP1 */ 517 REG_UPDATE(DOMAIN2_PG_CONFIG, 518 DOMAIN2_POWER_GATE, power_gate); 519 520 REG_WAIT(DOMAIN2_PG_STATUS, 521 DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 522 1, 1000); 523 break; 524 case 2: /* DCHUBP2 */ 525 REG_UPDATE(DOMAIN4_PG_CONFIG, 526 DOMAIN4_POWER_GATE, power_gate); 527 528 REG_WAIT(DOMAIN4_PG_STATUS, 529 DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 530 1, 1000); 531 break; 532 case 3: /* DCHUBP3 */ 533 REG_UPDATE(DOMAIN6_PG_CONFIG, 534 DOMAIN6_POWER_GATE, power_gate); 535 536 REG_WAIT(DOMAIN6_PG_STATUS, 537 DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 538 1, 1000); 539 break; 540 case 4: /* DCHUBP4 */ 541 REG_UPDATE(DOMAIN8_PG_CONFIG, 542 DOMAIN8_POWER_GATE, power_gate); 543 544 REG_WAIT(DOMAIN8_PG_STATUS, 545 DOMAIN8_PGFSM_PWR_STATUS, pwr_status, 546 1, 1000); 547 break; 548 case 5: /* DCHUBP5 */ 549 /* 550 * Do not power gate DCHUB5, should be left at HW default, power on permanently. 551 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 552 * reset. 553 * REG_UPDATE(DOMAIN10_PG_CONFIG, 554 * DOMAIN10_POWER_GATE, power_gate); 555 * 556 * REG_WAIT(DOMAIN10_PG_STATUS, 557 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status, 558 * 1, 1000); 559 */ 560 break; 561 default: 562 BREAK_TO_DEBUGGER(); 563 break; 564 } 565 } 566 567 568 /* disable HW used by plane. 569 * note: cannot disable until disconnect is complete 570 */ 571 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 572 { 573 struct dce_hwseq *hws = dc->hwseq; 574 struct hubp *hubp = pipe_ctx->plane_res.hubp; 575 struct dpp *dpp = pipe_ctx->plane_res.dpp; 576 577 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); 578 579 /* In flip immediate with pipe splitting case GSL is used for 580 * synchronization so we must disable it when the plane is disabled. 581 */ 582 if (pipe_ctx->stream_res.gsl_group != 0) 583 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false); 584 585 if (hubp->funcs->hubp_update_mall_sel) 586 hubp->funcs->hubp_update_mall_sel(hubp, 0, false); 587 588 dc->hwss.set_flip_control_gsl(pipe_ctx, false); 589 590 hubp->funcs->hubp_clk_cntl(hubp, false); 591 592 dpp->funcs->dpp_dppclk_control(dpp, false, false); 593 594 hubp->power_gated = true; 595 596 hws->funcs.plane_atomic_power_down(dc, 597 pipe_ctx->plane_res.dpp, 598 pipe_ctx->plane_res.hubp); 599 600 pipe_ctx->stream = NULL; 601 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); 602 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); 603 pipe_ctx->top_pipe = NULL; 604 pipe_ctx->bottom_pipe = NULL; 605 pipe_ctx->plane_state = NULL; 606 } 607 608 609 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) 610 { 611 bool is_phantom = pipe_ctx->plane_state && pipe_ctx->plane_state->is_phantom; 612 struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL; 613 614 DC_LOGGER_INIT(dc->ctx->logger); 615 616 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) 617 return; 618 619 dcn20_plane_atomic_disable(dc, pipe_ctx); 620 621 /* Turn back off the phantom OTG after the phantom plane is fully disabled 622 */ 623 if (is_phantom) 624 if (tg && tg->funcs->disable_phantom_crtc) 625 tg->funcs->disable_phantom_crtc(tg); 626 627 DC_LOG_DC("Power down front end %d\n", 628 pipe_ctx->pipe_idx); 629 } 630 631 void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank) 632 { 633 dcn20_blank_pixel_data(dc, pipe_ctx, blank); 634 } 635 636 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 637 int opp_cnt) 638 { 639 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 640 int flow_ctrl_cnt; 641 642 if (opp_cnt >= 2) 643 hblank_halved = true; 644 645 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 646 stream->timing.h_border_left - 647 stream->timing.h_border_right; 648 649 if (hblank_halved) 650 flow_ctrl_cnt /= 2; 651 652 /* ODM combine 4:1 case */ 653 if (opp_cnt == 4) 654 flow_ctrl_cnt /= 2; 655 656 return flow_ctrl_cnt; 657 } 658 659 enum dc_status dcn20_enable_stream_timing( 660 struct pipe_ctx *pipe_ctx, 661 struct dc_state *context, 662 struct dc *dc) 663 { 664 struct dce_hwseq *hws = dc->hwseq; 665 struct dc_stream_state *stream = pipe_ctx->stream; 666 struct drr_params params = {0}; 667 unsigned int event_triggers = 0; 668 struct pipe_ctx *odm_pipe; 669 int opp_cnt = 1; 670 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 671 bool interlace = stream->timing.flags.INTERLACE; 672 int i; 673 struct mpc_dwb_flow_control flow_control; 674 struct mpc *mpc = dc->res_pool->mpc; 675 bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing)); 676 unsigned int k1_div = PIXEL_RATE_DIV_NA; 677 unsigned int k2_div = PIXEL_RATE_DIV_NA; 678 679 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { 680 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); 681 682 dc->res_pool->dccg->funcs->set_pixel_rate_div( 683 dc->res_pool->dccg, 684 pipe_ctx->stream_res.tg->inst, 685 k1_div, k2_div); 686 } 687 /* by upper caller loop, pipe0 is parent pipe and be called first. 688 * back end is set up by for pipe0. Other children pipe share back end 689 * with pipe 0. No program is needed. 690 */ 691 if (pipe_ctx->top_pipe != NULL) 692 return DC_OK; 693 694 /* TODO check if timing_changed, disable stream if timing changed */ 695 696 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 697 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 698 opp_cnt++; 699 } 700 701 if (opp_cnt > 1) 702 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 703 pipe_ctx->stream_res.tg, 704 opp_inst, opp_cnt, 705 &pipe_ctx->stream->timing); 706 707 /* HW program guide assume display already disable 708 * by unplug sequence. OTG assume stop. 709 */ 710 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); 711 712 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 713 pipe_ctx->clock_source, 714 &pipe_ctx->stream_res.pix_clk_params, 715 dp_get_link_encoding_format(&pipe_ctx->link_config.dp_link_settings), 716 &pipe_ctx->pll_settings)) { 717 BREAK_TO_DEBUGGER(); 718 return DC_ERROR_UNEXPECTED; 719 } 720 721 if (dc_is_hdmi_tmds_signal(stream->signal)) { 722 stream->link->phy_state.symclk_ref_cnts.otg = 1; 723 if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF) 724 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; 725 else 726 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 727 } 728 729 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal))) 730 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx); 731 732 pipe_ctx->stream_res.tg->funcs->program_timing( 733 pipe_ctx->stream_res.tg, 734 &stream->timing, 735 pipe_ctx->pipe_dlg_param.vready_offset, 736 pipe_ctx->pipe_dlg_param.vstartup_start, 737 pipe_ctx->pipe_dlg_param.vupdate_offset, 738 pipe_ctx->pipe_dlg_param.vupdate_width, 739 pipe_ctx->stream->signal, 740 true); 741 742 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 743 flow_control.flow_ctrl_mode = 0; 744 flow_control.flow_ctrl_cnt0 = 0x80; 745 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt); 746 if (mpc->funcs->set_out_rate_control) { 747 for (i = 0; i < opp_cnt; ++i) { 748 mpc->funcs->set_out_rate_control( 749 mpc, opp_inst[i], 750 true, 751 rate_control_2x_pclk, 752 &flow_control); 753 } 754 } 755 756 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 757 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 758 odm_pipe->stream_res.opp, 759 true); 760 761 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 762 pipe_ctx->stream_res.opp, 763 true); 764 765 hws->funcs.blank_pixel_data(dc, pipe_ctx, true); 766 767 /* VTG is within DCHUB command block. DCFCLK is always on */ 768 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { 769 BREAK_TO_DEBUGGER(); 770 return DC_ERROR_UNEXPECTED; 771 } 772 773 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp); 774 775 params.vertical_total_min = stream->adjust.v_total_min; 776 params.vertical_total_max = stream->adjust.v_total_max; 777 params.vertical_total_mid = stream->adjust.v_total_mid; 778 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num; 779 if (pipe_ctx->stream_res.tg->funcs->set_drr) 780 pipe_ctx->stream_res.tg->funcs->set_drr( 781 pipe_ctx->stream_res.tg, ¶ms); 782 783 // DRR should set trigger event to monitor surface update event 784 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 785 event_triggers = 0x80; 786 /* Event triggers and num frames initialized for DRR, but can be 787 * later updated for PSR use. Note DRR trigger events are generated 788 * regardless of whether num frames met. 789 */ 790 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 791 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 792 pipe_ctx->stream_res.tg, event_triggers, 2); 793 794 /* TODO program crtc source select for non-virtual signal*/ 795 /* TODO program FMT */ 796 /* TODO setup link_enc */ 797 /* TODO set stream attributes */ 798 /* TODO program audio */ 799 /* TODO enable stream if timing changed */ 800 /* TODO unblank stream if DP */ 801 802 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) { 803 if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable) 804 pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg); 805 } 806 return DC_OK; 807 } 808 809 void dcn20_program_output_csc(struct dc *dc, 810 struct pipe_ctx *pipe_ctx, 811 enum dc_color_space colorspace, 812 uint16_t *matrix, 813 int opp_id) 814 { 815 struct mpc *mpc = dc->res_pool->mpc; 816 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; 817 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 818 819 if (mpc->funcs->power_on_mpc_mem_pwr) 820 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 821 822 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 823 if (mpc->funcs->set_output_csc != NULL) 824 mpc->funcs->set_output_csc(mpc, 825 opp_id, 826 matrix, 827 ocsc_mode); 828 } else { 829 if (mpc->funcs->set_ocsc_default != NULL) 830 mpc->funcs->set_ocsc_default(mpc, 831 opp_id, 832 colorspace, 833 ocsc_mode); 834 } 835 } 836 837 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 838 const struct dc_stream_state *stream) 839 { 840 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 841 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 842 struct pwl_params *params = NULL; 843 /* 844 * program OGAM only for the top pipe 845 * if there is a pipe split then fix diagnostic is required: 846 * how to pass OGAM parameter for stream. 847 * if programming for all pipes is required then remove condition 848 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic. 849 */ 850 if (mpc->funcs->power_on_mpc_mem_pwr) 851 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 852 if (pipe_ctx->top_pipe == NULL 853 && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 854 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 855 params = &stream->out_transfer_func->pwl; 856 else if (pipe_ctx->stream->out_transfer_func->type == 857 TF_TYPE_DISTRIBUTED_POINTS && 858 cm_helper_translate_curve_to_hw_format( 859 stream->out_transfer_func, 860 &mpc->blender_params, false)) 861 params = &mpc->blender_params; 862 /* 863 * there is no ROM 864 */ 865 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 866 BREAK_TO_DEBUGGER(); 867 } 868 /* 869 * if above if is not executed then 'params' equal to 0 and set in bypass 870 */ 871 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 872 873 return true; 874 } 875 876 bool dcn20_set_blend_lut( 877 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 878 { 879 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 880 bool result = true; 881 struct pwl_params *blend_lut = NULL; 882 883 if (plane_state->blend_tf) { 884 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 885 blend_lut = &plane_state->blend_tf->pwl; 886 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 887 cm_helper_translate_curve_to_hw_format( 888 plane_state->blend_tf, 889 &dpp_base->regamma_params, false); 890 blend_lut = &dpp_base->regamma_params; 891 } 892 } 893 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); 894 895 return result; 896 } 897 898 bool dcn20_set_shaper_3dlut( 899 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 900 { 901 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 902 bool result = true; 903 struct pwl_params *shaper_lut = NULL; 904 905 if (plane_state->in_shaper_func) { 906 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 907 shaper_lut = &plane_state->in_shaper_func->pwl; 908 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 909 cm_helper_translate_curve_to_hw_format( 910 plane_state->in_shaper_func, 911 &dpp_base->shaper_params, true); 912 shaper_lut = &dpp_base->shaper_params; 913 } 914 } 915 916 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); 917 if (plane_state->lut3d_func && 918 plane_state->lut3d_func->state.bits.initialized == 1) 919 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, 920 &plane_state->lut3d_func->lut_3d); 921 else 922 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); 923 924 return result; 925 } 926 927 bool dcn20_set_input_transfer_func(struct dc *dc, 928 struct pipe_ctx *pipe_ctx, 929 const struct dc_plane_state *plane_state) 930 { 931 struct dce_hwseq *hws = dc->hwseq; 932 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 933 const struct dc_transfer_func *tf = NULL; 934 bool result = true; 935 bool use_degamma_ram = false; 936 937 if (dpp_base == NULL || plane_state == NULL) 938 return false; 939 940 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); 941 hws->funcs.set_blend_lut(pipe_ctx, plane_state); 942 943 if (plane_state->in_transfer_func) 944 tf = plane_state->in_transfer_func; 945 946 947 if (tf == NULL) { 948 dpp_base->funcs->dpp_set_degamma(dpp_base, 949 IPP_DEGAMMA_MODE_BYPASS); 950 return true; 951 } 952 953 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS) 954 use_degamma_ram = true; 955 956 if (use_degamma_ram == true) { 957 if (tf->type == TF_TYPE_HWPWL) 958 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 959 &tf->pwl); 960 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 961 cm_helper_translate_curve_to_degamma_hw_format(tf, 962 &dpp_base->degamma_params); 963 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 964 &dpp_base->degamma_params); 965 } 966 return true; 967 } 968 /* handle here the optimized cases when de-gamma ROM could be used. 969 * 970 */ 971 if (tf->type == TF_TYPE_PREDEFINED) { 972 switch (tf->tf) { 973 case TRANSFER_FUNCTION_SRGB: 974 dpp_base->funcs->dpp_set_degamma(dpp_base, 975 IPP_DEGAMMA_MODE_HW_sRGB); 976 break; 977 case TRANSFER_FUNCTION_BT709: 978 dpp_base->funcs->dpp_set_degamma(dpp_base, 979 IPP_DEGAMMA_MODE_HW_xvYCC); 980 break; 981 case TRANSFER_FUNCTION_LINEAR: 982 dpp_base->funcs->dpp_set_degamma(dpp_base, 983 IPP_DEGAMMA_MODE_BYPASS); 984 break; 985 case TRANSFER_FUNCTION_PQ: 986 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL); 987 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params); 988 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params); 989 result = true; 990 break; 991 default: 992 result = false; 993 break; 994 } 995 } else if (tf->type == TF_TYPE_BYPASS) 996 dpp_base->funcs->dpp_set_degamma(dpp_base, 997 IPP_DEGAMMA_MODE_BYPASS); 998 else { 999 /* 1000 * if we are here, we did not handle correctly. 1001 * fix is required for this use case 1002 */ 1003 BREAK_TO_DEBUGGER(); 1004 dpp_base->funcs->dpp_set_degamma(dpp_base, 1005 IPP_DEGAMMA_MODE_BYPASS); 1006 } 1007 1008 return result; 1009 } 1010 1011 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1012 { 1013 struct pipe_ctx *odm_pipe; 1014 int opp_cnt = 1; 1015 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 1016 1017 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1018 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 1019 opp_cnt++; 1020 } 1021 1022 if (opp_cnt > 1) 1023 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 1024 pipe_ctx->stream_res.tg, 1025 opp_inst, opp_cnt, 1026 &pipe_ctx->stream->timing); 1027 else 1028 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1029 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1030 } 1031 1032 void dcn20_blank_pixel_data( 1033 struct dc *dc, 1034 struct pipe_ctx *pipe_ctx, 1035 bool blank) 1036 { 1037 struct tg_color black_color = {0}; 1038 struct stream_resource *stream_res = &pipe_ctx->stream_res; 1039 struct dc_stream_state *stream = pipe_ctx->stream; 1040 enum dc_color_space color_space = stream->output_color_space; 1041 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; 1042 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; 1043 struct pipe_ctx *odm_pipe; 1044 int odm_cnt = 1; 1045 1046 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 1047 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; 1048 1049 if (stream->link->test_pattern_enabled) 1050 return; 1051 1052 /* get opp dpg blank color */ 1053 color_space_to_black_color(dc, color_space, &black_color); 1054 1055 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1056 odm_cnt++; 1057 1058 width = width / odm_cnt; 1059 1060 if (blank) { 1061 dc->hwss.set_abm_immediate_disable(pipe_ctx); 1062 1063 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { 1064 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; 1065 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; 1066 } 1067 } else { 1068 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; 1069 } 1070 1071 dc->hwss.set_disp_pattern_generator(dc, 1072 pipe_ctx, 1073 test_pattern, 1074 test_pattern_color_space, 1075 stream->timing.display_color_depth, 1076 &black_color, 1077 width, 1078 height, 1079 0); 1080 1081 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1082 dc->hwss.set_disp_pattern_generator(dc, 1083 odm_pipe, 1084 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ? 1085 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern, 1086 test_pattern_color_space, 1087 stream->timing.display_color_depth, 1088 &black_color, 1089 width, 1090 height, 1091 0); 1092 } 1093 1094 if (!blank && dc->debug.enable_single_display_2to1_odm_policy) { 1095 /* when exiting dynamic ODM need to reinit DPG state for unused pipes */ 1096 struct pipe_ctx *old_odm_pipe = dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx].next_odm_pipe; 1097 1098 odm_pipe = pipe_ctx->next_odm_pipe; 1099 1100 while (old_odm_pipe) { 1101 if (!odm_pipe || old_odm_pipe->pipe_idx != odm_pipe->pipe_idx) 1102 dc->hwss.set_disp_pattern_generator(dc, 1103 old_odm_pipe, 1104 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 1105 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 1106 COLOR_DEPTH_888, 1107 NULL, 1108 0, 1109 0, 1110 0); 1111 old_odm_pipe = old_odm_pipe->next_odm_pipe; 1112 if (odm_pipe) 1113 odm_pipe = odm_pipe->next_odm_pipe; 1114 } 1115 } 1116 1117 if (!blank) 1118 if (stream_res->abm) { 1119 dc->hwss.set_pipe(pipe_ctx); 1120 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level); 1121 } 1122 } 1123 1124 1125 static void dcn20_power_on_plane( 1126 struct dce_hwseq *hws, 1127 struct pipe_ctx *pipe_ctx) 1128 { 1129 DC_LOGGER_INIT(hws->ctx->logger); 1130 if (REG(DC_IP_REQUEST_CNTL)) { 1131 REG_SET(DC_IP_REQUEST_CNTL, 0, 1132 IP_REQUEST_EN, 1); 1133 1134 if (hws->funcs.dpp_pg_control) 1135 hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); 1136 1137 if (hws->funcs.hubp_pg_control) 1138 hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true); 1139 1140 REG_SET(DC_IP_REQUEST_CNTL, 0, 1141 IP_REQUEST_EN, 0); 1142 DC_LOG_DEBUG( 1143 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst); 1144 } 1145 } 1146 1147 static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx, 1148 struct dc_state *context) 1149 { 1150 //if (dc->debug.sanity_checks) { 1151 // dcn10_verify_allow_pstate_change_high(dc); 1152 //} 1153 dcn20_power_on_plane(dc->hwseq, pipe_ctx); 1154 1155 /* enable DCFCLK current DCHUB */ 1156 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); 1157 1158 /* initialize HUBP on power up */ 1159 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); 1160 1161 /* make sure OPP_PIPE_CLOCK_EN = 1 */ 1162 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 1163 pipe_ctx->stream_res.opp, 1164 true); 1165 1166 /* TODO: enable/disable in dm as per update type. 1167 if (plane_state) { 1168 DC_LOG_DC(dc->ctx->logger, 1169 "Pipe:%d 0x%x: addr hi:0x%x, " 1170 "addr low:0x%x, " 1171 "src: %d, %d, %d," 1172 " %d; dst: %d, %d, %d, %d;\n", 1173 pipe_ctx->pipe_idx, 1174 plane_state, 1175 plane_state->address.grph.addr.high_part, 1176 plane_state->address.grph.addr.low_part, 1177 plane_state->src_rect.x, 1178 plane_state->src_rect.y, 1179 plane_state->src_rect.width, 1180 plane_state->src_rect.height, 1181 plane_state->dst_rect.x, 1182 plane_state->dst_rect.y, 1183 plane_state->dst_rect.width, 1184 plane_state->dst_rect.height); 1185 1186 DC_LOG_DC(dc->ctx->logger, 1187 "Pipe %d: width, height, x, y format:%d\n" 1188 "viewport:%d, %d, %d, %d\n" 1189 "recout: %d, %d, %d, %d\n", 1190 pipe_ctx->pipe_idx, 1191 plane_state->format, 1192 pipe_ctx->plane_res.scl_data.viewport.width, 1193 pipe_ctx->plane_res.scl_data.viewport.height, 1194 pipe_ctx->plane_res.scl_data.viewport.x, 1195 pipe_ctx->plane_res.scl_data.viewport.y, 1196 pipe_ctx->plane_res.scl_data.recout.width, 1197 pipe_ctx->plane_res.scl_data.recout.height, 1198 pipe_ctx->plane_res.scl_data.recout.x, 1199 pipe_ctx->plane_res.scl_data.recout.y); 1200 print_rq_dlg_ttu(dc, pipe_ctx); 1201 } 1202 */ 1203 if (dc->vm_pa_config.valid) { 1204 struct vm_system_aperture_param apt; 1205 1206 apt.sys_default.quad_part = 0; 1207 1208 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr; 1209 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr; 1210 1211 // Program system aperture settings 1212 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); 1213 } 1214 1215 if (!pipe_ctx->top_pipe 1216 && pipe_ctx->plane_state 1217 && pipe_ctx->plane_state->flip_int_enabled 1218 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) 1219 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); 1220 1221 // if (dc->debug.sanity_checks) { 1222 // dcn10_verify_allow_pstate_change_high(dc); 1223 // } 1224 } 1225 1226 void dcn20_pipe_control_lock( 1227 struct dc *dc, 1228 struct pipe_ctx *pipe, 1229 bool lock) 1230 { 1231 struct pipe_ctx *temp_pipe; 1232 bool flip_immediate = false; 1233 1234 /* use TG master update lock to lock everything on the TG 1235 * therefore only top pipe need to lock 1236 */ 1237 if (!pipe || pipe->top_pipe) 1238 return; 1239 1240 if (pipe->plane_state != NULL) 1241 flip_immediate = pipe->plane_state->flip_immediate; 1242 1243 if (pipe->stream_res.gsl_group > 0) { 1244 temp_pipe = pipe->bottom_pipe; 1245 while (!flip_immediate && temp_pipe) { 1246 if (temp_pipe->plane_state != NULL) 1247 flip_immediate = temp_pipe->plane_state->flip_immediate; 1248 temp_pipe = temp_pipe->bottom_pipe; 1249 } 1250 } 1251 1252 if (flip_immediate && lock) { 1253 const int TIMEOUT_FOR_FLIP_PENDING = 100000; 1254 int i; 1255 1256 temp_pipe = pipe; 1257 while (temp_pipe) { 1258 if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) { 1259 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) { 1260 if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp)) 1261 break; 1262 udelay(1); 1263 } 1264 1265 /* no reason it should take this long for immediate flips */ 1266 ASSERT(i != TIMEOUT_FOR_FLIP_PENDING); 1267 } 1268 temp_pipe = temp_pipe->bottom_pipe; 1269 } 1270 } 1271 1272 /* In flip immediate and pipe splitting case, we need to use GSL 1273 * for synchronization. Only do setup on locking and on flip type change. 1274 */ 1275 if (lock && (pipe->bottom_pipe != NULL || !flip_immediate)) 1276 if ((flip_immediate && pipe->stream_res.gsl_group == 0) || 1277 (!flip_immediate && pipe->stream_res.gsl_group > 0)) 1278 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate); 1279 1280 if (pipe->plane_state != NULL) 1281 flip_immediate = pipe->plane_state->flip_immediate; 1282 1283 temp_pipe = pipe->bottom_pipe; 1284 while (flip_immediate && temp_pipe) { 1285 if (temp_pipe->plane_state != NULL) 1286 flip_immediate = temp_pipe->plane_state->flip_immediate; 1287 temp_pipe = temp_pipe->bottom_pipe; 1288 } 1289 1290 if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state && 1291 !flip_immediate) 1292 dcn20_setup_gsl_group_as_lock(dc, pipe, false); 1293 1294 if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) { 1295 union dmub_hw_lock_flags hw_locks = { 0 }; 1296 struct dmub_hw_lock_inst_flags inst_flags = { 0 }; 1297 1298 hw_locks.bits.lock_pipe = 1; 1299 inst_flags.otg_inst = pipe->stream_res.tg->inst; 1300 1301 if (pipe->plane_state != NULL) 1302 hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips; 1303 1304 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, 1305 lock, 1306 &hw_locks, 1307 &inst_flags); 1308 } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) { 1309 if (lock) 1310 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); 1311 else 1312 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); 1313 } else { 1314 if (lock) 1315 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1316 else 1317 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1318 } 1319 } 1320 1321 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe) 1322 { 1323 new_pipe->update_flags.raw = 0; 1324 1325 /* If non-phantom pipe is being transitioned to a phantom pipe, 1326 * set disable and return immediately. This is because the pipe 1327 * that was previously in use must be fully disabled before we 1328 * can "enable" it as a phantom pipe (since the OTG will certainly 1329 * be different). The post_unlock sequence will set the correct 1330 * update flags to enable the phantom pipe. 1331 */ 1332 if (old_pipe->plane_state && !old_pipe->plane_state->is_phantom && 1333 new_pipe->plane_state && new_pipe->plane_state->is_phantom) { 1334 new_pipe->update_flags.bits.disable = 1; 1335 return; 1336 } 1337 1338 /* Exit on unchanged, unused pipe */ 1339 if (!old_pipe->plane_state && !new_pipe->plane_state) 1340 return; 1341 /* Detect pipe enable/disable */ 1342 if (!old_pipe->plane_state && new_pipe->plane_state) { 1343 new_pipe->update_flags.bits.enable = 1; 1344 new_pipe->update_flags.bits.mpcc = 1; 1345 new_pipe->update_flags.bits.dppclk = 1; 1346 new_pipe->update_flags.bits.hubp_interdependent = 1; 1347 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1348 new_pipe->update_flags.bits.gamut_remap = 1; 1349 new_pipe->update_flags.bits.scaler = 1; 1350 new_pipe->update_flags.bits.viewport = 1; 1351 new_pipe->update_flags.bits.det_size = 1; 1352 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1353 new_pipe->update_flags.bits.odm = 1; 1354 new_pipe->update_flags.bits.global_sync = 1; 1355 } 1356 return; 1357 } 1358 1359 /* For SubVP we need to unconditionally enable because any phantom pipes are 1360 * always removed then newly added for every full updates whenever SubVP is in use. 1361 * The remove-add sequence of the phantom pipe always results in the pipe 1362 * being blanked in enable_stream_timing (DPG). 1363 */ 1364 if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) 1365 new_pipe->update_flags.bits.enable = 1; 1366 1367 /* Phantom pipes are effectively disabled, if the pipe was previously phantom 1368 * we have to enable 1369 */ 1370 if (old_pipe->plane_state && old_pipe->plane_state->is_phantom && 1371 new_pipe->plane_state && !new_pipe->plane_state->is_phantom) 1372 new_pipe->update_flags.bits.enable = 1; 1373 1374 if (old_pipe->plane_state && !new_pipe->plane_state) { 1375 new_pipe->update_flags.bits.disable = 1; 1376 return; 1377 } 1378 1379 /* Detect plane change */ 1380 if (old_pipe->plane_state != new_pipe->plane_state) { 1381 new_pipe->update_flags.bits.plane_changed = true; 1382 } 1383 1384 /* Detect top pipe only changes */ 1385 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1386 /* Detect odm changes */ 1387 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe 1388 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx) 1389 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe) 1390 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe) 1391 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1392 new_pipe->update_flags.bits.odm = 1; 1393 1394 /* Detect global sync changes */ 1395 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset 1396 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start 1397 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset 1398 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) 1399 new_pipe->update_flags.bits.global_sync = 1; 1400 } 1401 1402 if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb) 1403 new_pipe->update_flags.bits.det_size = 1; 1404 1405 /* 1406 * Detect opp / tg change, only set on change, not on enable 1407 * Assume mpcc inst = pipe index, if not this code needs to be updated 1408 * since mpcc is what is affected by these. In fact all of our sequence 1409 * makes this assumption at the moment with how hubp reset is matched to 1410 * same index mpcc reset. 1411 */ 1412 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1413 new_pipe->update_flags.bits.opp_changed = 1; 1414 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg) 1415 new_pipe->update_flags.bits.tg_changed = 1; 1416 1417 /* 1418 * Detect mpcc blending changes, only dpp inst and opp matter here, 1419 * mpccs getting removed/inserted update connected ones during their own 1420 * programming 1421 */ 1422 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp 1423 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1424 new_pipe->update_flags.bits.mpcc = 1; 1425 1426 /* Detect dppclk change */ 1427 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) 1428 new_pipe->update_flags.bits.dppclk = 1; 1429 1430 /* Check for scl update */ 1431 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data))) 1432 new_pipe->update_flags.bits.scaler = 1; 1433 /* Check for vp update */ 1434 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect)) 1435 || memcmp(&old_pipe->plane_res.scl_data.viewport_c, 1436 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect))) 1437 new_pipe->update_flags.bits.viewport = 1; 1438 1439 /* Detect dlg/ttu/rq updates */ 1440 { 1441 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs; 1442 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs; 1443 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs; 1444 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs; 1445 1446 /* Detect pipe interdependent updates */ 1447 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch || 1448 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch || 1449 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c || 1450 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank || 1451 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank || 1452 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip || 1453 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip || 1454 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l || 1455 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c || 1456 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l || 1457 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l || 1458 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c || 1459 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l || 1460 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c || 1461 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 || 1462 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 || 1463 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank || 1464 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) { 1465 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch; 1466 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch; 1467 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c; 1468 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank; 1469 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank; 1470 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip; 1471 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip; 1472 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l; 1473 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c; 1474 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l; 1475 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l; 1476 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c; 1477 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l; 1478 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c; 1479 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0; 1480 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1; 1481 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank; 1482 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip; 1483 new_pipe->update_flags.bits.hubp_interdependent = 1; 1484 } 1485 /* Detect any other updates to ttu/rq/dlg */ 1486 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) || 1487 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) || 1488 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs))) 1489 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1490 } 1491 } 1492 1493 static void dcn20_update_dchubp_dpp( 1494 struct dc *dc, 1495 struct pipe_ctx *pipe_ctx, 1496 struct dc_state *context) 1497 { 1498 struct dce_hwseq *hws = dc->hwseq; 1499 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1500 struct dpp *dpp = pipe_ctx->plane_res.dpp; 1501 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1502 struct dccg *dccg = dc->res_pool->dccg; 1503 bool viewport_changed = false; 1504 1505 if (pipe_ctx->update_flags.bits.dppclk) 1506 dpp->funcs->dpp_dppclk_control(dpp, false, true); 1507 1508 if (pipe_ctx->update_flags.bits.enable) 1509 dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz); 1510 1511 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG 1512 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. 1513 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG 1514 */ 1515 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) { 1516 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst); 1517 1518 hubp->funcs->hubp_setup( 1519 hubp, 1520 &pipe_ctx->dlg_regs, 1521 &pipe_ctx->ttu_regs, 1522 &pipe_ctx->rq_regs, 1523 &pipe_ctx->pipe_dlg_param); 1524 1525 if (hubp->funcs->set_unbounded_requesting) 1526 hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req); 1527 } 1528 if (pipe_ctx->update_flags.bits.hubp_interdependent) 1529 hubp->funcs->hubp_setup_interdependent( 1530 hubp, 1531 &pipe_ctx->dlg_regs, 1532 &pipe_ctx->ttu_regs); 1533 1534 if (pipe_ctx->update_flags.bits.enable || 1535 pipe_ctx->update_flags.bits.plane_changed || 1536 plane_state->update_flags.bits.bpp_change || 1537 plane_state->update_flags.bits.input_csc_change || 1538 plane_state->update_flags.bits.color_space_change || 1539 plane_state->update_flags.bits.coeff_reduction_change) { 1540 struct dc_bias_and_scale bns_params = {0}; 1541 1542 // program the input csc 1543 dpp->funcs->dpp_setup(dpp, 1544 plane_state->format, 1545 EXPANSION_MODE_ZERO, 1546 plane_state->input_csc_color_matrix, 1547 plane_state->color_space, 1548 NULL); 1549 1550 if (dpp->funcs->dpp_program_bias_and_scale) { 1551 //TODO :for CNVC set scale and bias registers if necessary 1552 build_prescale_params(&bns_params, plane_state); 1553 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); 1554 } 1555 } 1556 1557 if (pipe_ctx->update_flags.bits.mpcc 1558 || pipe_ctx->update_flags.bits.plane_changed 1559 || plane_state->update_flags.bits.global_alpha_change 1560 || plane_state->update_flags.bits.per_pixel_alpha_change) { 1561 // MPCC inst is equal to pipe index in practice 1562 int mpcc_inst = hubp->inst; 1563 int opp_inst; 1564 int opp_count = dc->res_pool->pipe_count; 1565 1566 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) { 1567 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) { 1568 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); 1569 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; 1570 break; 1571 } 1572 } 1573 hws->funcs.update_mpcc(dc, pipe_ctx); 1574 } 1575 1576 if (pipe_ctx->update_flags.bits.scaler || 1577 plane_state->update_flags.bits.scaling_change || 1578 plane_state->update_flags.bits.position_change || 1579 plane_state->update_flags.bits.per_pixel_alpha_change || 1580 pipe_ctx->stream->update_flags.bits.scaling) { 1581 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; 1582 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP); 1583 /* scaler configuration */ 1584 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( 1585 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); 1586 } 1587 1588 if (pipe_ctx->update_flags.bits.viewport || 1589 (context == dc->current_state && plane_state->update_flags.bits.position_change) || 1590 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) || 1591 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) { 1592 1593 hubp->funcs->mem_program_viewport( 1594 hubp, 1595 &pipe_ctx->plane_res.scl_data.viewport, 1596 &pipe_ctx->plane_res.scl_data.viewport_c); 1597 viewport_changed = true; 1598 } 1599 1600 /* Any updates are handled in dc interface, just need to apply existing for plane enable */ 1601 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || 1602 pipe_ctx->update_flags.bits.scaler || viewport_changed == true) && 1603 pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { 1604 dc->hwss.set_cursor_position(pipe_ctx); 1605 dc->hwss.set_cursor_attribute(pipe_ctx); 1606 1607 if (dc->hwss.set_cursor_sdr_white_level) 1608 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 1609 } 1610 1611 /* Any updates are handled in dc interface, just need 1612 * to apply existing for plane enable / opp change */ 1613 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed 1614 || pipe_ctx->update_flags.bits.plane_changed 1615 || pipe_ctx->stream->update_flags.bits.gamut_remap 1616 || pipe_ctx->stream->update_flags.bits.out_csc) { 1617 /* dpp/cm gamut remap*/ 1618 dc->hwss.program_gamut_remap(pipe_ctx); 1619 1620 /*call the dcn2 method which uses mpc csc*/ 1621 dc->hwss.program_output_csc(dc, 1622 pipe_ctx, 1623 pipe_ctx->stream->output_color_space, 1624 pipe_ctx->stream->csc_color_matrix.matrix, 1625 hubp->opp_id); 1626 } 1627 1628 if (pipe_ctx->update_flags.bits.enable || 1629 pipe_ctx->update_flags.bits.plane_changed || 1630 pipe_ctx->update_flags.bits.opp_changed || 1631 plane_state->update_flags.bits.pixel_format_change || 1632 plane_state->update_flags.bits.horizontal_mirror_change || 1633 plane_state->update_flags.bits.rotation_change || 1634 plane_state->update_flags.bits.swizzle_change || 1635 plane_state->update_flags.bits.dcc_change || 1636 plane_state->update_flags.bits.bpp_change || 1637 plane_state->update_flags.bits.scaling_change || 1638 plane_state->update_flags.bits.plane_size_change) { 1639 struct plane_size size = plane_state->plane_size; 1640 1641 size.surface_size = pipe_ctx->plane_res.scl_data.viewport; 1642 hubp->funcs->hubp_program_surface_config( 1643 hubp, 1644 plane_state->format, 1645 &plane_state->tiling_info, 1646 &size, 1647 plane_state->rotation, 1648 &plane_state->dcc, 1649 plane_state->horizontal_mirror, 1650 0); 1651 hubp->power_gated = false; 1652 } 1653 1654 if (pipe_ctx->update_flags.bits.enable || 1655 pipe_ctx->update_flags.bits.plane_changed || 1656 plane_state->update_flags.bits.addr_update) 1657 hws->funcs.update_plane_addr(dc, pipe_ctx); 1658 1659 if (pipe_ctx->update_flags.bits.enable) 1660 hubp->funcs->set_blank(hubp, false); 1661 /* If the stream paired with this plane is phantom, the plane is also phantom */ 1662 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM 1663 && hubp->funcs->phantom_hubp_post_enable) 1664 hubp->funcs->phantom_hubp_post_enable(hubp); 1665 } 1666 1667 static int calculate_vready_offset_for_group(struct pipe_ctx *pipe) 1668 { 1669 struct pipe_ctx *other_pipe; 1670 int vready_offset = pipe->pipe_dlg_param.vready_offset; 1671 1672 /* Always use the largest vready_offset of all connected pipes */ 1673 for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) { 1674 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1675 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1676 } 1677 for (other_pipe = pipe->top_pipe; other_pipe != NULL; other_pipe = other_pipe->top_pipe) { 1678 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1679 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1680 } 1681 for (other_pipe = pipe->next_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->next_odm_pipe) { 1682 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1683 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1684 } 1685 for (other_pipe = pipe->prev_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->prev_odm_pipe) { 1686 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1687 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1688 } 1689 1690 return vready_offset; 1691 } 1692 1693 static void dcn20_program_pipe( 1694 struct dc *dc, 1695 struct pipe_ctx *pipe_ctx, 1696 struct dc_state *context) 1697 { 1698 struct dce_hwseq *hws = dc->hwseq; 1699 /* Only need to unblank on top pipe */ 1700 1701 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level) 1702 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) 1703 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible); 1704 1705 /* Only update TG on top pipe */ 1706 if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe 1707 && !pipe_ctx->prev_odm_pipe) { 1708 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1709 pipe_ctx->stream_res.tg, 1710 calculate_vready_offset_for_group(pipe_ctx), 1711 pipe_ctx->pipe_dlg_param.vstartup_start, 1712 pipe_ctx->pipe_dlg_param.vupdate_offset, 1713 pipe_ctx->pipe_dlg_param.vupdate_width); 1714 1715 if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1716 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); 1717 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); 1718 } 1719 1720 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1721 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true); 1722 1723 if (hws->funcs.setup_vupdate_interrupt) 1724 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1725 } 1726 1727 if (pipe_ctx->update_flags.bits.odm) 1728 hws->funcs.update_odm(dc, context, pipe_ctx); 1729 1730 if (pipe_ctx->update_flags.bits.enable) { 1731 dcn20_enable_plane(dc, pipe_ctx, context); 1732 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes) 1733 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub); 1734 } 1735 1736 if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size) 1737 dc->res_pool->hubbub->funcs->program_det_size( 1738 dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb); 1739 1740 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) 1741 dcn20_update_dchubp_dpp(dc, pipe_ctx, context); 1742 1743 if (pipe_ctx->update_flags.bits.enable 1744 || pipe_ctx->plane_state->update_flags.bits.hdr_mult) 1745 hws->funcs.set_hdr_multiplier(pipe_ctx); 1746 1747 if (pipe_ctx->update_flags.bits.enable || 1748 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 1749 pipe_ctx->plane_state->update_flags.bits.gamma_change) 1750 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 1751 1752 /* dcn10_translate_regamma_to_hw_format takes 750us to finish 1753 * only do gamma programming for powering on, internal memcmp to avoid 1754 * updating on slave planes 1755 */ 1756 if (pipe_ctx->update_flags.bits.enable || 1757 pipe_ctx->update_flags.bits.plane_changed || 1758 pipe_ctx->stream->update_flags.bits.out_tf || 1759 pipe_ctx->plane_state->update_flags.bits.output_tf_change) 1760 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 1761 1762 /* If the pipe has been enabled or has a different opp, we 1763 * should reprogram the fmt. This deals with cases where 1764 * interation between mpc and odm combine on different streams 1765 * causes a different pipe to be chosen to odm combine with. 1766 */ 1767 if (pipe_ctx->update_flags.bits.enable 1768 || pipe_ctx->update_flags.bits.opp_changed) { 1769 1770 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1771 pipe_ctx->stream_res.opp, 1772 COLOR_SPACE_YCBCR601, 1773 pipe_ctx->stream->timing.display_color_depth, 1774 pipe_ctx->stream->signal); 1775 1776 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1777 pipe_ctx->stream_res.opp, 1778 &pipe_ctx->stream->bit_depth_params, 1779 &pipe_ctx->stream->clamping); 1780 } 1781 } 1782 1783 void dcn20_program_front_end_for_ctx( 1784 struct dc *dc, 1785 struct dc_state *context) 1786 { 1787 int i; 1788 struct dce_hwseq *hws = dc->hwseq; 1789 DC_LOGGER_INIT(dc->ctx->logger); 1790 1791 /* Carry over GSL groups in case the context is changing. */ 1792 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1793 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1794 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 1795 1796 if (pipe_ctx->stream == old_pipe_ctx->stream) 1797 pipe_ctx->stream_res.gsl_group = old_pipe_ctx->stream_res.gsl_group; 1798 } 1799 1800 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) { 1801 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1802 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1803 1804 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) { 1805 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips); 1806 /*turn off triple buffer for full update*/ 1807 dc->hwss.program_triplebuffer( 1808 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); 1809 } 1810 } 1811 } 1812 1813 /* Set pipe update flags and lock pipes */ 1814 for (i = 0; i < dc->res_pool->pipe_count; i++) 1815 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i], 1816 &context->res_ctx.pipe_ctx[i]); 1817 1818 /* When disabling phantom pipes, turn on phantom OTG first (so we can get double 1819 * buffer updates properly) 1820 */ 1821 for (i = 0; i < dc->res_pool->pipe_count; i++) 1822 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1823 && dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { 1824 struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg; 1825 1826 if (tg->funcs->enable_crtc) 1827 tg->funcs->enable_crtc(tg); 1828 } 1829 1830 /* OTG blank before disabling all front ends */ 1831 for (i = 0; i < dc->res_pool->pipe_count; i++) 1832 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1833 && !context->res_ctx.pipe_ctx[i].top_pipe 1834 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe 1835 && context->res_ctx.pipe_ctx[i].stream) 1836 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); 1837 1838 1839 /* Disconnect mpcc */ 1840 for (i = 0; i < dc->res_pool->pipe_count; i++) 1841 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1842 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) { 1843 struct hubbub *hubbub = dc->res_pool->hubbub; 1844 1845 /* Phantom pipe DET should be 0, but if a pipe in use is being transitioned to phantom 1846 * then we want to do the programming here (effectively it's being disabled). If we do 1847 * the programming later the DET won't be updated until the OTG for the phantom pipe is 1848 * turned on (i.e. in an MCLK switch) which can come in too late and cause issues with 1849 * DET allocation. 1850 */ 1851 if (hubbub->funcs->program_det_size && (context->res_ctx.pipe_ctx[i].update_flags.bits.disable || 1852 (context->res_ctx.pipe_ctx[i].plane_state && context->res_ctx.pipe_ctx[i].plane_state->is_phantom))) 1853 hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0); 1854 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1855 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); 1856 } 1857 1858 /* 1859 * Program all updated pipes, order matters for mpcc setup. Start with 1860 * top pipe and program all pipes that follow in order 1861 */ 1862 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1863 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1864 1865 if (pipe->plane_state && !pipe->top_pipe) { 1866 while (pipe) { 1867 if (hws->funcs.program_pipe) 1868 hws->funcs.program_pipe(dc, pipe, context); 1869 else { 1870 /* Don't program phantom pipes in the regular front end programming sequence. 1871 * There is an MPO transition case where a pipe being used by a video plane is 1872 * transitioned directly to be a phantom pipe when closing the MPO video. However 1873 * the phantom pipe will program a new HUBP_VTG_SEL (update takes place right away), 1874 * but the MPO still exists until the double buffered update of the main pipe so we 1875 * will get a frame of underflow if the phantom pipe is programmed here. 1876 */ 1877 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) 1878 dcn20_program_pipe(dc, pipe, context); 1879 } 1880 1881 pipe = pipe->bottom_pipe; 1882 } 1883 } 1884 /* Program secondary blending tree and writeback pipes */ 1885 pipe = &context->res_ctx.pipe_ctx[i]; 1886 if (!pipe->top_pipe && !pipe->prev_odm_pipe 1887 && pipe->stream && pipe->stream->num_wb_info > 0 1888 && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw) 1889 || pipe->stream->update_flags.raw) 1890 && hws->funcs.program_all_writeback_pipes_in_tree) 1891 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context); 1892 1893 /* Avoid underflow by check of pipe line read when adding 2nd plane. */ 1894 if (hws->wa.wait_hubpret_read_start_during_mpo_transition && 1895 !pipe->top_pipe && 1896 pipe->stream && 1897 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start && 1898 dc->current_state->stream_status[0].plane_count == 1 && 1899 context->stream_status[0].plane_count > 1) { 1900 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp); 1901 } 1902 1903 /* when dynamic ODM is active, pipes must be reconfigured when all planes are 1904 * disabled, as some transitions will leave software and hardware state 1905 * mismatched. 1906 */ 1907 if (dc->debug.enable_single_display_2to1_odm_policy && 1908 pipe->stream && 1909 pipe->update_flags.bits.disable && 1910 !pipe->prev_odm_pipe && 1911 hws->funcs.update_odm) 1912 hws->funcs.update_odm(dc, context, pipe); 1913 } 1914 } 1915 1916 void dcn20_post_unlock_program_front_end( 1917 struct dc *dc, 1918 struct dc_state *context) 1919 { 1920 int i; 1921 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100; 1922 struct dce_hwseq *hwseq = dc->hwseq; 1923 1924 DC_LOGGER_INIT(dc->ctx->logger); 1925 1926 for (i = 0; i < dc->res_pool->pipe_count; i++) 1927 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1928 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1929 1930 /* 1931 * If we are enabling a pipe, we need to wait for pending clear as this is a critical 1932 * part of the enable operation otherwise, DM may request an immediate flip which 1933 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which 1934 * is unsupported on DCN. 1935 */ 1936 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1937 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1938 // Don't check flip pending on phantom pipes 1939 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable && 1940 pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1941 struct hubp *hubp = pipe->plane_res.hubp; 1942 int j = 0; 1943 1944 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000 1945 && hubp->funcs->hubp_is_flip_pending(hubp); j++) 1946 udelay(1); 1947 } 1948 } 1949 1950 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1951 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1952 1953 if (pipe->plane_state && !pipe->top_pipe) { 1954 /* Program phantom pipe here to prevent a frame of underflow in the MPO transition 1955 * case (if a pipe being used for a video plane transitions to a phantom pipe, it 1956 * can underflow due to HUBP_VTG_SEL programming if done in the regular front end 1957 * programming sequence). 1958 */ 1959 while (pipe) { 1960 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1961 /* When turning on the phantom pipe we want to run through the 1962 * entire enable sequence, so apply all the "enable" flags. 1963 */ 1964 if (dc->hwss.apply_update_flags_for_phantom) 1965 dc->hwss.apply_update_flags_for_phantom(pipe); 1966 if (dc->hwss.update_phantom_vp_position) 1967 dc->hwss.update_phantom_vp_position(dc, context, pipe); 1968 dcn20_program_pipe(dc, pipe, context); 1969 } 1970 pipe = pipe->bottom_pipe; 1971 } 1972 } 1973 } 1974 1975 /* Only program the MALL registers after all the main and phantom pipes 1976 * are done programming. 1977 */ 1978 if (hwseq->funcs.program_mall_pipe_config) 1979 hwseq->funcs.program_mall_pipe_config(dc, context); 1980 1981 /* WA to apply WM setting*/ 1982 if (hwseq->wa.DEGVIDCN21) 1983 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub); 1984 1985 1986 /* WA for stutter underflow during MPO transitions when adding 2nd plane */ 1987 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) { 1988 1989 if (dc->current_state->stream_status[0].plane_count == 1 && 1990 context->stream_status[0].plane_count > 1) { 1991 1992 struct timing_generator *tg = dc->res_pool->timing_generators[0]; 1993 1994 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false); 1995 1996 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true; 1997 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg); 1998 } 1999 } 2000 } 2001 2002 void dcn20_prepare_bandwidth( 2003 struct dc *dc, 2004 struct dc_state *context) 2005 { 2006 struct hubbub *hubbub = dc->res_pool->hubbub; 2007 unsigned int compbuf_size_kb = 0; 2008 unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns; 2009 unsigned int i; 2010 2011 dc->clk_mgr->funcs->update_clocks( 2012 dc->clk_mgr, 2013 context, 2014 false); 2015 2016 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2017 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2018 2019 // At optimize don't restore the original watermark value 2020 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) { 2021 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; 2022 break; 2023 } 2024 } 2025 2026 /* program dchubbub watermarks */ 2027 dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub, 2028 &context->bw_ctx.bw.dcn.watermarks, 2029 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 2030 false); 2031 2032 // Restore the real watermark so we can commit the value to DMCUB 2033 // DMCUB uses the "original" watermark value in SubVP MCLK switch 2034 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a; 2035 2036 /* decrease compbuf size */ 2037 if (hubbub->funcs->program_compbuf_size) { 2038 if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes) { 2039 compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes; 2040 dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.dml.ip.min_comp_buffer_size_kbytes); 2041 } else { 2042 compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb; 2043 dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.bw.dcn.compbuf_size_kb); 2044 } 2045 2046 hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false); 2047 } 2048 } 2049 2050 void dcn20_optimize_bandwidth( 2051 struct dc *dc, 2052 struct dc_state *context) 2053 { 2054 struct hubbub *hubbub = dc->res_pool->hubbub; 2055 int i; 2056 2057 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2058 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2059 2060 // At optimize don't need to restore the original watermark value 2061 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) { 2062 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; 2063 break; 2064 } 2065 } 2066 2067 /* program dchubbub watermarks */ 2068 hubbub->funcs->program_watermarks(hubbub, 2069 &context->bw_ctx.bw.dcn.watermarks, 2070 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 2071 true); 2072 2073 if (dc->clk_mgr->dc_mode_softmax_enabled) 2074 if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && 2075 context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) 2076 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk); 2077 2078 /* increase compbuf size */ 2079 if (hubbub->funcs->program_compbuf_size) 2080 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true); 2081 2082 dc->clk_mgr->funcs->update_clocks( 2083 dc->clk_mgr, 2084 context, 2085 true); 2086 if (dc_extended_blank_supported(dc) && context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) { 2087 for (i = 0; i < dc->res_pool->pipe_count; ++i) { 2088 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2089 2090 if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank 2091 && pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max 2092 && pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total) 2093 pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp, 2094 pipe_ctx->dlg_regs.optimized_min_dst_y_next_start); 2095 } 2096 } 2097 } 2098 2099 bool dcn20_update_bandwidth( 2100 struct dc *dc, 2101 struct dc_state *context) 2102 { 2103 int i; 2104 struct dce_hwseq *hws = dc->hwseq; 2105 2106 /* recalculate DML parameters */ 2107 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) 2108 return false; 2109 2110 /* apply updated bandwidth parameters */ 2111 dc->hwss.prepare_bandwidth(dc, context); 2112 2113 /* update hubp configs for all pipes */ 2114 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2115 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2116 2117 if (pipe_ctx->plane_state == NULL) 2118 continue; 2119 2120 if (pipe_ctx->top_pipe == NULL) { 2121 bool blank = !is_pipe_tree_visible(pipe_ctx); 2122 2123 pipe_ctx->stream_res.tg->funcs->program_global_sync( 2124 pipe_ctx->stream_res.tg, 2125 calculate_vready_offset_for_group(pipe_ctx), 2126 pipe_ctx->pipe_dlg_param.vstartup_start, 2127 pipe_ctx->pipe_dlg_param.vupdate_offset, 2128 pipe_ctx->pipe_dlg_param.vupdate_width); 2129 2130 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 2131 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false); 2132 2133 if (pipe_ctx->prev_odm_pipe == NULL) 2134 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank); 2135 2136 if (hws->funcs.setup_vupdate_interrupt) 2137 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 2138 } 2139 2140 pipe_ctx->plane_res.hubp->funcs->hubp_setup( 2141 pipe_ctx->plane_res.hubp, 2142 &pipe_ctx->dlg_regs, 2143 &pipe_ctx->ttu_regs, 2144 &pipe_ctx->rq_regs, 2145 &pipe_ctx->pipe_dlg_param); 2146 } 2147 2148 return true; 2149 } 2150 2151 void dcn20_enable_writeback( 2152 struct dc *dc, 2153 struct dc_writeback_info *wb_info, 2154 struct dc_state *context) 2155 { 2156 struct dwbc *dwb; 2157 struct mcif_wb *mcif_wb; 2158 struct timing_generator *optc; 2159 2160 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 2161 ASSERT(wb_info->wb_enabled); 2162 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 2163 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 2164 2165 /* set the OPTC source mux */ 2166 optc = dc->res_pool->timing_generators[dwb->otg_inst]; 2167 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); 2168 /* set MCIF_WB buffer and arbitration configuration */ 2169 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 2170 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 2171 /* Enable MCIF_WB */ 2172 mcif_wb->funcs->enable_mcif(mcif_wb); 2173 /* Enable DWB */ 2174 dwb->funcs->enable(dwb, &wb_info->dwb_params); 2175 /* TODO: add sequence to enable/disable warmup */ 2176 } 2177 2178 void dcn20_disable_writeback( 2179 struct dc *dc, 2180 unsigned int dwb_pipe_inst) 2181 { 2182 struct dwbc *dwb; 2183 struct mcif_wb *mcif_wb; 2184 2185 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); 2186 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; 2187 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; 2188 2189 dwb->funcs->disable(dwb); 2190 mcif_wb->funcs->disable_mcif(mcif_wb); 2191 } 2192 2193 bool dcn20_wait_for_blank_complete( 2194 struct output_pixel_processor *opp) 2195 { 2196 int counter; 2197 2198 for (counter = 0; counter < 1000; counter++) { 2199 if (opp->funcs->dpg_is_blanked(opp)) 2200 break; 2201 2202 udelay(100); 2203 } 2204 2205 if (counter == 1000) { 2206 dm_error("DC: failed to blank crtc!\n"); 2207 return false; 2208 } 2209 2210 return true; 2211 } 2212 2213 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) 2214 { 2215 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2216 2217 if (!hubp) 2218 return false; 2219 return hubp->funcs->dmdata_status_done(hubp); 2220 } 2221 2222 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 2223 { 2224 struct dce_hwseq *hws = dc->hwseq; 2225 2226 if (pipe_ctx->stream_res.dsc) { 2227 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2228 2229 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); 2230 while (odm_pipe) { 2231 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true); 2232 odm_pipe = odm_pipe->next_odm_pipe; 2233 } 2234 } 2235 } 2236 2237 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 2238 { 2239 struct dce_hwseq *hws = dc->hwseq; 2240 2241 if (pipe_ctx->stream_res.dsc) { 2242 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2243 2244 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false); 2245 while (odm_pipe) { 2246 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false); 2247 odm_pipe = odm_pipe->next_odm_pipe; 2248 } 2249 } 2250 } 2251 2252 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) 2253 { 2254 struct dc_dmdata_attributes attr = { 0 }; 2255 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2256 2257 attr.dmdata_mode = DMDATA_HW_MODE; 2258 attr.dmdata_size = 2259 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; 2260 attr.address.quad_part = 2261 pipe_ctx->stream->dmdata_address.quad_part; 2262 attr.dmdata_dl_delta = 0; 2263 attr.dmdata_qos_mode = 0; 2264 attr.dmdata_qos_level = 0; 2265 attr.dmdata_repeat = 1; /* always repeat */ 2266 attr.dmdata_updated = 1; 2267 attr.dmdata_sw_data = NULL; 2268 2269 hubp->funcs->dmdata_set_attributes(hubp, &attr); 2270 } 2271 2272 void dcn20_init_vm_ctx( 2273 struct dce_hwseq *hws, 2274 struct dc *dc, 2275 struct dc_virtual_addr_space_config *va_config, 2276 int vmid) 2277 { 2278 struct dcn_hubbub_virt_addr_config config; 2279 2280 if (vmid == 0) { 2281 ASSERT(0); /* VMID cannot be 0 for vm context */ 2282 return; 2283 } 2284 2285 config.page_table_start_addr = va_config->page_table_start_addr; 2286 config.page_table_end_addr = va_config->page_table_end_addr; 2287 config.page_table_block_size = va_config->page_table_block_size_in_bytes; 2288 config.page_table_depth = va_config->page_table_depth; 2289 config.page_table_base_addr = va_config->page_table_base_addr; 2290 2291 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); 2292 } 2293 2294 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 2295 { 2296 struct dcn_hubbub_phys_addr_config config; 2297 2298 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 2299 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 2300 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 2301 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 2302 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 2303 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 2304 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 2305 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 2306 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 2307 config.page_table_default_page_addr = pa_config->page_table_default_page_addr; 2308 2309 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 2310 } 2311 2312 static bool patch_address_for_sbs_tb_stereo( 2313 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) 2314 { 2315 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2316 bool sec_split = pipe_ctx->top_pipe && 2317 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; 2318 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && 2319 (pipe_ctx->stream->timing.timing_3d_format == 2320 TIMING_3D_FORMAT_SIDE_BY_SIDE || 2321 pipe_ctx->stream->timing.timing_3d_format == 2322 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { 2323 *addr = plane_state->address.grph_stereo.left_addr; 2324 plane_state->address.grph_stereo.left_addr = 2325 plane_state->address.grph_stereo.right_addr; 2326 return true; 2327 } 2328 2329 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && 2330 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { 2331 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; 2332 plane_state->address.grph_stereo.right_addr = 2333 plane_state->address.grph_stereo.left_addr; 2334 plane_state->address.grph_stereo.right_meta_addr = 2335 plane_state->address.grph_stereo.left_meta_addr; 2336 } 2337 return false; 2338 } 2339 2340 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) 2341 { 2342 bool addr_patched = false; 2343 PHYSICAL_ADDRESS_LOC addr; 2344 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2345 2346 if (plane_state == NULL) 2347 return; 2348 2349 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); 2350 2351 // Call Helper to track VMID use 2352 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); 2353 2354 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( 2355 pipe_ctx->plane_res.hubp, 2356 &plane_state->address, 2357 plane_state->flip_immediate); 2358 2359 plane_state->status.requested_address = plane_state->address; 2360 2361 if (plane_state->flip_immediate) 2362 plane_state->status.current_address = plane_state->address; 2363 2364 if (addr_patched) 2365 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; 2366 } 2367 2368 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, 2369 struct dc_link_settings *link_settings) 2370 { 2371 struct encoder_unblank_param params = {0}; 2372 struct dc_stream_state *stream = pipe_ctx->stream; 2373 struct dc_link *link = stream->link; 2374 struct dce_hwseq *hws = link->dc->hwseq; 2375 struct pipe_ctx *odm_pipe; 2376 2377 params.opp_cnt = 1; 2378 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 2379 params.opp_cnt++; 2380 } 2381 /* only 3 items below are used by unblank */ 2382 params.timing = pipe_ctx->stream->timing; 2383 2384 params.link_settings.link_rate = link_settings->link_rate; 2385 2386 if (is_dp_128b_132b_signal(pipe_ctx)) { 2387 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 2388 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 2389 pipe_ctx->stream_res.hpo_dp_stream_enc, 2390 pipe_ctx->stream_res.tg->inst); 2391 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 2392 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1) 2393 params.timing.pix_clk_100hz /= 2; 2394 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 2395 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1); 2396 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 2397 } 2398 2399 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 2400 hws->funcs.edp_backlight_control(link, true); 2401 } 2402 } 2403 2404 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx) 2405 { 2406 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2407 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx); 2408 2409 if (start_line < 0) 2410 start_line = 0; 2411 2412 if (tg->funcs->setup_vertical_interrupt2) 2413 tg->funcs->setup_vertical_interrupt2(tg, start_line); 2414 } 2415 2416 static void dcn20_reset_back_end_for_pipe( 2417 struct dc *dc, 2418 struct pipe_ctx *pipe_ctx, 2419 struct dc_state *context) 2420 { 2421 int i; 2422 struct dc_link *link = pipe_ctx->stream->link; 2423 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2424 2425 DC_LOGGER_INIT(dc->ctx->logger); 2426 if (pipe_ctx->stream_res.stream_enc == NULL) { 2427 pipe_ctx->stream = NULL; 2428 return; 2429 } 2430 2431 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 2432 /* DPMS may already disable or */ 2433 /* dpms_off status is incorrect due to fastboot 2434 * feature. When system resume from S4 with second 2435 * screen only, the dpms_off would be true but 2436 * VBIOS lit up eDP, so check link status too. 2437 */ 2438 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 2439 core_link_disable_stream(pipe_ctx); 2440 else if (pipe_ctx->stream_res.audio) 2441 dc->hwss.disable_audio_stream(pipe_ctx); 2442 2443 /* free acquired resources */ 2444 if (pipe_ctx->stream_res.audio) { 2445 /*disable az_endpoint*/ 2446 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 2447 2448 /*free audio*/ 2449 if (dc->caps.dynamic_audio == true) { 2450 /*we have to dynamic arbitrate the audio endpoints*/ 2451 /*we free the resource, need reset is_audio_acquired*/ 2452 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 2453 pipe_ctx->stream_res.audio, false); 2454 pipe_ctx->stream_res.audio = NULL; 2455 } 2456 } 2457 } 2458 else if (pipe_ctx->stream_res.dsc) { 2459 dp_set_dsc_enable(pipe_ctx, false); 2460 } 2461 2462 /* by upper caller loop, parent pipe: pipe0, will be reset last. 2463 * back end share by all pipes and will be disable only when disable 2464 * parent pipe. 2465 */ 2466 if (pipe_ctx->top_pipe == NULL) { 2467 2468 dc->hwss.set_abm_immediate_disable(pipe_ctx); 2469 2470 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 2471 2472 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 2473 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 2474 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 2475 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 2476 2477 if (pipe_ctx->stream_res.tg->funcs->set_drr) 2478 pipe_ctx->stream_res.tg->funcs->set_drr( 2479 pipe_ctx->stream_res.tg, NULL); 2480 /* TODO - convert symclk_ref_cnts for otg to a bit map to solve 2481 * the case where the same symclk is shared across multiple otg 2482 * instances 2483 */ 2484 link->phy_state.symclk_ref_cnts.otg = 0; 2485 if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) { 2486 link_hwss->disable_link_output(link, 2487 &pipe_ctx->link_res, pipe_ctx->stream->signal); 2488 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 2489 } 2490 } 2491 2492 for (i = 0; i < dc->res_pool->pipe_count; i++) 2493 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) 2494 break; 2495 2496 if (i == dc->res_pool->pipe_count) 2497 return; 2498 2499 pipe_ctx->stream = NULL; 2500 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 2501 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 2502 } 2503 2504 void dcn20_reset_hw_ctx_wrap( 2505 struct dc *dc, 2506 struct dc_state *context) 2507 { 2508 int i; 2509 struct dce_hwseq *hws = dc->hwseq; 2510 2511 /* Reset Back End*/ 2512 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 2513 struct pipe_ctx *pipe_ctx_old = 2514 &dc->current_state->res_ctx.pipe_ctx[i]; 2515 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2516 2517 if (!pipe_ctx_old->stream) 2518 continue; 2519 2520 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 2521 continue; 2522 2523 if (!pipe_ctx->stream || 2524 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 2525 struct clock_source *old_clk = pipe_ctx_old->clock_source; 2526 2527 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 2528 if (hws->funcs.enable_stream_gating) 2529 hws->funcs.enable_stream_gating(dc, pipe_ctx_old); 2530 if (old_clk) 2531 old_clk->funcs->cs_power_down(old_clk); 2532 } 2533 } 2534 } 2535 2536 void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id) 2537 { 2538 struct mpc *mpc = dc->res_pool->mpc; 2539 2540 // input to MPCC is always RGB, by default leave black_color at 0 2541 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) 2542 get_hdr_visual_confirm_color(pipe_ctx, color); 2543 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) 2544 get_surface_visual_confirm_color(pipe_ctx, color); 2545 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) 2546 get_mpctree_visual_confirm_color(pipe_ctx, color); 2547 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE) 2548 get_surface_tile_visual_confirm_color(pipe_ctx, color); 2549 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP) 2550 get_subvp_visual_confirm_color(dc, pipe_ctx, color); 2551 2552 if (mpc->funcs->set_bg_color) { 2553 memcpy(&pipe_ctx->plane_state->visual_confirm_color, color, sizeof(struct tg_color)); 2554 mpc->funcs->set_bg_color(mpc, color, mpcc_id); 2555 } 2556 } 2557 2558 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 2559 { 2560 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2561 struct mpcc_blnd_cfg blnd_cfg = {0}; 2562 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; 2563 int mpcc_id; 2564 struct mpcc *new_mpcc; 2565 struct mpc *mpc = dc->res_pool->mpc; 2566 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); 2567 2568 blnd_cfg.overlap_only = false; 2569 blnd_cfg.global_gain = 0xff; 2570 2571 if (per_pixel_alpha) { 2572 blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha; 2573 if (pipe_ctx->plane_state->global_alpha) { 2574 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; 2575 blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value; 2576 } else { 2577 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2578 } 2579 } else { 2580 blnd_cfg.pre_multiplied_alpha = false; 2581 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 2582 } 2583 2584 if (pipe_ctx->plane_state->global_alpha) 2585 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; 2586 else 2587 blnd_cfg.global_alpha = 0xff; 2588 2589 blnd_cfg.background_color_bpc = 4; 2590 blnd_cfg.bottom_gain_mode = 0; 2591 blnd_cfg.top_gain = 0x1f000; 2592 blnd_cfg.bottom_inside_gain = 0x1f000; 2593 blnd_cfg.bottom_outside_gain = 0x1f000; 2594 2595 if (pipe_ctx->plane_state->format 2596 == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA) 2597 blnd_cfg.pre_multiplied_alpha = false; 2598 2599 /* 2600 * TODO: remove hack 2601 * Note: currently there is a bug in init_hw such that 2602 * on resume from hibernate, BIOS sets up MPCC0, and 2603 * we do mpcc_remove but the mpcc cannot go to idle 2604 * after remove. This cause us to pick mpcc1 here, 2605 * which causes a pstate hang for yet unknown reason. 2606 */ 2607 mpcc_id = hubp->inst; 2608 2609 /* If there is no full update, don't need to touch MPC tree*/ 2610 if (!pipe_ctx->plane_state->update_flags.bits.full_update && 2611 !pipe_ctx->update_flags.bits.mpcc) { 2612 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); 2613 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); 2614 return; 2615 } 2616 2617 /* check if this MPCC is already being used */ 2618 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 2619 /* remove MPCC if being used */ 2620 if (new_mpcc != NULL) 2621 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); 2622 else 2623 if (dc->debug.sanity_checks) 2624 mpc->funcs->assert_mpcc_idle_before_connect( 2625 dc->res_pool->mpc, mpcc_id); 2626 2627 /* Call MPC to insert new plane */ 2628 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, 2629 mpc_tree_params, 2630 &blnd_cfg, 2631 NULL, 2632 NULL, 2633 hubp->inst, 2634 mpcc_id); 2635 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); 2636 2637 ASSERT(new_mpcc != NULL); 2638 hubp->opp_id = pipe_ctx->stream_res.opp->inst; 2639 hubp->mpcc_id = mpcc_id; 2640 } 2641 2642 static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link) 2643 { 2644 switch (link->link_enc->transmitter) { 2645 case TRANSMITTER_UNIPHY_A: 2646 return PHYD32CLKA; 2647 case TRANSMITTER_UNIPHY_B: 2648 return PHYD32CLKB; 2649 case TRANSMITTER_UNIPHY_C: 2650 return PHYD32CLKC; 2651 case TRANSMITTER_UNIPHY_D: 2652 return PHYD32CLKD; 2653 case TRANSMITTER_UNIPHY_E: 2654 return PHYD32CLKE; 2655 default: 2656 return PHYD32CLKA; 2657 } 2658 } 2659 2660 static int get_odm_segment_count(struct pipe_ctx *pipe_ctx) 2661 { 2662 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2663 int count = 1; 2664 2665 while (odm_pipe != NULL) { 2666 count++; 2667 odm_pipe = odm_pipe->next_odm_pipe; 2668 } 2669 2670 return count; 2671 } 2672 2673 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 2674 { 2675 enum dc_lane_count lane_count = 2676 pipe_ctx->stream->link->cur_link_settings.lane_count; 2677 2678 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 2679 struct dc_link *link = pipe_ctx->stream->link; 2680 2681 uint32_t active_total_with_borders; 2682 uint32_t early_control = 0; 2683 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2684 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2685 struct dc *dc = pipe_ctx->stream->ctx->dc; 2686 struct dtbclk_dto_params dto_params = {0}; 2687 struct dccg *dccg = dc->res_pool->dccg; 2688 enum phyd32clk_clock_source phyd32clk; 2689 int dp_hpo_inst; 2690 struct dce_hwseq *hws = dc->hwseq; 2691 unsigned int k1_div = PIXEL_RATE_DIV_NA; 2692 unsigned int k2_div = PIXEL_RATE_DIV_NA; 2693 2694 if (is_dp_128b_132b_signal(pipe_ctx)) { 2695 if (dc->hwseq->funcs.setup_hpo_hw_control) 2696 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, true); 2697 } 2698 2699 if (is_dp_128b_132b_signal(pipe_ctx)) { 2700 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; 2701 dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst); 2702 2703 phyd32clk = get_phyd32clk_src(link); 2704 dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); 2705 2706 dto_params.otg_inst = tg->inst; 2707 dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10; 2708 dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx); 2709 dto_params.timing = &pipe_ctx->stream->timing; 2710 dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); 2711 dccg->funcs->set_dtbclk_dto(dccg, &dto_params); 2712 } 2713 2714 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { 2715 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); 2716 2717 dc->res_pool->dccg->funcs->set_pixel_rate_div( 2718 dc->res_pool->dccg, 2719 pipe_ctx->stream_res.tg->inst, 2720 k1_div, k2_div); 2721 } 2722 2723 link_hwss->setup_stream_encoder(pipe_ctx); 2724 2725 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) { 2726 if (dc->hwss.program_dmdata_engine) 2727 dc->hwss.program_dmdata_engine(pipe_ctx); 2728 } 2729 2730 dc->hwss.update_info_frame(pipe_ctx); 2731 2732 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2733 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2734 2735 /* enable early control to avoid corruption on DP monitor*/ 2736 active_total_with_borders = 2737 timing->h_addressable 2738 + timing->h_border_left 2739 + timing->h_border_right; 2740 2741 if (lane_count != 0) 2742 early_control = active_total_with_borders % lane_count; 2743 2744 if (early_control == 0) 2745 early_control = lane_count; 2746 2747 tg->funcs->set_early_control(tg, early_control); 2748 2749 if (dc->hwseq->funcs.set_pixels_per_cycle) 2750 dc->hwseq->funcs.set_pixels_per_cycle(pipe_ctx); 2751 } 2752 2753 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx) 2754 { 2755 struct dc_stream_state *stream = pipe_ctx->stream; 2756 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2757 bool enable = false; 2758 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2759 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) 2760 ? dmdata_dp 2761 : dmdata_hdmi; 2762 2763 /* if using dynamic meta, don't set up generic infopackets */ 2764 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { 2765 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; 2766 enable = true; 2767 } 2768 2769 if (!hubp) 2770 return; 2771 2772 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) 2773 return; 2774 2775 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, 2776 hubp->inst, mode); 2777 } 2778 2779 void dcn20_fpga_init_hw(struct dc *dc) 2780 { 2781 int i, j; 2782 struct dce_hwseq *hws = dc->hwseq; 2783 struct resource_pool *res_pool = dc->res_pool; 2784 struct dc_state *context = dc->current_state; 2785 2786 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 2787 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 2788 2789 // Initialize the dccg 2790 if (res_pool->dccg->funcs->dccg_init) 2791 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 2792 2793 //Enable ability to power gate / don't force power on permanently 2794 hws->funcs.enable_power_gating_plane(hws, true); 2795 2796 // Specific to FPGA dccg and registers 2797 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); 2798 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 2799 2800 hws->funcs.dccg_init(hws); 2801 2802 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); 2803 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 2804 if (REG(REFCLK_CNTL)) 2805 REG_WRITE(REFCLK_CNTL, 0); 2806 // 2807 2808 2809 /* Blank pixel data with OPP DPG */ 2810 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2811 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2812 2813 if (tg->funcs->is_tg_enabled(tg)) 2814 dcn20_init_blank(dc, tg); 2815 } 2816 2817 for (i = 0; i < res_pool->timing_generator_count; i++) { 2818 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2819 2820 if (tg->funcs->is_tg_enabled(tg)) 2821 tg->funcs->lock(tg); 2822 } 2823 2824 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2825 struct dpp *dpp = res_pool->dpps[i]; 2826 2827 dpp->funcs->dpp_reset(dpp); 2828 } 2829 2830 /* Reset all MPCC muxes */ 2831 res_pool->mpc->funcs->mpc_init(res_pool->mpc); 2832 2833 /* initialize OPP mpc_tree parameter */ 2834 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 2835 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; 2836 res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2837 for (j = 0; j < MAX_PIPES; j++) 2838 res_pool->opps[i]->mpcc_disconnect_pending[j] = false; 2839 } 2840 2841 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2842 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2843 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2844 struct hubp *hubp = dc->res_pool->hubps[i]; 2845 struct dpp *dpp = dc->res_pool->dpps[i]; 2846 2847 pipe_ctx->stream_res.tg = tg; 2848 pipe_ctx->pipe_idx = i; 2849 2850 pipe_ctx->plane_res.hubp = hubp; 2851 pipe_ctx->plane_res.dpp = dpp; 2852 pipe_ctx->plane_res.mpcc_inst = dpp->inst; 2853 hubp->mpcc_id = dpp->inst; 2854 hubp->opp_id = OPP_ID_INVALID; 2855 hubp->power_gated = false; 2856 pipe_ctx->stream_res.opp = NULL; 2857 2858 hubp->funcs->hubp_init(hubp); 2859 2860 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; 2861 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2862 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; 2863 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; 2864 /*to do*/ 2865 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx); 2866 } 2867 2868 /* initialize DWB pointer to MCIF_WB */ 2869 for (i = 0; i < res_pool->res_cap->num_dwb; i++) 2870 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; 2871 2872 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2873 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2874 2875 if (tg->funcs->is_tg_enabled(tg)) 2876 tg->funcs->unlock(tg); 2877 } 2878 2879 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2880 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2881 2882 dc->hwss.disable_plane(dc, pipe_ctx); 2883 2884 pipe_ctx->stream_res.tg = NULL; 2885 pipe_ctx->plane_res.hubp = NULL; 2886 } 2887 2888 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2889 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2890 2891 tg->funcs->tg_init(tg); 2892 } 2893 2894 if (dc->res_pool->hubbub->funcs->init_crb) 2895 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 2896 } 2897 #ifndef TRIM_FSFT 2898 bool dcn20_optimize_timing_for_fsft(struct dc *dc, 2899 struct dc_crtc_timing *timing, 2900 unsigned int max_input_rate_in_khz) 2901 { 2902 unsigned int old_v_front_porch; 2903 unsigned int old_v_total; 2904 unsigned int max_input_rate_in_100hz; 2905 unsigned long long new_v_total; 2906 2907 max_input_rate_in_100hz = max_input_rate_in_khz * 10; 2908 if (max_input_rate_in_100hz < timing->pix_clk_100hz) 2909 return false; 2910 2911 old_v_total = timing->v_total; 2912 old_v_front_porch = timing->v_front_porch; 2913 2914 timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz; 2915 timing->pix_clk_100hz = max_input_rate_in_100hz; 2916 2917 new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz); 2918 2919 timing->v_total = new_v_total; 2920 timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total); 2921 return true; 2922 } 2923 #endif 2924 2925 void dcn20_set_disp_pattern_generator(const struct dc *dc, 2926 struct pipe_ctx *pipe_ctx, 2927 enum controller_dp_test_pattern test_pattern, 2928 enum controller_dp_color_space color_space, 2929 enum dc_color_depth color_depth, 2930 const struct tg_color *solid_color, 2931 int width, int height, int offset) 2932 { 2933 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern, 2934 color_space, color_depth, solid_color, width, height, offset); 2935 } 2936