1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include <linux/delay.h> 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dcn20/dcn20_resource.h" 32 #include "dce110/dce110_hw_sequencer.h" 33 #include "dcn10/dcn10_hw_sequencer.h" 34 #include "dcn20_hwseq.h" 35 #include "dce/dce_hwseq.h" 36 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 37 #include "dcn20/dcn20_dsc.h" 38 #endif 39 #include "abm.h" 40 #include "clk_mgr.h" 41 #include "dmcu.h" 42 #include "hubp.h" 43 #include "timing_generator.h" 44 #include "opp.h" 45 #include "ipp.h" 46 #include "mpc.h" 47 #include "mcif_wb.h" 48 #include "reg_helper.h" 49 #include "dcn10/dcn10_cm_common.h" 50 #include "dcn10/dcn10_hubbub.h" 51 #include "dcn10/dcn10_optc.h" 52 #include "dc_link_dp.h" 53 #include "vm_helper.h" 54 #include "dccg.h" 55 56 #define DC_LOGGER_INIT(logger) 57 58 #define CTX \ 59 hws->ctx 60 #define REG(reg)\ 61 hws->regs->reg 62 63 #undef FN 64 #define FN(reg_name, field_name) \ 65 hws->shifts->field_name, hws->masks->field_name 66 67 static void bios_golden_init(struct dc *dc) 68 { 69 struct dc_bios *bp = dc->ctx->dc_bios; 70 int i; 71 72 /* initialize dcn global */ 73 bp->funcs->enable_disp_power_gating(bp, 74 CONTROLLER_ID_D0, ASIC_PIPE_INIT); 75 76 for (i = 0; i < dc->res_pool->pipe_count; i++) { 77 /* initialize dcn per pipe */ 78 bp->funcs->enable_disp_power_gating(bp, 79 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE); 80 } 81 } 82 83 static void enable_power_gating_plane( 84 struct dce_hwseq *hws, 85 bool enable) 86 { 87 bool force_on = 1; /* disable power gating */ 88 89 if (enable) 90 force_on = 0; 91 92 /* DCHUBP0/1/2/3/4/5 */ 93 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); 94 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); 95 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); 96 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); 97 if (REG(DOMAIN8_PG_CONFIG)) 98 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 99 if (REG(DOMAIN10_PG_CONFIG)) 100 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 101 102 /* DPP0/1/2/3/4/5 */ 103 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); 104 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); 105 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); 106 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); 107 if (REG(DOMAIN9_PG_CONFIG)) 108 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 109 if (REG(DOMAIN11_PG_CONFIG)) 110 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 111 112 /* DCS0/1/2/3/4/5 */ 113 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on); 114 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on); 115 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on); 116 if (REG(DOMAIN19_PG_CONFIG)) 117 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on); 118 if (REG(DOMAIN20_PG_CONFIG)) 119 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on); 120 if (REG(DOMAIN21_PG_CONFIG)) 121 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); 122 } 123 124 void dcn20_dccg_init(struct dce_hwseq *hws) 125 { 126 /* 127 * set MICROSECOND_TIME_BASE_DIV 128 * 100Mhz refclk -> 0x120264 129 * 27Mhz refclk -> 0x12021b 130 * 48Mhz refclk -> 0x120230 131 * 132 */ 133 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); 134 135 /* 136 * set MILLISECOND_TIME_BASE_DIV 137 * 100Mhz refclk -> 0x1186a0 138 * 27Mhz refclk -> 0x106978 139 * 48Mhz refclk -> 0x10bb80 140 * 141 */ 142 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); 143 144 /* This value is dependent on the hardware pipeline delay so set once per SOC */ 145 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c); 146 } 147 void dcn20_display_init(struct dc *dc) 148 { 149 struct dce_hwseq *hws = dc->hwseq; 150 151 /* RBBMIF 152 * disable RBBMIF timeout detection for all clients 153 * Ensure RBBMIF does not drop register accesses due to the per-client timeout 154 */ 155 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); 156 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 157 158 /* DCCG */ 159 dcn20_dccg_init(hws); 160 161 /* Disable all memory low power mode. All memories are enabled. */ 162 REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 1); 163 164 /* DCHUB/MMHUBBUB 165 * set global timer refclk divider 166 * 100Mhz refclk -> 2 167 * 27Mhz refclk -> 1 168 * 48Mhz refclk -> 1 169 */ 170 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); 171 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 172 REG_WRITE(REFCLK_CNTL, 0); 173 174 /* OPTC 175 * OTG_CONTROL.OTG_DISABLE_POINT_CNTL = 0x3; will be set during optc2_enable_crtc 176 */ 177 178 /* AZ 179 * default value is 0x64 for 100Mhz ref clock, if the ref clock is 100Mhz, no need to program this regiser, 180 * if not, it should be programmed according to the ref clock 181 */ 182 REG_UPDATE(AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, 0x64); 183 /* Enable controller clock gating */ 184 REG_WRITE(AZALIA_CONTROLLER_CLOCK_GATING, 0x1); 185 } 186 187 static void disable_vga( 188 struct dce_hwseq *hws) 189 { 190 REG_WRITE(D1VGA_CONTROL, 0); 191 REG_WRITE(D2VGA_CONTROL, 0); 192 REG_WRITE(D3VGA_CONTROL, 0); 193 REG_WRITE(D4VGA_CONTROL, 0); 194 REG_WRITE(D5VGA_CONTROL, 0); 195 REG_WRITE(D6VGA_CONTROL, 0); 196 } 197 198 void dcn20_program_tripleBuffer( 199 const struct dc *dc, 200 struct pipe_ctx *pipe_ctx, 201 bool enableTripleBuffer) 202 { 203 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { 204 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( 205 pipe_ctx->plane_res.hubp, 206 enableTripleBuffer); 207 } 208 } 209 210 /* Blank pixel data during initialization */ 211 void dcn20_init_blank( 212 struct dc *dc, 213 struct timing_generator *tg) 214 { 215 enum dc_color_space color_space; 216 struct tg_color black_color = {0}; 217 struct output_pixel_processor *opp = NULL; 218 struct output_pixel_processor *bottom_opp = NULL; 219 uint32_t num_opps, opp_id_src0, opp_id_src1; 220 uint32_t otg_active_width, otg_active_height; 221 222 /* program opp dpg blank color */ 223 color_space = COLOR_SPACE_SRGB; 224 color_space_to_black_color(dc, color_space, &black_color); 225 226 /* get the OTG active size */ 227 tg->funcs->get_otg_active_size(tg, 228 &otg_active_width, 229 &otg_active_height); 230 231 /* get the OPTC source */ 232 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 233 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); 234 opp = dc->res_pool->opps[opp_id_src0]; 235 236 if (num_opps == 2) { 237 otg_active_width = otg_active_width / 2; 238 ASSERT(opp_id_src1 < dc->res_pool->res_cap->num_opp); 239 bottom_opp = dc->res_pool->opps[opp_id_src1]; 240 } 241 242 opp->funcs->opp_set_disp_pattern_generator( 243 opp, 244 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 245 COLOR_DEPTH_UNDEFINED, 246 &black_color, 247 otg_active_width, 248 otg_active_height); 249 250 if (num_opps == 2) { 251 bottom_opp->funcs->opp_set_disp_pattern_generator( 252 bottom_opp, 253 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 254 COLOR_DEPTH_UNDEFINED, 255 &black_color, 256 otg_active_width, 257 otg_active_height); 258 } 259 260 dcn20_hwss_wait_for_blank_complete(opp); 261 } 262 263 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 264 static void dcn20_dsc_pg_control( 265 struct dce_hwseq *hws, 266 unsigned int dsc_inst, 267 bool power_on) 268 { 269 uint32_t power_gate = power_on ? 0 : 1; 270 uint32_t pwr_status = power_on ? 0 : 2; 271 uint32_t org_ip_request_cntl = 0; 272 273 if (hws->ctx->dc->debug.disable_dsc_power_gate) 274 return; 275 276 if (REG(DOMAIN16_PG_CONFIG) == 0) 277 return; 278 279 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 280 if (org_ip_request_cntl == 0) 281 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 282 283 switch (dsc_inst) { 284 case 0: /* DSC0 */ 285 REG_UPDATE(DOMAIN16_PG_CONFIG, 286 DOMAIN16_POWER_GATE, power_gate); 287 288 REG_WAIT(DOMAIN16_PG_STATUS, 289 DOMAIN16_PGFSM_PWR_STATUS, pwr_status, 290 1, 1000); 291 break; 292 case 1: /* DSC1 */ 293 REG_UPDATE(DOMAIN17_PG_CONFIG, 294 DOMAIN17_POWER_GATE, power_gate); 295 296 REG_WAIT(DOMAIN17_PG_STATUS, 297 DOMAIN17_PGFSM_PWR_STATUS, pwr_status, 298 1, 1000); 299 break; 300 case 2: /* DSC2 */ 301 REG_UPDATE(DOMAIN18_PG_CONFIG, 302 DOMAIN18_POWER_GATE, power_gate); 303 304 REG_WAIT(DOMAIN18_PG_STATUS, 305 DOMAIN18_PGFSM_PWR_STATUS, pwr_status, 306 1, 1000); 307 break; 308 case 3: /* DSC3 */ 309 REG_UPDATE(DOMAIN19_PG_CONFIG, 310 DOMAIN19_POWER_GATE, power_gate); 311 312 REG_WAIT(DOMAIN19_PG_STATUS, 313 DOMAIN19_PGFSM_PWR_STATUS, pwr_status, 314 1, 1000); 315 break; 316 case 4: /* DSC4 */ 317 REG_UPDATE(DOMAIN20_PG_CONFIG, 318 DOMAIN20_POWER_GATE, power_gate); 319 320 REG_WAIT(DOMAIN20_PG_STATUS, 321 DOMAIN20_PGFSM_PWR_STATUS, pwr_status, 322 1, 1000); 323 break; 324 case 5: /* DSC5 */ 325 REG_UPDATE(DOMAIN21_PG_CONFIG, 326 DOMAIN21_POWER_GATE, power_gate); 327 328 REG_WAIT(DOMAIN21_PG_STATUS, 329 DOMAIN21_PGFSM_PWR_STATUS, pwr_status, 330 1, 1000); 331 break; 332 default: 333 BREAK_TO_DEBUGGER(); 334 break; 335 } 336 337 if (org_ip_request_cntl == 0) 338 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 339 } 340 #endif 341 342 static void dcn20_dpp_pg_control( 343 struct dce_hwseq *hws, 344 unsigned int dpp_inst, 345 bool power_on) 346 { 347 uint32_t power_gate = power_on ? 0 : 1; 348 uint32_t pwr_status = power_on ? 0 : 2; 349 350 if (hws->ctx->dc->debug.disable_dpp_power_gate) 351 return; 352 if (REG(DOMAIN1_PG_CONFIG) == 0) 353 return; 354 355 switch (dpp_inst) { 356 case 0: /* DPP0 */ 357 REG_UPDATE(DOMAIN1_PG_CONFIG, 358 DOMAIN1_POWER_GATE, power_gate); 359 360 REG_WAIT(DOMAIN1_PG_STATUS, 361 DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 362 1, 1000); 363 break; 364 case 1: /* DPP1 */ 365 REG_UPDATE(DOMAIN3_PG_CONFIG, 366 DOMAIN3_POWER_GATE, power_gate); 367 368 REG_WAIT(DOMAIN3_PG_STATUS, 369 DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 370 1, 1000); 371 break; 372 case 2: /* DPP2 */ 373 REG_UPDATE(DOMAIN5_PG_CONFIG, 374 DOMAIN5_POWER_GATE, power_gate); 375 376 REG_WAIT(DOMAIN5_PG_STATUS, 377 DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 378 1, 1000); 379 break; 380 case 3: /* DPP3 */ 381 REG_UPDATE(DOMAIN7_PG_CONFIG, 382 DOMAIN7_POWER_GATE, power_gate); 383 384 REG_WAIT(DOMAIN7_PG_STATUS, 385 DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 386 1, 1000); 387 break; 388 case 4: /* DPP4 */ 389 REG_UPDATE(DOMAIN9_PG_CONFIG, 390 DOMAIN9_POWER_GATE, power_gate); 391 392 REG_WAIT(DOMAIN9_PG_STATUS, 393 DOMAIN9_PGFSM_PWR_STATUS, pwr_status, 394 1, 1000); 395 break; 396 case 5: /* DPP5 */ 397 /* 398 * Do not power gate DPP5, should be left at HW default, power on permanently. 399 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 400 * reset. 401 * REG_UPDATE(DOMAIN11_PG_CONFIG, 402 * DOMAIN11_POWER_GATE, power_gate); 403 * 404 * REG_WAIT(DOMAIN11_PG_STATUS, 405 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, 406 * 1, 1000); 407 */ 408 break; 409 default: 410 BREAK_TO_DEBUGGER(); 411 break; 412 } 413 } 414 415 416 static void dcn20_hubp_pg_control( 417 struct dce_hwseq *hws, 418 unsigned int hubp_inst, 419 bool power_on) 420 { 421 uint32_t power_gate = power_on ? 0 : 1; 422 uint32_t pwr_status = power_on ? 0 : 2; 423 424 if (hws->ctx->dc->debug.disable_hubp_power_gate) 425 return; 426 if (REG(DOMAIN0_PG_CONFIG) == 0) 427 return; 428 429 switch (hubp_inst) { 430 case 0: /* DCHUBP0 */ 431 REG_UPDATE(DOMAIN0_PG_CONFIG, 432 DOMAIN0_POWER_GATE, power_gate); 433 434 REG_WAIT(DOMAIN0_PG_STATUS, 435 DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 436 1, 1000); 437 break; 438 case 1: /* DCHUBP1 */ 439 REG_UPDATE(DOMAIN2_PG_CONFIG, 440 DOMAIN2_POWER_GATE, power_gate); 441 442 REG_WAIT(DOMAIN2_PG_STATUS, 443 DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 444 1, 1000); 445 break; 446 case 2: /* DCHUBP2 */ 447 REG_UPDATE(DOMAIN4_PG_CONFIG, 448 DOMAIN4_POWER_GATE, power_gate); 449 450 REG_WAIT(DOMAIN4_PG_STATUS, 451 DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 452 1, 1000); 453 break; 454 case 3: /* DCHUBP3 */ 455 REG_UPDATE(DOMAIN6_PG_CONFIG, 456 DOMAIN6_POWER_GATE, power_gate); 457 458 REG_WAIT(DOMAIN6_PG_STATUS, 459 DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 460 1, 1000); 461 break; 462 case 4: /* DCHUBP4 */ 463 REG_UPDATE(DOMAIN8_PG_CONFIG, 464 DOMAIN8_POWER_GATE, power_gate); 465 466 REG_WAIT(DOMAIN8_PG_STATUS, 467 DOMAIN8_PGFSM_PWR_STATUS, pwr_status, 468 1, 1000); 469 break; 470 case 5: /* DCHUBP5 */ 471 /* 472 * Do not power gate DCHUB5, should be left at HW default, power on permanently. 473 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 474 * reset. 475 * REG_UPDATE(DOMAIN10_PG_CONFIG, 476 * DOMAIN10_POWER_GATE, power_gate); 477 * 478 * REG_WAIT(DOMAIN10_PG_STATUS, 479 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status, 480 * 1, 1000); 481 */ 482 break; 483 default: 484 BREAK_TO_DEBUGGER(); 485 break; 486 } 487 } 488 489 490 491 static void dcn20_plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx) 492 { 493 struct dce_hwseq *hws = dc->hwseq; 494 struct dpp *dpp = pipe_ctx->plane_res.dpp; 495 496 DC_LOGGER_INIT(dc->ctx->logger); 497 498 if (REG(DC_IP_REQUEST_CNTL)) { 499 REG_SET(DC_IP_REQUEST_CNTL, 0, 500 IP_REQUEST_EN, 1); 501 dcn20_dpp_pg_control(hws, dpp->inst, false); 502 dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, false); 503 dpp->funcs->dpp_reset(dpp); 504 REG_SET(DC_IP_REQUEST_CNTL, 0, 505 IP_REQUEST_EN, 0); 506 DC_LOG_DEBUG( 507 "Power gated front end %d\n", pipe_ctx->pipe_idx); 508 } 509 } 510 511 512 513 /* disable HW used by plane. 514 * note: cannot disable until disconnect is complete 515 */ 516 static void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 517 { 518 struct hubp *hubp = pipe_ctx->plane_res.hubp; 519 struct dpp *dpp = pipe_ctx->plane_res.dpp; 520 521 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); 522 523 /* In flip immediate with pipe splitting case GSL is used for 524 * synchronization so we must disable it when the plane is disabled. 525 */ 526 if (pipe_ctx->stream_res.gsl_group != 0) 527 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false); 528 529 dc->hwss.set_flip_control_gsl(pipe_ctx, false); 530 531 hubp->funcs->hubp_clk_cntl(hubp, false); 532 533 dpp->funcs->dpp_dppclk_control(dpp, false, false); 534 535 hubp->power_gated = true; 536 dc->optimized_required = false; /* We're powering off, no need to optimize */ 537 538 dcn20_plane_atomic_power_down(dc, pipe_ctx); 539 540 pipe_ctx->stream = NULL; 541 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); 542 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); 543 pipe_ctx->top_pipe = NULL; 544 pipe_ctx->bottom_pipe = NULL; 545 pipe_ctx->plane_state = NULL; 546 } 547 548 549 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) 550 { 551 DC_LOGGER_INIT(dc->ctx->logger); 552 553 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) 554 return; 555 556 dcn20_plane_atomic_disable(dc, pipe_ctx); 557 558 DC_LOG_DC("Power down front end %d\n", 559 pipe_ctx->pipe_idx); 560 } 561 562 static void dcn20_init_hw(struct dc *dc) 563 { 564 int i, j; 565 struct abm *abm = dc->res_pool->abm; 566 struct dmcu *dmcu = dc->res_pool->dmcu; 567 struct dce_hwseq *hws = dc->hwseq; 568 struct dc_bios *dcb = dc->ctx->dc_bios; 569 struct resource_pool *res_pool = dc->res_pool; 570 struct dc_state *context = dc->current_state; 571 572 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 573 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 574 575 // Initialize the dccg 576 if (res_pool->dccg->funcs->dccg_init) 577 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 578 579 //Enable ability to power gate / don't force power on permanently 580 enable_power_gating_plane(dc->hwseq, true); 581 582 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 583 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); 584 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 585 586 dcn20_dccg_init(hws); 587 588 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); 589 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 590 REG_WRITE(REFCLK_CNTL, 0); 591 } else { 592 if (!dcb->funcs->is_accelerated_mode(dcb)) { 593 bios_golden_init(dc); 594 if (dc->ctx->dc_bios->fw_info_valid) { 595 res_pool->ref_clocks.xtalin_clock_inKhz = 596 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 597 598 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 599 if (res_pool->dccg && res_pool->hubbub) { 600 601 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 602 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 603 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 604 605 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 606 res_pool->ref_clocks.dccg_ref_clock_inKhz, 607 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 608 } else { 609 // Not all ASICs have DCCG sw component 610 res_pool->ref_clocks.dccg_ref_clock_inKhz = 611 res_pool->ref_clocks.xtalin_clock_inKhz; 612 res_pool->ref_clocks.dchub_ref_clock_inKhz = 613 res_pool->ref_clocks.xtalin_clock_inKhz; 614 } 615 } 616 } else 617 ASSERT_CRITICAL(false); 618 disable_vga(dc->hwseq); 619 } 620 621 for (i = 0; i < dc->link_count; i++) { 622 /* Power up AND update implementation according to the 623 * required signal (which may be different from the 624 * default signal on connector). 625 */ 626 struct dc_link *link = dc->links[i]; 627 628 link->link_enc->funcs->hw_init(link->link_enc); 629 } 630 } 631 632 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 633 /* Power gate DSCs */ 634 for (i = 0; i < res_pool->res_cap->num_dsc; i++) 635 dcn20_dsc_pg_control(hws, res_pool->dscs[i]->inst, false); 636 #endif 637 638 /* Blank pixel data with OPP DPG */ 639 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 640 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 641 642 if (tg->funcs->is_tg_enabled(tg)) { 643 dcn20_init_blank(dc, tg); 644 } 645 } 646 647 for (i = 0; i < res_pool->timing_generator_count; i++) { 648 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 649 650 if (tg->funcs->is_tg_enabled(tg)) 651 tg->funcs->lock(tg); 652 } 653 654 for (i = 0; i < dc->res_pool->pipe_count; i++) { 655 struct dpp *dpp = res_pool->dpps[i]; 656 657 dpp->funcs->dpp_reset(dpp); 658 } 659 660 /* Reset all MPCC muxes */ 661 res_pool->mpc->funcs->mpc_init(res_pool->mpc); 662 663 /* initialize OPP mpc_tree parameter */ 664 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 665 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; 666 res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 667 for (j = 0; j < MAX_PIPES; j++) 668 res_pool->opps[i]->mpcc_disconnect_pending[j] = false; 669 } 670 671 for (i = 0; i < dc->res_pool->pipe_count; i++) { 672 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 673 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 674 struct hubp *hubp = dc->res_pool->hubps[i]; 675 struct dpp *dpp = dc->res_pool->dpps[i]; 676 677 pipe_ctx->stream_res.tg = tg; 678 pipe_ctx->pipe_idx = i; 679 680 pipe_ctx->plane_res.hubp = hubp; 681 pipe_ctx->plane_res.dpp = dpp; 682 pipe_ctx->plane_res.mpcc_inst = dpp->inst; 683 hubp->mpcc_id = dpp->inst; 684 hubp->opp_id = OPP_ID_INVALID; 685 hubp->power_gated = false; 686 pipe_ctx->stream_res.opp = NULL; 687 688 hubp->funcs->hubp_init(hubp); 689 690 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; 691 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 692 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; 693 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; 694 /*to do*/ 695 hwss1_plane_atomic_disconnect(dc, pipe_ctx); 696 } 697 698 /* initialize DWB pointer to MCIF_WB */ 699 for (i = 0; i < res_pool->res_cap->num_dwb; i++) 700 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; 701 702 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 703 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 704 705 if (tg->funcs->is_tg_enabled(tg)) 706 tg->funcs->unlock(tg); 707 } 708 709 for (i = 0; i < dc->res_pool->pipe_count; i++) { 710 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 711 712 dc->hwss.disable_plane(dc, pipe_ctx); 713 714 pipe_ctx->stream_res.tg = NULL; 715 pipe_ctx->plane_res.hubp = NULL; 716 } 717 718 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 719 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 720 721 tg->funcs->tg_init(tg); 722 } 723 724 /* end of FPGA. Below if real ASIC */ 725 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 726 return; 727 728 729 for (i = 0; i < res_pool->audio_count; i++) { 730 struct audio *audio = res_pool->audios[i]; 731 732 audio->funcs->hw_init(audio); 733 } 734 735 if (abm != NULL) { 736 abm->funcs->init_backlight(abm); 737 abm->funcs->abm_init(abm); 738 } 739 740 if (dmcu != NULL) 741 dmcu->funcs->dmcu_init(dmcu); 742 743 if (abm != NULL && dmcu != NULL) 744 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 745 746 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 747 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 748 749 if (!dc->debug.disable_clock_gate) { 750 /* enable all DCN clock gating */ 751 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 752 753 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 754 755 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 756 } 757 758 } 759 760 enum dc_status dcn20_enable_stream_timing( 761 struct pipe_ctx *pipe_ctx, 762 struct dc_state *context, 763 struct dc *dc) 764 { 765 struct dc_stream_state *stream = pipe_ctx->stream; 766 struct drr_params params = {0}; 767 unsigned int event_triggers = 0; 768 769 770 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 771 struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); 772 #endif 773 774 /* by upper caller loop, pipe0 is parent pipe and be called first. 775 * back end is set up by for pipe0. Other children pipe share back end 776 * with pipe 0. No program is needed. 777 */ 778 if (pipe_ctx->top_pipe != NULL) 779 return DC_OK; 780 781 /* TODO check if timing_changed, disable stream if timing changed */ 782 783 if (odm_pipe) 784 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 785 pipe_ctx->stream_res.tg, 786 odm_pipe->stream_res.opp->inst, 787 pipe_ctx->stream->timing.h_addressable/2, 788 pipe_ctx->stream->timing.pixel_encoding); 789 /* HW program guide assume display already disable 790 * by unplug sequence. OTG assume stop. 791 */ 792 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); 793 794 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 795 pipe_ctx->clock_source, 796 &pipe_ctx->stream_res.pix_clk_params, 797 &pipe_ctx->pll_settings)) { 798 BREAK_TO_DEBUGGER(); 799 return DC_ERROR_UNEXPECTED; 800 } 801 802 pipe_ctx->stream_res.tg->funcs->program_timing( 803 pipe_ctx->stream_res.tg, 804 &stream->timing, 805 pipe_ctx->pipe_dlg_param.vready_offset, 806 pipe_ctx->pipe_dlg_param.vstartup_start, 807 pipe_ctx->pipe_dlg_param.vupdate_offset, 808 pipe_ctx->pipe_dlg_param.vupdate_width, 809 pipe_ctx->stream->signal, 810 true); 811 812 if (pipe_ctx->stream_res.tg->funcs->setup_global_lock) 813 pipe_ctx->stream_res.tg->funcs->setup_global_lock( 814 pipe_ctx->stream_res.tg); 815 816 if (odm_pipe) 817 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 818 odm_pipe->stream_res.opp, 819 true); 820 821 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 822 pipe_ctx->stream_res.opp, 823 true); 824 825 dc->hwss.blank_pixel_data(dc, pipe_ctx, true); 826 827 /* VTG is within DCHUB command block. DCFCLK is always on */ 828 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { 829 BREAK_TO_DEBUGGER(); 830 return DC_ERROR_UNEXPECTED; 831 } 832 833 dcn20_hwss_wait_for_blank_complete(pipe_ctx->stream_res.opp); 834 835 params.vertical_total_min = stream->adjust.v_total_min; 836 params.vertical_total_max = stream->adjust.v_total_max; 837 if (pipe_ctx->stream_res.tg->funcs->set_drr) 838 pipe_ctx->stream_res.tg->funcs->set_drr( 839 pipe_ctx->stream_res.tg, ¶ms); 840 841 // DRR should set trigger event to monitor surface update event 842 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 843 event_triggers = 0x80; 844 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 845 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 846 pipe_ctx->stream_res.tg, event_triggers); 847 848 /* TODO program crtc source select for non-virtual signal*/ 849 /* TODO program FMT */ 850 /* TODO setup link_enc */ 851 /* TODO set stream attributes */ 852 /* TODO program audio */ 853 /* TODO enable stream if timing changed */ 854 /* TODO unblank stream if DP */ 855 856 return DC_OK; 857 } 858 859 void dcn20_program_output_csc(struct dc *dc, 860 struct pipe_ctx *pipe_ctx, 861 enum dc_color_space colorspace, 862 uint16_t *matrix, 863 int opp_id) 864 { 865 struct mpc *mpc = dc->res_pool->mpc; 866 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; 867 868 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 869 if (mpc->funcs->set_output_csc != NULL) 870 mpc->funcs->set_output_csc(mpc, 871 opp_id, 872 matrix, 873 ocsc_mode); 874 } else { 875 if (mpc->funcs->set_ocsc_default != NULL) 876 mpc->funcs->set_ocsc_default(mpc, 877 opp_id, 878 colorspace, 879 ocsc_mode); 880 } 881 } 882 883 bool dcn20_set_output_transfer_func(struct pipe_ctx *pipe_ctx, 884 const struct dc_stream_state *stream) 885 { 886 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 887 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 888 struct pwl_params *params = NULL; 889 /* 890 * program OGAM only for the top pipe 891 * if there is a pipe split then fix diagnostic is required: 892 * how to pass OGAM parameter for stream. 893 * if programming for all pipes is required then remove condition 894 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic. 895 */ 896 if ((pipe_ctx->top_pipe == NULL || dc_res_is_odm_head_pipe(pipe_ctx)) 897 && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 898 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 899 params = &stream->out_transfer_func->pwl; 900 else if (pipe_ctx->stream->out_transfer_func->type == 901 TF_TYPE_DISTRIBUTED_POINTS && 902 cm_helper_translate_curve_to_hw_format( 903 stream->out_transfer_func, 904 &mpc->blender_params, false)) 905 params = &mpc->blender_params; 906 /* 907 * there is no ROM 908 */ 909 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 910 BREAK_TO_DEBUGGER(); 911 } 912 /* 913 * if above if is not executed then 'params' equal to 0 and set in bypass 914 */ 915 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 916 917 return true; 918 } 919 920 static bool dcn20_set_blend_lut( 921 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 922 { 923 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 924 bool result = true; 925 struct pwl_params *blend_lut = NULL; 926 927 if (plane_state->blend_tf) { 928 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 929 blend_lut = &plane_state->blend_tf->pwl; 930 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 931 cm_helper_translate_curve_to_hw_format( 932 plane_state->blend_tf, 933 &dpp_base->regamma_params, false); 934 blend_lut = &dpp_base->regamma_params; 935 } 936 } 937 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); 938 939 return result; 940 } 941 942 static bool dcn20_set_shaper_3dlut( 943 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 944 { 945 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 946 bool result = true; 947 struct pwl_params *shaper_lut = NULL; 948 949 if (plane_state->in_shaper_func) { 950 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 951 shaper_lut = &plane_state->in_shaper_func->pwl; 952 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 953 cm_helper_translate_curve_to_hw_format( 954 plane_state->in_shaper_func, 955 &dpp_base->shaper_params, true); 956 shaper_lut = &dpp_base->shaper_params; 957 } 958 } 959 960 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); 961 if (plane_state->lut3d_func && 962 plane_state->lut3d_func->state.bits.initialized == 1) 963 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, 964 &plane_state->lut3d_func->lut_3d); 965 else 966 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); 967 968 if (plane_state->lut3d_func && 969 plane_state->lut3d_func->state.bits.initialized == 1 && 970 plane_state->lut3d_func->hdr_multiplier != 0) 971 dpp_base->funcs->dpp_set_hdr_multiplier(dpp_base, 972 plane_state->lut3d_func->hdr_multiplier); 973 else 974 dpp_base->funcs->dpp_set_hdr_multiplier(dpp_base, 0x1f000); 975 976 return result; 977 } 978 979 bool dcn20_set_input_transfer_func(struct pipe_ctx *pipe_ctx, 980 const struct dc_plane_state *plane_state) 981 { 982 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 983 const struct dc_transfer_func *tf = NULL; 984 bool result = true; 985 bool use_degamma_ram = false; 986 987 if (dpp_base == NULL || plane_state == NULL) 988 return false; 989 990 dcn20_set_shaper_3dlut(pipe_ctx, plane_state); 991 dcn20_set_blend_lut(pipe_ctx, plane_state); 992 993 if (plane_state->in_transfer_func) 994 tf = plane_state->in_transfer_func; 995 996 997 if (tf == NULL) { 998 dpp_base->funcs->dpp_set_degamma(dpp_base, 999 IPP_DEGAMMA_MODE_BYPASS); 1000 return true; 1001 } 1002 1003 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS) 1004 use_degamma_ram = true; 1005 1006 if (use_degamma_ram == true) { 1007 if (tf->type == TF_TYPE_HWPWL) 1008 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 1009 &tf->pwl); 1010 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 1011 cm_helper_translate_curve_to_degamma_hw_format(tf, 1012 &dpp_base->degamma_params); 1013 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 1014 &dpp_base->degamma_params); 1015 } 1016 return true; 1017 } 1018 /* handle here the optimized cases when de-gamma ROM could be used. 1019 * 1020 */ 1021 if (tf->type == TF_TYPE_PREDEFINED) { 1022 switch (tf->tf) { 1023 case TRANSFER_FUNCTION_SRGB: 1024 dpp_base->funcs->dpp_set_degamma(dpp_base, 1025 IPP_DEGAMMA_MODE_HW_sRGB); 1026 break; 1027 case TRANSFER_FUNCTION_BT709: 1028 dpp_base->funcs->dpp_set_degamma(dpp_base, 1029 IPP_DEGAMMA_MODE_HW_xvYCC); 1030 break; 1031 case TRANSFER_FUNCTION_LINEAR: 1032 dpp_base->funcs->dpp_set_degamma(dpp_base, 1033 IPP_DEGAMMA_MODE_BYPASS); 1034 break; 1035 case TRANSFER_FUNCTION_PQ: 1036 default: 1037 result = false; 1038 break; 1039 } 1040 } else if (tf->type == TF_TYPE_BYPASS) 1041 dpp_base->funcs->dpp_set_degamma(dpp_base, 1042 IPP_DEGAMMA_MODE_BYPASS); 1043 else { 1044 /* 1045 * if we are here, we did not handle correctly. 1046 * fix is required for this use case 1047 */ 1048 BREAK_TO_DEBUGGER(); 1049 dpp_base->funcs->dpp_set_degamma(dpp_base, 1050 IPP_DEGAMMA_MODE_BYPASS); 1051 } 1052 1053 return result; 1054 } 1055 1056 static void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1057 { 1058 struct pipe_ctx *combine_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); 1059 1060 if (combine_pipe) 1061 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 1062 pipe_ctx->stream_res.tg, 1063 combine_pipe->stream_res.opp->inst, 1064 pipe_ctx->plane_res.scl_data.h_active, 1065 pipe_ctx->stream->timing.pixel_encoding); 1066 else 1067 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1068 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1069 } 1070 1071 void dcn20_blank_pixel_data( 1072 struct dc *dc, 1073 struct pipe_ctx *pipe_ctx, 1074 bool blank) 1075 { 1076 struct tg_color black_color = {0}; 1077 struct stream_resource *stream_res = &pipe_ctx->stream_res; 1078 struct dc_stream_state *stream = pipe_ctx->stream; 1079 enum dc_color_space color_space = stream->output_color_space; 1080 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; 1081 struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); 1082 1083 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 1084 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; 1085 1086 /* get opp dpg blank color */ 1087 color_space_to_black_color(dc, color_space, &black_color); 1088 1089 if (bot_odm_pipe) 1090 width = width / 2; 1091 1092 if (blank) { 1093 if (stream_res->abm) 1094 stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm); 1095 1096 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) 1097 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; 1098 } else { 1099 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; 1100 } 1101 1102 stream_res->opp->funcs->opp_set_disp_pattern_generator( 1103 stream_res->opp, 1104 test_pattern, 1105 stream->timing.display_color_depth, 1106 &black_color, 1107 width, 1108 height); 1109 1110 if (bot_odm_pipe) { 1111 bot_odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator( 1112 bot_odm_pipe->stream_res.opp, 1113 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE ? 1114 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern, 1115 stream->timing.display_color_depth, 1116 &black_color, 1117 width, 1118 height); 1119 } 1120 1121 if (!blank) 1122 if (stream_res->abm) { 1123 stream_res->abm->funcs->set_pipe(stream_res->abm, stream_res->tg->inst + 1); 1124 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level); 1125 } 1126 } 1127 1128 1129 static void dcn20_power_on_plane( 1130 struct dce_hwseq *hws, 1131 struct pipe_ctx *pipe_ctx) 1132 { 1133 DC_LOGGER_INIT(hws->ctx->logger); 1134 if (REG(DC_IP_REQUEST_CNTL)) { 1135 REG_SET(DC_IP_REQUEST_CNTL, 0, 1136 IP_REQUEST_EN, 1); 1137 dcn20_dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); 1138 dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true); 1139 REG_SET(DC_IP_REQUEST_CNTL, 0, 1140 IP_REQUEST_EN, 0); 1141 DC_LOG_DEBUG( 1142 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst); 1143 } 1144 } 1145 1146 void dcn20_enable_plane( 1147 struct dc *dc, 1148 struct pipe_ctx *pipe_ctx, 1149 struct dc_state *context) 1150 { 1151 //if (dc->debug.sanity_checks) { 1152 // dcn10_verify_allow_pstate_change_high(dc); 1153 //} 1154 dcn20_power_on_plane(dc->hwseq, pipe_ctx); 1155 1156 /* enable DCFCLK current DCHUB */ 1157 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); 1158 1159 /* make sure OPP_PIPE_CLOCK_EN = 1 */ 1160 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 1161 pipe_ctx->stream_res.opp, 1162 true); 1163 1164 /* TODO: enable/disable in dm as per update type. 1165 if (plane_state) { 1166 DC_LOG_DC(dc->ctx->logger, 1167 "Pipe:%d 0x%x: addr hi:0x%x, " 1168 "addr low:0x%x, " 1169 "src: %d, %d, %d," 1170 " %d; dst: %d, %d, %d, %d;\n", 1171 pipe_ctx->pipe_idx, 1172 plane_state, 1173 plane_state->address.grph.addr.high_part, 1174 plane_state->address.grph.addr.low_part, 1175 plane_state->src_rect.x, 1176 plane_state->src_rect.y, 1177 plane_state->src_rect.width, 1178 plane_state->src_rect.height, 1179 plane_state->dst_rect.x, 1180 plane_state->dst_rect.y, 1181 plane_state->dst_rect.width, 1182 plane_state->dst_rect.height); 1183 1184 DC_LOG_DC(dc->ctx->logger, 1185 "Pipe %d: width, height, x, y format:%d\n" 1186 "viewport:%d, %d, %d, %d\n" 1187 "recout: %d, %d, %d, %d\n", 1188 pipe_ctx->pipe_idx, 1189 plane_state->format, 1190 pipe_ctx->plane_res.scl_data.viewport.width, 1191 pipe_ctx->plane_res.scl_data.viewport.height, 1192 pipe_ctx->plane_res.scl_data.viewport.x, 1193 pipe_ctx->plane_res.scl_data.viewport.y, 1194 pipe_ctx->plane_res.scl_data.recout.width, 1195 pipe_ctx->plane_res.scl_data.recout.height, 1196 pipe_ctx->plane_res.scl_data.recout.x, 1197 pipe_ctx->plane_res.scl_data.recout.y); 1198 print_rq_dlg_ttu(dc, pipe_ctx); 1199 } 1200 */ 1201 if (dc->vm_pa_config.valid) { 1202 struct vm_system_aperture_param apt; 1203 1204 apt.sys_default.quad_part = 0; 1205 1206 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr; 1207 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr; 1208 1209 // Program system aperture settings 1210 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); 1211 } 1212 1213 // if (dc->debug.sanity_checks) { 1214 // dcn10_verify_allow_pstate_change_high(dc); 1215 // } 1216 } 1217 1218 1219 static void dcn20_program_pipe( 1220 struct dc *dc, 1221 struct pipe_ctx *pipe_ctx, 1222 struct dc_state *context) 1223 { 1224 pipe_ctx->plane_state->update_flags.bits.full_update = 1225 context->commit_hints.full_update_needed ? 1 : pipe_ctx->plane_state->update_flags.bits.full_update; 1226 1227 if (pipe_ctx->plane_state->update_flags.bits.full_update) 1228 dcn20_enable_plane(dc, pipe_ctx, context); 1229 1230 update_dchubp_dpp(dc, pipe_ctx, context); 1231 1232 set_hdr_multiplier(pipe_ctx); 1233 1234 if (pipe_ctx->plane_state->update_flags.bits.full_update || 1235 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 1236 pipe_ctx->plane_state->update_flags.bits.gamma_change) 1237 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); 1238 1239 /* dcn10_translate_regamma_to_hw_format takes 750us to finish 1240 * only do gamma programming for full update. 1241 * TODO: This can be further optimized/cleaned up 1242 * Always call this for now since it does memcmp inside before 1243 * doing heavy calculation and programming 1244 */ 1245 if (pipe_ctx->plane_state->update_flags.bits.full_update) 1246 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); 1247 } 1248 1249 static void dcn20_program_all_pipe_in_tree( 1250 struct dc *dc, 1251 struct pipe_ctx *pipe_ctx, 1252 struct dc_state *context) 1253 { 1254 if (pipe_ctx->top_pipe == NULL) { 1255 bool blank = !is_pipe_tree_visible(pipe_ctx); 1256 1257 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1258 pipe_ctx->stream_res.tg, 1259 pipe_ctx->pipe_dlg_param.vready_offset, 1260 pipe_ctx->pipe_dlg_param.vstartup_start, 1261 pipe_ctx->pipe_dlg_param.vupdate_offset, 1262 pipe_ctx->pipe_dlg_param.vupdate_width); 1263 1264 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1265 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1266 1267 dc->hwss.blank_pixel_data(dc, pipe_ctx, blank); 1268 1269 if (dc->hwss.update_odm) 1270 dc->hwss.update_odm(dc, context, pipe_ctx); 1271 } 1272 1273 if (pipe_ctx->plane_state != NULL) 1274 dcn20_program_pipe(dc, pipe_ctx, context); 1275 1276 if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx) 1277 dcn20_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context); 1278 } 1279 1280 void dcn20_pipe_control_lock_global( 1281 struct dc *dc, 1282 struct pipe_ctx *pipe, 1283 bool lock) 1284 { 1285 if (lock) { 1286 pipe->stream_res.tg->funcs->lock_doublebuffer_enable( 1287 pipe->stream_res.tg); 1288 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1289 } else { 1290 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1291 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, 1292 CRTC_STATE_VACTIVE); 1293 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, 1294 CRTC_STATE_VBLANK); 1295 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, 1296 CRTC_STATE_VACTIVE); 1297 pipe->stream_res.tg->funcs->lock_doublebuffer_disable( 1298 pipe->stream_res.tg); 1299 } 1300 } 1301 1302 void dcn20_pipe_control_lock( 1303 struct dc *dc, 1304 struct pipe_ctx *pipe, 1305 bool lock) 1306 { 1307 bool flip_immediate = false; 1308 1309 /* use TG master update lock to lock everything on the TG 1310 * therefore only top pipe need to lock 1311 */ 1312 if (pipe->top_pipe) 1313 return; 1314 1315 if (pipe->plane_state != NULL) 1316 flip_immediate = pipe->plane_state->flip_immediate; 1317 1318 if (flip_immediate && lock) { 1319 while (pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp)) { 1320 udelay(1); 1321 } 1322 1323 if (pipe->bottom_pipe != NULL) 1324 while (pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp)) { 1325 udelay(1); 1326 } 1327 } 1328 1329 /* In flip immediate and pipe splitting case, we need to use GSL 1330 * for synchronization. Only do setup on locking and on flip type change. 1331 */ 1332 if (lock && pipe->bottom_pipe != NULL) 1333 if ((flip_immediate && pipe->stream_res.gsl_group == 0) || 1334 (!flip_immediate && pipe->stream_res.gsl_group > 0)) 1335 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate); 1336 1337 if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) { 1338 if (lock) 1339 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); 1340 else 1341 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); 1342 } else { 1343 if (lock) 1344 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1345 else 1346 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1347 } 1348 } 1349 1350 static void dcn20_apply_ctx_for_surface( 1351 struct dc *dc, 1352 const struct dc_stream_state *stream, 1353 int num_planes, 1354 struct dc_state *context) 1355 { 1356 1357 int i; 1358 struct timing_generator *tg; 1359 bool removed_pipe[6] = { false }; 1360 bool interdependent_update = false; 1361 struct pipe_ctx *top_pipe_to_program = 1362 find_top_pipe_for_stream(dc, context, stream); 1363 DC_LOGGER_INIT(dc->ctx->logger); 1364 1365 if (!top_pipe_to_program) 1366 return; 1367 1368 /* Carry over GSL groups in case the context is changing. */ 1369 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1370 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1371 struct pipe_ctx *old_pipe_ctx = 1372 &dc->current_state->res_ctx.pipe_ctx[i]; 1373 1374 if (pipe_ctx->stream == stream && 1375 pipe_ctx->stream == old_pipe_ctx->stream) 1376 pipe_ctx->stream_res.gsl_group = 1377 old_pipe_ctx->stream_res.gsl_group; 1378 } 1379 1380 tg = top_pipe_to_program->stream_res.tg; 1381 1382 interdependent_update = top_pipe_to_program->plane_state && 1383 top_pipe_to_program->plane_state->update_flags.bits.full_update; 1384 1385 if (interdependent_update) 1386 lock_all_pipes(dc, context, true); 1387 else 1388 dcn20_pipe_control_lock(dc, top_pipe_to_program, true); 1389 1390 if (num_planes == 0) { 1391 /* OTG blank before remove all front end */ 1392 dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true); 1393 } 1394 1395 /* Disconnect unused mpcc */ 1396 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1397 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1398 struct pipe_ctx *old_pipe_ctx = 1399 &dc->current_state->res_ctx.pipe_ctx[i]; 1400 /* 1401 * Powergate reused pipes that are not powergated 1402 * fairly hacky right now, using opp_id as indicator 1403 * TODO: After move dc_post to dc_update, this will 1404 * be removed. 1405 */ 1406 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) { 1407 if (old_pipe_ctx->stream_res.tg == tg && 1408 old_pipe_ctx->plane_res.hubp && 1409 old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID) 1410 dcn20_disable_plane(dc, old_pipe_ctx); 1411 } 1412 1413 if ((!pipe_ctx->plane_state || 1414 pipe_ctx->stream_res.tg != old_pipe_ctx->stream_res.tg) && 1415 old_pipe_ctx->plane_state && 1416 old_pipe_ctx->stream_res.tg == tg) { 1417 1418 dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx); 1419 removed_pipe[i] = true; 1420 1421 DC_LOG_DC("Reset mpcc for pipe %d\n", 1422 old_pipe_ctx->pipe_idx); 1423 } 1424 } 1425 1426 if (num_planes > 0) 1427 dcn20_program_all_pipe_in_tree(dc, top_pipe_to_program, context); 1428 1429 /* Program secondary blending tree and writeback pipes */ 1430 if ((stream->num_wb_info > 0) && (dc->hwss.program_all_writeback_pipes_in_tree)) 1431 dc->hwss.program_all_writeback_pipes_in_tree(dc, stream, context); 1432 1433 if (interdependent_update) 1434 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1435 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1436 1437 /* Skip inactive pipes and ones already updated */ 1438 if (!pipe_ctx->stream || pipe_ctx->stream == stream || 1439 !pipe_ctx->plane_state || !tg->funcs->is_tg_enabled(tg)) 1440 continue; 1441 1442 pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent( 1443 pipe_ctx->plane_res.hubp, 1444 &pipe_ctx->dlg_regs, 1445 &pipe_ctx->ttu_regs); 1446 } 1447 1448 if (interdependent_update) 1449 lock_all_pipes(dc, context, false); 1450 else 1451 dcn20_pipe_control_lock(dc, top_pipe_to_program, false); 1452 1453 for (i = 0; i < dc->res_pool->pipe_count; i++) 1454 if (removed_pipe[i]) 1455 dcn20_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1456 } 1457 1458 1459 void dcn20_prepare_bandwidth( 1460 struct dc *dc, 1461 struct dc_state *context) 1462 { 1463 struct hubbub *hubbub = dc->res_pool->hubbub; 1464 1465 dc->clk_mgr->funcs->update_clocks( 1466 dc->clk_mgr, 1467 context, 1468 false); 1469 1470 /* program dchubbub watermarks */ 1471 hubbub->funcs->program_watermarks(hubbub, 1472 &context->bw_ctx.bw.dcn.watermarks, 1473 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1474 false); 1475 } 1476 1477 void dcn20_optimize_bandwidth( 1478 struct dc *dc, 1479 struct dc_state *context) 1480 { 1481 struct hubbub *hubbub = dc->res_pool->hubbub; 1482 1483 /* program dchubbub watermarks */ 1484 hubbub->funcs->program_watermarks(hubbub, 1485 &context->bw_ctx.bw.dcn.watermarks, 1486 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1487 true); 1488 1489 dc->clk_mgr->funcs->update_clocks( 1490 dc->clk_mgr, 1491 context, 1492 true); 1493 } 1494 1495 bool dcn20_update_bandwidth( 1496 struct dc *dc, 1497 struct dc_state *context) 1498 { 1499 int i; 1500 1501 /* recalculate DML parameters */ 1502 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) 1503 return false; 1504 1505 /* apply updated bandwidth parameters */ 1506 dc->hwss.prepare_bandwidth(dc, context); 1507 1508 /* update hubp configs for all pipes */ 1509 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1510 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1511 1512 if (pipe_ctx->plane_state == NULL) 1513 continue; 1514 1515 if (pipe_ctx->top_pipe == NULL) { 1516 bool blank = !is_pipe_tree_visible(pipe_ctx); 1517 1518 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1519 pipe_ctx->stream_res.tg, 1520 pipe_ctx->pipe_dlg_param.vready_offset, 1521 pipe_ctx->pipe_dlg_param.vstartup_start, 1522 pipe_ctx->pipe_dlg_param.vupdate_offset, 1523 pipe_ctx->pipe_dlg_param.vupdate_width); 1524 1525 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1526 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1527 1528 dc->hwss.blank_pixel_data(dc, pipe_ctx, blank); 1529 } 1530 1531 pipe_ctx->plane_res.hubp->funcs->hubp_setup( 1532 pipe_ctx->plane_res.hubp, 1533 &pipe_ctx->dlg_regs, 1534 &pipe_ctx->ttu_regs, 1535 &pipe_ctx->rq_regs, 1536 &pipe_ctx->pipe_dlg_param); 1537 } 1538 1539 return true; 1540 } 1541 1542 static void dcn20_enable_writeback( 1543 struct dc *dc, 1544 const struct dc_stream_status *stream_status, 1545 struct dc_writeback_info *wb_info) 1546 { 1547 struct dwbc *dwb; 1548 struct mcif_wb *mcif_wb; 1549 struct timing_generator *optc; 1550 1551 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 1552 ASSERT(wb_info->wb_enabled); 1553 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 1554 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 1555 1556 /* set the OPTC source mux */ 1557 ASSERT(stream_status->primary_otg_inst < MAX_PIPES); 1558 optc = dc->res_pool->timing_generators[stream_status->primary_otg_inst]; 1559 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); 1560 /* set MCIF_WB buffer and arbitration configuration */ 1561 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 1562 mcif_wb->funcs->config_mcif_arb(mcif_wb, &dc->current_state->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 1563 /* Enable MCIF_WB */ 1564 mcif_wb->funcs->enable_mcif(mcif_wb); 1565 /* Enable DWB */ 1566 dwb->funcs->enable(dwb, &wb_info->dwb_params); 1567 /* TODO: add sequence to enable/disable warmup */ 1568 } 1569 1570 void dcn20_disable_writeback( 1571 struct dc *dc, 1572 unsigned int dwb_pipe_inst) 1573 { 1574 struct dwbc *dwb; 1575 struct mcif_wb *mcif_wb; 1576 1577 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); 1578 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; 1579 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; 1580 1581 dwb->funcs->disable(dwb); 1582 mcif_wb->funcs->disable_mcif(mcif_wb); 1583 } 1584 1585 bool dcn20_hwss_wait_for_blank_complete( 1586 struct output_pixel_processor *opp) 1587 { 1588 int counter; 1589 1590 for (counter = 0; counter < 1000; counter++) { 1591 if (opp->funcs->dpg_is_blanked(opp)) 1592 break; 1593 1594 udelay(100); 1595 } 1596 1597 if (counter == 1000) { 1598 dm_error("DC: failed to blank crtc!\n"); 1599 return false; 1600 } 1601 1602 return true; 1603 } 1604 1605 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) 1606 { 1607 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1608 1609 if (!hubp) 1610 return false; 1611 return hubp->funcs->dmdata_status_done(hubp); 1612 } 1613 1614 static void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 1615 { 1616 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1617 struct dce_hwseq *hws = dc->hwseq; 1618 struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); 1619 1620 if (pipe_ctx->stream_res.dsc) { 1621 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); 1622 if (bot_odm_pipe) 1623 dcn20_dsc_pg_control(hws, bot_odm_pipe->stream_res.dsc->inst, true); 1624 } 1625 #endif 1626 } 1627 1628 static void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 1629 { 1630 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1631 struct dce_hwseq *hws = dc->hwseq; 1632 struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); 1633 1634 if (pipe_ctx->stream_res.dsc) { 1635 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false); 1636 if (bot_odm_pipe) 1637 dcn20_dsc_pg_control(hws, bot_odm_pipe->stream_res.dsc->inst, false); 1638 } 1639 #endif 1640 } 1641 1642 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) 1643 { 1644 struct dc_dmdata_attributes attr = { 0 }; 1645 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1646 1647 attr.dmdata_mode = DMDATA_HW_MODE; 1648 attr.dmdata_size = 1649 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; 1650 attr.address.quad_part = 1651 pipe_ctx->stream->dmdata_address.quad_part; 1652 attr.dmdata_dl_delta = 0; 1653 attr.dmdata_qos_mode = 0; 1654 attr.dmdata_qos_level = 0; 1655 attr.dmdata_repeat = 1; /* always repeat */ 1656 attr.dmdata_updated = 1; 1657 attr.dmdata_sw_data = NULL; 1658 1659 hubp->funcs->dmdata_set_attributes(hubp, &attr); 1660 } 1661 1662 void dcn20_disable_stream(struct pipe_ctx *pipe_ctx, int option) 1663 { 1664 dce110_disable_stream(pipe_ctx, option); 1665 } 1666 1667 static void dcn20_init_vm_ctx( 1668 struct dce_hwseq *hws, 1669 struct dc *dc, 1670 struct dc_virtual_addr_space_config *va_config, 1671 int vmid) 1672 { 1673 struct dcn_hubbub_virt_addr_config config; 1674 1675 if (vmid == 0) { 1676 ASSERT(0); /* VMID cannot be 0 for vm context */ 1677 return; 1678 } 1679 1680 config.page_table_start_addr = va_config->page_table_start_addr; 1681 config.page_table_end_addr = va_config->page_table_end_addr; 1682 config.page_table_block_size = va_config->page_table_block_size_in_bytes; 1683 config.page_table_depth = va_config->page_table_depth; 1684 config.page_table_base_addr = va_config->page_table_base_addr; 1685 1686 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); 1687 } 1688 1689 static int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 1690 { 1691 struct dcn_hubbub_phys_addr_config config; 1692 1693 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 1694 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 1695 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 1696 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 1697 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 1698 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 1699 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 1700 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 1701 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 1702 1703 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 1704 } 1705 1706 static bool patch_address_for_sbs_tb_stereo( 1707 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) 1708 { 1709 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1710 bool sec_split = pipe_ctx->top_pipe && 1711 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; 1712 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && 1713 (pipe_ctx->stream->timing.timing_3d_format == 1714 TIMING_3D_FORMAT_SIDE_BY_SIDE || 1715 pipe_ctx->stream->timing.timing_3d_format == 1716 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { 1717 *addr = plane_state->address.grph_stereo.left_addr; 1718 plane_state->address.grph_stereo.left_addr = 1719 plane_state->address.grph_stereo.right_addr; 1720 return true; 1721 } 1722 1723 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && 1724 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { 1725 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; 1726 plane_state->address.grph_stereo.right_addr = 1727 plane_state->address.grph_stereo.left_addr; 1728 } 1729 return false; 1730 } 1731 1732 1733 static void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) 1734 { 1735 bool addr_patched = false; 1736 PHYSICAL_ADDRESS_LOC addr; 1737 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1738 1739 if (plane_state == NULL) 1740 return; 1741 1742 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); 1743 1744 // Call Helper to track VMID use 1745 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); 1746 1747 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( 1748 pipe_ctx->plane_res.hubp, 1749 &plane_state->address, 1750 plane_state->flip_immediate); 1751 1752 plane_state->status.requested_address = plane_state->address; 1753 1754 if (plane_state->flip_immediate) 1755 plane_state->status.current_address = plane_state->address; 1756 1757 if (addr_patched) 1758 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; 1759 } 1760 1761 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, 1762 struct dc_link_settings *link_settings) 1763 { 1764 struct encoder_unblank_param params = { { 0 } }; 1765 struct dc_stream_state *stream = pipe_ctx->stream; 1766 struct dc_link *link = stream->link; 1767 params.odm = dc_res_get_odm_bottom_pipe(pipe_ctx); 1768 1769 /* only 3 items below are used by unblank */ 1770 params.timing = pipe_ctx->stream->timing; 1771 1772 params.link_settings.link_rate = link_settings->link_rate; 1773 1774 if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1775 if (optc1_is_two_pixels_per_containter(&stream->timing) || params.odm) 1776 params.timing.pix_clk_100hz /= 2; 1777 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 1778 pipe_ctx->stream_res.stream_enc, params.odm); 1779 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); 1780 } 1781 1782 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1783 link->dc->hwss.edp_backlight_control(link, true); 1784 } 1785 } 1786 1787 void dcn20_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx) 1788 { 1789 struct timing_generator *tg = pipe_ctx->stream_res.tg; 1790 int start_line = get_vupdate_offset_from_vsync(pipe_ctx); 1791 1792 if (start_line < 0) 1793 start_line = 0; 1794 1795 if (tg->funcs->setup_vertical_interrupt2) 1796 tg->funcs->setup_vertical_interrupt2(tg, start_line); 1797 } 1798 1799 static void dcn20_reset_back_end_for_pipe( 1800 struct dc *dc, 1801 struct pipe_ctx *pipe_ctx, 1802 struct dc_state *context) 1803 { 1804 int i; 1805 DC_LOGGER_INIT(dc->ctx->logger); 1806 if (pipe_ctx->stream_res.stream_enc == NULL) { 1807 pipe_ctx->stream = NULL; 1808 return; 1809 } 1810 1811 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 1812 /* DPMS may already disable */ 1813 if (!pipe_ctx->stream->dpms_off) 1814 core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE); 1815 else if (pipe_ctx->stream_res.audio) { 1816 dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE); 1817 } 1818 } 1819 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1820 else if (pipe_ctx->stream_res.dsc) { 1821 dp_set_dsc_enable(pipe_ctx, false); 1822 } 1823 #endif 1824 1825 /* by upper caller loop, parent pipe: pipe0, will be reset last. 1826 * back end share by all pipes and will be disable only when disable 1827 * parent pipe. 1828 */ 1829 if (pipe_ctx->top_pipe == NULL) { 1830 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 1831 1832 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 1833 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 1834 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1835 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1836 1837 if (pipe_ctx->stream_res.tg->funcs->set_drr) 1838 pipe_ctx->stream_res.tg->funcs->set_drr( 1839 pipe_ctx->stream_res.tg, NULL); 1840 } 1841 1842 for (i = 0; i < dc->res_pool->pipe_count; i++) 1843 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) 1844 break; 1845 1846 if (i == dc->res_pool->pipe_count) 1847 return; 1848 1849 pipe_ctx->stream = NULL; 1850 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 1851 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 1852 } 1853 1854 static void dcn20_reset_hw_ctx_wrap( 1855 struct dc *dc, 1856 struct dc_state *context) 1857 { 1858 int i; 1859 1860 /* Reset Back End*/ 1861 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 1862 struct pipe_ctx *pipe_ctx_old = 1863 &dc->current_state->res_ctx.pipe_ctx[i]; 1864 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1865 1866 if (!pipe_ctx_old->stream) 1867 continue; 1868 1869 if (pipe_ctx_old->top_pipe) 1870 continue; 1871 1872 if (!pipe_ctx->stream || 1873 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 1874 struct clock_source *old_clk = pipe_ctx_old->clock_source; 1875 1876 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 1877 if (dc->hwss.enable_stream_gating) 1878 dc->hwss.enable_stream_gating(dc, pipe_ctx); 1879 if (old_clk) 1880 old_clk->funcs->cs_power_down(old_clk); 1881 } 1882 } 1883 } 1884 1885 static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 1886 { 1887 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1888 struct mpcc_blnd_cfg blnd_cfg = { {0} }; 1889 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; 1890 int mpcc_id; 1891 struct mpcc *new_mpcc; 1892 struct mpc *mpc = dc->res_pool->mpc; 1893 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); 1894 1895 // input to MPCC is always RGB, by default leave black_color at 0 1896 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) { 1897 dcn10_get_hdr_visual_confirm_color( 1898 pipe_ctx, &blnd_cfg.black_color); 1899 } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) { 1900 dcn10_get_surface_visual_confirm_color( 1901 pipe_ctx, &blnd_cfg.black_color); 1902 } 1903 1904 if (per_pixel_alpha) 1905 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 1906 else 1907 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 1908 1909 blnd_cfg.overlap_only = false; 1910 blnd_cfg.global_gain = 0xff; 1911 1912 if (pipe_ctx->plane_state->global_alpha) 1913 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; 1914 else 1915 blnd_cfg.global_alpha = 0xff; 1916 1917 blnd_cfg.background_color_bpc = 4; 1918 blnd_cfg.bottom_gain_mode = 0; 1919 blnd_cfg.top_gain = 0x1f000; 1920 blnd_cfg.bottom_inside_gain = 0x1f000; 1921 blnd_cfg.bottom_outside_gain = 0x1f000; 1922 blnd_cfg.pre_multiplied_alpha = per_pixel_alpha; 1923 1924 /* 1925 * TODO: remove hack 1926 * Note: currently there is a bug in init_hw such that 1927 * on resume from hibernate, BIOS sets up MPCC0, and 1928 * we do mpcc_remove but the mpcc cannot go to idle 1929 * after remove. This cause us to pick mpcc1 here, 1930 * which causes a pstate hang for yet unknown reason. 1931 */ 1932 mpcc_id = hubp->inst; 1933 1934 /* If there is no full update, don't need to touch MPC tree*/ 1935 if (!pipe_ctx->plane_state->update_flags.bits.full_update) { 1936 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); 1937 return; 1938 } 1939 1940 /* check if this MPCC is already being used */ 1941 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 1942 /* remove MPCC if being used */ 1943 if (new_mpcc != NULL) 1944 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); 1945 else 1946 if (dc->debug.sanity_checks) 1947 mpc->funcs->assert_mpcc_idle_before_connect( 1948 dc->res_pool->mpc, mpcc_id); 1949 1950 /* Call MPC to insert new plane */ 1951 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, 1952 mpc_tree_params, 1953 &blnd_cfg, 1954 NULL, 1955 NULL, 1956 hubp->inst, 1957 mpcc_id); 1958 1959 ASSERT(new_mpcc != NULL); 1960 hubp->opp_id = pipe_ctx->stream_res.opp->inst; 1961 hubp->mpcc_id = mpcc_id; 1962 } 1963 1964 static int find_free_gsl_group(const struct dc *dc) 1965 { 1966 if (dc->res_pool->gsl_groups.gsl_0 == 0) 1967 return 1; 1968 if (dc->res_pool->gsl_groups.gsl_1 == 0) 1969 return 2; 1970 if (dc->res_pool->gsl_groups.gsl_2 == 0) 1971 return 3; 1972 1973 return 0; 1974 } 1975 1976 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock) 1977 * This is only used to lock pipes in pipe splitting case with immediate flip 1978 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate, 1979 * so we get tearing with freesync since we cannot flip multiple pipes 1980 * atomically. 1981 * We use GSL for this: 1982 * - immediate flip: find first available GSL group if not already assigned 1983 * program gsl with that group, set current OTG as master 1984 * and always us 0x4 = AND of flip_ready from all pipes 1985 * - vsync flip: disable GSL if used 1986 * 1987 * Groups in stream_res are stored as +1 from HW registers, i.e. 1988 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1 1989 * Using a magic value like -1 would require tracking all inits/resets 1990 */ 1991 void dcn20_setup_gsl_group_as_lock( 1992 const struct dc *dc, 1993 struct pipe_ctx *pipe_ctx, 1994 bool enable) 1995 { 1996 struct gsl_params gsl; 1997 int group_idx; 1998 1999 memset(&gsl, 0, sizeof(struct gsl_params)); 2000 2001 if (enable) { 2002 /* return if group already assigned since GSL was set up 2003 * for vsync flip, we would unassign so it can't be "left over" 2004 */ 2005 if (pipe_ctx->stream_res.gsl_group > 0) 2006 return; 2007 2008 group_idx = find_free_gsl_group(dc); 2009 ASSERT(group_idx != 0); 2010 pipe_ctx->stream_res.gsl_group = group_idx; 2011 2012 /* set gsl group reg field and mark resource used */ 2013 switch (group_idx) { 2014 case 1: 2015 gsl.gsl0_en = 1; 2016 dc->res_pool->gsl_groups.gsl_0 = 1; 2017 break; 2018 case 2: 2019 gsl.gsl1_en = 1; 2020 dc->res_pool->gsl_groups.gsl_1 = 1; 2021 break; 2022 case 3: 2023 gsl.gsl2_en = 1; 2024 dc->res_pool->gsl_groups.gsl_2 = 1; 2025 break; 2026 default: 2027 BREAK_TO_DEBUGGER(); 2028 return; // invalid case 2029 } 2030 gsl.gsl_master_en = 1; 2031 } else { 2032 group_idx = pipe_ctx->stream_res.gsl_group; 2033 if (group_idx == 0) 2034 return; // if not in use, just return 2035 2036 pipe_ctx->stream_res.gsl_group = 0; 2037 2038 /* unset gsl group reg field and mark resource free */ 2039 switch (group_idx) { 2040 case 1: 2041 gsl.gsl0_en = 0; 2042 dc->res_pool->gsl_groups.gsl_0 = 0; 2043 break; 2044 case 2: 2045 gsl.gsl1_en = 0; 2046 dc->res_pool->gsl_groups.gsl_1 = 0; 2047 break; 2048 case 3: 2049 gsl.gsl2_en = 0; 2050 dc->res_pool->gsl_groups.gsl_2 = 0; 2051 break; 2052 default: 2053 BREAK_TO_DEBUGGER(); 2054 return; 2055 } 2056 gsl.gsl_master_en = 0; 2057 } 2058 2059 /* at this point we want to program whether it's to enable or disable */ 2060 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && 2061 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { 2062 pipe_ctx->stream_res.tg->funcs->set_gsl( 2063 pipe_ctx->stream_res.tg, 2064 &gsl); 2065 2066 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( 2067 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); 2068 } else 2069 BREAK_TO_DEBUGGER(); 2070 } 2071 2072 static void dcn20_set_flip_control_gsl( 2073 struct pipe_ctx *pipe_ctx, 2074 bool flip_immediate) 2075 { 2076 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) 2077 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( 2078 pipe_ctx->plane_res.hubp, flip_immediate); 2079 2080 } 2081 2082 static void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 2083 { 2084 enum dc_lane_count lane_count = 2085 pipe_ctx->stream->link->cur_link_settings.lane_count; 2086 2087 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 2088 struct dc_link *link = pipe_ctx->stream->link; 2089 2090 uint32_t active_total_with_borders; 2091 uint32_t early_control = 0; 2092 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2093 2094 /* For MST, there are multiply stream go to only one link. 2095 * connect DIG back_end to front_end while enable_stream and 2096 * disconnect them during disable_stream 2097 * BY this, it is logic clean to separate stream and link 2098 */ 2099 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, 2100 pipe_ctx->stream_res.stream_enc->id, true); 2101 2102 if (link->dc->hwss.program_dmdata_engine) 2103 link->dc->hwss.program_dmdata_engine(pipe_ctx); 2104 2105 link->dc->hwss.update_info_frame(pipe_ctx); 2106 2107 /* enable early control to avoid corruption on DP monitor*/ 2108 active_total_with_borders = 2109 timing->h_addressable 2110 + timing->h_border_left 2111 + timing->h_border_right; 2112 2113 if (lane_count != 0) 2114 early_control = active_total_with_borders % lane_count; 2115 2116 if (early_control == 0) 2117 early_control = lane_count; 2118 2119 tg->funcs->set_early_control(tg, early_control); 2120 2121 /* enable audio only within mode set */ 2122 if (pipe_ctx->stream_res.audio != NULL) { 2123 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2124 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 2125 } 2126 } 2127 2128 static void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx) 2129 { 2130 struct dc_stream_state *stream = pipe_ctx->stream; 2131 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2132 bool enable = false; 2133 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2134 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) 2135 ? dmdata_dp 2136 : dmdata_hdmi; 2137 2138 /* if using dynamic meta, don't set up generic infopackets */ 2139 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { 2140 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; 2141 enable = true; 2142 } 2143 2144 if (!hubp) 2145 return; 2146 2147 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) 2148 return; 2149 2150 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, 2151 hubp->inst, mode); 2152 } 2153 2154 void dcn20_hw_sequencer_construct(struct dc *dc) 2155 { 2156 dcn10_hw_sequencer_construct(dc); 2157 dc->hwss.init_hw = dcn20_init_hw; 2158 dc->hwss.init_pipes = NULL; 2159 dc->hwss.unblank_stream = dcn20_unblank_stream; 2160 dc->hwss.update_plane_addr = dcn20_update_plane_addr; 2161 dc->hwss.disable_plane = dcn20_disable_plane, 2162 dc->hwss.enable_stream_timing = dcn20_enable_stream_timing; 2163 dc->hwss.program_triplebuffer = dcn20_program_tripleBuffer; 2164 dc->hwss.set_input_transfer_func = dcn20_set_input_transfer_func; 2165 dc->hwss.set_output_transfer_func = dcn20_set_output_transfer_func; 2166 dc->hwss.apply_ctx_for_surface = dcn20_apply_ctx_for_surface; 2167 dc->hwss.pipe_control_lock = dcn20_pipe_control_lock; 2168 dc->hwss.pipe_control_lock_global = dcn20_pipe_control_lock_global; 2169 dc->hwss.optimize_bandwidth = dcn20_optimize_bandwidth; 2170 dc->hwss.prepare_bandwidth = dcn20_prepare_bandwidth; 2171 dc->hwss.update_bandwidth = dcn20_update_bandwidth; 2172 dc->hwss.enable_writeback = dcn20_enable_writeback; 2173 dc->hwss.disable_writeback = dcn20_disable_writeback; 2174 dc->hwss.program_output_csc = dcn20_program_output_csc; 2175 dc->hwss.update_odm = dcn20_update_odm; 2176 dc->hwss.blank_pixel_data = dcn20_blank_pixel_data; 2177 dc->hwss.dmdata_status_done = dcn20_dmdata_status_done; 2178 dc->hwss.program_dmdata_engine = dcn20_program_dmdata_engine; 2179 dc->hwss.enable_stream = dcn20_enable_stream; 2180 dc->hwss.disable_stream = dcn20_disable_stream; 2181 dc->hwss.init_sys_ctx = dcn20_init_sys_ctx; 2182 dc->hwss.init_vm_ctx = dcn20_init_vm_ctx; 2183 dc->hwss.disable_stream_gating = dcn20_disable_stream_gating; 2184 dc->hwss.enable_stream_gating = dcn20_enable_stream_gating; 2185 dc->hwss.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt; 2186 dc->hwss.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap; 2187 dc->hwss.update_mpcc = dcn20_update_mpcc; 2188 dc->hwss.set_flip_control_gsl = dcn20_set_flip_control_gsl; 2189 dc->hwss.did_underflow_occur = dcn10_did_underflow_occur; 2190 } 2191