1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include <linux/delay.h> 26 27 #include "dm_services.h" 28 #include "basics/dc_common.h" 29 #include "dm_helpers.h" 30 #include "core_types.h" 31 #include "resource.h" 32 #include "dcn20_resource.h" 33 #include "dcn20_hwseq.h" 34 #include "dce/dce_hwseq.h" 35 #include "dcn20_dsc.h" 36 #include "dcn20_optc.h" 37 #include "abm.h" 38 #include "clk_mgr.h" 39 #include "dmcu.h" 40 #include "hubp.h" 41 #include "timing_generator.h" 42 #include "opp.h" 43 #include "ipp.h" 44 #include "mpc.h" 45 #include "mcif_wb.h" 46 #include "dchubbub.h" 47 #include "reg_helper.h" 48 #include "dcn10/dcn10_cm_common.h" 49 #include "vm_helper.h" 50 #include "dccg.h" 51 #include "dc_dmub_srv.h" 52 #include "dce/dmub_hw_lock_mgr.h" 53 #include "hw_sequencer.h" 54 #include "dpcd_defs.h" 55 #include "inc/link_enc_cfg.h" 56 #include "link_hwss.h" 57 #include "link.h" 58 59 #define DC_LOGGER_INIT(logger) 60 61 #define CTX \ 62 hws->ctx 63 #define REG(reg)\ 64 hws->regs->reg 65 66 #undef FN 67 #define FN(reg_name, field_name) \ 68 hws->shifts->field_name, hws->masks->field_name 69 70 static int find_free_gsl_group(const struct dc *dc) 71 { 72 if (dc->res_pool->gsl_groups.gsl_0 == 0) 73 return 1; 74 if (dc->res_pool->gsl_groups.gsl_1 == 0) 75 return 2; 76 if (dc->res_pool->gsl_groups.gsl_2 == 0) 77 return 3; 78 79 return 0; 80 } 81 82 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock) 83 * This is only used to lock pipes in pipe splitting case with immediate flip 84 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate, 85 * so we get tearing with freesync since we cannot flip multiple pipes 86 * atomically. 87 * We use GSL for this: 88 * - immediate flip: find first available GSL group if not already assigned 89 * program gsl with that group, set current OTG as master 90 * and always us 0x4 = AND of flip_ready from all pipes 91 * - vsync flip: disable GSL if used 92 * 93 * Groups in stream_res are stored as +1 from HW registers, i.e. 94 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1 95 * Using a magic value like -1 would require tracking all inits/resets 96 */ 97 static void dcn20_setup_gsl_group_as_lock( 98 const struct dc *dc, 99 struct pipe_ctx *pipe_ctx, 100 bool enable) 101 { 102 struct gsl_params gsl; 103 int group_idx; 104 105 memset(&gsl, 0, sizeof(struct gsl_params)); 106 107 if (enable) { 108 /* return if group already assigned since GSL was set up 109 * for vsync flip, we would unassign so it can't be "left over" 110 */ 111 if (pipe_ctx->stream_res.gsl_group > 0) 112 return; 113 114 group_idx = find_free_gsl_group(dc); 115 ASSERT(group_idx != 0); 116 pipe_ctx->stream_res.gsl_group = group_idx; 117 118 /* set gsl group reg field and mark resource used */ 119 switch (group_idx) { 120 case 1: 121 gsl.gsl0_en = 1; 122 dc->res_pool->gsl_groups.gsl_0 = 1; 123 break; 124 case 2: 125 gsl.gsl1_en = 1; 126 dc->res_pool->gsl_groups.gsl_1 = 1; 127 break; 128 case 3: 129 gsl.gsl2_en = 1; 130 dc->res_pool->gsl_groups.gsl_2 = 1; 131 break; 132 default: 133 BREAK_TO_DEBUGGER(); 134 return; // invalid case 135 } 136 gsl.gsl_master_en = 1; 137 } else { 138 group_idx = pipe_ctx->stream_res.gsl_group; 139 if (group_idx == 0) 140 return; // if not in use, just return 141 142 pipe_ctx->stream_res.gsl_group = 0; 143 144 /* unset gsl group reg field and mark resource free */ 145 switch (group_idx) { 146 case 1: 147 gsl.gsl0_en = 0; 148 dc->res_pool->gsl_groups.gsl_0 = 0; 149 break; 150 case 2: 151 gsl.gsl1_en = 0; 152 dc->res_pool->gsl_groups.gsl_1 = 0; 153 break; 154 case 3: 155 gsl.gsl2_en = 0; 156 dc->res_pool->gsl_groups.gsl_2 = 0; 157 break; 158 default: 159 BREAK_TO_DEBUGGER(); 160 return; 161 } 162 gsl.gsl_master_en = 0; 163 } 164 165 /* at this point we want to program whether it's to enable or disable */ 166 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && 167 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { 168 pipe_ctx->stream_res.tg->funcs->set_gsl( 169 pipe_ctx->stream_res.tg, 170 &gsl); 171 172 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( 173 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); 174 } else 175 BREAK_TO_DEBUGGER(); 176 } 177 178 void dcn20_set_flip_control_gsl( 179 struct pipe_ctx *pipe_ctx, 180 bool flip_immediate) 181 { 182 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) 183 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( 184 pipe_ctx->plane_res.hubp, flip_immediate); 185 186 } 187 188 void dcn20_enable_power_gating_plane( 189 struct dce_hwseq *hws, 190 bool enable) 191 { 192 bool force_on = true; /* disable power gating */ 193 uint32_t org_ip_request_cntl = 0; 194 195 if (enable) 196 force_on = false; 197 198 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 199 if (org_ip_request_cntl == 0) 200 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 201 202 /* DCHUBP0/1/2/3/4/5 */ 203 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); 204 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); 205 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); 206 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); 207 if (REG(DOMAIN8_PG_CONFIG)) 208 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 209 if (REG(DOMAIN10_PG_CONFIG)) 210 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 211 212 /* DPP0/1/2/3/4/5 */ 213 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); 214 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); 215 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); 216 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); 217 if (REG(DOMAIN9_PG_CONFIG)) 218 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 219 if (REG(DOMAIN11_PG_CONFIG)) 220 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 221 222 /* DCS0/1/2/3/4/5 */ 223 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on); 224 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on); 225 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on); 226 if (REG(DOMAIN19_PG_CONFIG)) 227 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on); 228 if (REG(DOMAIN20_PG_CONFIG)) 229 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on); 230 if (REG(DOMAIN21_PG_CONFIG)) 231 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); 232 233 if (org_ip_request_cntl == 0) 234 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 235 236 } 237 238 void dcn20_dccg_init(struct dce_hwseq *hws) 239 { 240 /* 241 * set MICROSECOND_TIME_BASE_DIV 242 * 100Mhz refclk -> 0x120264 243 * 27Mhz refclk -> 0x12021b 244 * 48Mhz refclk -> 0x120230 245 * 246 */ 247 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); 248 249 /* 250 * set MILLISECOND_TIME_BASE_DIV 251 * 100Mhz refclk -> 0x1186a0 252 * 27Mhz refclk -> 0x106978 253 * 48Mhz refclk -> 0x10bb80 254 * 255 */ 256 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); 257 258 /* This value is dependent on the hardware pipeline delay so set once per SOC */ 259 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c); 260 } 261 262 void dcn20_disable_vga( 263 struct dce_hwseq *hws) 264 { 265 REG_WRITE(D1VGA_CONTROL, 0); 266 REG_WRITE(D2VGA_CONTROL, 0); 267 REG_WRITE(D3VGA_CONTROL, 0); 268 REG_WRITE(D4VGA_CONTROL, 0); 269 REG_WRITE(D5VGA_CONTROL, 0); 270 REG_WRITE(D6VGA_CONTROL, 0); 271 } 272 273 void dcn20_program_triple_buffer( 274 const struct dc *dc, 275 struct pipe_ctx *pipe_ctx, 276 bool enable_triple_buffer) 277 { 278 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { 279 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( 280 pipe_ctx->plane_res.hubp, 281 enable_triple_buffer); 282 } 283 } 284 285 /* Blank pixel data during initialization */ 286 void dcn20_init_blank( 287 struct dc *dc, 288 struct timing_generator *tg) 289 { 290 struct dce_hwseq *hws = dc->hwseq; 291 enum dc_color_space color_space; 292 struct tg_color black_color = {0}; 293 struct output_pixel_processor *opp = NULL; 294 struct output_pixel_processor *bottom_opp = NULL; 295 uint32_t num_opps, opp_id_src0, opp_id_src1; 296 uint32_t otg_active_width, otg_active_height; 297 298 /* program opp dpg blank color */ 299 color_space = COLOR_SPACE_SRGB; 300 color_space_to_black_color(dc, color_space, &black_color); 301 302 /* get the OTG active size */ 303 tg->funcs->get_otg_active_size(tg, 304 &otg_active_width, 305 &otg_active_height); 306 307 /* get the OPTC source */ 308 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 309 310 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { 311 ASSERT(false); 312 return; 313 } 314 opp = dc->res_pool->opps[opp_id_src0]; 315 316 /* don't override the blank pattern if already enabled with the correct one. */ 317 if (opp->funcs->dpg_is_blanked && opp->funcs->dpg_is_blanked(opp)) 318 return; 319 320 if (num_opps == 2) { 321 otg_active_width = otg_active_width / 2; 322 323 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { 324 ASSERT(false); 325 return; 326 } 327 bottom_opp = dc->res_pool->opps[opp_id_src1]; 328 } 329 330 opp->funcs->opp_set_disp_pattern_generator( 331 opp, 332 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 333 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 334 COLOR_DEPTH_UNDEFINED, 335 &black_color, 336 otg_active_width, 337 otg_active_height, 338 0); 339 340 if (num_opps == 2) { 341 bottom_opp->funcs->opp_set_disp_pattern_generator( 342 bottom_opp, 343 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 344 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 345 COLOR_DEPTH_UNDEFINED, 346 &black_color, 347 otg_active_width, 348 otg_active_height, 349 0); 350 } 351 352 hws->funcs.wait_for_blank_complete(opp); 353 } 354 355 void dcn20_dsc_pg_control( 356 struct dce_hwseq *hws, 357 unsigned int dsc_inst, 358 bool power_on) 359 { 360 uint32_t power_gate = power_on ? 0 : 1; 361 uint32_t pwr_status = power_on ? 0 : 2; 362 uint32_t org_ip_request_cntl = 0; 363 364 if (hws->ctx->dc->debug.disable_dsc_power_gate) 365 return; 366 367 if (REG(DOMAIN16_PG_CONFIG) == 0) 368 return; 369 370 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 371 if (org_ip_request_cntl == 0) 372 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 373 374 switch (dsc_inst) { 375 case 0: /* DSC0 */ 376 REG_UPDATE(DOMAIN16_PG_CONFIG, 377 DOMAIN16_POWER_GATE, power_gate); 378 379 REG_WAIT(DOMAIN16_PG_STATUS, 380 DOMAIN16_PGFSM_PWR_STATUS, pwr_status, 381 1, 1000); 382 break; 383 case 1: /* DSC1 */ 384 REG_UPDATE(DOMAIN17_PG_CONFIG, 385 DOMAIN17_POWER_GATE, power_gate); 386 387 REG_WAIT(DOMAIN17_PG_STATUS, 388 DOMAIN17_PGFSM_PWR_STATUS, pwr_status, 389 1, 1000); 390 break; 391 case 2: /* DSC2 */ 392 REG_UPDATE(DOMAIN18_PG_CONFIG, 393 DOMAIN18_POWER_GATE, power_gate); 394 395 REG_WAIT(DOMAIN18_PG_STATUS, 396 DOMAIN18_PGFSM_PWR_STATUS, pwr_status, 397 1, 1000); 398 break; 399 case 3: /* DSC3 */ 400 REG_UPDATE(DOMAIN19_PG_CONFIG, 401 DOMAIN19_POWER_GATE, power_gate); 402 403 REG_WAIT(DOMAIN19_PG_STATUS, 404 DOMAIN19_PGFSM_PWR_STATUS, pwr_status, 405 1, 1000); 406 break; 407 case 4: /* DSC4 */ 408 REG_UPDATE(DOMAIN20_PG_CONFIG, 409 DOMAIN20_POWER_GATE, power_gate); 410 411 REG_WAIT(DOMAIN20_PG_STATUS, 412 DOMAIN20_PGFSM_PWR_STATUS, pwr_status, 413 1, 1000); 414 break; 415 case 5: /* DSC5 */ 416 REG_UPDATE(DOMAIN21_PG_CONFIG, 417 DOMAIN21_POWER_GATE, power_gate); 418 419 REG_WAIT(DOMAIN21_PG_STATUS, 420 DOMAIN21_PGFSM_PWR_STATUS, pwr_status, 421 1, 1000); 422 break; 423 default: 424 BREAK_TO_DEBUGGER(); 425 break; 426 } 427 428 if (org_ip_request_cntl == 0) 429 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 430 } 431 432 void dcn20_dpp_pg_control( 433 struct dce_hwseq *hws, 434 unsigned int dpp_inst, 435 bool power_on) 436 { 437 uint32_t power_gate = power_on ? 0 : 1; 438 uint32_t pwr_status = power_on ? 0 : 2; 439 440 if (hws->ctx->dc->debug.disable_dpp_power_gate) 441 return; 442 if (REG(DOMAIN1_PG_CONFIG) == 0) 443 return; 444 445 switch (dpp_inst) { 446 case 0: /* DPP0 */ 447 REG_UPDATE(DOMAIN1_PG_CONFIG, 448 DOMAIN1_POWER_GATE, power_gate); 449 450 REG_WAIT(DOMAIN1_PG_STATUS, 451 DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 452 1, 1000); 453 break; 454 case 1: /* DPP1 */ 455 REG_UPDATE(DOMAIN3_PG_CONFIG, 456 DOMAIN3_POWER_GATE, power_gate); 457 458 REG_WAIT(DOMAIN3_PG_STATUS, 459 DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 460 1, 1000); 461 break; 462 case 2: /* DPP2 */ 463 REG_UPDATE(DOMAIN5_PG_CONFIG, 464 DOMAIN5_POWER_GATE, power_gate); 465 466 REG_WAIT(DOMAIN5_PG_STATUS, 467 DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 468 1, 1000); 469 break; 470 case 3: /* DPP3 */ 471 REG_UPDATE(DOMAIN7_PG_CONFIG, 472 DOMAIN7_POWER_GATE, power_gate); 473 474 REG_WAIT(DOMAIN7_PG_STATUS, 475 DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 476 1, 1000); 477 break; 478 case 4: /* DPP4 */ 479 REG_UPDATE(DOMAIN9_PG_CONFIG, 480 DOMAIN9_POWER_GATE, power_gate); 481 482 REG_WAIT(DOMAIN9_PG_STATUS, 483 DOMAIN9_PGFSM_PWR_STATUS, pwr_status, 484 1, 1000); 485 break; 486 case 5: /* DPP5 */ 487 /* 488 * Do not power gate DPP5, should be left at HW default, power on permanently. 489 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 490 * reset. 491 * REG_UPDATE(DOMAIN11_PG_CONFIG, 492 * DOMAIN11_POWER_GATE, power_gate); 493 * 494 * REG_WAIT(DOMAIN11_PG_STATUS, 495 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, 496 * 1, 1000); 497 */ 498 break; 499 default: 500 BREAK_TO_DEBUGGER(); 501 break; 502 } 503 } 504 505 506 void dcn20_hubp_pg_control( 507 struct dce_hwseq *hws, 508 unsigned int hubp_inst, 509 bool power_on) 510 { 511 uint32_t power_gate = power_on ? 0 : 1; 512 uint32_t pwr_status = power_on ? 0 : 2; 513 514 if (hws->ctx->dc->debug.disable_hubp_power_gate) 515 return; 516 if (REG(DOMAIN0_PG_CONFIG) == 0) 517 return; 518 519 switch (hubp_inst) { 520 case 0: /* DCHUBP0 */ 521 REG_UPDATE(DOMAIN0_PG_CONFIG, 522 DOMAIN0_POWER_GATE, power_gate); 523 524 REG_WAIT(DOMAIN0_PG_STATUS, 525 DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 526 1, 1000); 527 break; 528 case 1: /* DCHUBP1 */ 529 REG_UPDATE(DOMAIN2_PG_CONFIG, 530 DOMAIN2_POWER_GATE, power_gate); 531 532 REG_WAIT(DOMAIN2_PG_STATUS, 533 DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 534 1, 1000); 535 break; 536 case 2: /* DCHUBP2 */ 537 REG_UPDATE(DOMAIN4_PG_CONFIG, 538 DOMAIN4_POWER_GATE, power_gate); 539 540 REG_WAIT(DOMAIN4_PG_STATUS, 541 DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 542 1, 1000); 543 break; 544 case 3: /* DCHUBP3 */ 545 REG_UPDATE(DOMAIN6_PG_CONFIG, 546 DOMAIN6_POWER_GATE, power_gate); 547 548 REG_WAIT(DOMAIN6_PG_STATUS, 549 DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 550 1, 1000); 551 break; 552 case 4: /* DCHUBP4 */ 553 REG_UPDATE(DOMAIN8_PG_CONFIG, 554 DOMAIN8_POWER_GATE, power_gate); 555 556 REG_WAIT(DOMAIN8_PG_STATUS, 557 DOMAIN8_PGFSM_PWR_STATUS, pwr_status, 558 1, 1000); 559 break; 560 case 5: /* DCHUBP5 */ 561 /* 562 * Do not power gate DCHUB5, should be left at HW default, power on permanently. 563 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 564 * reset. 565 * REG_UPDATE(DOMAIN10_PG_CONFIG, 566 * DOMAIN10_POWER_GATE, power_gate); 567 * 568 * REG_WAIT(DOMAIN10_PG_STATUS, 569 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status, 570 * 1, 1000); 571 */ 572 break; 573 default: 574 BREAK_TO_DEBUGGER(); 575 break; 576 } 577 } 578 579 580 /* disable HW used by plane. 581 * note: cannot disable until disconnect is complete 582 */ 583 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 584 { 585 struct dce_hwseq *hws = dc->hwseq; 586 struct hubp *hubp = pipe_ctx->plane_res.hubp; 587 struct dpp *dpp = pipe_ctx->plane_res.dpp; 588 589 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); 590 591 /* In flip immediate with pipe splitting case GSL is used for 592 * synchronization so we must disable it when the plane is disabled. 593 */ 594 if (pipe_ctx->stream_res.gsl_group != 0) 595 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false); 596 597 if (hubp->funcs->hubp_update_mall_sel) 598 hubp->funcs->hubp_update_mall_sel(hubp, 0, false); 599 600 dc->hwss.set_flip_control_gsl(pipe_ctx, false); 601 602 hubp->funcs->hubp_clk_cntl(hubp, false); 603 604 dpp->funcs->dpp_dppclk_control(dpp, false, false); 605 606 hubp->power_gated = true; 607 608 hws->funcs.plane_atomic_power_down(dc, 609 pipe_ctx->plane_res.dpp, 610 pipe_ctx->plane_res.hubp); 611 612 pipe_ctx->stream = NULL; 613 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); 614 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); 615 pipe_ctx->top_pipe = NULL; 616 pipe_ctx->bottom_pipe = NULL; 617 pipe_ctx->plane_state = NULL; 618 } 619 620 621 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) 622 { 623 bool is_phantom = pipe_ctx->plane_state && pipe_ctx->plane_state->is_phantom; 624 struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL; 625 626 DC_LOGGER_INIT(dc->ctx->logger); 627 628 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) 629 return; 630 631 dcn20_plane_atomic_disable(dc, pipe_ctx); 632 633 /* Turn back off the phantom OTG after the phantom plane is fully disabled 634 */ 635 if (is_phantom) 636 if (tg && tg->funcs->disable_phantom_crtc) 637 tg->funcs->disable_phantom_crtc(tg); 638 639 DC_LOG_DC("Power down front end %d\n", 640 pipe_ctx->pipe_idx); 641 } 642 643 void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank) 644 { 645 dcn20_blank_pixel_data(dc, pipe_ctx, blank); 646 } 647 648 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 649 int opp_cnt) 650 { 651 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 652 int flow_ctrl_cnt; 653 654 if (opp_cnt >= 2) 655 hblank_halved = true; 656 657 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 658 stream->timing.h_border_left - 659 stream->timing.h_border_right; 660 661 if (hblank_halved) 662 flow_ctrl_cnt /= 2; 663 664 /* ODM combine 4:1 case */ 665 if (opp_cnt == 4) 666 flow_ctrl_cnt /= 2; 667 668 return flow_ctrl_cnt; 669 } 670 671 enum dc_status dcn20_enable_stream_timing( 672 struct pipe_ctx *pipe_ctx, 673 struct dc_state *context, 674 struct dc *dc) 675 { 676 struct dce_hwseq *hws = dc->hwseq; 677 struct dc_stream_state *stream = pipe_ctx->stream; 678 struct drr_params params = {0}; 679 unsigned int event_triggers = 0; 680 struct pipe_ctx *odm_pipe; 681 int opp_cnt = 1; 682 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 683 bool interlace = stream->timing.flags.INTERLACE; 684 int i; 685 struct mpc_dwb_flow_control flow_control; 686 struct mpc *mpc = dc->res_pool->mpc; 687 bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing)); 688 unsigned int k1_div = PIXEL_RATE_DIV_NA; 689 unsigned int k2_div = PIXEL_RATE_DIV_NA; 690 691 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { 692 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); 693 694 dc->res_pool->dccg->funcs->set_pixel_rate_div( 695 dc->res_pool->dccg, 696 pipe_ctx->stream_res.tg->inst, 697 k1_div, k2_div); 698 } 699 /* by upper caller loop, pipe0 is parent pipe and be called first. 700 * back end is set up by for pipe0. Other children pipe share back end 701 * with pipe 0. No program is needed. 702 */ 703 if (pipe_ctx->top_pipe != NULL) 704 return DC_OK; 705 706 /* TODO check if timing_changed, disable stream if timing changed */ 707 708 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 709 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 710 opp_cnt++; 711 } 712 713 if (opp_cnt > 1) 714 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 715 pipe_ctx->stream_res.tg, 716 opp_inst, opp_cnt, 717 &pipe_ctx->stream->timing); 718 719 /* HW program guide assume display already disable 720 * by unplug sequence. OTG assume stop. 721 */ 722 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); 723 724 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 725 pipe_ctx->clock_source, 726 &pipe_ctx->stream_res.pix_clk_params, 727 dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings), 728 &pipe_ctx->pll_settings)) { 729 BREAK_TO_DEBUGGER(); 730 return DC_ERROR_UNEXPECTED; 731 } 732 733 if (dc_is_hdmi_tmds_signal(stream->signal)) { 734 stream->link->phy_state.symclk_ref_cnts.otg = 1; 735 if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF) 736 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; 737 else 738 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 739 } 740 741 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal))) 742 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx); 743 744 pipe_ctx->stream_res.tg->funcs->program_timing( 745 pipe_ctx->stream_res.tg, 746 &stream->timing, 747 pipe_ctx->pipe_dlg_param.vready_offset, 748 pipe_ctx->pipe_dlg_param.vstartup_start, 749 pipe_ctx->pipe_dlg_param.vupdate_offset, 750 pipe_ctx->pipe_dlg_param.vupdate_width, 751 pipe_ctx->stream->signal, 752 true); 753 754 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 755 flow_control.flow_ctrl_mode = 0; 756 flow_control.flow_ctrl_cnt0 = 0x80; 757 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt); 758 if (mpc->funcs->set_out_rate_control) { 759 for (i = 0; i < opp_cnt; ++i) { 760 mpc->funcs->set_out_rate_control( 761 mpc, opp_inst[i], 762 true, 763 rate_control_2x_pclk, 764 &flow_control); 765 } 766 } 767 768 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 769 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 770 odm_pipe->stream_res.opp, 771 true); 772 773 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 774 pipe_ctx->stream_res.opp, 775 true); 776 777 hws->funcs.blank_pixel_data(dc, pipe_ctx, true); 778 779 /* VTG is within DCHUB command block. DCFCLK is always on */ 780 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { 781 BREAK_TO_DEBUGGER(); 782 return DC_ERROR_UNEXPECTED; 783 } 784 785 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp); 786 787 params.vertical_total_min = stream->adjust.v_total_min; 788 params.vertical_total_max = stream->adjust.v_total_max; 789 params.vertical_total_mid = stream->adjust.v_total_mid; 790 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num; 791 if (pipe_ctx->stream_res.tg->funcs->set_drr) 792 pipe_ctx->stream_res.tg->funcs->set_drr( 793 pipe_ctx->stream_res.tg, ¶ms); 794 795 // DRR should set trigger event to monitor surface update event 796 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 797 event_triggers = 0x80; 798 /* Event triggers and num frames initialized for DRR, but can be 799 * later updated for PSR use. Note DRR trigger events are generated 800 * regardless of whether num frames met. 801 */ 802 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 803 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 804 pipe_ctx->stream_res.tg, event_triggers, 2); 805 806 /* TODO program crtc source select for non-virtual signal*/ 807 /* TODO program FMT */ 808 /* TODO setup link_enc */ 809 /* TODO set stream attributes */ 810 /* TODO program audio */ 811 /* TODO enable stream if timing changed */ 812 /* TODO unblank stream if DP */ 813 814 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) { 815 if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable) 816 pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg); 817 } 818 return DC_OK; 819 } 820 821 void dcn20_program_output_csc(struct dc *dc, 822 struct pipe_ctx *pipe_ctx, 823 enum dc_color_space colorspace, 824 uint16_t *matrix, 825 int opp_id) 826 { 827 struct mpc *mpc = dc->res_pool->mpc; 828 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; 829 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 830 831 if (mpc->funcs->power_on_mpc_mem_pwr) 832 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 833 834 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 835 if (mpc->funcs->set_output_csc != NULL) 836 mpc->funcs->set_output_csc(mpc, 837 opp_id, 838 matrix, 839 ocsc_mode); 840 } else { 841 if (mpc->funcs->set_ocsc_default != NULL) 842 mpc->funcs->set_ocsc_default(mpc, 843 opp_id, 844 colorspace, 845 ocsc_mode); 846 } 847 } 848 849 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 850 const struct dc_stream_state *stream) 851 { 852 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 853 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 854 struct pwl_params *params = NULL; 855 /* 856 * program OGAM only for the top pipe 857 * if there is a pipe split then fix diagnostic is required: 858 * how to pass OGAM parameter for stream. 859 * if programming for all pipes is required then remove condition 860 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic. 861 */ 862 if (mpc->funcs->power_on_mpc_mem_pwr) 863 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 864 if (pipe_ctx->top_pipe == NULL 865 && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 866 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 867 params = &stream->out_transfer_func->pwl; 868 else if (pipe_ctx->stream->out_transfer_func->type == 869 TF_TYPE_DISTRIBUTED_POINTS && 870 cm_helper_translate_curve_to_hw_format( 871 stream->out_transfer_func, 872 &mpc->blender_params, false)) 873 params = &mpc->blender_params; 874 /* 875 * there is no ROM 876 */ 877 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 878 BREAK_TO_DEBUGGER(); 879 } 880 /* 881 * if above if is not executed then 'params' equal to 0 and set in bypass 882 */ 883 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 884 885 return true; 886 } 887 888 bool dcn20_set_blend_lut( 889 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 890 { 891 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 892 bool result = true; 893 struct pwl_params *blend_lut = NULL; 894 895 if (plane_state->blend_tf) { 896 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 897 blend_lut = &plane_state->blend_tf->pwl; 898 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 899 cm_helper_translate_curve_to_hw_format( 900 plane_state->blend_tf, 901 &dpp_base->regamma_params, false); 902 blend_lut = &dpp_base->regamma_params; 903 } 904 } 905 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); 906 907 return result; 908 } 909 910 bool dcn20_set_shaper_3dlut( 911 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 912 { 913 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 914 bool result = true; 915 struct pwl_params *shaper_lut = NULL; 916 917 if (plane_state->in_shaper_func) { 918 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 919 shaper_lut = &plane_state->in_shaper_func->pwl; 920 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 921 cm_helper_translate_curve_to_hw_format( 922 plane_state->in_shaper_func, 923 &dpp_base->shaper_params, true); 924 shaper_lut = &dpp_base->shaper_params; 925 } 926 } 927 928 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); 929 if (plane_state->lut3d_func && 930 plane_state->lut3d_func->state.bits.initialized == 1) 931 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, 932 &plane_state->lut3d_func->lut_3d); 933 else 934 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); 935 936 return result; 937 } 938 939 bool dcn20_set_input_transfer_func(struct dc *dc, 940 struct pipe_ctx *pipe_ctx, 941 const struct dc_plane_state *plane_state) 942 { 943 struct dce_hwseq *hws = dc->hwseq; 944 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 945 const struct dc_transfer_func *tf = NULL; 946 bool result = true; 947 bool use_degamma_ram = false; 948 949 if (dpp_base == NULL || plane_state == NULL) 950 return false; 951 952 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); 953 hws->funcs.set_blend_lut(pipe_ctx, plane_state); 954 955 if (plane_state->in_transfer_func) 956 tf = plane_state->in_transfer_func; 957 958 959 if (tf == NULL) { 960 dpp_base->funcs->dpp_set_degamma(dpp_base, 961 IPP_DEGAMMA_MODE_BYPASS); 962 return true; 963 } 964 965 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS) 966 use_degamma_ram = true; 967 968 if (use_degamma_ram == true) { 969 if (tf->type == TF_TYPE_HWPWL) 970 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 971 &tf->pwl); 972 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 973 cm_helper_translate_curve_to_degamma_hw_format(tf, 974 &dpp_base->degamma_params); 975 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 976 &dpp_base->degamma_params); 977 } 978 return true; 979 } 980 /* handle here the optimized cases when de-gamma ROM could be used. 981 * 982 */ 983 if (tf->type == TF_TYPE_PREDEFINED) { 984 switch (tf->tf) { 985 case TRANSFER_FUNCTION_SRGB: 986 dpp_base->funcs->dpp_set_degamma(dpp_base, 987 IPP_DEGAMMA_MODE_HW_sRGB); 988 break; 989 case TRANSFER_FUNCTION_BT709: 990 dpp_base->funcs->dpp_set_degamma(dpp_base, 991 IPP_DEGAMMA_MODE_HW_xvYCC); 992 break; 993 case TRANSFER_FUNCTION_LINEAR: 994 dpp_base->funcs->dpp_set_degamma(dpp_base, 995 IPP_DEGAMMA_MODE_BYPASS); 996 break; 997 case TRANSFER_FUNCTION_PQ: 998 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL); 999 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params); 1000 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params); 1001 result = true; 1002 break; 1003 default: 1004 result = false; 1005 break; 1006 } 1007 } else if (tf->type == TF_TYPE_BYPASS) 1008 dpp_base->funcs->dpp_set_degamma(dpp_base, 1009 IPP_DEGAMMA_MODE_BYPASS); 1010 else { 1011 /* 1012 * if we are here, we did not handle correctly. 1013 * fix is required for this use case 1014 */ 1015 BREAK_TO_DEBUGGER(); 1016 dpp_base->funcs->dpp_set_degamma(dpp_base, 1017 IPP_DEGAMMA_MODE_BYPASS); 1018 } 1019 1020 return result; 1021 } 1022 1023 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1024 { 1025 struct pipe_ctx *odm_pipe; 1026 int opp_cnt = 1; 1027 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 1028 1029 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1030 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 1031 opp_cnt++; 1032 } 1033 1034 if (opp_cnt > 1) 1035 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 1036 pipe_ctx->stream_res.tg, 1037 opp_inst, opp_cnt, 1038 &pipe_ctx->stream->timing); 1039 else 1040 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1041 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1042 } 1043 1044 void dcn20_blank_pixel_data( 1045 struct dc *dc, 1046 struct pipe_ctx *pipe_ctx, 1047 bool blank) 1048 { 1049 struct tg_color black_color = {0}; 1050 struct stream_resource *stream_res = &pipe_ctx->stream_res; 1051 struct dc_stream_state *stream = pipe_ctx->stream; 1052 enum dc_color_space color_space = stream->output_color_space; 1053 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; 1054 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; 1055 struct pipe_ctx *odm_pipe; 1056 int odm_cnt = 1; 1057 1058 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 1059 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; 1060 1061 if (stream->link->test_pattern_enabled) 1062 return; 1063 1064 /* get opp dpg blank color */ 1065 color_space_to_black_color(dc, color_space, &black_color); 1066 1067 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1068 odm_cnt++; 1069 1070 width = width / odm_cnt; 1071 1072 if (blank) { 1073 dc->hwss.set_abm_immediate_disable(pipe_ctx); 1074 1075 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { 1076 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; 1077 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; 1078 } 1079 } else { 1080 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; 1081 } 1082 1083 dc->hwss.set_disp_pattern_generator(dc, 1084 pipe_ctx, 1085 test_pattern, 1086 test_pattern_color_space, 1087 stream->timing.display_color_depth, 1088 &black_color, 1089 width, 1090 height, 1091 0); 1092 1093 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1094 dc->hwss.set_disp_pattern_generator(dc, 1095 odm_pipe, 1096 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ? 1097 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern, 1098 test_pattern_color_space, 1099 stream->timing.display_color_depth, 1100 &black_color, 1101 width, 1102 height, 1103 0); 1104 } 1105 1106 if (!blank && dc->debug.enable_single_display_2to1_odm_policy) { 1107 /* when exiting dynamic ODM need to reinit DPG state for unused pipes */ 1108 struct pipe_ctx *old_odm_pipe = dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx].next_odm_pipe; 1109 1110 odm_pipe = pipe_ctx->next_odm_pipe; 1111 1112 while (old_odm_pipe) { 1113 if (!odm_pipe || old_odm_pipe->pipe_idx != odm_pipe->pipe_idx) 1114 dc->hwss.set_disp_pattern_generator(dc, 1115 old_odm_pipe, 1116 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 1117 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 1118 COLOR_DEPTH_888, 1119 NULL, 1120 0, 1121 0, 1122 0); 1123 old_odm_pipe = old_odm_pipe->next_odm_pipe; 1124 if (odm_pipe) 1125 odm_pipe = odm_pipe->next_odm_pipe; 1126 } 1127 } 1128 1129 if (!blank) 1130 if (stream_res->abm) { 1131 dc->hwss.set_pipe(pipe_ctx); 1132 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level); 1133 } 1134 } 1135 1136 1137 static void dcn20_power_on_plane_resources( 1138 struct dce_hwseq *hws, 1139 struct pipe_ctx *pipe_ctx) 1140 { 1141 DC_LOGGER_INIT(hws->ctx->logger); 1142 1143 if (hws->funcs.dpp_root_clock_control) 1144 hws->funcs.dpp_root_clock_control(hws, pipe_ctx->plane_res.dpp->inst, true); 1145 1146 if (REG(DC_IP_REQUEST_CNTL)) { 1147 REG_SET(DC_IP_REQUEST_CNTL, 0, 1148 IP_REQUEST_EN, 1); 1149 1150 if (hws->funcs.dpp_pg_control) 1151 hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); 1152 1153 if (hws->funcs.hubp_pg_control) 1154 hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true); 1155 1156 REG_SET(DC_IP_REQUEST_CNTL, 0, 1157 IP_REQUEST_EN, 0); 1158 DC_LOG_DEBUG( 1159 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst); 1160 } 1161 } 1162 1163 static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx, 1164 struct dc_state *context) 1165 { 1166 //if (dc->debug.sanity_checks) { 1167 // dcn10_verify_allow_pstate_change_high(dc); 1168 //} 1169 dcn20_power_on_plane_resources(dc->hwseq, pipe_ctx); 1170 1171 /* enable DCFCLK current DCHUB */ 1172 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); 1173 1174 /* initialize HUBP on power up */ 1175 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); 1176 1177 /* make sure OPP_PIPE_CLOCK_EN = 1 */ 1178 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 1179 pipe_ctx->stream_res.opp, 1180 true); 1181 1182 /* TODO: enable/disable in dm as per update type. 1183 if (plane_state) { 1184 DC_LOG_DC(dc->ctx->logger, 1185 "Pipe:%d 0x%x: addr hi:0x%x, " 1186 "addr low:0x%x, " 1187 "src: %d, %d, %d," 1188 " %d; dst: %d, %d, %d, %d;\n", 1189 pipe_ctx->pipe_idx, 1190 plane_state, 1191 plane_state->address.grph.addr.high_part, 1192 plane_state->address.grph.addr.low_part, 1193 plane_state->src_rect.x, 1194 plane_state->src_rect.y, 1195 plane_state->src_rect.width, 1196 plane_state->src_rect.height, 1197 plane_state->dst_rect.x, 1198 plane_state->dst_rect.y, 1199 plane_state->dst_rect.width, 1200 plane_state->dst_rect.height); 1201 1202 DC_LOG_DC(dc->ctx->logger, 1203 "Pipe %d: width, height, x, y format:%d\n" 1204 "viewport:%d, %d, %d, %d\n" 1205 "recout: %d, %d, %d, %d\n", 1206 pipe_ctx->pipe_idx, 1207 plane_state->format, 1208 pipe_ctx->plane_res.scl_data.viewport.width, 1209 pipe_ctx->plane_res.scl_data.viewport.height, 1210 pipe_ctx->plane_res.scl_data.viewport.x, 1211 pipe_ctx->plane_res.scl_data.viewport.y, 1212 pipe_ctx->plane_res.scl_data.recout.width, 1213 pipe_ctx->plane_res.scl_data.recout.height, 1214 pipe_ctx->plane_res.scl_data.recout.x, 1215 pipe_ctx->plane_res.scl_data.recout.y); 1216 print_rq_dlg_ttu(dc, pipe_ctx); 1217 } 1218 */ 1219 if (dc->vm_pa_config.valid) { 1220 struct vm_system_aperture_param apt; 1221 1222 apt.sys_default.quad_part = 0; 1223 1224 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr; 1225 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr; 1226 1227 // Program system aperture settings 1228 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); 1229 } 1230 1231 if (!pipe_ctx->top_pipe 1232 && pipe_ctx->plane_state 1233 && pipe_ctx->plane_state->flip_int_enabled 1234 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) 1235 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); 1236 1237 // if (dc->debug.sanity_checks) { 1238 // dcn10_verify_allow_pstate_change_high(dc); 1239 // } 1240 } 1241 1242 void dcn20_pipe_control_lock( 1243 struct dc *dc, 1244 struct pipe_ctx *pipe, 1245 bool lock) 1246 { 1247 struct pipe_ctx *temp_pipe; 1248 bool flip_immediate = false; 1249 1250 /* use TG master update lock to lock everything on the TG 1251 * therefore only top pipe need to lock 1252 */ 1253 if (!pipe || pipe->top_pipe) 1254 return; 1255 1256 if (pipe->plane_state != NULL) 1257 flip_immediate = pipe->plane_state->flip_immediate; 1258 1259 if (pipe->stream_res.gsl_group > 0) { 1260 temp_pipe = pipe->bottom_pipe; 1261 while (!flip_immediate && temp_pipe) { 1262 if (temp_pipe->plane_state != NULL) 1263 flip_immediate = temp_pipe->plane_state->flip_immediate; 1264 temp_pipe = temp_pipe->bottom_pipe; 1265 } 1266 } 1267 1268 if (flip_immediate && lock) { 1269 const int TIMEOUT_FOR_FLIP_PENDING = 100000; 1270 int i; 1271 1272 temp_pipe = pipe; 1273 while (temp_pipe) { 1274 if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) { 1275 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) { 1276 if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp)) 1277 break; 1278 udelay(1); 1279 } 1280 1281 /* no reason it should take this long for immediate flips */ 1282 ASSERT(i != TIMEOUT_FOR_FLIP_PENDING); 1283 } 1284 temp_pipe = temp_pipe->bottom_pipe; 1285 } 1286 } 1287 1288 /* In flip immediate and pipe splitting case, we need to use GSL 1289 * for synchronization. Only do setup on locking and on flip type change. 1290 */ 1291 if (lock && (pipe->bottom_pipe != NULL || !flip_immediate)) 1292 if ((flip_immediate && pipe->stream_res.gsl_group == 0) || 1293 (!flip_immediate && pipe->stream_res.gsl_group > 0)) 1294 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate); 1295 1296 if (pipe->plane_state != NULL) 1297 flip_immediate = pipe->plane_state->flip_immediate; 1298 1299 temp_pipe = pipe->bottom_pipe; 1300 while (flip_immediate && temp_pipe) { 1301 if (temp_pipe->plane_state != NULL) 1302 flip_immediate = temp_pipe->plane_state->flip_immediate; 1303 temp_pipe = temp_pipe->bottom_pipe; 1304 } 1305 1306 if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state && 1307 !flip_immediate) 1308 dcn20_setup_gsl_group_as_lock(dc, pipe, false); 1309 1310 if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) { 1311 union dmub_hw_lock_flags hw_locks = { 0 }; 1312 struct dmub_hw_lock_inst_flags inst_flags = { 0 }; 1313 1314 hw_locks.bits.lock_pipe = 1; 1315 inst_flags.otg_inst = pipe->stream_res.tg->inst; 1316 1317 if (pipe->plane_state != NULL) 1318 hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips; 1319 1320 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, 1321 lock, 1322 &hw_locks, 1323 &inst_flags); 1324 } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) { 1325 if (lock) 1326 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); 1327 else 1328 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); 1329 } else { 1330 if (lock) 1331 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1332 else 1333 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1334 } 1335 } 1336 1337 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe) 1338 { 1339 new_pipe->update_flags.raw = 0; 1340 1341 /* If non-phantom pipe is being transitioned to a phantom pipe, 1342 * set disable and return immediately. This is because the pipe 1343 * that was previously in use must be fully disabled before we 1344 * can "enable" it as a phantom pipe (since the OTG will certainly 1345 * be different). The post_unlock sequence will set the correct 1346 * update flags to enable the phantom pipe. 1347 */ 1348 if (old_pipe->plane_state && !old_pipe->plane_state->is_phantom && 1349 new_pipe->plane_state && new_pipe->plane_state->is_phantom) { 1350 new_pipe->update_flags.bits.disable = 1; 1351 return; 1352 } 1353 1354 /* Exit on unchanged, unused pipe */ 1355 if (!old_pipe->plane_state && !new_pipe->plane_state) 1356 return; 1357 /* Detect pipe enable/disable */ 1358 if (!old_pipe->plane_state && new_pipe->plane_state) { 1359 new_pipe->update_flags.bits.enable = 1; 1360 new_pipe->update_flags.bits.mpcc = 1; 1361 new_pipe->update_flags.bits.dppclk = 1; 1362 new_pipe->update_flags.bits.hubp_interdependent = 1; 1363 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1364 new_pipe->update_flags.bits.unbounded_req = 1; 1365 new_pipe->update_flags.bits.gamut_remap = 1; 1366 new_pipe->update_flags.bits.scaler = 1; 1367 new_pipe->update_flags.bits.viewport = 1; 1368 new_pipe->update_flags.bits.det_size = 1; 1369 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1370 new_pipe->update_flags.bits.odm = 1; 1371 new_pipe->update_flags.bits.global_sync = 1; 1372 } 1373 return; 1374 } 1375 1376 /* For SubVP we need to unconditionally enable because any phantom pipes are 1377 * always removed then newly added for every full updates whenever SubVP is in use. 1378 * The remove-add sequence of the phantom pipe always results in the pipe 1379 * being blanked in enable_stream_timing (DPG). 1380 */ 1381 if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) 1382 new_pipe->update_flags.bits.enable = 1; 1383 1384 /* Phantom pipes are effectively disabled, if the pipe was previously phantom 1385 * we have to enable 1386 */ 1387 if (old_pipe->plane_state && old_pipe->plane_state->is_phantom && 1388 new_pipe->plane_state && !new_pipe->plane_state->is_phantom) 1389 new_pipe->update_flags.bits.enable = 1; 1390 1391 if (old_pipe->plane_state && !new_pipe->plane_state) { 1392 new_pipe->update_flags.bits.disable = 1; 1393 return; 1394 } 1395 1396 /* Detect plane change */ 1397 if (old_pipe->plane_state != new_pipe->plane_state) { 1398 new_pipe->update_flags.bits.plane_changed = true; 1399 } 1400 1401 /* Detect top pipe only changes */ 1402 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1403 /* Detect odm changes */ 1404 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe 1405 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx) 1406 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe) 1407 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe) 1408 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1409 new_pipe->update_flags.bits.odm = 1; 1410 1411 /* Detect global sync changes */ 1412 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset 1413 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start 1414 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset 1415 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) 1416 new_pipe->update_flags.bits.global_sync = 1; 1417 } 1418 1419 if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb) 1420 new_pipe->update_flags.bits.det_size = 1; 1421 1422 /* 1423 * Detect opp / tg change, only set on change, not on enable 1424 * Assume mpcc inst = pipe index, if not this code needs to be updated 1425 * since mpcc is what is affected by these. In fact all of our sequence 1426 * makes this assumption at the moment with how hubp reset is matched to 1427 * same index mpcc reset. 1428 */ 1429 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1430 new_pipe->update_flags.bits.opp_changed = 1; 1431 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg) 1432 new_pipe->update_flags.bits.tg_changed = 1; 1433 1434 /* 1435 * Detect mpcc blending changes, only dpp inst and opp matter here, 1436 * mpccs getting removed/inserted update connected ones during their own 1437 * programming 1438 */ 1439 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp 1440 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1441 new_pipe->update_flags.bits.mpcc = 1; 1442 1443 /* Detect dppclk change */ 1444 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) 1445 new_pipe->update_flags.bits.dppclk = 1; 1446 1447 /* Check for scl update */ 1448 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data))) 1449 new_pipe->update_flags.bits.scaler = 1; 1450 /* Check for vp update */ 1451 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect)) 1452 || memcmp(&old_pipe->plane_res.scl_data.viewport_c, 1453 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect))) 1454 new_pipe->update_flags.bits.viewport = 1; 1455 1456 /* Detect dlg/ttu/rq updates */ 1457 { 1458 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs; 1459 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs; 1460 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs; 1461 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs; 1462 1463 /* Detect pipe interdependent updates */ 1464 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch || 1465 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch || 1466 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c || 1467 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank || 1468 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank || 1469 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip || 1470 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip || 1471 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l || 1472 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c || 1473 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l || 1474 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l || 1475 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c || 1476 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l || 1477 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c || 1478 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 || 1479 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 || 1480 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank || 1481 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) { 1482 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch; 1483 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch; 1484 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c; 1485 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank; 1486 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank; 1487 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip; 1488 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip; 1489 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l; 1490 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c; 1491 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l; 1492 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l; 1493 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c; 1494 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l; 1495 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c; 1496 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0; 1497 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1; 1498 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank; 1499 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip; 1500 new_pipe->update_flags.bits.hubp_interdependent = 1; 1501 } 1502 /* Detect any other updates to ttu/rq/dlg */ 1503 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) || 1504 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) || 1505 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs))) 1506 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1507 } 1508 1509 if (old_pipe->unbounded_req != new_pipe->unbounded_req) 1510 new_pipe->update_flags.bits.unbounded_req = 1; 1511 } 1512 1513 static void dcn20_update_dchubp_dpp( 1514 struct dc *dc, 1515 struct pipe_ctx *pipe_ctx, 1516 struct dc_state *context) 1517 { 1518 struct dce_hwseq *hws = dc->hwseq; 1519 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1520 struct dpp *dpp = pipe_ctx->plane_res.dpp; 1521 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1522 struct dccg *dccg = dc->res_pool->dccg; 1523 bool viewport_changed = false; 1524 1525 if (pipe_ctx->update_flags.bits.dppclk) 1526 dpp->funcs->dpp_dppclk_control(dpp, false, true); 1527 1528 if (pipe_ctx->update_flags.bits.enable) 1529 dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz); 1530 1531 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG 1532 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. 1533 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG 1534 */ 1535 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) { 1536 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst); 1537 1538 hubp->funcs->hubp_setup( 1539 hubp, 1540 &pipe_ctx->dlg_regs, 1541 &pipe_ctx->ttu_regs, 1542 &pipe_ctx->rq_regs, 1543 &pipe_ctx->pipe_dlg_param); 1544 } 1545 1546 if (pipe_ctx->update_flags.bits.unbounded_req && hubp->funcs->set_unbounded_requesting) 1547 hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req); 1548 1549 if (pipe_ctx->update_flags.bits.hubp_interdependent) 1550 hubp->funcs->hubp_setup_interdependent( 1551 hubp, 1552 &pipe_ctx->dlg_regs, 1553 &pipe_ctx->ttu_regs); 1554 1555 if (pipe_ctx->update_flags.bits.enable || 1556 pipe_ctx->update_flags.bits.plane_changed || 1557 plane_state->update_flags.bits.bpp_change || 1558 plane_state->update_flags.bits.input_csc_change || 1559 plane_state->update_flags.bits.color_space_change || 1560 plane_state->update_flags.bits.coeff_reduction_change) { 1561 struct dc_bias_and_scale bns_params = {0}; 1562 1563 // program the input csc 1564 dpp->funcs->dpp_setup(dpp, 1565 plane_state->format, 1566 EXPANSION_MODE_ZERO, 1567 plane_state->input_csc_color_matrix, 1568 plane_state->color_space, 1569 NULL); 1570 1571 if (dpp->funcs->dpp_program_bias_and_scale) { 1572 //TODO :for CNVC set scale and bias registers if necessary 1573 build_prescale_params(&bns_params, plane_state); 1574 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); 1575 } 1576 } 1577 1578 if (pipe_ctx->update_flags.bits.mpcc 1579 || pipe_ctx->update_flags.bits.plane_changed 1580 || plane_state->update_flags.bits.global_alpha_change 1581 || plane_state->update_flags.bits.per_pixel_alpha_change) { 1582 // MPCC inst is equal to pipe index in practice 1583 int mpcc_inst = hubp->inst; 1584 int opp_inst; 1585 int opp_count = dc->res_pool->pipe_count; 1586 1587 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) { 1588 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) { 1589 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); 1590 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; 1591 break; 1592 } 1593 } 1594 hws->funcs.update_mpcc(dc, pipe_ctx); 1595 } 1596 1597 if (pipe_ctx->update_flags.bits.scaler || 1598 plane_state->update_flags.bits.scaling_change || 1599 plane_state->update_flags.bits.position_change || 1600 plane_state->update_flags.bits.per_pixel_alpha_change || 1601 pipe_ctx->stream->update_flags.bits.scaling) { 1602 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; 1603 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP); 1604 /* scaler configuration */ 1605 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( 1606 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); 1607 } 1608 1609 if (pipe_ctx->update_flags.bits.viewport || 1610 (context == dc->current_state && plane_state->update_flags.bits.position_change) || 1611 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) || 1612 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) { 1613 1614 hubp->funcs->mem_program_viewport( 1615 hubp, 1616 &pipe_ctx->plane_res.scl_data.viewport, 1617 &pipe_ctx->plane_res.scl_data.viewport_c); 1618 viewport_changed = true; 1619 } 1620 1621 /* Any updates are handled in dc interface, just need to apply existing for plane enable */ 1622 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || 1623 pipe_ctx->update_flags.bits.scaler || viewport_changed == true) && 1624 pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { 1625 dc->hwss.set_cursor_position(pipe_ctx); 1626 dc->hwss.set_cursor_attribute(pipe_ctx); 1627 1628 if (dc->hwss.set_cursor_sdr_white_level) 1629 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 1630 } 1631 1632 /* Any updates are handled in dc interface, just need 1633 * to apply existing for plane enable / opp change */ 1634 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed 1635 || pipe_ctx->update_flags.bits.plane_changed 1636 || pipe_ctx->stream->update_flags.bits.gamut_remap 1637 || pipe_ctx->stream->update_flags.bits.out_csc) { 1638 /* dpp/cm gamut remap*/ 1639 dc->hwss.program_gamut_remap(pipe_ctx); 1640 1641 /*call the dcn2 method which uses mpc csc*/ 1642 dc->hwss.program_output_csc(dc, 1643 pipe_ctx, 1644 pipe_ctx->stream->output_color_space, 1645 pipe_ctx->stream->csc_color_matrix.matrix, 1646 hubp->opp_id); 1647 } 1648 1649 if (pipe_ctx->update_flags.bits.enable || 1650 pipe_ctx->update_flags.bits.plane_changed || 1651 pipe_ctx->update_flags.bits.opp_changed || 1652 plane_state->update_flags.bits.pixel_format_change || 1653 plane_state->update_flags.bits.horizontal_mirror_change || 1654 plane_state->update_flags.bits.rotation_change || 1655 plane_state->update_flags.bits.swizzle_change || 1656 plane_state->update_flags.bits.dcc_change || 1657 plane_state->update_flags.bits.bpp_change || 1658 plane_state->update_flags.bits.scaling_change || 1659 plane_state->update_flags.bits.plane_size_change) { 1660 struct plane_size size = plane_state->plane_size; 1661 1662 size.surface_size = pipe_ctx->plane_res.scl_data.viewport; 1663 hubp->funcs->hubp_program_surface_config( 1664 hubp, 1665 plane_state->format, 1666 &plane_state->tiling_info, 1667 &size, 1668 plane_state->rotation, 1669 &plane_state->dcc, 1670 plane_state->horizontal_mirror, 1671 0); 1672 hubp->power_gated = false; 1673 } 1674 1675 if (pipe_ctx->update_flags.bits.enable || 1676 pipe_ctx->update_flags.bits.plane_changed || 1677 plane_state->update_flags.bits.addr_update) 1678 hws->funcs.update_plane_addr(dc, pipe_ctx); 1679 1680 if (pipe_ctx->update_flags.bits.enable) 1681 hubp->funcs->set_blank(hubp, false); 1682 /* If the stream paired with this plane is phantom, the plane is also phantom */ 1683 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM 1684 && hubp->funcs->phantom_hubp_post_enable) 1685 hubp->funcs->phantom_hubp_post_enable(hubp); 1686 } 1687 1688 static int calculate_vready_offset_for_group(struct pipe_ctx *pipe) 1689 { 1690 struct pipe_ctx *other_pipe; 1691 int vready_offset = pipe->pipe_dlg_param.vready_offset; 1692 1693 /* Always use the largest vready_offset of all connected pipes */ 1694 for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) { 1695 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1696 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1697 } 1698 for (other_pipe = pipe->top_pipe; other_pipe != NULL; other_pipe = other_pipe->top_pipe) { 1699 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1700 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1701 } 1702 for (other_pipe = pipe->next_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->next_odm_pipe) { 1703 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1704 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1705 } 1706 for (other_pipe = pipe->prev_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->prev_odm_pipe) { 1707 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1708 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1709 } 1710 1711 return vready_offset; 1712 } 1713 1714 static void dcn20_program_pipe( 1715 struct dc *dc, 1716 struct pipe_ctx *pipe_ctx, 1717 struct dc_state *context) 1718 { 1719 struct dce_hwseq *hws = dc->hwseq; 1720 /* Only need to unblank on top pipe */ 1721 1722 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level) 1723 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) 1724 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible); 1725 1726 /* Only update TG on top pipe */ 1727 if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe 1728 && !pipe_ctx->prev_odm_pipe) { 1729 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1730 pipe_ctx->stream_res.tg, 1731 calculate_vready_offset_for_group(pipe_ctx), 1732 pipe_ctx->pipe_dlg_param.vstartup_start, 1733 pipe_ctx->pipe_dlg_param.vupdate_offset, 1734 pipe_ctx->pipe_dlg_param.vupdate_width); 1735 1736 if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) 1737 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); 1738 1739 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1740 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true); 1741 1742 if (hws->funcs.setup_vupdate_interrupt) 1743 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1744 1745 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { 1746 unsigned int k1_div, k2_div; 1747 1748 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); 1749 1750 dc->res_pool->dccg->funcs->set_pixel_rate_div( 1751 dc->res_pool->dccg, 1752 pipe_ctx->stream_res.tg->inst, 1753 k1_div, k2_div); 1754 } 1755 } 1756 1757 if (pipe_ctx->update_flags.bits.odm) 1758 hws->funcs.update_odm(dc, context, pipe_ctx); 1759 1760 if (pipe_ctx->update_flags.bits.enable) { 1761 dcn20_enable_plane(dc, pipe_ctx, context); 1762 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes) 1763 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub); 1764 } 1765 1766 if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size) 1767 dc->res_pool->hubbub->funcs->program_det_size( 1768 dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb); 1769 1770 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) 1771 dcn20_update_dchubp_dpp(dc, pipe_ctx, context); 1772 1773 if (pipe_ctx->update_flags.bits.enable 1774 || pipe_ctx->plane_state->update_flags.bits.hdr_mult) 1775 hws->funcs.set_hdr_multiplier(pipe_ctx); 1776 1777 if (pipe_ctx->update_flags.bits.enable || 1778 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 1779 pipe_ctx->plane_state->update_flags.bits.gamma_change) 1780 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 1781 1782 /* dcn10_translate_regamma_to_hw_format takes 750us to finish 1783 * only do gamma programming for powering on, internal memcmp to avoid 1784 * updating on slave planes 1785 */ 1786 if (pipe_ctx->update_flags.bits.enable || 1787 pipe_ctx->update_flags.bits.plane_changed || 1788 pipe_ctx->stream->update_flags.bits.out_tf || 1789 pipe_ctx->plane_state->update_flags.bits.output_tf_change) 1790 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 1791 1792 /* If the pipe has been enabled or has a different opp, we 1793 * should reprogram the fmt. This deals with cases where 1794 * interation between mpc and odm combine on different streams 1795 * causes a different pipe to be chosen to odm combine with. 1796 */ 1797 if (pipe_ctx->update_flags.bits.enable 1798 || pipe_ctx->update_flags.bits.opp_changed) { 1799 1800 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1801 pipe_ctx->stream_res.opp, 1802 COLOR_SPACE_YCBCR601, 1803 pipe_ctx->stream->timing.display_color_depth, 1804 pipe_ctx->stream->signal); 1805 1806 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1807 pipe_ctx->stream_res.opp, 1808 &pipe_ctx->stream->bit_depth_params, 1809 &pipe_ctx->stream->clamping); 1810 } 1811 1812 /* Set ABM pipe after other pipe configurations done */ 1813 if (pipe_ctx->plane_state->visible) { 1814 if (pipe_ctx->stream_res.abm) { 1815 dc->hwss.set_pipe(pipe_ctx); 1816 pipe_ctx->stream_res.abm->funcs->set_abm_level(pipe_ctx->stream_res.abm, 1817 pipe_ctx->stream->abm_level); 1818 } 1819 } 1820 } 1821 1822 void dcn20_program_front_end_for_ctx( 1823 struct dc *dc, 1824 struct dc_state *context) 1825 { 1826 int i; 1827 struct dce_hwseq *hws = dc->hwseq; 1828 DC_LOGGER_INIT(dc->ctx->logger); 1829 1830 /* Carry over GSL groups in case the context is changing. */ 1831 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1832 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1833 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 1834 1835 if (pipe_ctx->stream == old_pipe_ctx->stream) 1836 pipe_ctx->stream_res.gsl_group = old_pipe_ctx->stream_res.gsl_group; 1837 } 1838 1839 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) { 1840 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1841 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1842 1843 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) { 1844 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips); 1845 /*turn off triple buffer for full update*/ 1846 dc->hwss.program_triplebuffer( 1847 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); 1848 } 1849 } 1850 } 1851 1852 /* Set pipe update flags and lock pipes */ 1853 for (i = 0; i < dc->res_pool->pipe_count; i++) 1854 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i], 1855 &context->res_ctx.pipe_ctx[i]); 1856 1857 /* When disabling phantom pipes, turn on phantom OTG first (so we can get double 1858 * buffer updates properly) 1859 */ 1860 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1861 struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream; 1862 1863 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream && 1864 dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { 1865 struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg; 1866 1867 if (tg->funcs->enable_crtc) 1868 tg->funcs->enable_crtc(tg); 1869 } 1870 } 1871 /* OTG blank before disabling all front ends */ 1872 for (i = 0; i < dc->res_pool->pipe_count; i++) 1873 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1874 && !context->res_ctx.pipe_ctx[i].top_pipe 1875 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe 1876 && context->res_ctx.pipe_ctx[i].stream) 1877 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); 1878 1879 1880 /* Disconnect mpcc */ 1881 for (i = 0; i < dc->res_pool->pipe_count; i++) 1882 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1883 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) { 1884 struct hubbub *hubbub = dc->res_pool->hubbub; 1885 1886 /* Phantom pipe DET should be 0, but if a pipe in use is being transitioned to phantom 1887 * then we want to do the programming here (effectively it's being disabled). If we do 1888 * the programming later the DET won't be updated until the OTG for the phantom pipe is 1889 * turned on (i.e. in an MCLK switch) which can come in too late and cause issues with 1890 * DET allocation. 1891 */ 1892 if (hubbub->funcs->program_det_size && (context->res_ctx.pipe_ctx[i].update_flags.bits.disable || 1893 (context->res_ctx.pipe_ctx[i].plane_state && context->res_ctx.pipe_ctx[i].plane_state->is_phantom))) 1894 hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0); 1895 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1896 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); 1897 } 1898 1899 /* 1900 * Program all updated pipes, order matters for mpcc setup. Start with 1901 * top pipe and program all pipes that follow in order 1902 */ 1903 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1904 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1905 1906 if (pipe->plane_state && !pipe->top_pipe) { 1907 while (pipe) { 1908 if (hws->funcs.program_pipe) 1909 hws->funcs.program_pipe(dc, pipe, context); 1910 else { 1911 /* Don't program phantom pipes in the regular front end programming sequence. 1912 * There is an MPO transition case where a pipe being used by a video plane is 1913 * transitioned directly to be a phantom pipe when closing the MPO video. However 1914 * the phantom pipe will program a new HUBP_VTG_SEL (update takes place right away), 1915 * but the MPO still exists until the double buffered update of the main pipe so we 1916 * will get a frame of underflow if the phantom pipe is programmed here. 1917 */ 1918 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) 1919 dcn20_program_pipe(dc, pipe, context); 1920 } 1921 1922 pipe = pipe->bottom_pipe; 1923 } 1924 } 1925 /* Program secondary blending tree and writeback pipes */ 1926 pipe = &context->res_ctx.pipe_ctx[i]; 1927 if (!pipe->top_pipe && !pipe->prev_odm_pipe 1928 && pipe->stream && pipe->stream->num_wb_info > 0 1929 && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw) 1930 || pipe->stream->update_flags.raw) 1931 && hws->funcs.program_all_writeback_pipes_in_tree) 1932 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context); 1933 1934 /* Avoid underflow by check of pipe line read when adding 2nd plane. */ 1935 if (hws->wa.wait_hubpret_read_start_during_mpo_transition && 1936 !pipe->top_pipe && 1937 pipe->stream && 1938 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start && 1939 dc->current_state->stream_status[0].plane_count == 1 && 1940 context->stream_status[0].plane_count > 1) { 1941 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp); 1942 } 1943 1944 /* when dynamic ODM is active, pipes must be reconfigured when all planes are 1945 * disabled, as some transitions will leave software and hardware state 1946 * mismatched. 1947 */ 1948 if (dc->debug.enable_single_display_2to1_odm_policy && 1949 pipe->stream && 1950 pipe->update_flags.bits.disable && 1951 !pipe->prev_odm_pipe && 1952 hws->funcs.update_odm) 1953 hws->funcs.update_odm(dc, context, pipe); 1954 } 1955 } 1956 1957 void dcn20_post_unlock_program_front_end( 1958 struct dc *dc, 1959 struct dc_state *context) 1960 { 1961 int i; 1962 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100; 1963 struct dce_hwseq *hwseq = dc->hwseq; 1964 1965 DC_LOGGER_INIT(dc->ctx->logger); 1966 1967 for (i = 0; i < dc->res_pool->pipe_count; i++) 1968 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1969 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1970 1971 /* 1972 * If we are enabling a pipe, we need to wait for pending clear as this is a critical 1973 * part of the enable operation otherwise, DM may request an immediate flip which 1974 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which 1975 * is unsupported on DCN. 1976 */ 1977 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1978 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1979 // Don't check flip pending on phantom pipes 1980 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable && 1981 pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1982 struct hubp *hubp = pipe->plane_res.hubp; 1983 int j = 0; 1984 1985 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000 1986 && hubp->funcs->hubp_is_flip_pending(hubp); j++) 1987 udelay(1); 1988 } 1989 } 1990 1991 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1992 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1993 1994 if (pipe->plane_state && !pipe->top_pipe) { 1995 /* Program phantom pipe here to prevent a frame of underflow in the MPO transition 1996 * case (if a pipe being used for a video plane transitions to a phantom pipe, it 1997 * can underflow due to HUBP_VTG_SEL programming if done in the regular front end 1998 * programming sequence). 1999 */ 2000 while (pipe) { 2001 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 2002 /* When turning on the phantom pipe we want to run through the 2003 * entire enable sequence, so apply all the "enable" flags. 2004 */ 2005 if (dc->hwss.apply_update_flags_for_phantom) 2006 dc->hwss.apply_update_flags_for_phantom(pipe); 2007 if (dc->hwss.update_phantom_vp_position) 2008 dc->hwss.update_phantom_vp_position(dc, context, pipe); 2009 dcn20_program_pipe(dc, pipe, context); 2010 } 2011 pipe = pipe->bottom_pipe; 2012 } 2013 } 2014 } 2015 2016 /* P-State support transitions: 2017 * Natural -> FPO: P-State disabled in prepare, force disallow anytime is safe 2018 * FPO -> Natural: Unforce anytime after FW disable is safe (P-State will assert naturally) 2019 * Unsupported -> FPO: P-State enabled in optimize, force disallow anytime is safe 2020 * FPO -> Unsupported: P-State disabled in prepare, unforce disallow anytime is safe 2021 * FPO <-> SubVP: Force disallow is maintained on the FPO / SubVP pipes 2022 */ 2023 if (hwseq && hwseq->funcs.update_force_pstate) 2024 dc->hwseq->funcs.update_force_pstate(dc, context); 2025 2026 /* Only program the MALL registers after all the main and phantom pipes 2027 * are done programming. 2028 */ 2029 if (hwseq->funcs.program_mall_pipe_config) 2030 hwseq->funcs.program_mall_pipe_config(dc, context); 2031 2032 /* WA to apply WM setting*/ 2033 if (hwseq->wa.DEGVIDCN21) 2034 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub); 2035 2036 2037 /* WA for stutter underflow during MPO transitions when adding 2nd plane */ 2038 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) { 2039 2040 if (dc->current_state->stream_status[0].plane_count == 1 && 2041 context->stream_status[0].plane_count > 1) { 2042 2043 struct timing_generator *tg = dc->res_pool->timing_generators[0]; 2044 2045 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false); 2046 2047 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true; 2048 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg); 2049 } 2050 } 2051 } 2052 2053 void dcn20_prepare_bandwidth( 2054 struct dc *dc, 2055 struct dc_state *context) 2056 { 2057 struct hubbub *hubbub = dc->res_pool->hubbub; 2058 unsigned int compbuf_size_kb = 0; 2059 unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns; 2060 unsigned int i; 2061 2062 dc->clk_mgr->funcs->update_clocks( 2063 dc->clk_mgr, 2064 context, 2065 false); 2066 2067 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2068 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2069 2070 // At optimize don't restore the original watermark value 2071 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) { 2072 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; 2073 break; 2074 } 2075 } 2076 2077 /* program dchubbub watermarks: 2078 * For assigning wm_optimized_required, use |= operator since we don't want 2079 * to clear the value if the optimize has not happened yet 2080 */ 2081 dc->wm_optimized_required |= hubbub->funcs->program_watermarks(hubbub, 2082 &context->bw_ctx.bw.dcn.watermarks, 2083 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 2084 false); 2085 2086 // Restore the real watermark so we can commit the value to DMCUB 2087 // DMCUB uses the "original" watermark value in SubVP MCLK switch 2088 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a; 2089 2090 /* decrease compbuf size */ 2091 if (hubbub->funcs->program_compbuf_size) { 2092 if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes) { 2093 compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes; 2094 dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.dml.ip.min_comp_buffer_size_kbytes); 2095 } else { 2096 compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb; 2097 dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.bw.dcn.compbuf_size_kb); 2098 } 2099 2100 hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false); 2101 } 2102 } 2103 2104 void dcn20_optimize_bandwidth( 2105 struct dc *dc, 2106 struct dc_state *context) 2107 { 2108 struct hubbub *hubbub = dc->res_pool->hubbub; 2109 int i; 2110 2111 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2112 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2113 2114 // At optimize don't need to restore the original watermark value 2115 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) { 2116 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; 2117 break; 2118 } 2119 } 2120 2121 /* program dchubbub watermarks */ 2122 hubbub->funcs->program_watermarks(hubbub, 2123 &context->bw_ctx.bw.dcn.watermarks, 2124 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 2125 true); 2126 2127 if (dc->clk_mgr->dc_mode_softmax_enabled) 2128 if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && 2129 context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) 2130 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk); 2131 2132 /* increase compbuf size */ 2133 if (hubbub->funcs->program_compbuf_size) 2134 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true); 2135 2136 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { 2137 dc_dmub_srv_p_state_delegate(dc, 2138 true, context); 2139 context->bw_ctx.bw.dcn.clk.p_state_change_support = true; 2140 dc->clk_mgr->clks.fw_based_mclk_switching = true; 2141 } else { 2142 dc->clk_mgr->clks.fw_based_mclk_switching = false; 2143 } 2144 2145 dc->clk_mgr->funcs->update_clocks( 2146 dc->clk_mgr, 2147 context, 2148 true); 2149 if (context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) { 2150 for (i = 0; i < dc->res_pool->pipe_count; ++i) { 2151 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2152 2153 if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank 2154 && pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max 2155 && pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total) 2156 pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp, 2157 pipe_ctx->dlg_regs.min_dst_y_next_start); 2158 } 2159 } 2160 } 2161 2162 bool dcn20_update_bandwidth( 2163 struct dc *dc, 2164 struct dc_state *context) 2165 { 2166 int i; 2167 struct dce_hwseq *hws = dc->hwseq; 2168 2169 /* recalculate DML parameters */ 2170 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) 2171 return false; 2172 2173 /* apply updated bandwidth parameters */ 2174 dc->hwss.prepare_bandwidth(dc, context); 2175 2176 /* update hubp configs for all pipes */ 2177 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2178 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2179 2180 if (pipe_ctx->plane_state == NULL) 2181 continue; 2182 2183 if (pipe_ctx->top_pipe == NULL) { 2184 bool blank = !is_pipe_tree_visible(pipe_ctx); 2185 2186 pipe_ctx->stream_res.tg->funcs->program_global_sync( 2187 pipe_ctx->stream_res.tg, 2188 calculate_vready_offset_for_group(pipe_ctx), 2189 pipe_ctx->pipe_dlg_param.vstartup_start, 2190 pipe_ctx->pipe_dlg_param.vupdate_offset, 2191 pipe_ctx->pipe_dlg_param.vupdate_width); 2192 2193 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 2194 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false); 2195 2196 if (pipe_ctx->prev_odm_pipe == NULL) 2197 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank); 2198 2199 if (hws->funcs.setup_vupdate_interrupt) 2200 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 2201 } 2202 2203 pipe_ctx->plane_res.hubp->funcs->hubp_setup( 2204 pipe_ctx->plane_res.hubp, 2205 &pipe_ctx->dlg_regs, 2206 &pipe_ctx->ttu_regs, 2207 &pipe_ctx->rq_regs, 2208 &pipe_ctx->pipe_dlg_param); 2209 } 2210 2211 return true; 2212 } 2213 2214 void dcn20_enable_writeback( 2215 struct dc *dc, 2216 struct dc_writeback_info *wb_info, 2217 struct dc_state *context) 2218 { 2219 struct dwbc *dwb; 2220 struct mcif_wb *mcif_wb; 2221 struct timing_generator *optc; 2222 2223 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 2224 ASSERT(wb_info->wb_enabled); 2225 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 2226 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 2227 2228 /* set the OPTC source mux */ 2229 optc = dc->res_pool->timing_generators[dwb->otg_inst]; 2230 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); 2231 /* set MCIF_WB buffer and arbitration configuration */ 2232 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 2233 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 2234 /* Enable MCIF_WB */ 2235 mcif_wb->funcs->enable_mcif(mcif_wb); 2236 /* Enable DWB */ 2237 dwb->funcs->enable(dwb, &wb_info->dwb_params); 2238 /* TODO: add sequence to enable/disable warmup */ 2239 } 2240 2241 void dcn20_disable_writeback( 2242 struct dc *dc, 2243 unsigned int dwb_pipe_inst) 2244 { 2245 struct dwbc *dwb; 2246 struct mcif_wb *mcif_wb; 2247 2248 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); 2249 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; 2250 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; 2251 2252 dwb->funcs->disable(dwb); 2253 mcif_wb->funcs->disable_mcif(mcif_wb); 2254 } 2255 2256 bool dcn20_wait_for_blank_complete( 2257 struct output_pixel_processor *opp) 2258 { 2259 int counter; 2260 2261 for (counter = 0; counter < 1000; counter++) { 2262 if (opp->funcs->dpg_is_blanked(opp)) 2263 break; 2264 2265 udelay(100); 2266 } 2267 2268 if (counter == 1000) { 2269 dm_error("DC: failed to blank crtc!\n"); 2270 return false; 2271 } 2272 2273 return true; 2274 } 2275 2276 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) 2277 { 2278 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2279 2280 if (!hubp) 2281 return false; 2282 return hubp->funcs->dmdata_status_done(hubp); 2283 } 2284 2285 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 2286 { 2287 struct dce_hwseq *hws = dc->hwseq; 2288 2289 if (pipe_ctx->stream_res.dsc) { 2290 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2291 2292 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); 2293 while (odm_pipe) { 2294 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true); 2295 odm_pipe = odm_pipe->next_odm_pipe; 2296 } 2297 } 2298 } 2299 2300 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 2301 { 2302 struct dce_hwseq *hws = dc->hwseq; 2303 2304 if (pipe_ctx->stream_res.dsc) { 2305 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2306 2307 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false); 2308 while (odm_pipe) { 2309 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false); 2310 odm_pipe = odm_pipe->next_odm_pipe; 2311 } 2312 } 2313 } 2314 2315 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) 2316 { 2317 struct dc_dmdata_attributes attr = { 0 }; 2318 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2319 2320 attr.dmdata_mode = DMDATA_HW_MODE; 2321 attr.dmdata_size = 2322 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; 2323 attr.address.quad_part = 2324 pipe_ctx->stream->dmdata_address.quad_part; 2325 attr.dmdata_dl_delta = 0; 2326 attr.dmdata_qos_mode = 0; 2327 attr.dmdata_qos_level = 0; 2328 attr.dmdata_repeat = 1; /* always repeat */ 2329 attr.dmdata_updated = 1; 2330 attr.dmdata_sw_data = NULL; 2331 2332 hubp->funcs->dmdata_set_attributes(hubp, &attr); 2333 } 2334 2335 void dcn20_init_vm_ctx( 2336 struct dce_hwseq *hws, 2337 struct dc *dc, 2338 struct dc_virtual_addr_space_config *va_config, 2339 int vmid) 2340 { 2341 struct dcn_hubbub_virt_addr_config config; 2342 2343 if (vmid == 0) { 2344 ASSERT(0); /* VMID cannot be 0 for vm context */ 2345 return; 2346 } 2347 2348 config.page_table_start_addr = va_config->page_table_start_addr; 2349 config.page_table_end_addr = va_config->page_table_end_addr; 2350 config.page_table_block_size = va_config->page_table_block_size_in_bytes; 2351 config.page_table_depth = va_config->page_table_depth; 2352 config.page_table_base_addr = va_config->page_table_base_addr; 2353 2354 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); 2355 } 2356 2357 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 2358 { 2359 struct dcn_hubbub_phys_addr_config config; 2360 2361 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 2362 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 2363 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 2364 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 2365 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 2366 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 2367 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 2368 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 2369 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 2370 config.page_table_default_page_addr = pa_config->page_table_default_page_addr; 2371 2372 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 2373 } 2374 2375 static bool patch_address_for_sbs_tb_stereo( 2376 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) 2377 { 2378 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2379 bool sec_split = pipe_ctx->top_pipe && 2380 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; 2381 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && 2382 (pipe_ctx->stream->timing.timing_3d_format == 2383 TIMING_3D_FORMAT_SIDE_BY_SIDE || 2384 pipe_ctx->stream->timing.timing_3d_format == 2385 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { 2386 *addr = plane_state->address.grph_stereo.left_addr; 2387 plane_state->address.grph_stereo.left_addr = 2388 plane_state->address.grph_stereo.right_addr; 2389 return true; 2390 } 2391 2392 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && 2393 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { 2394 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; 2395 plane_state->address.grph_stereo.right_addr = 2396 plane_state->address.grph_stereo.left_addr; 2397 plane_state->address.grph_stereo.right_meta_addr = 2398 plane_state->address.grph_stereo.left_meta_addr; 2399 } 2400 return false; 2401 } 2402 2403 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) 2404 { 2405 bool addr_patched = false; 2406 PHYSICAL_ADDRESS_LOC addr; 2407 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2408 2409 if (plane_state == NULL) 2410 return; 2411 2412 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); 2413 2414 // Call Helper to track VMID use 2415 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); 2416 2417 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( 2418 pipe_ctx->plane_res.hubp, 2419 &plane_state->address, 2420 plane_state->flip_immediate); 2421 2422 plane_state->status.requested_address = plane_state->address; 2423 2424 if (plane_state->flip_immediate) 2425 plane_state->status.current_address = plane_state->address; 2426 2427 if (addr_patched) 2428 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; 2429 } 2430 2431 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, 2432 struct dc_link_settings *link_settings) 2433 { 2434 struct encoder_unblank_param params = {0}; 2435 struct dc_stream_state *stream = pipe_ctx->stream; 2436 struct dc_link *link = stream->link; 2437 struct dce_hwseq *hws = link->dc->hwseq; 2438 struct pipe_ctx *odm_pipe; 2439 2440 params.opp_cnt = 1; 2441 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 2442 params.opp_cnt++; 2443 } 2444 /* only 3 items below are used by unblank */ 2445 params.timing = pipe_ctx->stream->timing; 2446 2447 params.link_settings.link_rate = link_settings->link_rate; 2448 2449 if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 2450 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 2451 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 2452 pipe_ctx->stream_res.hpo_dp_stream_enc, 2453 pipe_ctx->stream_res.tg->inst); 2454 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 2455 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1) 2456 params.timing.pix_clk_100hz /= 2; 2457 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 2458 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1); 2459 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 2460 } 2461 2462 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 2463 hws->funcs.edp_backlight_control(link, true); 2464 } 2465 } 2466 2467 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx) 2468 { 2469 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2470 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx); 2471 2472 if (start_line < 0) 2473 start_line = 0; 2474 2475 if (tg->funcs->setup_vertical_interrupt2) 2476 tg->funcs->setup_vertical_interrupt2(tg, start_line); 2477 } 2478 2479 static void dcn20_reset_back_end_for_pipe( 2480 struct dc *dc, 2481 struct pipe_ctx *pipe_ctx, 2482 struct dc_state *context) 2483 { 2484 int i; 2485 struct dc_link *link = pipe_ctx->stream->link; 2486 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2487 2488 DC_LOGGER_INIT(dc->ctx->logger); 2489 if (pipe_ctx->stream_res.stream_enc == NULL) { 2490 pipe_ctx->stream = NULL; 2491 return; 2492 } 2493 2494 /* DPMS may already disable or */ 2495 /* dpms_off status is incorrect due to fastboot 2496 * feature. When system resume from S4 with second 2497 * screen only, the dpms_off would be true but 2498 * VBIOS lit up eDP, so check link status too. 2499 */ 2500 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 2501 dc->link_srv->set_dpms_off(pipe_ctx); 2502 else if (pipe_ctx->stream_res.audio) 2503 dc->hwss.disable_audio_stream(pipe_ctx); 2504 2505 /* free acquired resources */ 2506 if (pipe_ctx->stream_res.audio) { 2507 /*disable az_endpoint*/ 2508 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 2509 2510 /*free audio*/ 2511 if (dc->caps.dynamic_audio == true) { 2512 /*we have to dynamic arbitrate the audio endpoints*/ 2513 /*we free the resource, need reset is_audio_acquired*/ 2514 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 2515 pipe_ctx->stream_res.audio, false); 2516 pipe_ctx->stream_res.audio = NULL; 2517 } 2518 } 2519 2520 /* by upper caller loop, parent pipe: pipe0, will be reset last. 2521 * back end share by all pipes and will be disable only when disable 2522 * parent pipe. 2523 */ 2524 if (pipe_ctx->top_pipe == NULL) { 2525 2526 dc->hwss.set_abm_immediate_disable(pipe_ctx); 2527 2528 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 2529 2530 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 2531 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 2532 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 2533 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 2534 2535 if (pipe_ctx->stream_res.tg->funcs->set_drr) 2536 pipe_ctx->stream_res.tg->funcs->set_drr( 2537 pipe_ctx->stream_res.tg, NULL); 2538 /* TODO - convert symclk_ref_cnts for otg to a bit map to solve 2539 * the case where the same symclk is shared across multiple otg 2540 * instances 2541 */ 2542 link->phy_state.symclk_ref_cnts.otg = 0; 2543 if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) { 2544 link_hwss->disable_link_output(link, 2545 &pipe_ctx->link_res, pipe_ctx->stream->signal); 2546 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 2547 } 2548 } 2549 2550 for (i = 0; i < dc->res_pool->pipe_count; i++) 2551 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) 2552 break; 2553 2554 if (i == dc->res_pool->pipe_count) 2555 return; 2556 2557 pipe_ctx->stream = NULL; 2558 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 2559 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 2560 } 2561 2562 void dcn20_reset_hw_ctx_wrap( 2563 struct dc *dc, 2564 struct dc_state *context) 2565 { 2566 int i; 2567 struct dce_hwseq *hws = dc->hwseq; 2568 2569 /* Reset Back End*/ 2570 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 2571 struct pipe_ctx *pipe_ctx_old = 2572 &dc->current_state->res_ctx.pipe_ctx[i]; 2573 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2574 2575 if (!pipe_ctx_old->stream) 2576 continue; 2577 2578 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 2579 continue; 2580 2581 if (!pipe_ctx->stream || 2582 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 2583 struct clock_source *old_clk = pipe_ctx_old->clock_source; 2584 2585 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 2586 if (hws->funcs.enable_stream_gating) 2587 hws->funcs.enable_stream_gating(dc, pipe_ctx_old); 2588 if (old_clk) 2589 old_clk->funcs->cs_power_down(old_clk); 2590 } 2591 } 2592 } 2593 2594 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 2595 { 2596 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2597 struct mpcc_blnd_cfg blnd_cfg = {0}; 2598 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; 2599 int mpcc_id; 2600 struct mpcc *new_mpcc; 2601 struct mpc *mpc = dc->res_pool->mpc; 2602 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); 2603 2604 blnd_cfg.overlap_only = false; 2605 blnd_cfg.global_gain = 0xff; 2606 2607 if (per_pixel_alpha) { 2608 blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha; 2609 if (pipe_ctx->plane_state->global_alpha) { 2610 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; 2611 blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value; 2612 } else { 2613 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2614 } 2615 } else { 2616 blnd_cfg.pre_multiplied_alpha = false; 2617 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 2618 } 2619 2620 if (pipe_ctx->plane_state->global_alpha) 2621 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; 2622 else 2623 blnd_cfg.global_alpha = 0xff; 2624 2625 blnd_cfg.background_color_bpc = 4; 2626 blnd_cfg.bottom_gain_mode = 0; 2627 blnd_cfg.top_gain = 0x1f000; 2628 blnd_cfg.bottom_inside_gain = 0x1f000; 2629 blnd_cfg.bottom_outside_gain = 0x1f000; 2630 2631 if (pipe_ctx->plane_state->format 2632 == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA) 2633 blnd_cfg.pre_multiplied_alpha = false; 2634 2635 /* 2636 * TODO: remove hack 2637 * Note: currently there is a bug in init_hw such that 2638 * on resume from hibernate, BIOS sets up MPCC0, and 2639 * we do mpcc_remove but the mpcc cannot go to idle 2640 * after remove. This cause us to pick mpcc1 here, 2641 * which causes a pstate hang for yet unknown reason. 2642 */ 2643 mpcc_id = hubp->inst; 2644 2645 /* If there is no full update, don't need to touch MPC tree*/ 2646 if (!pipe_ctx->plane_state->update_flags.bits.full_update && 2647 !pipe_ctx->update_flags.bits.mpcc) { 2648 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); 2649 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); 2650 return; 2651 } 2652 2653 /* check if this MPCC is already being used */ 2654 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 2655 /* remove MPCC if being used */ 2656 if (new_mpcc != NULL) 2657 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); 2658 else 2659 if (dc->debug.sanity_checks) 2660 mpc->funcs->assert_mpcc_idle_before_connect( 2661 dc->res_pool->mpc, mpcc_id); 2662 2663 /* Call MPC to insert new plane */ 2664 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, 2665 mpc_tree_params, 2666 &blnd_cfg, 2667 NULL, 2668 NULL, 2669 hubp->inst, 2670 mpcc_id); 2671 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); 2672 2673 ASSERT(new_mpcc != NULL); 2674 hubp->opp_id = pipe_ctx->stream_res.opp->inst; 2675 hubp->mpcc_id = mpcc_id; 2676 } 2677 2678 static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link) 2679 { 2680 switch (link->link_enc->transmitter) { 2681 case TRANSMITTER_UNIPHY_A: 2682 return PHYD32CLKA; 2683 case TRANSMITTER_UNIPHY_B: 2684 return PHYD32CLKB; 2685 case TRANSMITTER_UNIPHY_C: 2686 return PHYD32CLKC; 2687 case TRANSMITTER_UNIPHY_D: 2688 return PHYD32CLKD; 2689 case TRANSMITTER_UNIPHY_E: 2690 return PHYD32CLKE; 2691 default: 2692 return PHYD32CLKA; 2693 } 2694 } 2695 2696 static int get_odm_segment_count(struct pipe_ctx *pipe_ctx) 2697 { 2698 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2699 int count = 1; 2700 2701 while (odm_pipe != NULL) { 2702 count++; 2703 odm_pipe = odm_pipe->next_odm_pipe; 2704 } 2705 2706 return count; 2707 } 2708 2709 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 2710 { 2711 enum dc_lane_count lane_count = 2712 pipe_ctx->stream->link->cur_link_settings.lane_count; 2713 2714 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 2715 struct dc_link *link = pipe_ctx->stream->link; 2716 2717 uint32_t active_total_with_borders; 2718 uint32_t early_control = 0; 2719 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2720 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2721 struct dc *dc = pipe_ctx->stream->ctx->dc; 2722 struct dtbclk_dto_params dto_params = {0}; 2723 struct dccg *dccg = dc->res_pool->dccg; 2724 enum phyd32clk_clock_source phyd32clk; 2725 int dp_hpo_inst; 2726 struct dce_hwseq *hws = dc->hwseq; 2727 unsigned int k1_div = PIXEL_RATE_DIV_NA; 2728 unsigned int k2_div = PIXEL_RATE_DIV_NA; 2729 2730 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 2731 if (dc->hwseq->funcs.setup_hpo_hw_control) 2732 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, true); 2733 } 2734 2735 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 2736 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; 2737 dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst); 2738 2739 phyd32clk = get_phyd32clk_src(link); 2740 dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); 2741 2742 dto_params.otg_inst = tg->inst; 2743 dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10; 2744 dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx); 2745 dto_params.timing = &pipe_ctx->stream->timing; 2746 dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); 2747 dccg->funcs->set_dtbclk_dto(dccg, &dto_params); 2748 } 2749 2750 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { 2751 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); 2752 2753 dc->res_pool->dccg->funcs->set_pixel_rate_div( 2754 dc->res_pool->dccg, 2755 pipe_ctx->stream_res.tg->inst, 2756 k1_div, k2_div); 2757 } 2758 2759 link_hwss->setup_stream_encoder(pipe_ctx); 2760 2761 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) { 2762 if (dc->hwss.program_dmdata_engine) 2763 dc->hwss.program_dmdata_engine(pipe_ctx); 2764 } 2765 2766 dc->hwss.update_info_frame(pipe_ctx); 2767 2768 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2769 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2770 2771 /* enable early control to avoid corruption on DP monitor*/ 2772 active_total_with_borders = 2773 timing->h_addressable 2774 + timing->h_border_left 2775 + timing->h_border_right; 2776 2777 if (lane_count != 0) 2778 early_control = active_total_with_borders % lane_count; 2779 2780 if (early_control == 0) 2781 early_control = lane_count; 2782 2783 tg->funcs->set_early_control(tg, early_control); 2784 2785 if (dc->hwseq->funcs.set_pixels_per_cycle) 2786 dc->hwseq->funcs.set_pixels_per_cycle(pipe_ctx); 2787 } 2788 2789 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx) 2790 { 2791 struct dc_stream_state *stream = pipe_ctx->stream; 2792 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2793 bool enable = false; 2794 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2795 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) 2796 ? dmdata_dp 2797 : dmdata_hdmi; 2798 2799 /* if using dynamic meta, don't set up generic infopackets */ 2800 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { 2801 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; 2802 enable = true; 2803 } 2804 2805 if (!hubp) 2806 return; 2807 2808 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) 2809 return; 2810 2811 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, 2812 hubp->inst, mode); 2813 } 2814 2815 void dcn20_fpga_init_hw(struct dc *dc) 2816 { 2817 int i, j; 2818 struct dce_hwseq *hws = dc->hwseq; 2819 struct resource_pool *res_pool = dc->res_pool; 2820 struct dc_state *context = dc->current_state; 2821 2822 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 2823 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 2824 2825 // Initialize the dccg 2826 if (res_pool->dccg->funcs->dccg_init) 2827 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 2828 2829 //Enable ability to power gate / don't force power on permanently 2830 hws->funcs.enable_power_gating_plane(hws, true); 2831 2832 // Specific to FPGA dccg and registers 2833 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); 2834 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 2835 2836 hws->funcs.dccg_init(hws); 2837 2838 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); 2839 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 2840 if (REG(REFCLK_CNTL)) 2841 REG_WRITE(REFCLK_CNTL, 0); 2842 // 2843 2844 2845 /* Blank pixel data with OPP DPG */ 2846 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2847 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2848 2849 if (tg->funcs->is_tg_enabled(tg)) 2850 dcn20_init_blank(dc, tg); 2851 } 2852 2853 for (i = 0; i < res_pool->timing_generator_count; i++) { 2854 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2855 2856 if (tg->funcs->is_tg_enabled(tg)) 2857 tg->funcs->lock(tg); 2858 } 2859 2860 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2861 struct dpp *dpp = res_pool->dpps[i]; 2862 2863 dpp->funcs->dpp_reset(dpp); 2864 } 2865 2866 /* Reset all MPCC muxes */ 2867 res_pool->mpc->funcs->mpc_init(res_pool->mpc); 2868 2869 /* initialize OPP mpc_tree parameter */ 2870 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 2871 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; 2872 res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2873 for (j = 0; j < MAX_PIPES; j++) 2874 res_pool->opps[i]->mpcc_disconnect_pending[j] = false; 2875 } 2876 2877 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2878 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2879 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2880 struct hubp *hubp = dc->res_pool->hubps[i]; 2881 struct dpp *dpp = dc->res_pool->dpps[i]; 2882 2883 pipe_ctx->stream_res.tg = tg; 2884 pipe_ctx->pipe_idx = i; 2885 2886 pipe_ctx->plane_res.hubp = hubp; 2887 pipe_ctx->plane_res.dpp = dpp; 2888 pipe_ctx->plane_res.mpcc_inst = dpp->inst; 2889 hubp->mpcc_id = dpp->inst; 2890 hubp->opp_id = OPP_ID_INVALID; 2891 hubp->power_gated = false; 2892 pipe_ctx->stream_res.opp = NULL; 2893 2894 hubp->funcs->hubp_init(hubp); 2895 2896 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; 2897 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2898 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; 2899 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; 2900 /*to do*/ 2901 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx); 2902 } 2903 2904 /* initialize DWB pointer to MCIF_WB */ 2905 for (i = 0; i < res_pool->res_cap->num_dwb; i++) 2906 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; 2907 2908 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2909 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2910 2911 if (tg->funcs->is_tg_enabled(tg)) 2912 tg->funcs->unlock(tg); 2913 } 2914 2915 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2916 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2917 2918 dc->hwss.disable_plane(dc, pipe_ctx); 2919 2920 pipe_ctx->stream_res.tg = NULL; 2921 pipe_ctx->plane_res.hubp = NULL; 2922 } 2923 2924 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2925 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2926 2927 tg->funcs->tg_init(tg); 2928 } 2929 2930 if (dc->res_pool->hubbub->funcs->init_crb) 2931 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 2932 } 2933 #ifndef TRIM_FSFT 2934 bool dcn20_optimize_timing_for_fsft(struct dc *dc, 2935 struct dc_crtc_timing *timing, 2936 unsigned int max_input_rate_in_khz) 2937 { 2938 unsigned int old_v_front_porch; 2939 unsigned int old_v_total; 2940 unsigned int max_input_rate_in_100hz; 2941 unsigned long long new_v_total; 2942 2943 max_input_rate_in_100hz = max_input_rate_in_khz * 10; 2944 if (max_input_rate_in_100hz < timing->pix_clk_100hz) 2945 return false; 2946 2947 old_v_total = timing->v_total; 2948 old_v_front_porch = timing->v_front_porch; 2949 2950 timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz; 2951 timing->pix_clk_100hz = max_input_rate_in_100hz; 2952 2953 new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz); 2954 2955 timing->v_total = new_v_total; 2956 timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total); 2957 return true; 2958 } 2959 #endif 2960 2961 void dcn20_set_disp_pattern_generator(const struct dc *dc, 2962 struct pipe_ctx *pipe_ctx, 2963 enum controller_dp_test_pattern test_pattern, 2964 enum controller_dp_color_space color_space, 2965 enum dc_color_depth color_depth, 2966 const struct tg_color *solid_color, 2967 int width, int height, int offset) 2968 { 2969 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern, 2970 color_space, color_depth, solid_color, width, height, offset); 2971 } 2972