1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include <linux/delay.h> 26 27 #include "dm_services.h" 28 #include "basics/dc_common.h" 29 #include "dm_helpers.h" 30 #include "core_types.h" 31 #include "resource.h" 32 #include "dcn20_resource.h" 33 #include "dcn20_hwseq.h" 34 #include "dce/dce_hwseq.h" 35 #include "dcn20_dsc.h" 36 #include "dcn20_optc.h" 37 #include "abm.h" 38 #include "clk_mgr.h" 39 #include "dmcu.h" 40 #include "hubp.h" 41 #include "timing_generator.h" 42 #include "opp.h" 43 #include "ipp.h" 44 #include "mpc.h" 45 #include "mcif_wb.h" 46 #include "dchubbub.h" 47 #include "reg_helper.h" 48 #include "dcn10/dcn10_cm_common.h" 49 #include "vm_helper.h" 50 #include "dccg.h" 51 #include "dc_dmub_srv.h" 52 #include "dce/dmub_hw_lock_mgr.h" 53 #include "hw_sequencer.h" 54 #include "dpcd_defs.h" 55 #include "inc/link_enc_cfg.h" 56 #include "link_hwss.h" 57 #include "link.h" 58 59 #define DC_LOGGER_INIT(logger) 60 61 #define CTX \ 62 hws->ctx 63 #define REG(reg)\ 64 hws->regs->reg 65 66 #undef FN 67 #define FN(reg_name, field_name) \ 68 hws->shifts->field_name, hws->masks->field_name 69 70 static int find_free_gsl_group(const struct dc *dc) 71 { 72 if (dc->res_pool->gsl_groups.gsl_0 == 0) 73 return 1; 74 if (dc->res_pool->gsl_groups.gsl_1 == 0) 75 return 2; 76 if (dc->res_pool->gsl_groups.gsl_2 == 0) 77 return 3; 78 79 return 0; 80 } 81 82 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock) 83 * This is only used to lock pipes in pipe splitting case with immediate flip 84 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate, 85 * so we get tearing with freesync since we cannot flip multiple pipes 86 * atomically. 87 * We use GSL for this: 88 * - immediate flip: find first available GSL group if not already assigned 89 * program gsl with that group, set current OTG as master 90 * and always us 0x4 = AND of flip_ready from all pipes 91 * - vsync flip: disable GSL if used 92 * 93 * Groups in stream_res are stored as +1 from HW registers, i.e. 94 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1 95 * Using a magic value like -1 would require tracking all inits/resets 96 */ 97 static void dcn20_setup_gsl_group_as_lock( 98 const struct dc *dc, 99 struct pipe_ctx *pipe_ctx, 100 bool enable) 101 { 102 struct gsl_params gsl; 103 int group_idx; 104 105 memset(&gsl, 0, sizeof(struct gsl_params)); 106 107 if (enable) { 108 /* return if group already assigned since GSL was set up 109 * for vsync flip, we would unassign so it can't be "left over" 110 */ 111 if (pipe_ctx->stream_res.gsl_group > 0) 112 return; 113 114 group_idx = find_free_gsl_group(dc); 115 ASSERT(group_idx != 0); 116 pipe_ctx->stream_res.gsl_group = group_idx; 117 118 /* set gsl group reg field and mark resource used */ 119 switch (group_idx) { 120 case 1: 121 gsl.gsl0_en = 1; 122 dc->res_pool->gsl_groups.gsl_0 = 1; 123 break; 124 case 2: 125 gsl.gsl1_en = 1; 126 dc->res_pool->gsl_groups.gsl_1 = 1; 127 break; 128 case 3: 129 gsl.gsl2_en = 1; 130 dc->res_pool->gsl_groups.gsl_2 = 1; 131 break; 132 default: 133 BREAK_TO_DEBUGGER(); 134 return; // invalid case 135 } 136 gsl.gsl_master_en = 1; 137 } else { 138 group_idx = pipe_ctx->stream_res.gsl_group; 139 if (group_idx == 0) 140 return; // if not in use, just return 141 142 pipe_ctx->stream_res.gsl_group = 0; 143 144 /* unset gsl group reg field and mark resource free */ 145 switch (group_idx) { 146 case 1: 147 gsl.gsl0_en = 0; 148 dc->res_pool->gsl_groups.gsl_0 = 0; 149 break; 150 case 2: 151 gsl.gsl1_en = 0; 152 dc->res_pool->gsl_groups.gsl_1 = 0; 153 break; 154 case 3: 155 gsl.gsl2_en = 0; 156 dc->res_pool->gsl_groups.gsl_2 = 0; 157 break; 158 default: 159 BREAK_TO_DEBUGGER(); 160 return; 161 } 162 gsl.gsl_master_en = 0; 163 } 164 165 /* at this point we want to program whether it's to enable or disable */ 166 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && 167 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { 168 pipe_ctx->stream_res.tg->funcs->set_gsl( 169 pipe_ctx->stream_res.tg, 170 &gsl); 171 172 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( 173 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); 174 } else 175 BREAK_TO_DEBUGGER(); 176 } 177 178 void dcn20_set_flip_control_gsl( 179 struct pipe_ctx *pipe_ctx, 180 bool flip_immediate) 181 { 182 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) 183 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( 184 pipe_ctx->plane_res.hubp, flip_immediate); 185 186 } 187 188 void dcn20_enable_power_gating_plane( 189 struct dce_hwseq *hws, 190 bool enable) 191 { 192 bool force_on = true; /* disable power gating */ 193 uint32_t org_ip_request_cntl = 0; 194 195 if (enable) 196 force_on = false; 197 198 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 199 if (org_ip_request_cntl == 0) 200 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 201 202 /* DCHUBP0/1/2/3/4/5 */ 203 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); 204 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); 205 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); 206 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); 207 if (REG(DOMAIN8_PG_CONFIG)) 208 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 209 if (REG(DOMAIN10_PG_CONFIG)) 210 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 211 212 /* DPP0/1/2/3/4/5 */ 213 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); 214 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); 215 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); 216 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); 217 if (REG(DOMAIN9_PG_CONFIG)) 218 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 219 if (REG(DOMAIN11_PG_CONFIG)) 220 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 221 222 /* DCS0/1/2/3/4/5 */ 223 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on); 224 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on); 225 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on); 226 if (REG(DOMAIN19_PG_CONFIG)) 227 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on); 228 if (REG(DOMAIN20_PG_CONFIG)) 229 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on); 230 if (REG(DOMAIN21_PG_CONFIG)) 231 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); 232 233 if (org_ip_request_cntl == 0) 234 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 235 236 } 237 238 void dcn20_dccg_init(struct dce_hwseq *hws) 239 { 240 /* 241 * set MICROSECOND_TIME_BASE_DIV 242 * 100Mhz refclk -> 0x120264 243 * 27Mhz refclk -> 0x12021b 244 * 48Mhz refclk -> 0x120230 245 * 246 */ 247 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); 248 249 /* 250 * set MILLISECOND_TIME_BASE_DIV 251 * 100Mhz refclk -> 0x1186a0 252 * 27Mhz refclk -> 0x106978 253 * 48Mhz refclk -> 0x10bb80 254 * 255 */ 256 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); 257 258 /* This value is dependent on the hardware pipeline delay so set once per SOC */ 259 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c); 260 } 261 262 void dcn20_disable_vga( 263 struct dce_hwseq *hws) 264 { 265 REG_WRITE(D1VGA_CONTROL, 0); 266 REG_WRITE(D2VGA_CONTROL, 0); 267 REG_WRITE(D3VGA_CONTROL, 0); 268 REG_WRITE(D4VGA_CONTROL, 0); 269 REG_WRITE(D5VGA_CONTROL, 0); 270 REG_WRITE(D6VGA_CONTROL, 0); 271 } 272 273 void dcn20_program_triple_buffer( 274 const struct dc *dc, 275 struct pipe_ctx *pipe_ctx, 276 bool enable_triple_buffer) 277 { 278 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { 279 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( 280 pipe_ctx->plane_res.hubp, 281 enable_triple_buffer); 282 } 283 } 284 285 /* Blank pixel data during initialization */ 286 void dcn20_init_blank( 287 struct dc *dc, 288 struct timing_generator *tg) 289 { 290 struct dce_hwseq *hws = dc->hwseq; 291 enum dc_color_space color_space; 292 struct tg_color black_color = {0}; 293 struct output_pixel_processor *opp = NULL; 294 struct output_pixel_processor *bottom_opp = NULL; 295 uint32_t num_opps, opp_id_src0, opp_id_src1; 296 uint32_t otg_active_width, otg_active_height; 297 298 /* program opp dpg blank color */ 299 color_space = COLOR_SPACE_SRGB; 300 color_space_to_black_color(dc, color_space, &black_color); 301 302 /* get the OTG active size */ 303 tg->funcs->get_otg_active_size(tg, 304 &otg_active_width, 305 &otg_active_height); 306 307 /* get the OPTC source */ 308 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 309 310 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { 311 ASSERT(false); 312 return; 313 } 314 opp = dc->res_pool->opps[opp_id_src0]; 315 316 if (num_opps == 2) { 317 otg_active_width = otg_active_width / 2; 318 319 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { 320 ASSERT(false); 321 return; 322 } 323 bottom_opp = dc->res_pool->opps[opp_id_src1]; 324 } 325 326 opp->funcs->opp_set_disp_pattern_generator( 327 opp, 328 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 329 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 330 COLOR_DEPTH_UNDEFINED, 331 &black_color, 332 otg_active_width, 333 otg_active_height, 334 0); 335 336 if (num_opps == 2) { 337 bottom_opp->funcs->opp_set_disp_pattern_generator( 338 bottom_opp, 339 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 340 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 341 COLOR_DEPTH_UNDEFINED, 342 &black_color, 343 otg_active_width, 344 otg_active_height, 345 0); 346 } 347 348 hws->funcs.wait_for_blank_complete(opp); 349 } 350 351 void dcn20_dsc_pg_control( 352 struct dce_hwseq *hws, 353 unsigned int dsc_inst, 354 bool power_on) 355 { 356 uint32_t power_gate = power_on ? 0 : 1; 357 uint32_t pwr_status = power_on ? 0 : 2; 358 uint32_t org_ip_request_cntl = 0; 359 360 if (hws->ctx->dc->debug.disable_dsc_power_gate) 361 return; 362 363 if (REG(DOMAIN16_PG_CONFIG) == 0) 364 return; 365 366 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 367 if (org_ip_request_cntl == 0) 368 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 369 370 switch (dsc_inst) { 371 case 0: /* DSC0 */ 372 REG_UPDATE(DOMAIN16_PG_CONFIG, 373 DOMAIN16_POWER_GATE, power_gate); 374 375 REG_WAIT(DOMAIN16_PG_STATUS, 376 DOMAIN16_PGFSM_PWR_STATUS, pwr_status, 377 1, 1000); 378 break; 379 case 1: /* DSC1 */ 380 REG_UPDATE(DOMAIN17_PG_CONFIG, 381 DOMAIN17_POWER_GATE, power_gate); 382 383 REG_WAIT(DOMAIN17_PG_STATUS, 384 DOMAIN17_PGFSM_PWR_STATUS, pwr_status, 385 1, 1000); 386 break; 387 case 2: /* DSC2 */ 388 REG_UPDATE(DOMAIN18_PG_CONFIG, 389 DOMAIN18_POWER_GATE, power_gate); 390 391 REG_WAIT(DOMAIN18_PG_STATUS, 392 DOMAIN18_PGFSM_PWR_STATUS, pwr_status, 393 1, 1000); 394 break; 395 case 3: /* DSC3 */ 396 REG_UPDATE(DOMAIN19_PG_CONFIG, 397 DOMAIN19_POWER_GATE, power_gate); 398 399 REG_WAIT(DOMAIN19_PG_STATUS, 400 DOMAIN19_PGFSM_PWR_STATUS, pwr_status, 401 1, 1000); 402 break; 403 case 4: /* DSC4 */ 404 REG_UPDATE(DOMAIN20_PG_CONFIG, 405 DOMAIN20_POWER_GATE, power_gate); 406 407 REG_WAIT(DOMAIN20_PG_STATUS, 408 DOMAIN20_PGFSM_PWR_STATUS, pwr_status, 409 1, 1000); 410 break; 411 case 5: /* DSC5 */ 412 REG_UPDATE(DOMAIN21_PG_CONFIG, 413 DOMAIN21_POWER_GATE, power_gate); 414 415 REG_WAIT(DOMAIN21_PG_STATUS, 416 DOMAIN21_PGFSM_PWR_STATUS, pwr_status, 417 1, 1000); 418 break; 419 default: 420 BREAK_TO_DEBUGGER(); 421 break; 422 } 423 424 if (org_ip_request_cntl == 0) 425 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 426 } 427 428 void dcn20_dpp_pg_control( 429 struct dce_hwseq *hws, 430 unsigned int dpp_inst, 431 bool power_on) 432 { 433 uint32_t power_gate = power_on ? 0 : 1; 434 uint32_t pwr_status = power_on ? 0 : 2; 435 436 if (hws->ctx->dc->debug.disable_dpp_power_gate) 437 return; 438 if (REG(DOMAIN1_PG_CONFIG) == 0) 439 return; 440 441 switch (dpp_inst) { 442 case 0: /* DPP0 */ 443 REG_UPDATE(DOMAIN1_PG_CONFIG, 444 DOMAIN1_POWER_GATE, power_gate); 445 446 REG_WAIT(DOMAIN1_PG_STATUS, 447 DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 448 1, 1000); 449 break; 450 case 1: /* DPP1 */ 451 REG_UPDATE(DOMAIN3_PG_CONFIG, 452 DOMAIN3_POWER_GATE, power_gate); 453 454 REG_WAIT(DOMAIN3_PG_STATUS, 455 DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 456 1, 1000); 457 break; 458 case 2: /* DPP2 */ 459 REG_UPDATE(DOMAIN5_PG_CONFIG, 460 DOMAIN5_POWER_GATE, power_gate); 461 462 REG_WAIT(DOMAIN5_PG_STATUS, 463 DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 464 1, 1000); 465 break; 466 case 3: /* DPP3 */ 467 REG_UPDATE(DOMAIN7_PG_CONFIG, 468 DOMAIN7_POWER_GATE, power_gate); 469 470 REG_WAIT(DOMAIN7_PG_STATUS, 471 DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 472 1, 1000); 473 break; 474 case 4: /* DPP4 */ 475 REG_UPDATE(DOMAIN9_PG_CONFIG, 476 DOMAIN9_POWER_GATE, power_gate); 477 478 REG_WAIT(DOMAIN9_PG_STATUS, 479 DOMAIN9_PGFSM_PWR_STATUS, pwr_status, 480 1, 1000); 481 break; 482 case 5: /* DPP5 */ 483 /* 484 * Do not power gate DPP5, should be left at HW default, power on permanently. 485 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 486 * reset. 487 * REG_UPDATE(DOMAIN11_PG_CONFIG, 488 * DOMAIN11_POWER_GATE, power_gate); 489 * 490 * REG_WAIT(DOMAIN11_PG_STATUS, 491 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, 492 * 1, 1000); 493 */ 494 break; 495 default: 496 BREAK_TO_DEBUGGER(); 497 break; 498 } 499 } 500 501 502 void dcn20_hubp_pg_control( 503 struct dce_hwseq *hws, 504 unsigned int hubp_inst, 505 bool power_on) 506 { 507 uint32_t power_gate = power_on ? 0 : 1; 508 uint32_t pwr_status = power_on ? 0 : 2; 509 510 if (hws->ctx->dc->debug.disable_hubp_power_gate) 511 return; 512 if (REG(DOMAIN0_PG_CONFIG) == 0) 513 return; 514 515 switch (hubp_inst) { 516 case 0: /* DCHUBP0 */ 517 REG_UPDATE(DOMAIN0_PG_CONFIG, 518 DOMAIN0_POWER_GATE, power_gate); 519 520 REG_WAIT(DOMAIN0_PG_STATUS, 521 DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 522 1, 1000); 523 break; 524 case 1: /* DCHUBP1 */ 525 REG_UPDATE(DOMAIN2_PG_CONFIG, 526 DOMAIN2_POWER_GATE, power_gate); 527 528 REG_WAIT(DOMAIN2_PG_STATUS, 529 DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 530 1, 1000); 531 break; 532 case 2: /* DCHUBP2 */ 533 REG_UPDATE(DOMAIN4_PG_CONFIG, 534 DOMAIN4_POWER_GATE, power_gate); 535 536 REG_WAIT(DOMAIN4_PG_STATUS, 537 DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 538 1, 1000); 539 break; 540 case 3: /* DCHUBP3 */ 541 REG_UPDATE(DOMAIN6_PG_CONFIG, 542 DOMAIN6_POWER_GATE, power_gate); 543 544 REG_WAIT(DOMAIN6_PG_STATUS, 545 DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 546 1, 1000); 547 break; 548 case 4: /* DCHUBP4 */ 549 REG_UPDATE(DOMAIN8_PG_CONFIG, 550 DOMAIN8_POWER_GATE, power_gate); 551 552 REG_WAIT(DOMAIN8_PG_STATUS, 553 DOMAIN8_PGFSM_PWR_STATUS, pwr_status, 554 1, 1000); 555 break; 556 case 5: /* DCHUBP5 */ 557 /* 558 * Do not power gate DCHUB5, should be left at HW default, power on permanently. 559 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 560 * reset. 561 * REG_UPDATE(DOMAIN10_PG_CONFIG, 562 * DOMAIN10_POWER_GATE, power_gate); 563 * 564 * REG_WAIT(DOMAIN10_PG_STATUS, 565 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status, 566 * 1, 1000); 567 */ 568 break; 569 default: 570 BREAK_TO_DEBUGGER(); 571 break; 572 } 573 } 574 575 576 /* disable HW used by plane. 577 * note: cannot disable until disconnect is complete 578 */ 579 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 580 { 581 struct dce_hwseq *hws = dc->hwseq; 582 struct hubp *hubp = pipe_ctx->plane_res.hubp; 583 struct dpp *dpp = pipe_ctx->plane_res.dpp; 584 585 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); 586 587 /* In flip immediate with pipe splitting case GSL is used for 588 * synchronization so we must disable it when the plane is disabled. 589 */ 590 if (pipe_ctx->stream_res.gsl_group != 0) 591 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false); 592 593 if (hubp->funcs->hubp_update_mall_sel) 594 hubp->funcs->hubp_update_mall_sel(hubp, 0, false); 595 596 dc->hwss.set_flip_control_gsl(pipe_ctx, false); 597 598 hubp->funcs->hubp_clk_cntl(hubp, false); 599 600 dpp->funcs->dpp_dppclk_control(dpp, false, false); 601 602 hubp->power_gated = true; 603 604 hws->funcs.plane_atomic_power_down(dc, 605 pipe_ctx->plane_res.dpp, 606 pipe_ctx->plane_res.hubp); 607 608 pipe_ctx->stream = NULL; 609 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); 610 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); 611 pipe_ctx->top_pipe = NULL; 612 pipe_ctx->bottom_pipe = NULL; 613 pipe_ctx->plane_state = NULL; 614 } 615 616 617 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) 618 { 619 bool is_phantom = pipe_ctx->plane_state && pipe_ctx->plane_state->is_phantom; 620 struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL; 621 622 DC_LOGGER_INIT(dc->ctx->logger); 623 624 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) 625 return; 626 627 dcn20_plane_atomic_disable(dc, pipe_ctx); 628 629 /* Turn back off the phantom OTG after the phantom plane is fully disabled 630 */ 631 if (is_phantom) 632 if (tg && tg->funcs->disable_phantom_crtc) 633 tg->funcs->disable_phantom_crtc(tg); 634 635 DC_LOG_DC("Power down front end %d\n", 636 pipe_ctx->pipe_idx); 637 } 638 639 void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank) 640 { 641 dcn20_blank_pixel_data(dc, pipe_ctx, blank); 642 } 643 644 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 645 int opp_cnt) 646 { 647 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 648 int flow_ctrl_cnt; 649 650 if (opp_cnt >= 2) 651 hblank_halved = true; 652 653 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 654 stream->timing.h_border_left - 655 stream->timing.h_border_right; 656 657 if (hblank_halved) 658 flow_ctrl_cnt /= 2; 659 660 /* ODM combine 4:1 case */ 661 if (opp_cnt == 4) 662 flow_ctrl_cnt /= 2; 663 664 return flow_ctrl_cnt; 665 } 666 667 enum dc_status dcn20_enable_stream_timing( 668 struct pipe_ctx *pipe_ctx, 669 struct dc_state *context, 670 struct dc *dc) 671 { 672 struct dce_hwseq *hws = dc->hwseq; 673 struct dc_stream_state *stream = pipe_ctx->stream; 674 struct drr_params params = {0}; 675 unsigned int event_triggers = 0; 676 struct pipe_ctx *odm_pipe; 677 int opp_cnt = 1; 678 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 679 bool interlace = stream->timing.flags.INTERLACE; 680 int i; 681 struct mpc_dwb_flow_control flow_control; 682 struct mpc *mpc = dc->res_pool->mpc; 683 bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing)); 684 unsigned int k1_div = PIXEL_RATE_DIV_NA; 685 unsigned int k2_div = PIXEL_RATE_DIV_NA; 686 687 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { 688 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); 689 690 dc->res_pool->dccg->funcs->set_pixel_rate_div( 691 dc->res_pool->dccg, 692 pipe_ctx->stream_res.tg->inst, 693 k1_div, k2_div); 694 } 695 /* by upper caller loop, pipe0 is parent pipe and be called first. 696 * back end is set up by for pipe0. Other children pipe share back end 697 * with pipe 0. No program is needed. 698 */ 699 if (pipe_ctx->top_pipe != NULL) 700 return DC_OK; 701 702 /* TODO check if timing_changed, disable stream if timing changed */ 703 704 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 705 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 706 opp_cnt++; 707 } 708 709 if (opp_cnt > 1) 710 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 711 pipe_ctx->stream_res.tg, 712 opp_inst, opp_cnt, 713 &pipe_ctx->stream->timing); 714 715 /* HW program guide assume display already disable 716 * by unplug sequence. OTG assume stop. 717 */ 718 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); 719 720 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 721 pipe_ctx->clock_source, 722 &pipe_ctx->stream_res.pix_clk_params, 723 dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings), 724 &pipe_ctx->pll_settings)) { 725 BREAK_TO_DEBUGGER(); 726 return DC_ERROR_UNEXPECTED; 727 } 728 729 if (dc_is_hdmi_tmds_signal(stream->signal)) { 730 stream->link->phy_state.symclk_ref_cnts.otg = 1; 731 if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF) 732 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; 733 else 734 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 735 } 736 737 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal))) 738 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx); 739 740 pipe_ctx->stream_res.tg->funcs->program_timing( 741 pipe_ctx->stream_res.tg, 742 &stream->timing, 743 pipe_ctx->pipe_dlg_param.vready_offset, 744 pipe_ctx->pipe_dlg_param.vstartup_start, 745 pipe_ctx->pipe_dlg_param.vupdate_offset, 746 pipe_ctx->pipe_dlg_param.vupdate_width, 747 pipe_ctx->stream->signal, 748 true); 749 750 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 751 flow_control.flow_ctrl_mode = 0; 752 flow_control.flow_ctrl_cnt0 = 0x80; 753 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt); 754 if (mpc->funcs->set_out_rate_control) { 755 for (i = 0; i < opp_cnt; ++i) { 756 mpc->funcs->set_out_rate_control( 757 mpc, opp_inst[i], 758 true, 759 rate_control_2x_pclk, 760 &flow_control); 761 } 762 } 763 764 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 765 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 766 odm_pipe->stream_res.opp, 767 true); 768 769 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 770 pipe_ctx->stream_res.opp, 771 true); 772 773 hws->funcs.blank_pixel_data(dc, pipe_ctx, true); 774 775 /* VTG is within DCHUB command block. DCFCLK is always on */ 776 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { 777 BREAK_TO_DEBUGGER(); 778 return DC_ERROR_UNEXPECTED; 779 } 780 781 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp); 782 783 params.vertical_total_min = stream->adjust.v_total_min; 784 params.vertical_total_max = stream->adjust.v_total_max; 785 params.vertical_total_mid = stream->adjust.v_total_mid; 786 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num; 787 if (pipe_ctx->stream_res.tg->funcs->set_drr) 788 pipe_ctx->stream_res.tg->funcs->set_drr( 789 pipe_ctx->stream_res.tg, ¶ms); 790 791 // DRR should set trigger event to monitor surface update event 792 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 793 event_triggers = 0x80; 794 /* Event triggers and num frames initialized for DRR, but can be 795 * later updated for PSR use. Note DRR trigger events are generated 796 * regardless of whether num frames met. 797 */ 798 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 799 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 800 pipe_ctx->stream_res.tg, event_triggers, 2); 801 802 /* TODO program crtc source select for non-virtual signal*/ 803 /* TODO program FMT */ 804 /* TODO setup link_enc */ 805 /* TODO set stream attributes */ 806 /* TODO program audio */ 807 /* TODO enable stream if timing changed */ 808 /* TODO unblank stream if DP */ 809 810 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) { 811 if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable) 812 pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg); 813 } 814 return DC_OK; 815 } 816 817 void dcn20_program_output_csc(struct dc *dc, 818 struct pipe_ctx *pipe_ctx, 819 enum dc_color_space colorspace, 820 uint16_t *matrix, 821 int opp_id) 822 { 823 struct mpc *mpc = dc->res_pool->mpc; 824 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; 825 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 826 827 if (mpc->funcs->power_on_mpc_mem_pwr) 828 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 829 830 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 831 if (mpc->funcs->set_output_csc != NULL) 832 mpc->funcs->set_output_csc(mpc, 833 opp_id, 834 matrix, 835 ocsc_mode); 836 } else { 837 if (mpc->funcs->set_ocsc_default != NULL) 838 mpc->funcs->set_ocsc_default(mpc, 839 opp_id, 840 colorspace, 841 ocsc_mode); 842 } 843 } 844 845 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 846 const struct dc_stream_state *stream) 847 { 848 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 849 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 850 struct pwl_params *params = NULL; 851 /* 852 * program OGAM only for the top pipe 853 * if there is a pipe split then fix diagnostic is required: 854 * how to pass OGAM parameter for stream. 855 * if programming for all pipes is required then remove condition 856 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic. 857 */ 858 if (mpc->funcs->power_on_mpc_mem_pwr) 859 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 860 if (pipe_ctx->top_pipe == NULL 861 && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 862 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 863 params = &stream->out_transfer_func->pwl; 864 else if (pipe_ctx->stream->out_transfer_func->type == 865 TF_TYPE_DISTRIBUTED_POINTS && 866 cm_helper_translate_curve_to_hw_format( 867 stream->out_transfer_func, 868 &mpc->blender_params, false)) 869 params = &mpc->blender_params; 870 /* 871 * there is no ROM 872 */ 873 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 874 BREAK_TO_DEBUGGER(); 875 } 876 /* 877 * if above if is not executed then 'params' equal to 0 and set in bypass 878 */ 879 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 880 881 return true; 882 } 883 884 bool dcn20_set_blend_lut( 885 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 886 { 887 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 888 bool result = true; 889 struct pwl_params *blend_lut = NULL; 890 891 if (plane_state->blend_tf) { 892 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 893 blend_lut = &plane_state->blend_tf->pwl; 894 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 895 cm_helper_translate_curve_to_hw_format( 896 plane_state->blend_tf, 897 &dpp_base->regamma_params, false); 898 blend_lut = &dpp_base->regamma_params; 899 } 900 } 901 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); 902 903 return result; 904 } 905 906 bool dcn20_set_shaper_3dlut( 907 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 908 { 909 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 910 bool result = true; 911 struct pwl_params *shaper_lut = NULL; 912 913 if (plane_state->in_shaper_func) { 914 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 915 shaper_lut = &plane_state->in_shaper_func->pwl; 916 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 917 cm_helper_translate_curve_to_hw_format( 918 plane_state->in_shaper_func, 919 &dpp_base->shaper_params, true); 920 shaper_lut = &dpp_base->shaper_params; 921 } 922 } 923 924 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); 925 if (plane_state->lut3d_func && 926 plane_state->lut3d_func->state.bits.initialized == 1) 927 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, 928 &plane_state->lut3d_func->lut_3d); 929 else 930 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); 931 932 return result; 933 } 934 935 bool dcn20_set_input_transfer_func(struct dc *dc, 936 struct pipe_ctx *pipe_ctx, 937 const struct dc_plane_state *plane_state) 938 { 939 struct dce_hwseq *hws = dc->hwseq; 940 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 941 const struct dc_transfer_func *tf = NULL; 942 bool result = true; 943 bool use_degamma_ram = false; 944 945 if (dpp_base == NULL || plane_state == NULL) 946 return false; 947 948 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); 949 hws->funcs.set_blend_lut(pipe_ctx, plane_state); 950 951 if (plane_state->in_transfer_func) 952 tf = plane_state->in_transfer_func; 953 954 955 if (tf == NULL) { 956 dpp_base->funcs->dpp_set_degamma(dpp_base, 957 IPP_DEGAMMA_MODE_BYPASS); 958 return true; 959 } 960 961 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS) 962 use_degamma_ram = true; 963 964 if (use_degamma_ram == true) { 965 if (tf->type == TF_TYPE_HWPWL) 966 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 967 &tf->pwl); 968 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 969 cm_helper_translate_curve_to_degamma_hw_format(tf, 970 &dpp_base->degamma_params); 971 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 972 &dpp_base->degamma_params); 973 } 974 return true; 975 } 976 /* handle here the optimized cases when de-gamma ROM could be used. 977 * 978 */ 979 if (tf->type == TF_TYPE_PREDEFINED) { 980 switch (tf->tf) { 981 case TRANSFER_FUNCTION_SRGB: 982 dpp_base->funcs->dpp_set_degamma(dpp_base, 983 IPP_DEGAMMA_MODE_HW_sRGB); 984 break; 985 case TRANSFER_FUNCTION_BT709: 986 dpp_base->funcs->dpp_set_degamma(dpp_base, 987 IPP_DEGAMMA_MODE_HW_xvYCC); 988 break; 989 case TRANSFER_FUNCTION_LINEAR: 990 dpp_base->funcs->dpp_set_degamma(dpp_base, 991 IPP_DEGAMMA_MODE_BYPASS); 992 break; 993 case TRANSFER_FUNCTION_PQ: 994 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL); 995 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params); 996 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params); 997 result = true; 998 break; 999 default: 1000 result = false; 1001 break; 1002 } 1003 } else if (tf->type == TF_TYPE_BYPASS) 1004 dpp_base->funcs->dpp_set_degamma(dpp_base, 1005 IPP_DEGAMMA_MODE_BYPASS); 1006 else { 1007 /* 1008 * if we are here, we did not handle correctly. 1009 * fix is required for this use case 1010 */ 1011 BREAK_TO_DEBUGGER(); 1012 dpp_base->funcs->dpp_set_degamma(dpp_base, 1013 IPP_DEGAMMA_MODE_BYPASS); 1014 } 1015 1016 return result; 1017 } 1018 1019 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1020 { 1021 struct pipe_ctx *odm_pipe; 1022 int opp_cnt = 1; 1023 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 1024 1025 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1026 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 1027 opp_cnt++; 1028 } 1029 1030 if (opp_cnt > 1) 1031 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 1032 pipe_ctx->stream_res.tg, 1033 opp_inst, opp_cnt, 1034 &pipe_ctx->stream->timing); 1035 else 1036 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1037 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1038 } 1039 1040 void dcn20_blank_pixel_data( 1041 struct dc *dc, 1042 struct pipe_ctx *pipe_ctx, 1043 bool blank) 1044 { 1045 struct tg_color black_color = {0}; 1046 struct stream_resource *stream_res = &pipe_ctx->stream_res; 1047 struct dc_stream_state *stream = pipe_ctx->stream; 1048 enum dc_color_space color_space = stream->output_color_space; 1049 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; 1050 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; 1051 struct pipe_ctx *odm_pipe; 1052 int odm_cnt = 1; 1053 1054 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 1055 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; 1056 1057 if (stream->link->test_pattern_enabled) 1058 return; 1059 1060 /* get opp dpg blank color */ 1061 color_space_to_black_color(dc, color_space, &black_color); 1062 1063 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1064 odm_cnt++; 1065 1066 width = width / odm_cnt; 1067 1068 if (blank) { 1069 dc->hwss.set_abm_immediate_disable(pipe_ctx); 1070 1071 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { 1072 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; 1073 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; 1074 } 1075 } else { 1076 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; 1077 } 1078 1079 dc->hwss.set_disp_pattern_generator(dc, 1080 pipe_ctx, 1081 test_pattern, 1082 test_pattern_color_space, 1083 stream->timing.display_color_depth, 1084 &black_color, 1085 width, 1086 height, 1087 0); 1088 1089 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1090 dc->hwss.set_disp_pattern_generator(dc, 1091 odm_pipe, 1092 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ? 1093 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern, 1094 test_pattern_color_space, 1095 stream->timing.display_color_depth, 1096 &black_color, 1097 width, 1098 height, 1099 0); 1100 } 1101 1102 if (!blank && dc->debug.enable_single_display_2to1_odm_policy) { 1103 /* when exiting dynamic ODM need to reinit DPG state for unused pipes */ 1104 struct pipe_ctx *old_odm_pipe = dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx].next_odm_pipe; 1105 1106 odm_pipe = pipe_ctx->next_odm_pipe; 1107 1108 while (old_odm_pipe) { 1109 if (!odm_pipe || old_odm_pipe->pipe_idx != odm_pipe->pipe_idx) 1110 dc->hwss.set_disp_pattern_generator(dc, 1111 old_odm_pipe, 1112 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 1113 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 1114 COLOR_DEPTH_888, 1115 NULL, 1116 0, 1117 0, 1118 0); 1119 old_odm_pipe = old_odm_pipe->next_odm_pipe; 1120 if (odm_pipe) 1121 odm_pipe = odm_pipe->next_odm_pipe; 1122 } 1123 } 1124 1125 if (!blank) 1126 if (stream_res->abm) { 1127 dc->hwss.set_pipe(pipe_ctx); 1128 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level); 1129 } 1130 } 1131 1132 1133 static void dcn20_power_on_plane( 1134 struct dce_hwseq *hws, 1135 struct pipe_ctx *pipe_ctx) 1136 { 1137 DC_LOGGER_INIT(hws->ctx->logger); 1138 if (REG(DC_IP_REQUEST_CNTL)) { 1139 REG_SET(DC_IP_REQUEST_CNTL, 0, 1140 IP_REQUEST_EN, 1); 1141 1142 if (hws->funcs.dpp_pg_control) 1143 hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); 1144 1145 if (hws->funcs.hubp_pg_control) 1146 hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true); 1147 1148 REG_SET(DC_IP_REQUEST_CNTL, 0, 1149 IP_REQUEST_EN, 0); 1150 DC_LOG_DEBUG( 1151 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst); 1152 } 1153 } 1154 1155 static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx, 1156 struct dc_state *context) 1157 { 1158 //if (dc->debug.sanity_checks) { 1159 // dcn10_verify_allow_pstate_change_high(dc); 1160 //} 1161 dcn20_power_on_plane(dc->hwseq, pipe_ctx); 1162 1163 /* enable DCFCLK current DCHUB */ 1164 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); 1165 1166 /* initialize HUBP on power up */ 1167 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); 1168 1169 /* make sure OPP_PIPE_CLOCK_EN = 1 */ 1170 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 1171 pipe_ctx->stream_res.opp, 1172 true); 1173 1174 /* TODO: enable/disable in dm as per update type. 1175 if (plane_state) { 1176 DC_LOG_DC(dc->ctx->logger, 1177 "Pipe:%d 0x%x: addr hi:0x%x, " 1178 "addr low:0x%x, " 1179 "src: %d, %d, %d," 1180 " %d; dst: %d, %d, %d, %d;\n", 1181 pipe_ctx->pipe_idx, 1182 plane_state, 1183 plane_state->address.grph.addr.high_part, 1184 plane_state->address.grph.addr.low_part, 1185 plane_state->src_rect.x, 1186 plane_state->src_rect.y, 1187 plane_state->src_rect.width, 1188 plane_state->src_rect.height, 1189 plane_state->dst_rect.x, 1190 plane_state->dst_rect.y, 1191 plane_state->dst_rect.width, 1192 plane_state->dst_rect.height); 1193 1194 DC_LOG_DC(dc->ctx->logger, 1195 "Pipe %d: width, height, x, y format:%d\n" 1196 "viewport:%d, %d, %d, %d\n" 1197 "recout: %d, %d, %d, %d\n", 1198 pipe_ctx->pipe_idx, 1199 plane_state->format, 1200 pipe_ctx->plane_res.scl_data.viewport.width, 1201 pipe_ctx->plane_res.scl_data.viewport.height, 1202 pipe_ctx->plane_res.scl_data.viewport.x, 1203 pipe_ctx->plane_res.scl_data.viewport.y, 1204 pipe_ctx->plane_res.scl_data.recout.width, 1205 pipe_ctx->plane_res.scl_data.recout.height, 1206 pipe_ctx->plane_res.scl_data.recout.x, 1207 pipe_ctx->plane_res.scl_data.recout.y); 1208 print_rq_dlg_ttu(dc, pipe_ctx); 1209 } 1210 */ 1211 if (dc->vm_pa_config.valid) { 1212 struct vm_system_aperture_param apt; 1213 1214 apt.sys_default.quad_part = 0; 1215 1216 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr; 1217 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr; 1218 1219 // Program system aperture settings 1220 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); 1221 } 1222 1223 if (!pipe_ctx->top_pipe 1224 && pipe_ctx->plane_state 1225 && pipe_ctx->plane_state->flip_int_enabled 1226 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) 1227 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); 1228 1229 // if (dc->debug.sanity_checks) { 1230 // dcn10_verify_allow_pstate_change_high(dc); 1231 // } 1232 } 1233 1234 void dcn20_pipe_control_lock( 1235 struct dc *dc, 1236 struct pipe_ctx *pipe, 1237 bool lock) 1238 { 1239 struct pipe_ctx *temp_pipe; 1240 bool flip_immediate = false; 1241 1242 /* use TG master update lock to lock everything on the TG 1243 * therefore only top pipe need to lock 1244 */ 1245 if (!pipe || pipe->top_pipe) 1246 return; 1247 1248 if (pipe->plane_state != NULL) 1249 flip_immediate = pipe->plane_state->flip_immediate; 1250 1251 if (pipe->stream_res.gsl_group > 0) { 1252 temp_pipe = pipe->bottom_pipe; 1253 while (!flip_immediate && temp_pipe) { 1254 if (temp_pipe->plane_state != NULL) 1255 flip_immediate = temp_pipe->plane_state->flip_immediate; 1256 temp_pipe = temp_pipe->bottom_pipe; 1257 } 1258 } 1259 1260 if (flip_immediate && lock) { 1261 const int TIMEOUT_FOR_FLIP_PENDING = 100000; 1262 int i; 1263 1264 temp_pipe = pipe; 1265 while (temp_pipe) { 1266 if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) { 1267 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) { 1268 if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp)) 1269 break; 1270 udelay(1); 1271 } 1272 1273 /* no reason it should take this long for immediate flips */ 1274 ASSERT(i != TIMEOUT_FOR_FLIP_PENDING); 1275 } 1276 temp_pipe = temp_pipe->bottom_pipe; 1277 } 1278 } 1279 1280 /* In flip immediate and pipe splitting case, we need to use GSL 1281 * for synchronization. Only do setup on locking and on flip type change. 1282 */ 1283 if (lock && (pipe->bottom_pipe != NULL || !flip_immediate)) 1284 if ((flip_immediate && pipe->stream_res.gsl_group == 0) || 1285 (!flip_immediate && pipe->stream_res.gsl_group > 0)) 1286 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate); 1287 1288 if (pipe->plane_state != NULL) 1289 flip_immediate = pipe->plane_state->flip_immediate; 1290 1291 temp_pipe = pipe->bottom_pipe; 1292 while (flip_immediate && temp_pipe) { 1293 if (temp_pipe->plane_state != NULL) 1294 flip_immediate = temp_pipe->plane_state->flip_immediate; 1295 temp_pipe = temp_pipe->bottom_pipe; 1296 } 1297 1298 if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state && 1299 !flip_immediate) 1300 dcn20_setup_gsl_group_as_lock(dc, pipe, false); 1301 1302 if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) { 1303 union dmub_hw_lock_flags hw_locks = { 0 }; 1304 struct dmub_hw_lock_inst_flags inst_flags = { 0 }; 1305 1306 hw_locks.bits.lock_pipe = 1; 1307 inst_flags.otg_inst = pipe->stream_res.tg->inst; 1308 1309 if (pipe->plane_state != NULL) 1310 hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips; 1311 1312 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, 1313 lock, 1314 &hw_locks, 1315 &inst_flags); 1316 } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) { 1317 if (lock) 1318 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); 1319 else 1320 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); 1321 } else { 1322 if (lock) 1323 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1324 else 1325 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1326 } 1327 } 1328 1329 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe) 1330 { 1331 new_pipe->update_flags.raw = 0; 1332 1333 /* If non-phantom pipe is being transitioned to a phantom pipe, 1334 * set disable and return immediately. This is because the pipe 1335 * that was previously in use must be fully disabled before we 1336 * can "enable" it as a phantom pipe (since the OTG will certainly 1337 * be different). The post_unlock sequence will set the correct 1338 * update flags to enable the phantom pipe. 1339 */ 1340 if (old_pipe->plane_state && !old_pipe->plane_state->is_phantom && 1341 new_pipe->plane_state && new_pipe->plane_state->is_phantom) { 1342 new_pipe->update_flags.bits.disable = 1; 1343 return; 1344 } 1345 1346 /* Exit on unchanged, unused pipe */ 1347 if (!old_pipe->plane_state && !new_pipe->plane_state) 1348 return; 1349 /* Detect pipe enable/disable */ 1350 if (!old_pipe->plane_state && new_pipe->plane_state) { 1351 new_pipe->update_flags.bits.enable = 1; 1352 new_pipe->update_flags.bits.mpcc = 1; 1353 new_pipe->update_flags.bits.dppclk = 1; 1354 new_pipe->update_flags.bits.hubp_interdependent = 1; 1355 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1356 new_pipe->update_flags.bits.gamut_remap = 1; 1357 new_pipe->update_flags.bits.scaler = 1; 1358 new_pipe->update_flags.bits.viewport = 1; 1359 new_pipe->update_flags.bits.det_size = 1; 1360 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1361 new_pipe->update_flags.bits.odm = 1; 1362 new_pipe->update_flags.bits.global_sync = 1; 1363 } 1364 return; 1365 } 1366 1367 /* For SubVP we need to unconditionally enable because any phantom pipes are 1368 * always removed then newly added for every full updates whenever SubVP is in use. 1369 * The remove-add sequence of the phantom pipe always results in the pipe 1370 * being blanked in enable_stream_timing (DPG). 1371 */ 1372 if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) 1373 new_pipe->update_flags.bits.enable = 1; 1374 1375 /* Phantom pipes are effectively disabled, if the pipe was previously phantom 1376 * we have to enable 1377 */ 1378 if (old_pipe->plane_state && old_pipe->plane_state->is_phantom && 1379 new_pipe->plane_state && !new_pipe->plane_state->is_phantom) 1380 new_pipe->update_flags.bits.enable = 1; 1381 1382 if (old_pipe->plane_state && !new_pipe->plane_state) { 1383 new_pipe->update_flags.bits.disable = 1; 1384 return; 1385 } 1386 1387 /* Detect plane change */ 1388 if (old_pipe->plane_state != new_pipe->plane_state) { 1389 new_pipe->update_flags.bits.plane_changed = true; 1390 } 1391 1392 /* Detect top pipe only changes */ 1393 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1394 /* Detect odm changes */ 1395 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe 1396 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx) 1397 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe) 1398 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe) 1399 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1400 new_pipe->update_flags.bits.odm = 1; 1401 1402 /* Detect global sync changes */ 1403 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset 1404 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start 1405 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset 1406 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) 1407 new_pipe->update_flags.bits.global_sync = 1; 1408 } 1409 1410 if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb) 1411 new_pipe->update_flags.bits.det_size = 1; 1412 1413 /* 1414 * Detect opp / tg change, only set on change, not on enable 1415 * Assume mpcc inst = pipe index, if not this code needs to be updated 1416 * since mpcc is what is affected by these. In fact all of our sequence 1417 * makes this assumption at the moment with how hubp reset is matched to 1418 * same index mpcc reset. 1419 */ 1420 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1421 new_pipe->update_flags.bits.opp_changed = 1; 1422 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg) 1423 new_pipe->update_flags.bits.tg_changed = 1; 1424 1425 /* 1426 * Detect mpcc blending changes, only dpp inst and opp matter here, 1427 * mpccs getting removed/inserted update connected ones during their own 1428 * programming 1429 */ 1430 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp 1431 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1432 new_pipe->update_flags.bits.mpcc = 1; 1433 1434 /* Detect dppclk change */ 1435 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) 1436 new_pipe->update_flags.bits.dppclk = 1; 1437 1438 /* Check for scl update */ 1439 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data))) 1440 new_pipe->update_flags.bits.scaler = 1; 1441 /* Check for vp update */ 1442 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect)) 1443 || memcmp(&old_pipe->plane_res.scl_data.viewport_c, 1444 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect))) 1445 new_pipe->update_flags.bits.viewport = 1; 1446 1447 /* Detect dlg/ttu/rq updates */ 1448 { 1449 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs; 1450 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs; 1451 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs; 1452 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs; 1453 1454 /* Detect pipe interdependent updates */ 1455 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch || 1456 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch || 1457 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c || 1458 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank || 1459 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank || 1460 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip || 1461 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip || 1462 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l || 1463 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c || 1464 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l || 1465 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l || 1466 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c || 1467 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l || 1468 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c || 1469 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 || 1470 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 || 1471 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank || 1472 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) { 1473 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch; 1474 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch; 1475 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c; 1476 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank; 1477 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank; 1478 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip; 1479 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip; 1480 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l; 1481 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c; 1482 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l; 1483 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l; 1484 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c; 1485 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l; 1486 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c; 1487 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0; 1488 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1; 1489 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank; 1490 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip; 1491 new_pipe->update_flags.bits.hubp_interdependent = 1; 1492 } 1493 /* Detect any other updates to ttu/rq/dlg */ 1494 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) || 1495 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) || 1496 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs))) 1497 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1498 } 1499 } 1500 1501 static void dcn20_update_dchubp_dpp( 1502 struct dc *dc, 1503 struct pipe_ctx *pipe_ctx, 1504 struct dc_state *context) 1505 { 1506 struct dce_hwseq *hws = dc->hwseq; 1507 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1508 struct dpp *dpp = pipe_ctx->plane_res.dpp; 1509 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1510 struct dccg *dccg = dc->res_pool->dccg; 1511 bool viewport_changed = false; 1512 1513 if (pipe_ctx->update_flags.bits.dppclk) 1514 dpp->funcs->dpp_dppclk_control(dpp, false, true); 1515 1516 if (pipe_ctx->update_flags.bits.enable) 1517 dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz); 1518 1519 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG 1520 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. 1521 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG 1522 */ 1523 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) { 1524 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst); 1525 1526 hubp->funcs->hubp_setup( 1527 hubp, 1528 &pipe_ctx->dlg_regs, 1529 &pipe_ctx->ttu_regs, 1530 &pipe_ctx->rq_regs, 1531 &pipe_ctx->pipe_dlg_param); 1532 1533 if (hubp->funcs->set_unbounded_requesting) 1534 hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req); 1535 } 1536 if (pipe_ctx->update_flags.bits.hubp_interdependent) 1537 hubp->funcs->hubp_setup_interdependent( 1538 hubp, 1539 &pipe_ctx->dlg_regs, 1540 &pipe_ctx->ttu_regs); 1541 1542 if (pipe_ctx->update_flags.bits.enable || 1543 pipe_ctx->update_flags.bits.plane_changed || 1544 plane_state->update_flags.bits.bpp_change || 1545 plane_state->update_flags.bits.input_csc_change || 1546 plane_state->update_flags.bits.color_space_change || 1547 plane_state->update_flags.bits.coeff_reduction_change) { 1548 struct dc_bias_and_scale bns_params = {0}; 1549 1550 // program the input csc 1551 dpp->funcs->dpp_setup(dpp, 1552 plane_state->format, 1553 EXPANSION_MODE_ZERO, 1554 plane_state->input_csc_color_matrix, 1555 plane_state->color_space, 1556 NULL); 1557 1558 if (dpp->funcs->dpp_program_bias_and_scale) { 1559 //TODO :for CNVC set scale and bias registers if necessary 1560 build_prescale_params(&bns_params, plane_state); 1561 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); 1562 } 1563 } 1564 1565 if (pipe_ctx->update_flags.bits.mpcc 1566 || pipe_ctx->update_flags.bits.plane_changed 1567 || plane_state->update_flags.bits.global_alpha_change 1568 || plane_state->update_flags.bits.per_pixel_alpha_change) { 1569 // MPCC inst is equal to pipe index in practice 1570 int mpcc_inst = hubp->inst; 1571 int opp_inst; 1572 int opp_count = dc->res_pool->pipe_count; 1573 1574 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) { 1575 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) { 1576 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); 1577 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; 1578 break; 1579 } 1580 } 1581 hws->funcs.update_mpcc(dc, pipe_ctx); 1582 } 1583 1584 if (pipe_ctx->update_flags.bits.scaler || 1585 plane_state->update_flags.bits.scaling_change || 1586 plane_state->update_flags.bits.position_change || 1587 plane_state->update_flags.bits.per_pixel_alpha_change || 1588 pipe_ctx->stream->update_flags.bits.scaling) { 1589 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; 1590 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP); 1591 /* scaler configuration */ 1592 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( 1593 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); 1594 } 1595 1596 if (pipe_ctx->update_flags.bits.viewport || 1597 (context == dc->current_state && plane_state->update_flags.bits.position_change) || 1598 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) || 1599 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) { 1600 1601 hubp->funcs->mem_program_viewport( 1602 hubp, 1603 &pipe_ctx->plane_res.scl_data.viewport, 1604 &pipe_ctx->plane_res.scl_data.viewport_c); 1605 viewport_changed = true; 1606 } 1607 1608 /* Any updates are handled in dc interface, just need to apply existing for plane enable */ 1609 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || 1610 pipe_ctx->update_flags.bits.scaler || viewport_changed == true) && 1611 pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { 1612 dc->hwss.set_cursor_position(pipe_ctx); 1613 dc->hwss.set_cursor_attribute(pipe_ctx); 1614 1615 if (dc->hwss.set_cursor_sdr_white_level) 1616 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 1617 } 1618 1619 /* Any updates are handled in dc interface, just need 1620 * to apply existing for plane enable / opp change */ 1621 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed 1622 || pipe_ctx->update_flags.bits.plane_changed 1623 || pipe_ctx->stream->update_flags.bits.gamut_remap 1624 || pipe_ctx->stream->update_flags.bits.out_csc) { 1625 /* dpp/cm gamut remap*/ 1626 dc->hwss.program_gamut_remap(pipe_ctx); 1627 1628 /*call the dcn2 method which uses mpc csc*/ 1629 dc->hwss.program_output_csc(dc, 1630 pipe_ctx, 1631 pipe_ctx->stream->output_color_space, 1632 pipe_ctx->stream->csc_color_matrix.matrix, 1633 hubp->opp_id); 1634 } 1635 1636 if (pipe_ctx->update_flags.bits.enable || 1637 pipe_ctx->update_flags.bits.plane_changed || 1638 pipe_ctx->update_flags.bits.opp_changed || 1639 plane_state->update_flags.bits.pixel_format_change || 1640 plane_state->update_flags.bits.horizontal_mirror_change || 1641 plane_state->update_flags.bits.rotation_change || 1642 plane_state->update_flags.bits.swizzle_change || 1643 plane_state->update_flags.bits.dcc_change || 1644 plane_state->update_flags.bits.bpp_change || 1645 plane_state->update_flags.bits.scaling_change || 1646 plane_state->update_flags.bits.plane_size_change) { 1647 struct plane_size size = plane_state->plane_size; 1648 1649 size.surface_size = pipe_ctx->plane_res.scl_data.viewport; 1650 hubp->funcs->hubp_program_surface_config( 1651 hubp, 1652 plane_state->format, 1653 &plane_state->tiling_info, 1654 &size, 1655 plane_state->rotation, 1656 &plane_state->dcc, 1657 plane_state->horizontal_mirror, 1658 0); 1659 hubp->power_gated = false; 1660 } 1661 1662 if (pipe_ctx->update_flags.bits.enable || 1663 pipe_ctx->update_flags.bits.plane_changed || 1664 plane_state->update_flags.bits.addr_update) 1665 hws->funcs.update_plane_addr(dc, pipe_ctx); 1666 1667 if (pipe_ctx->update_flags.bits.enable) 1668 hubp->funcs->set_blank(hubp, false); 1669 /* If the stream paired with this plane is phantom, the plane is also phantom */ 1670 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM 1671 && hubp->funcs->phantom_hubp_post_enable) 1672 hubp->funcs->phantom_hubp_post_enable(hubp); 1673 } 1674 1675 static int calculate_vready_offset_for_group(struct pipe_ctx *pipe) 1676 { 1677 struct pipe_ctx *other_pipe; 1678 int vready_offset = pipe->pipe_dlg_param.vready_offset; 1679 1680 /* Always use the largest vready_offset of all connected pipes */ 1681 for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) { 1682 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1683 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1684 } 1685 for (other_pipe = pipe->top_pipe; other_pipe != NULL; other_pipe = other_pipe->top_pipe) { 1686 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1687 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1688 } 1689 for (other_pipe = pipe->next_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->next_odm_pipe) { 1690 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1691 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1692 } 1693 for (other_pipe = pipe->prev_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->prev_odm_pipe) { 1694 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1695 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1696 } 1697 1698 return vready_offset; 1699 } 1700 1701 static void dcn20_program_pipe( 1702 struct dc *dc, 1703 struct pipe_ctx *pipe_ctx, 1704 struct dc_state *context) 1705 { 1706 struct dce_hwseq *hws = dc->hwseq; 1707 /* Only need to unblank on top pipe */ 1708 1709 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level) 1710 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) 1711 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible); 1712 1713 /* Only update TG on top pipe */ 1714 if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe 1715 && !pipe_ctx->prev_odm_pipe) { 1716 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1717 pipe_ctx->stream_res.tg, 1718 calculate_vready_offset_for_group(pipe_ctx), 1719 pipe_ctx->pipe_dlg_param.vstartup_start, 1720 pipe_ctx->pipe_dlg_param.vupdate_offset, 1721 pipe_ctx->pipe_dlg_param.vupdate_width); 1722 1723 if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) 1724 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); 1725 1726 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1727 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true); 1728 1729 if (hws->funcs.setup_vupdate_interrupt) 1730 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1731 } 1732 1733 if (pipe_ctx->update_flags.bits.odm) 1734 hws->funcs.update_odm(dc, context, pipe_ctx); 1735 1736 if (pipe_ctx->update_flags.bits.enable) { 1737 dcn20_enable_plane(dc, pipe_ctx, context); 1738 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes) 1739 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub); 1740 } 1741 1742 if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size) 1743 dc->res_pool->hubbub->funcs->program_det_size( 1744 dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb); 1745 1746 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) 1747 dcn20_update_dchubp_dpp(dc, pipe_ctx, context); 1748 1749 if (pipe_ctx->update_flags.bits.enable 1750 || pipe_ctx->plane_state->update_flags.bits.hdr_mult) 1751 hws->funcs.set_hdr_multiplier(pipe_ctx); 1752 1753 if (pipe_ctx->update_flags.bits.enable || 1754 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 1755 pipe_ctx->plane_state->update_flags.bits.gamma_change) 1756 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 1757 1758 /* dcn10_translate_regamma_to_hw_format takes 750us to finish 1759 * only do gamma programming for powering on, internal memcmp to avoid 1760 * updating on slave planes 1761 */ 1762 if (pipe_ctx->update_flags.bits.enable || 1763 pipe_ctx->update_flags.bits.plane_changed || 1764 pipe_ctx->stream->update_flags.bits.out_tf || 1765 pipe_ctx->plane_state->update_flags.bits.output_tf_change) 1766 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 1767 1768 /* If the pipe has been enabled or has a different opp, we 1769 * should reprogram the fmt. This deals with cases where 1770 * interation between mpc and odm combine on different streams 1771 * causes a different pipe to be chosen to odm combine with. 1772 */ 1773 if (pipe_ctx->update_flags.bits.enable 1774 || pipe_ctx->update_flags.bits.opp_changed) { 1775 1776 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1777 pipe_ctx->stream_res.opp, 1778 COLOR_SPACE_YCBCR601, 1779 pipe_ctx->stream->timing.display_color_depth, 1780 pipe_ctx->stream->signal); 1781 1782 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1783 pipe_ctx->stream_res.opp, 1784 &pipe_ctx->stream->bit_depth_params, 1785 &pipe_ctx->stream->clamping); 1786 } 1787 1788 /* Set ABM pipe after other pipe configurations done */ 1789 if (pipe_ctx->plane_state->visible) { 1790 if (pipe_ctx->stream_res.abm) { 1791 dc->hwss.set_pipe(pipe_ctx); 1792 pipe_ctx->stream_res.abm->funcs->set_abm_level(pipe_ctx->stream_res.abm, 1793 pipe_ctx->stream->abm_level); 1794 } 1795 } 1796 } 1797 1798 void dcn20_program_front_end_for_ctx( 1799 struct dc *dc, 1800 struct dc_state *context) 1801 { 1802 int i; 1803 struct dce_hwseq *hws = dc->hwseq; 1804 DC_LOGGER_INIT(dc->ctx->logger); 1805 1806 /* Carry over GSL groups in case the context is changing. */ 1807 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1808 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1809 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 1810 1811 if (pipe_ctx->stream == old_pipe_ctx->stream) 1812 pipe_ctx->stream_res.gsl_group = old_pipe_ctx->stream_res.gsl_group; 1813 } 1814 1815 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) { 1816 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1817 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1818 1819 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) { 1820 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips); 1821 /*turn off triple buffer for full update*/ 1822 dc->hwss.program_triplebuffer( 1823 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); 1824 } 1825 } 1826 } 1827 1828 /* Set pipe update flags and lock pipes */ 1829 for (i = 0; i < dc->res_pool->pipe_count; i++) 1830 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i], 1831 &context->res_ctx.pipe_ctx[i]); 1832 1833 /* When disabling phantom pipes, turn on phantom OTG first (so we can get double 1834 * buffer updates properly) 1835 */ 1836 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1837 struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream; 1838 1839 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream && 1840 dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { 1841 struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg; 1842 1843 if (tg->funcs->enable_crtc) 1844 tg->funcs->enable_crtc(tg); 1845 } 1846 } 1847 /* OTG blank before disabling all front ends */ 1848 for (i = 0; i < dc->res_pool->pipe_count; i++) 1849 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1850 && !context->res_ctx.pipe_ctx[i].top_pipe 1851 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe 1852 && context->res_ctx.pipe_ctx[i].stream) 1853 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); 1854 1855 1856 /* Disconnect mpcc */ 1857 for (i = 0; i < dc->res_pool->pipe_count; i++) 1858 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1859 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) { 1860 struct hubbub *hubbub = dc->res_pool->hubbub; 1861 1862 /* Phantom pipe DET should be 0, but if a pipe in use is being transitioned to phantom 1863 * then we want to do the programming here (effectively it's being disabled). If we do 1864 * the programming later the DET won't be updated until the OTG for the phantom pipe is 1865 * turned on (i.e. in an MCLK switch) which can come in too late and cause issues with 1866 * DET allocation. 1867 */ 1868 if (hubbub->funcs->program_det_size && (context->res_ctx.pipe_ctx[i].update_flags.bits.disable || 1869 (context->res_ctx.pipe_ctx[i].plane_state && context->res_ctx.pipe_ctx[i].plane_state->is_phantom))) 1870 hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0); 1871 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1872 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); 1873 } 1874 1875 /* 1876 * Program all updated pipes, order matters for mpcc setup. Start with 1877 * top pipe and program all pipes that follow in order 1878 */ 1879 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1880 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1881 1882 if (pipe->plane_state && !pipe->top_pipe) { 1883 while (pipe) { 1884 if (hws->funcs.program_pipe) 1885 hws->funcs.program_pipe(dc, pipe, context); 1886 else { 1887 /* Don't program phantom pipes in the regular front end programming sequence. 1888 * There is an MPO transition case where a pipe being used by a video plane is 1889 * transitioned directly to be a phantom pipe when closing the MPO video. However 1890 * the phantom pipe will program a new HUBP_VTG_SEL (update takes place right away), 1891 * but the MPO still exists until the double buffered update of the main pipe so we 1892 * will get a frame of underflow if the phantom pipe is programmed here. 1893 */ 1894 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) 1895 dcn20_program_pipe(dc, pipe, context); 1896 } 1897 1898 pipe = pipe->bottom_pipe; 1899 } 1900 } 1901 /* Program secondary blending tree and writeback pipes */ 1902 pipe = &context->res_ctx.pipe_ctx[i]; 1903 if (!pipe->top_pipe && !pipe->prev_odm_pipe 1904 && pipe->stream && pipe->stream->num_wb_info > 0 1905 && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw) 1906 || pipe->stream->update_flags.raw) 1907 && hws->funcs.program_all_writeback_pipes_in_tree) 1908 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context); 1909 1910 /* Avoid underflow by check of pipe line read when adding 2nd plane. */ 1911 if (hws->wa.wait_hubpret_read_start_during_mpo_transition && 1912 !pipe->top_pipe && 1913 pipe->stream && 1914 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start && 1915 dc->current_state->stream_status[0].plane_count == 1 && 1916 context->stream_status[0].plane_count > 1) { 1917 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp); 1918 } 1919 1920 /* when dynamic ODM is active, pipes must be reconfigured when all planes are 1921 * disabled, as some transitions will leave software and hardware state 1922 * mismatched. 1923 */ 1924 if (dc->debug.enable_single_display_2to1_odm_policy && 1925 pipe->stream && 1926 pipe->update_flags.bits.disable && 1927 !pipe->prev_odm_pipe && 1928 hws->funcs.update_odm) 1929 hws->funcs.update_odm(dc, context, pipe); 1930 } 1931 } 1932 1933 void dcn20_post_unlock_program_front_end( 1934 struct dc *dc, 1935 struct dc_state *context) 1936 { 1937 int i; 1938 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100; 1939 struct dce_hwseq *hwseq = dc->hwseq; 1940 1941 DC_LOGGER_INIT(dc->ctx->logger); 1942 1943 for (i = 0; i < dc->res_pool->pipe_count; i++) 1944 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1945 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1946 1947 /* 1948 * If we are enabling a pipe, we need to wait for pending clear as this is a critical 1949 * part of the enable operation otherwise, DM may request an immediate flip which 1950 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which 1951 * is unsupported on DCN. 1952 */ 1953 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1954 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1955 // Don't check flip pending on phantom pipes 1956 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable && 1957 pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1958 struct hubp *hubp = pipe->plane_res.hubp; 1959 int j = 0; 1960 1961 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000 1962 && hubp->funcs->hubp_is_flip_pending(hubp); j++) 1963 udelay(1); 1964 } 1965 } 1966 1967 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1968 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1969 1970 if (pipe->plane_state && !pipe->top_pipe) { 1971 /* Program phantom pipe here to prevent a frame of underflow in the MPO transition 1972 * case (if a pipe being used for a video plane transitions to a phantom pipe, it 1973 * can underflow due to HUBP_VTG_SEL programming if done in the regular front end 1974 * programming sequence). 1975 */ 1976 while (pipe) { 1977 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1978 /* When turning on the phantom pipe we want to run through the 1979 * entire enable sequence, so apply all the "enable" flags. 1980 */ 1981 if (dc->hwss.apply_update_flags_for_phantom) 1982 dc->hwss.apply_update_flags_for_phantom(pipe); 1983 if (dc->hwss.update_phantom_vp_position) 1984 dc->hwss.update_phantom_vp_position(dc, context, pipe); 1985 dcn20_program_pipe(dc, pipe, context); 1986 } 1987 pipe = pipe->bottom_pipe; 1988 } 1989 } 1990 } 1991 1992 /* Only program the MALL registers after all the main and phantom pipes 1993 * are done programming. 1994 */ 1995 if (hwseq->funcs.program_mall_pipe_config) 1996 hwseq->funcs.program_mall_pipe_config(dc, context); 1997 1998 /* WA to apply WM setting*/ 1999 if (hwseq->wa.DEGVIDCN21) 2000 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub); 2001 2002 2003 /* WA for stutter underflow during MPO transitions when adding 2nd plane */ 2004 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) { 2005 2006 if (dc->current_state->stream_status[0].plane_count == 1 && 2007 context->stream_status[0].plane_count > 1) { 2008 2009 struct timing_generator *tg = dc->res_pool->timing_generators[0]; 2010 2011 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false); 2012 2013 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true; 2014 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg); 2015 } 2016 } 2017 } 2018 2019 void dcn20_prepare_bandwidth( 2020 struct dc *dc, 2021 struct dc_state *context) 2022 { 2023 struct hubbub *hubbub = dc->res_pool->hubbub; 2024 unsigned int compbuf_size_kb = 0; 2025 unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns; 2026 unsigned int i; 2027 2028 dc->clk_mgr->funcs->update_clocks( 2029 dc->clk_mgr, 2030 context, 2031 false); 2032 2033 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2034 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2035 2036 // At optimize don't restore the original watermark value 2037 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) { 2038 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; 2039 break; 2040 } 2041 } 2042 2043 /* program dchubbub watermarks: 2044 * For assigning wm_optimized_required, use |= operator since we don't want 2045 * to clear the value if the optimize has not happened yet 2046 */ 2047 dc->wm_optimized_required |= hubbub->funcs->program_watermarks(hubbub, 2048 &context->bw_ctx.bw.dcn.watermarks, 2049 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 2050 false); 2051 2052 // Restore the real watermark so we can commit the value to DMCUB 2053 // DMCUB uses the "original" watermark value in SubVP MCLK switch 2054 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a; 2055 2056 /* decrease compbuf size */ 2057 if (hubbub->funcs->program_compbuf_size) { 2058 if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes) { 2059 compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes; 2060 dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.dml.ip.min_comp_buffer_size_kbytes); 2061 } else { 2062 compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb; 2063 dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.bw.dcn.compbuf_size_kb); 2064 } 2065 2066 hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false); 2067 } 2068 } 2069 2070 void dcn20_optimize_bandwidth( 2071 struct dc *dc, 2072 struct dc_state *context) 2073 { 2074 struct hubbub *hubbub = dc->res_pool->hubbub; 2075 int i; 2076 2077 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2078 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2079 2080 // At optimize don't need to restore the original watermark value 2081 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) { 2082 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; 2083 break; 2084 } 2085 } 2086 2087 /* program dchubbub watermarks */ 2088 hubbub->funcs->program_watermarks(hubbub, 2089 &context->bw_ctx.bw.dcn.watermarks, 2090 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 2091 true); 2092 2093 if (dc->clk_mgr->dc_mode_softmax_enabled) 2094 if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && 2095 context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) 2096 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk); 2097 2098 /* increase compbuf size */ 2099 if (hubbub->funcs->program_compbuf_size) 2100 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true); 2101 2102 dc->clk_mgr->funcs->update_clocks( 2103 dc->clk_mgr, 2104 context, 2105 true); 2106 if (dc_extended_blank_supported(dc) && context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) { 2107 for (i = 0; i < dc->res_pool->pipe_count; ++i) { 2108 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2109 2110 if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank 2111 && pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max 2112 && pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total) 2113 pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp, 2114 pipe_ctx->dlg_regs.optimized_min_dst_y_next_start); 2115 } 2116 } 2117 } 2118 2119 bool dcn20_update_bandwidth( 2120 struct dc *dc, 2121 struct dc_state *context) 2122 { 2123 int i; 2124 struct dce_hwseq *hws = dc->hwseq; 2125 2126 /* recalculate DML parameters */ 2127 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) 2128 return false; 2129 2130 /* apply updated bandwidth parameters */ 2131 dc->hwss.prepare_bandwidth(dc, context); 2132 2133 /* update hubp configs for all pipes */ 2134 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2135 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2136 2137 if (pipe_ctx->plane_state == NULL) 2138 continue; 2139 2140 if (pipe_ctx->top_pipe == NULL) { 2141 bool blank = !is_pipe_tree_visible(pipe_ctx); 2142 2143 pipe_ctx->stream_res.tg->funcs->program_global_sync( 2144 pipe_ctx->stream_res.tg, 2145 calculate_vready_offset_for_group(pipe_ctx), 2146 pipe_ctx->pipe_dlg_param.vstartup_start, 2147 pipe_ctx->pipe_dlg_param.vupdate_offset, 2148 pipe_ctx->pipe_dlg_param.vupdate_width); 2149 2150 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 2151 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false); 2152 2153 if (pipe_ctx->prev_odm_pipe == NULL) 2154 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank); 2155 2156 if (hws->funcs.setup_vupdate_interrupt) 2157 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 2158 } 2159 2160 pipe_ctx->plane_res.hubp->funcs->hubp_setup( 2161 pipe_ctx->plane_res.hubp, 2162 &pipe_ctx->dlg_regs, 2163 &pipe_ctx->ttu_regs, 2164 &pipe_ctx->rq_regs, 2165 &pipe_ctx->pipe_dlg_param); 2166 } 2167 2168 return true; 2169 } 2170 2171 void dcn20_enable_writeback( 2172 struct dc *dc, 2173 struct dc_writeback_info *wb_info, 2174 struct dc_state *context) 2175 { 2176 struct dwbc *dwb; 2177 struct mcif_wb *mcif_wb; 2178 struct timing_generator *optc; 2179 2180 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 2181 ASSERT(wb_info->wb_enabled); 2182 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 2183 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 2184 2185 /* set the OPTC source mux */ 2186 optc = dc->res_pool->timing_generators[dwb->otg_inst]; 2187 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); 2188 /* set MCIF_WB buffer and arbitration configuration */ 2189 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 2190 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 2191 /* Enable MCIF_WB */ 2192 mcif_wb->funcs->enable_mcif(mcif_wb); 2193 /* Enable DWB */ 2194 dwb->funcs->enable(dwb, &wb_info->dwb_params); 2195 /* TODO: add sequence to enable/disable warmup */ 2196 } 2197 2198 void dcn20_disable_writeback( 2199 struct dc *dc, 2200 unsigned int dwb_pipe_inst) 2201 { 2202 struct dwbc *dwb; 2203 struct mcif_wb *mcif_wb; 2204 2205 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); 2206 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; 2207 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; 2208 2209 dwb->funcs->disable(dwb); 2210 mcif_wb->funcs->disable_mcif(mcif_wb); 2211 } 2212 2213 bool dcn20_wait_for_blank_complete( 2214 struct output_pixel_processor *opp) 2215 { 2216 int counter; 2217 2218 for (counter = 0; counter < 1000; counter++) { 2219 if (opp->funcs->dpg_is_blanked(opp)) 2220 break; 2221 2222 udelay(100); 2223 } 2224 2225 if (counter == 1000) { 2226 dm_error("DC: failed to blank crtc!\n"); 2227 return false; 2228 } 2229 2230 return true; 2231 } 2232 2233 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) 2234 { 2235 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2236 2237 if (!hubp) 2238 return false; 2239 return hubp->funcs->dmdata_status_done(hubp); 2240 } 2241 2242 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 2243 { 2244 struct dce_hwseq *hws = dc->hwseq; 2245 2246 if (pipe_ctx->stream_res.dsc) { 2247 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2248 2249 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); 2250 while (odm_pipe) { 2251 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true); 2252 odm_pipe = odm_pipe->next_odm_pipe; 2253 } 2254 } 2255 } 2256 2257 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 2258 { 2259 struct dce_hwseq *hws = dc->hwseq; 2260 2261 if (pipe_ctx->stream_res.dsc) { 2262 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2263 2264 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false); 2265 while (odm_pipe) { 2266 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false); 2267 odm_pipe = odm_pipe->next_odm_pipe; 2268 } 2269 } 2270 } 2271 2272 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) 2273 { 2274 struct dc_dmdata_attributes attr = { 0 }; 2275 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2276 2277 attr.dmdata_mode = DMDATA_HW_MODE; 2278 attr.dmdata_size = 2279 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; 2280 attr.address.quad_part = 2281 pipe_ctx->stream->dmdata_address.quad_part; 2282 attr.dmdata_dl_delta = 0; 2283 attr.dmdata_qos_mode = 0; 2284 attr.dmdata_qos_level = 0; 2285 attr.dmdata_repeat = 1; /* always repeat */ 2286 attr.dmdata_updated = 1; 2287 attr.dmdata_sw_data = NULL; 2288 2289 hubp->funcs->dmdata_set_attributes(hubp, &attr); 2290 } 2291 2292 void dcn20_init_vm_ctx( 2293 struct dce_hwseq *hws, 2294 struct dc *dc, 2295 struct dc_virtual_addr_space_config *va_config, 2296 int vmid) 2297 { 2298 struct dcn_hubbub_virt_addr_config config; 2299 2300 if (vmid == 0) { 2301 ASSERT(0); /* VMID cannot be 0 for vm context */ 2302 return; 2303 } 2304 2305 config.page_table_start_addr = va_config->page_table_start_addr; 2306 config.page_table_end_addr = va_config->page_table_end_addr; 2307 config.page_table_block_size = va_config->page_table_block_size_in_bytes; 2308 config.page_table_depth = va_config->page_table_depth; 2309 config.page_table_base_addr = va_config->page_table_base_addr; 2310 2311 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); 2312 } 2313 2314 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 2315 { 2316 struct dcn_hubbub_phys_addr_config config; 2317 2318 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 2319 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 2320 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 2321 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 2322 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 2323 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 2324 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 2325 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 2326 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 2327 config.page_table_default_page_addr = pa_config->page_table_default_page_addr; 2328 2329 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 2330 } 2331 2332 static bool patch_address_for_sbs_tb_stereo( 2333 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) 2334 { 2335 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2336 bool sec_split = pipe_ctx->top_pipe && 2337 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; 2338 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && 2339 (pipe_ctx->stream->timing.timing_3d_format == 2340 TIMING_3D_FORMAT_SIDE_BY_SIDE || 2341 pipe_ctx->stream->timing.timing_3d_format == 2342 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { 2343 *addr = plane_state->address.grph_stereo.left_addr; 2344 plane_state->address.grph_stereo.left_addr = 2345 plane_state->address.grph_stereo.right_addr; 2346 return true; 2347 } 2348 2349 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && 2350 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { 2351 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; 2352 plane_state->address.grph_stereo.right_addr = 2353 plane_state->address.grph_stereo.left_addr; 2354 plane_state->address.grph_stereo.right_meta_addr = 2355 plane_state->address.grph_stereo.left_meta_addr; 2356 } 2357 return false; 2358 } 2359 2360 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) 2361 { 2362 bool addr_patched = false; 2363 PHYSICAL_ADDRESS_LOC addr; 2364 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2365 2366 if (plane_state == NULL) 2367 return; 2368 2369 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); 2370 2371 // Call Helper to track VMID use 2372 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); 2373 2374 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( 2375 pipe_ctx->plane_res.hubp, 2376 &plane_state->address, 2377 plane_state->flip_immediate); 2378 2379 plane_state->status.requested_address = plane_state->address; 2380 2381 if (plane_state->flip_immediate) 2382 plane_state->status.current_address = plane_state->address; 2383 2384 if (addr_patched) 2385 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; 2386 } 2387 2388 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, 2389 struct dc_link_settings *link_settings) 2390 { 2391 struct encoder_unblank_param params = {0}; 2392 struct dc_stream_state *stream = pipe_ctx->stream; 2393 struct dc_link *link = stream->link; 2394 struct dce_hwseq *hws = link->dc->hwseq; 2395 struct pipe_ctx *odm_pipe; 2396 2397 params.opp_cnt = 1; 2398 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 2399 params.opp_cnt++; 2400 } 2401 /* only 3 items below are used by unblank */ 2402 params.timing = pipe_ctx->stream->timing; 2403 2404 params.link_settings.link_rate = link_settings->link_rate; 2405 2406 if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 2407 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 2408 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 2409 pipe_ctx->stream_res.hpo_dp_stream_enc, 2410 pipe_ctx->stream_res.tg->inst); 2411 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 2412 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1) 2413 params.timing.pix_clk_100hz /= 2; 2414 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 2415 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1); 2416 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 2417 } 2418 2419 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 2420 hws->funcs.edp_backlight_control(link, true); 2421 } 2422 } 2423 2424 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx) 2425 { 2426 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2427 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx); 2428 2429 if (start_line < 0) 2430 start_line = 0; 2431 2432 if (tg->funcs->setup_vertical_interrupt2) 2433 tg->funcs->setup_vertical_interrupt2(tg, start_line); 2434 } 2435 2436 static void dcn20_reset_back_end_for_pipe( 2437 struct dc *dc, 2438 struct pipe_ctx *pipe_ctx, 2439 struct dc_state *context) 2440 { 2441 int i; 2442 struct dc_link *link = pipe_ctx->stream->link; 2443 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2444 2445 DC_LOGGER_INIT(dc->ctx->logger); 2446 if (pipe_ctx->stream_res.stream_enc == NULL) { 2447 pipe_ctx->stream = NULL; 2448 return; 2449 } 2450 2451 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 2452 /* DPMS may already disable or */ 2453 /* dpms_off status is incorrect due to fastboot 2454 * feature. When system resume from S4 with second 2455 * screen only, the dpms_off would be true but 2456 * VBIOS lit up eDP, so check link status too. 2457 */ 2458 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 2459 dc->link_srv->set_dpms_off(pipe_ctx); 2460 else if (pipe_ctx->stream_res.audio) 2461 dc->hwss.disable_audio_stream(pipe_ctx); 2462 2463 /* free acquired resources */ 2464 if (pipe_ctx->stream_res.audio) { 2465 /*disable az_endpoint*/ 2466 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 2467 2468 /*free audio*/ 2469 if (dc->caps.dynamic_audio == true) { 2470 /*we have to dynamic arbitrate the audio endpoints*/ 2471 /*we free the resource, need reset is_audio_acquired*/ 2472 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 2473 pipe_ctx->stream_res.audio, false); 2474 pipe_ctx->stream_res.audio = NULL; 2475 } 2476 } 2477 } 2478 else if (pipe_ctx->stream_res.dsc) { 2479 dc->link_srv->set_dsc_enable(pipe_ctx, false); 2480 } 2481 2482 /* by upper caller loop, parent pipe: pipe0, will be reset last. 2483 * back end share by all pipes and will be disable only when disable 2484 * parent pipe. 2485 */ 2486 if (pipe_ctx->top_pipe == NULL) { 2487 2488 dc->hwss.set_abm_immediate_disable(pipe_ctx); 2489 2490 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 2491 2492 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 2493 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 2494 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 2495 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 2496 2497 if (pipe_ctx->stream_res.tg->funcs->set_drr) 2498 pipe_ctx->stream_res.tg->funcs->set_drr( 2499 pipe_ctx->stream_res.tg, NULL); 2500 /* TODO - convert symclk_ref_cnts for otg to a bit map to solve 2501 * the case where the same symclk is shared across multiple otg 2502 * instances 2503 */ 2504 link->phy_state.symclk_ref_cnts.otg = 0; 2505 if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) { 2506 link_hwss->disable_link_output(link, 2507 &pipe_ctx->link_res, pipe_ctx->stream->signal); 2508 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 2509 } 2510 } 2511 2512 for (i = 0; i < dc->res_pool->pipe_count; i++) 2513 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) 2514 break; 2515 2516 if (i == dc->res_pool->pipe_count) 2517 return; 2518 2519 pipe_ctx->stream = NULL; 2520 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 2521 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 2522 } 2523 2524 void dcn20_reset_hw_ctx_wrap( 2525 struct dc *dc, 2526 struct dc_state *context) 2527 { 2528 int i; 2529 struct dce_hwseq *hws = dc->hwseq; 2530 2531 /* Reset Back End*/ 2532 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 2533 struct pipe_ctx *pipe_ctx_old = 2534 &dc->current_state->res_ctx.pipe_ctx[i]; 2535 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2536 2537 if (!pipe_ctx_old->stream) 2538 continue; 2539 2540 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 2541 continue; 2542 2543 if (!pipe_ctx->stream || 2544 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 2545 struct clock_source *old_clk = pipe_ctx_old->clock_source; 2546 2547 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 2548 if (hws->funcs.enable_stream_gating) 2549 hws->funcs.enable_stream_gating(dc, pipe_ctx_old); 2550 if (old_clk) 2551 old_clk->funcs->cs_power_down(old_clk); 2552 } 2553 } 2554 } 2555 2556 void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id) 2557 { 2558 struct mpc *mpc = dc->res_pool->mpc; 2559 2560 // input to MPCC is always RGB, by default leave black_color at 0 2561 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) 2562 get_hdr_visual_confirm_color(pipe_ctx, color); 2563 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) 2564 get_surface_visual_confirm_color(pipe_ctx, color); 2565 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) 2566 get_mpctree_visual_confirm_color(pipe_ctx, color); 2567 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE) 2568 get_surface_tile_visual_confirm_color(pipe_ctx, color); 2569 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP) 2570 get_subvp_visual_confirm_color(dc, pipe_ctx, color); 2571 2572 if (mpc->funcs->set_bg_color) { 2573 memcpy(&pipe_ctx->plane_state->visual_confirm_color, color, sizeof(struct tg_color)); 2574 mpc->funcs->set_bg_color(mpc, color, mpcc_id); 2575 } 2576 } 2577 2578 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 2579 { 2580 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2581 struct mpcc_blnd_cfg blnd_cfg = {0}; 2582 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; 2583 int mpcc_id; 2584 struct mpcc *new_mpcc; 2585 struct mpc *mpc = dc->res_pool->mpc; 2586 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); 2587 2588 blnd_cfg.overlap_only = false; 2589 blnd_cfg.global_gain = 0xff; 2590 2591 if (per_pixel_alpha) { 2592 blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha; 2593 if (pipe_ctx->plane_state->global_alpha) { 2594 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; 2595 blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value; 2596 } else { 2597 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2598 } 2599 } else { 2600 blnd_cfg.pre_multiplied_alpha = false; 2601 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 2602 } 2603 2604 if (pipe_ctx->plane_state->global_alpha) 2605 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; 2606 else 2607 blnd_cfg.global_alpha = 0xff; 2608 2609 blnd_cfg.background_color_bpc = 4; 2610 blnd_cfg.bottom_gain_mode = 0; 2611 blnd_cfg.top_gain = 0x1f000; 2612 blnd_cfg.bottom_inside_gain = 0x1f000; 2613 blnd_cfg.bottom_outside_gain = 0x1f000; 2614 2615 if (pipe_ctx->plane_state->format 2616 == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA) 2617 blnd_cfg.pre_multiplied_alpha = false; 2618 2619 /* 2620 * TODO: remove hack 2621 * Note: currently there is a bug in init_hw such that 2622 * on resume from hibernate, BIOS sets up MPCC0, and 2623 * we do mpcc_remove but the mpcc cannot go to idle 2624 * after remove. This cause us to pick mpcc1 here, 2625 * which causes a pstate hang for yet unknown reason. 2626 */ 2627 mpcc_id = hubp->inst; 2628 2629 /* If there is no full update, don't need to touch MPC tree*/ 2630 if (!pipe_ctx->plane_state->update_flags.bits.full_update && 2631 !pipe_ctx->update_flags.bits.mpcc) { 2632 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); 2633 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); 2634 return; 2635 } 2636 2637 /* check if this MPCC is already being used */ 2638 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 2639 /* remove MPCC if being used */ 2640 if (new_mpcc != NULL) 2641 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); 2642 else 2643 if (dc->debug.sanity_checks) 2644 mpc->funcs->assert_mpcc_idle_before_connect( 2645 dc->res_pool->mpc, mpcc_id); 2646 2647 /* Call MPC to insert new plane */ 2648 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, 2649 mpc_tree_params, 2650 &blnd_cfg, 2651 NULL, 2652 NULL, 2653 hubp->inst, 2654 mpcc_id); 2655 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); 2656 2657 ASSERT(new_mpcc != NULL); 2658 hubp->opp_id = pipe_ctx->stream_res.opp->inst; 2659 hubp->mpcc_id = mpcc_id; 2660 } 2661 2662 static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link) 2663 { 2664 switch (link->link_enc->transmitter) { 2665 case TRANSMITTER_UNIPHY_A: 2666 return PHYD32CLKA; 2667 case TRANSMITTER_UNIPHY_B: 2668 return PHYD32CLKB; 2669 case TRANSMITTER_UNIPHY_C: 2670 return PHYD32CLKC; 2671 case TRANSMITTER_UNIPHY_D: 2672 return PHYD32CLKD; 2673 case TRANSMITTER_UNIPHY_E: 2674 return PHYD32CLKE; 2675 default: 2676 return PHYD32CLKA; 2677 } 2678 } 2679 2680 static int get_odm_segment_count(struct pipe_ctx *pipe_ctx) 2681 { 2682 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2683 int count = 1; 2684 2685 while (odm_pipe != NULL) { 2686 count++; 2687 odm_pipe = odm_pipe->next_odm_pipe; 2688 } 2689 2690 return count; 2691 } 2692 2693 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 2694 { 2695 enum dc_lane_count lane_count = 2696 pipe_ctx->stream->link->cur_link_settings.lane_count; 2697 2698 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 2699 struct dc_link *link = pipe_ctx->stream->link; 2700 2701 uint32_t active_total_with_borders; 2702 uint32_t early_control = 0; 2703 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2704 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2705 struct dc *dc = pipe_ctx->stream->ctx->dc; 2706 struct dtbclk_dto_params dto_params = {0}; 2707 struct dccg *dccg = dc->res_pool->dccg; 2708 enum phyd32clk_clock_source phyd32clk; 2709 int dp_hpo_inst; 2710 struct dce_hwseq *hws = dc->hwseq; 2711 unsigned int k1_div = PIXEL_RATE_DIV_NA; 2712 unsigned int k2_div = PIXEL_RATE_DIV_NA; 2713 2714 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 2715 if (dc->hwseq->funcs.setup_hpo_hw_control) 2716 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, true); 2717 } 2718 2719 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 2720 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; 2721 dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst); 2722 2723 phyd32clk = get_phyd32clk_src(link); 2724 dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); 2725 2726 dto_params.otg_inst = tg->inst; 2727 dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10; 2728 dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx); 2729 dto_params.timing = &pipe_ctx->stream->timing; 2730 dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); 2731 dccg->funcs->set_dtbclk_dto(dccg, &dto_params); 2732 } 2733 2734 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { 2735 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); 2736 2737 dc->res_pool->dccg->funcs->set_pixel_rate_div( 2738 dc->res_pool->dccg, 2739 pipe_ctx->stream_res.tg->inst, 2740 k1_div, k2_div); 2741 } 2742 2743 link_hwss->setup_stream_encoder(pipe_ctx); 2744 2745 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) { 2746 if (dc->hwss.program_dmdata_engine) 2747 dc->hwss.program_dmdata_engine(pipe_ctx); 2748 } 2749 2750 dc->hwss.update_info_frame(pipe_ctx); 2751 2752 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2753 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2754 2755 /* enable early control to avoid corruption on DP monitor*/ 2756 active_total_with_borders = 2757 timing->h_addressable 2758 + timing->h_border_left 2759 + timing->h_border_right; 2760 2761 if (lane_count != 0) 2762 early_control = active_total_with_borders % lane_count; 2763 2764 if (early_control == 0) 2765 early_control = lane_count; 2766 2767 tg->funcs->set_early_control(tg, early_control); 2768 2769 if (dc->hwseq->funcs.set_pixels_per_cycle) 2770 dc->hwseq->funcs.set_pixels_per_cycle(pipe_ctx); 2771 } 2772 2773 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx) 2774 { 2775 struct dc_stream_state *stream = pipe_ctx->stream; 2776 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2777 bool enable = false; 2778 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2779 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) 2780 ? dmdata_dp 2781 : dmdata_hdmi; 2782 2783 /* if using dynamic meta, don't set up generic infopackets */ 2784 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { 2785 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; 2786 enable = true; 2787 } 2788 2789 if (!hubp) 2790 return; 2791 2792 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) 2793 return; 2794 2795 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, 2796 hubp->inst, mode); 2797 } 2798 2799 void dcn20_fpga_init_hw(struct dc *dc) 2800 { 2801 int i, j; 2802 struct dce_hwseq *hws = dc->hwseq; 2803 struct resource_pool *res_pool = dc->res_pool; 2804 struct dc_state *context = dc->current_state; 2805 2806 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 2807 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 2808 2809 // Initialize the dccg 2810 if (res_pool->dccg->funcs->dccg_init) 2811 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 2812 2813 //Enable ability to power gate / don't force power on permanently 2814 hws->funcs.enable_power_gating_plane(hws, true); 2815 2816 // Specific to FPGA dccg and registers 2817 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); 2818 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 2819 2820 hws->funcs.dccg_init(hws); 2821 2822 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); 2823 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 2824 if (REG(REFCLK_CNTL)) 2825 REG_WRITE(REFCLK_CNTL, 0); 2826 // 2827 2828 2829 /* Blank pixel data with OPP DPG */ 2830 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2831 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2832 2833 if (tg->funcs->is_tg_enabled(tg)) 2834 dcn20_init_blank(dc, tg); 2835 } 2836 2837 for (i = 0; i < res_pool->timing_generator_count; i++) { 2838 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2839 2840 if (tg->funcs->is_tg_enabled(tg)) 2841 tg->funcs->lock(tg); 2842 } 2843 2844 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2845 struct dpp *dpp = res_pool->dpps[i]; 2846 2847 dpp->funcs->dpp_reset(dpp); 2848 } 2849 2850 /* Reset all MPCC muxes */ 2851 res_pool->mpc->funcs->mpc_init(res_pool->mpc); 2852 2853 /* initialize OPP mpc_tree parameter */ 2854 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 2855 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; 2856 res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2857 for (j = 0; j < MAX_PIPES; j++) 2858 res_pool->opps[i]->mpcc_disconnect_pending[j] = false; 2859 } 2860 2861 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2862 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2863 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2864 struct hubp *hubp = dc->res_pool->hubps[i]; 2865 struct dpp *dpp = dc->res_pool->dpps[i]; 2866 2867 pipe_ctx->stream_res.tg = tg; 2868 pipe_ctx->pipe_idx = i; 2869 2870 pipe_ctx->plane_res.hubp = hubp; 2871 pipe_ctx->plane_res.dpp = dpp; 2872 pipe_ctx->plane_res.mpcc_inst = dpp->inst; 2873 hubp->mpcc_id = dpp->inst; 2874 hubp->opp_id = OPP_ID_INVALID; 2875 hubp->power_gated = false; 2876 pipe_ctx->stream_res.opp = NULL; 2877 2878 hubp->funcs->hubp_init(hubp); 2879 2880 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; 2881 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2882 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; 2883 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; 2884 /*to do*/ 2885 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx); 2886 } 2887 2888 /* initialize DWB pointer to MCIF_WB */ 2889 for (i = 0; i < res_pool->res_cap->num_dwb; i++) 2890 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; 2891 2892 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2893 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2894 2895 if (tg->funcs->is_tg_enabled(tg)) 2896 tg->funcs->unlock(tg); 2897 } 2898 2899 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2900 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2901 2902 dc->hwss.disable_plane(dc, pipe_ctx); 2903 2904 pipe_ctx->stream_res.tg = NULL; 2905 pipe_ctx->plane_res.hubp = NULL; 2906 } 2907 2908 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2909 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2910 2911 tg->funcs->tg_init(tg); 2912 } 2913 2914 if (dc->res_pool->hubbub->funcs->init_crb) 2915 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 2916 } 2917 #ifndef TRIM_FSFT 2918 bool dcn20_optimize_timing_for_fsft(struct dc *dc, 2919 struct dc_crtc_timing *timing, 2920 unsigned int max_input_rate_in_khz) 2921 { 2922 unsigned int old_v_front_porch; 2923 unsigned int old_v_total; 2924 unsigned int max_input_rate_in_100hz; 2925 unsigned long long new_v_total; 2926 2927 max_input_rate_in_100hz = max_input_rate_in_khz * 10; 2928 if (max_input_rate_in_100hz < timing->pix_clk_100hz) 2929 return false; 2930 2931 old_v_total = timing->v_total; 2932 old_v_front_porch = timing->v_front_porch; 2933 2934 timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz; 2935 timing->pix_clk_100hz = max_input_rate_in_100hz; 2936 2937 new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz); 2938 2939 timing->v_total = new_v_total; 2940 timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total); 2941 return true; 2942 } 2943 #endif 2944 2945 void dcn20_set_disp_pattern_generator(const struct dc *dc, 2946 struct pipe_ctx *pipe_ctx, 2947 enum controller_dp_test_pattern test_pattern, 2948 enum controller_dp_color_space color_space, 2949 enum dc_color_depth color_depth, 2950 const struct tg_color *solid_color, 2951 int width, int height, int offset) 2952 { 2953 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern, 2954 color_space, color_depth, solid_color, width, height, offset); 2955 } 2956