1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include <linux/delay.h> 26 27 #include "dm_services.h" 28 #include "basics/dc_common.h" 29 #include "dm_helpers.h" 30 #include "core_types.h" 31 #include "resource.h" 32 #include "dcn20_resource.h" 33 #include "dcn20_hwseq.h" 34 #include "dce/dce_hwseq.h" 35 #include "dcn20_dsc.h" 36 #include "dcn20_optc.h" 37 #include "abm.h" 38 #include "clk_mgr.h" 39 #include "dmcu.h" 40 #include "hubp.h" 41 #include "timing_generator.h" 42 #include "opp.h" 43 #include "ipp.h" 44 #include "mpc.h" 45 #include "mcif_wb.h" 46 #include "dchubbub.h" 47 #include "reg_helper.h" 48 #include "dcn10/dcn10_cm_common.h" 49 #include "dc_link_dp.h" 50 #include "vm_helper.h" 51 #include "dccg.h" 52 53 #define DC_LOGGER_INIT(logger) 54 55 #define CTX \ 56 hws->ctx 57 #define REG(reg)\ 58 hws->regs->reg 59 60 #undef FN 61 #define FN(reg_name, field_name) \ 62 hws->shifts->field_name, hws->masks->field_name 63 64 static int find_free_gsl_group(const struct dc *dc) 65 { 66 if (dc->res_pool->gsl_groups.gsl_0 == 0) 67 return 1; 68 if (dc->res_pool->gsl_groups.gsl_1 == 0) 69 return 2; 70 if (dc->res_pool->gsl_groups.gsl_2 == 0) 71 return 3; 72 73 return 0; 74 } 75 76 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock) 77 * This is only used to lock pipes in pipe splitting case with immediate flip 78 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate, 79 * so we get tearing with freesync since we cannot flip multiple pipes 80 * atomically. 81 * We use GSL for this: 82 * - immediate flip: find first available GSL group if not already assigned 83 * program gsl with that group, set current OTG as master 84 * and always us 0x4 = AND of flip_ready from all pipes 85 * - vsync flip: disable GSL if used 86 * 87 * Groups in stream_res are stored as +1 from HW registers, i.e. 88 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1 89 * Using a magic value like -1 would require tracking all inits/resets 90 */ 91 static void dcn20_setup_gsl_group_as_lock( 92 const struct dc *dc, 93 struct pipe_ctx *pipe_ctx, 94 bool enable) 95 { 96 struct gsl_params gsl; 97 int group_idx; 98 99 memset(&gsl, 0, sizeof(struct gsl_params)); 100 101 if (enable) { 102 /* return if group already assigned since GSL was set up 103 * for vsync flip, we would unassign so it can't be "left over" 104 */ 105 if (pipe_ctx->stream_res.gsl_group > 0) 106 return; 107 108 group_idx = find_free_gsl_group(dc); 109 ASSERT(group_idx != 0); 110 pipe_ctx->stream_res.gsl_group = group_idx; 111 112 /* set gsl group reg field and mark resource used */ 113 switch (group_idx) { 114 case 1: 115 gsl.gsl0_en = 1; 116 dc->res_pool->gsl_groups.gsl_0 = 1; 117 break; 118 case 2: 119 gsl.gsl1_en = 1; 120 dc->res_pool->gsl_groups.gsl_1 = 1; 121 break; 122 case 3: 123 gsl.gsl2_en = 1; 124 dc->res_pool->gsl_groups.gsl_2 = 1; 125 break; 126 default: 127 BREAK_TO_DEBUGGER(); 128 return; // invalid case 129 } 130 gsl.gsl_master_en = 1; 131 } else { 132 group_idx = pipe_ctx->stream_res.gsl_group; 133 if (group_idx == 0) 134 return; // if not in use, just return 135 136 pipe_ctx->stream_res.gsl_group = 0; 137 138 /* unset gsl group reg field and mark resource free */ 139 switch (group_idx) { 140 case 1: 141 gsl.gsl0_en = 0; 142 dc->res_pool->gsl_groups.gsl_0 = 0; 143 break; 144 case 2: 145 gsl.gsl1_en = 0; 146 dc->res_pool->gsl_groups.gsl_1 = 0; 147 break; 148 case 3: 149 gsl.gsl2_en = 0; 150 dc->res_pool->gsl_groups.gsl_2 = 0; 151 break; 152 default: 153 BREAK_TO_DEBUGGER(); 154 return; 155 } 156 gsl.gsl_master_en = 0; 157 } 158 159 /* at this point we want to program whether it's to enable or disable */ 160 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && 161 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { 162 pipe_ctx->stream_res.tg->funcs->set_gsl( 163 pipe_ctx->stream_res.tg, 164 &gsl); 165 166 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( 167 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); 168 } else 169 BREAK_TO_DEBUGGER(); 170 } 171 172 void dcn20_set_flip_control_gsl( 173 struct pipe_ctx *pipe_ctx, 174 bool flip_immediate) 175 { 176 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) 177 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( 178 pipe_ctx->plane_res.hubp, flip_immediate); 179 180 } 181 182 void dcn20_enable_power_gating_plane( 183 struct dce_hwseq *hws, 184 bool enable) 185 { 186 bool force_on = 1; /* disable power gating */ 187 188 if (enable) 189 force_on = 0; 190 191 /* DCHUBP0/1/2/3/4/5 */ 192 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); 193 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); 194 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); 195 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); 196 if (REG(DOMAIN8_PG_CONFIG)) 197 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 198 if (REG(DOMAIN10_PG_CONFIG)) 199 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 200 201 /* DPP0/1/2/3/4/5 */ 202 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); 203 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); 204 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); 205 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); 206 if (REG(DOMAIN9_PG_CONFIG)) 207 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 208 if (REG(DOMAIN11_PG_CONFIG)) 209 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 210 211 /* DCS0/1/2/3/4/5 */ 212 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on); 213 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on); 214 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on); 215 if (REG(DOMAIN19_PG_CONFIG)) 216 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on); 217 if (REG(DOMAIN20_PG_CONFIG)) 218 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on); 219 if (REG(DOMAIN21_PG_CONFIG)) 220 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); 221 } 222 223 void dcn20_dccg_init(struct dce_hwseq *hws) 224 { 225 /* 226 * set MICROSECOND_TIME_BASE_DIV 227 * 100Mhz refclk -> 0x120264 228 * 27Mhz refclk -> 0x12021b 229 * 48Mhz refclk -> 0x120230 230 * 231 */ 232 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); 233 234 /* 235 * set MILLISECOND_TIME_BASE_DIV 236 * 100Mhz refclk -> 0x1186a0 237 * 27Mhz refclk -> 0x106978 238 * 48Mhz refclk -> 0x10bb80 239 * 240 */ 241 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); 242 243 /* This value is dependent on the hardware pipeline delay so set once per SOC */ 244 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c); 245 } 246 247 void dcn20_disable_vga( 248 struct dce_hwseq *hws) 249 { 250 REG_WRITE(D1VGA_CONTROL, 0); 251 REG_WRITE(D2VGA_CONTROL, 0); 252 REG_WRITE(D3VGA_CONTROL, 0); 253 REG_WRITE(D4VGA_CONTROL, 0); 254 REG_WRITE(D5VGA_CONTROL, 0); 255 REG_WRITE(D6VGA_CONTROL, 0); 256 } 257 258 void dcn20_program_triple_buffer( 259 const struct dc *dc, 260 struct pipe_ctx *pipe_ctx, 261 bool enable_triple_buffer) 262 { 263 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { 264 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( 265 pipe_ctx->plane_res.hubp, 266 enable_triple_buffer); 267 } 268 } 269 270 /* Blank pixel data during initialization */ 271 void dcn20_init_blank( 272 struct dc *dc, 273 struct timing_generator *tg) 274 { 275 enum dc_color_space color_space; 276 struct tg_color black_color = {0}; 277 struct output_pixel_processor *opp = NULL; 278 struct output_pixel_processor *bottom_opp = NULL; 279 uint32_t num_opps, opp_id_src0, opp_id_src1; 280 uint32_t otg_active_width, otg_active_height; 281 282 /* program opp dpg blank color */ 283 color_space = COLOR_SPACE_SRGB; 284 color_space_to_black_color(dc, color_space, &black_color); 285 286 /* get the OTG active size */ 287 tg->funcs->get_otg_active_size(tg, 288 &otg_active_width, 289 &otg_active_height); 290 291 /* get the OPTC source */ 292 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 293 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); 294 opp = dc->res_pool->opps[opp_id_src0]; 295 296 if (num_opps == 2) { 297 otg_active_width = otg_active_width / 2; 298 ASSERT(opp_id_src1 < dc->res_pool->res_cap->num_opp); 299 bottom_opp = dc->res_pool->opps[opp_id_src1]; 300 } 301 302 opp->funcs->opp_set_disp_pattern_generator( 303 opp, 304 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 305 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 306 COLOR_DEPTH_UNDEFINED, 307 &black_color, 308 otg_active_width, 309 otg_active_height); 310 311 if (num_opps == 2) { 312 bottom_opp->funcs->opp_set_disp_pattern_generator( 313 bottom_opp, 314 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 315 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 316 COLOR_DEPTH_UNDEFINED, 317 &black_color, 318 otg_active_width, 319 otg_active_height); 320 } 321 322 dc->hwss.wait_for_blank_complete(opp); 323 } 324 325 void dcn20_dsc_pg_control( 326 struct dce_hwseq *hws, 327 unsigned int dsc_inst, 328 bool power_on) 329 { 330 uint32_t power_gate = power_on ? 0 : 1; 331 uint32_t pwr_status = power_on ? 0 : 2; 332 uint32_t org_ip_request_cntl = 0; 333 334 if (hws->ctx->dc->debug.disable_dsc_power_gate) 335 return; 336 337 if (REG(DOMAIN16_PG_CONFIG) == 0) 338 return; 339 340 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 341 if (org_ip_request_cntl == 0) 342 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 343 344 switch (dsc_inst) { 345 case 0: /* DSC0 */ 346 REG_UPDATE(DOMAIN16_PG_CONFIG, 347 DOMAIN16_POWER_GATE, power_gate); 348 349 REG_WAIT(DOMAIN16_PG_STATUS, 350 DOMAIN16_PGFSM_PWR_STATUS, pwr_status, 351 1, 1000); 352 break; 353 case 1: /* DSC1 */ 354 REG_UPDATE(DOMAIN17_PG_CONFIG, 355 DOMAIN17_POWER_GATE, power_gate); 356 357 REG_WAIT(DOMAIN17_PG_STATUS, 358 DOMAIN17_PGFSM_PWR_STATUS, pwr_status, 359 1, 1000); 360 break; 361 case 2: /* DSC2 */ 362 REG_UPDATE(DOMAIN18_PG_CONFIG, 363 DOMAIN18_POWER_GATE, power_gate); 364 365 REG_WAIT(DOMAIN18_PG_STATUS, 366 DOMAIN18_PGFSM_PWR_STATUS, pwr_status, 367 1, 1000); 368 break; 369 case 3: /* DSC3 */ 370 REG_UPDATE(DOMAIN19_PG_CONFIG, 371 DOMAIN19_POWER_GATE, power_gate); 372 373 REG_WAIT(DOMAIN19_PG_STATUS, 374 DOMAIN19_PGFSM_PWR_STATUS, pwr_status, 375 1, 1000); 376 break; 377 case 4: /* DSC4 */ 378 REG_UPDATE(DOMAIN20_PG_CONFIG, 379 DOMAIN20_POWER_GATE, power_gate); 380 381 REG_WAIT(DOMAIN20_PG_STATUS, 382 DOMAIN20_PGFSM_PWR_STATUS, pwr_status, 383 1, 1000); 384 break; 385 case 5: /* DSC5 */ 386 REG_UPDATE(DOMAIN21_PG_CONFIG, 387 DOMAIN21_POWER_GATE, power_gate); 388 389 REG_WAIT(DOMAIN21_PG_STATUS, 390 DOMAIN21_PGFSM_PWR_STATUS, pwr_status, 391 1, 1000); 392 break; 393 default: 394 BREAK_TO_DEBUGGER(); 395 break; 396 } 397 398 if (org_ip_request_cntl == 0) 399 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 400 } 401 402 void dcn20_dpp_pg_control( 403 struct dce_hwseq *hws, 404 unsigned int dpp_inst, 405 bool power_on) 406 { 407 uint32_t power_gate = power_on ? 0 : 1; 408 uint32_t pwr_status = power_on ? 0 : 2; 409 410 if (hws->ctx->dc->debug.disable_dpp_power_gate) 411 return; 412 if (REG(DOMAIN1_PG_CONFIG) == 0) 413 return; 414 415 switch (dpp_inst) { 416 case 0: /* DPP0 */ 417 REG_UPDATE(DOMAIN1_PG_CONFIG, 418 DOMAIN1_POWER_GATE, power_gate); 419 420 REG_WAIT(DOMAIN1_PG_STATUS, 421 DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 422 1, 1000); 423 break; 424 case 1: /* DPP1 */ 425 REG_UPDATE(DOMAIN3_PG_CONFIG, 426 DOMAIN3_POWER_GATE, power_gate); 427 428 REG_WAIT(DOMAIN3_PG_STATUS, 429 DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 430 1, 1000); 431 break; 432 case 2: /* DPP2 */ 433 REG_UPDATE(DOMAIN5_PG_CONFIG, 434 DOMAIN5_POWER_GATE, power_gate); 435 436 REG_WAIT(DOMAIN5_PG_STATUS, 437 DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 438 1, 1000); 439 break; 440 case 3: /* DPP3 */ 441 REG_UPDATE(DOMAIN7_PG_CONFIG, 442 DOMAIN7_POWER_GATE, power_gate); 443 444 REG_WAIT(DOMAIN7_PG_STATUS, 445 DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 446 1, 1000); 447 break; 448 case 4: /* DPP4 */ 449 REG_UPDATE(DOMAIN9_PG_CONFIG, 450 DOMAIN9_POWER_GATE, power_gate); 451 452 REG_WAIT(DOMAIN9_PG_STATUS, 453 DOMAIN9_PGFSM_PWR_STATUS, pwr_status, 454 1, 1000); 455 break; 456 case 5: /* DPP5 */ 457 /* 458 * Do not power gate DPP5, should be left at HW default, power on permanently. 459 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 460 * reset. 461 * REG_UPDATE(DOMAIN11_PG_CONFIG, 462 * DOMAIN11_POWER_GATE, power_gate); 463 * 464 * REG_WAIT(DOMAIN11_PG_STATUS, 465 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, 466 * 1, 1000); 467 */ 468 break; 469 default: 470 BREAK_TO_DEBUGGER(); 471 break; 472 } 473 } 474 475 476 void dcn20_hubp_pg_control( 477 struct dce_hwseq *hws, 478 unsigned int hubp_inst, 479 bool power_on) 480 { 481 uint32_t power_gate = power_on ? 0 : 1; 482 uint32_t pwr_status = power_on ? 0 : 2; 483 484 if (hws->ctx->dc->debug.disable_hubp_power_gate) 485 return; 486 if (REG(DOMAIN0_PG_CONFIG) == 0) 487 return; 488 489 switch (hubp_inst) { 490 case 0: /* DCHUBP0 */ 491 REG_UPDATE(DOMAIN0_PG_CONFIG, 492 DOMAIN0_POWER_GATE, power_gate); 493 494 REG_WAIT(DOMAIN0_PG_STATUS, 495 DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 496 1, 1000); 497 break; 498 case 1: /* DCHUBP1 */ 499 REG_UPDATE(DOMAIN2_PG_CONFIG, 500 DOMAIN2_POWER_GATE, power_gate); 501 502 REG_WAIT(DOMAIN2_PG_STATUS, 503 DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 504 1, 1000); 505 break; 506 case 2: /* DCHUBP2 */ 507 REG_UPDATE(DOMAIN4_PG_CONFIG, 508 DOMAIN4_POWER_GATE, power_gate); 509 510 REG_WAIT(DOMAIN4_PG_STATUS, 511 DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 512 1, 1000); 513 break; 514 case 3: /* DCHUBP3 */ 515 REG_UPDATE(DOMAIN6_PG_CONFIG, 516 DOMAIN6_POWER_GATE, power_gate); 517 518 REG_WAIT(DOMAIN6_PG_STATUS, 519 DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 520 1, 1000); 521 break; 522 case 4: /* DCHUBP4 */ 523 REG_UPDATE(DOMAIN8_PG_CONFIG, 524 DOMAIN8_POWER_GATE, power_gate); 525 526 REG_WAIT(DOMAIN8_PG_STATUS, 527 DOMAIN8_PGFSM_PWR_STATUS, pwr_status, 528 1, 1000); 529 break; 530 case 5: /* DCHUBP5 */ 531 /* 532 * Do not power gate DCHUB5, should be left at HW default, power on permanently. 533 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 534 * reset. 535 * REG_UPDATE(DOMAIN10_PG_CONFIG, 536 * DOMAIN10_POWER_GATE, power_gate); 537 * 538 * REG_WAIT(DOMAIN10_PG_STATUS, 539 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status, 540 * 1, 1000); 541 */ 542 break; 543 default: 544 BREAK_TO_DEBUGGER(); 545 break; 546 } 547 } 548 549 550 /* disable HW used by plane. 551 * note: cannot disable until disconnect is complete 552 */ 553 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 554 { 555 struct hubp *hubp = pipe_ctx->plane_res.hubp; 556 struct dpp *dpp = pipe_ctx->plane_res.dpp; 557 558 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); 559 560 /* In flip immediate with pipe splitting case GSL is used for 561 * synchronization so we must disable it when the plane is disabled. 562 */ 563 if (pipe_ctx->stream_res.gsl_group != 0) 564 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false); 565 566 dc->hwss.set_flip_control_gsl(pipe_ctx, false); 567 568 hubp->funcs->hubp_clk_cntl(hubp, false); 569 570 dpp->funcs->dpp_dppclk_control(dpp, false, false); 571 572 hubp->power_gated = true; 573 dc->optimized_required = false; /* We're powering off, no need to optimize */ 574 575 dc->hwss.plane_atomic_power_down(dc, 576 pipe_ctx->plane_res.dpp, 577 pipe_ctx->plane_res.hubp); 578 579 pipe_ctx->stream = NULL; 580 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); 581 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); 582 pipe_ctx->top_pipe = NULL; 583 pipe_ctx->bottom_pipe = NULL; 584 pipe_ctx->plane_state = NULL; 585 } 586 587 588 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) 589 { 590 DC_LOGGER_INIT(dc->ctx->logger); 591 592 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) 593 return; 594 595 dcn20_plane_atomic_disable(dc, pipe_ctx); 596 597 DC_LOG_DC("Power down front end %d\n", 598 pipe_ctx->pipe_idx); 599 } 600 601 enum dc_status dcn20_enable_stream_timing( 602 struct pipe_ctx *pipe_ctx, 603 struct dc_state *context, 604 struct dc *dc) 605 { 606 struct dc_stream_state *stream = pipe_ctx->stream; 607 struct drr_params params = {0}; 608 unsigned int event_triggers = 0; 609 struct pipe_ctx *odm_pipe; 610 int opp_cnt = 1; 611 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 612 613 /* by upper caller loop, pipe0 is parent pipe and be called first. 614 * back end is set up by for pipe0. Other children pipe share back end 615 * with pipe 0. No program is needed. 616 */ 617 if (pipe_ctx->top_pipe != NULL) 618 return DC_OK; 619 620 /* TODO check if timing_changed, disable stream if timing changed */ 621 622 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 623 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 624 opp_cnt++; 625 } 626 627 if (opp_cnt > 1) 628 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 629 pipe_ctx->stream_res.tg, 630 opp_inst, opp_cnt, 631 &pipe_ctx->stream->timing); 632 633 /* HW program guide assume display already disable 634 * by unplug sequence. OTG assume stop. 635 */ 636 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); 637 638 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 639 pipe_ctx->clock_source, 640 &pipe_ctx->stream_res.pix_clk_params, 641 &pipe_ctx->pll_settings)) { 642 BREAK_TO_DEBUGGER(); 643 return DC_ERROR_UNEXPECTED; 644 } 645 646 pipe_ctx->stream_res.tg->funcs->program_timing( 647 pipe_ctx->stream_res.tg, 648 &stream->timing, 649 pipe_ctx->pipe_dlg_param.vready_offset, 650 pipe_ctx->pipe_dlg_param.vstartup_start, 651 pipe_ctx->pipe_dlg_param.vupdate_offset, 652 pipe_ctx->pipe_dlg_param.vupdate_width, 653 pipe_ctx->stream->signal, 654 true); 655 656 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 657 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 658 odm_pipe->stream_res.opp, 659 true); 660 661 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 662 pipe_ctx->stream_res.opp, 663 true); 664 665 dc->hwss.blank_pixel_data(dc, pipe_ctx, true); 666 667 /* VTG is within DCHUB command block. DCFCLK is always on */ 668 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { 669 BREAK_TO_DEBUGGER(); 670 return DC_ERROR_UNEXPECTED; 671 } 672 673 dc->hwss.wait_for_blank_complete(pipe_ctx->stream_res.opp); 674 675 params.vertical_total_min = stream->adjust.v_total_min; 676 params.vertical_total_max = stream->adjust.v_total_max; 677 params.vertical_total_mid = stream->adjust.v_total_mid; 678 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num; 679 if (pipe_ctx->stream_res.tg->funcs->set_drr) 680 pipe_ctx->stream_res.tg->funcs->set_drr( 681 pipe_ctx->stream_res.tg, ¶ms); 682 683 // DRR should set trigger event to monitor surface update event 684 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 685 event_triggers = 0x80; 686 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 687 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 688 pipe_ctx->stream_res.tg, event_triggers); 689 690 /* TODO program crtc source select for non-virtual signal*/ 691 /* TODO program FMT */ 692 /* TODO setup link_enc */ 693 /* TODO set stream attributes */ 694 /* TODO program audio */ 695 /* TODO enable stream if timing changed */ 696 /* TODO unblank stream if DP */ 697 698 return DC_OK; 699 } 700 701 void dcn20_program_output_csc(struct dc *dc, 702 struct pipe_ctx *pipe_ctx, 703 enum dc_color_space colorspace, 704 uint16_t *matrix, 705 int opp_id) 706 { 707 struct mpc *mpc = dc->res_pool->mpc; 708 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; 709 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 710 711 if (mpc->funcs->power_on_mpc_mem_pwr) 712 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 713 714 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 715 if (mpc->funcs->set_output_csc != NULL) 716 mpc->funcs->set_output_csc(mpc, 717 opp_id, 718 matrix, 719 ocsc_mode); 720 } else { 721 if (mpc->funcs->set_ocsc_default != NULL) 722 mpc->funcs->set_ocsc_default(mpc, 723 opp_id, 724 colorspace, 725 ocsc_mode); 726 } 727 } 728 729 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 730 const struct dc_stream_state *stream) 731 { 732 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 733 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 734 struct pwl_params *params = NULL; 735 /* 736 * program OGAM only for the top pipe 737 * if there is a pipe split then fix diagnostic is required: 738 * how to pass OGAM parameter for stream. 739 * if programming for all pipes is required then remove condition 740 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic. 741 */ 742 if (mpc->funcs->power_on_mpc_mem_pwr) 743 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 744 if (pipe_ctx->top_pipe == NULL 745 && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 746 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 747 params = &stream->out_transfer_func->pwl; 748 else if (pipe_ctx->stream->out_transfer_func->type == 749 TF_TYPE_DISTRIBUTED_POINTS && 750 cm_helper_translate_curve_to_hw_format( 751 stream->out_transfer_func, 752 &mpc->blender_params, false)) 753 params = &mpc->blender_params; 754 /* 755 * there is no ROM 756 */ 757 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 758 BREAK_TO_DEBUGGER(); 759 } 760 /* 761 * if above if is not executed then 'params' equal to 0 and set in bypass 762 */ 763 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 764 765 return true; 766 } 767 768 bool dcn20_set_blend_lut( 769 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 770 { 771 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 772 bool result = true; 773 struct pwl_params *blend_lut = NULL; 774 775 if (plane_state->blend_tf) { 776 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 777 blend_lut = &plane_state->blend_tf->pwl; 778 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 779 cm_helper_translate_curve_to_hw_format( 780 plane_state->blend_tf, 781 &dpp_base->regamma_params, false); 782 blend_lut = &dpp_base->regamma_params; 783 } 784 } 785 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); 786 787 return result; 788 } 789 790 bool dcn20_set_shaper_3dlut( 791 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 792 { 793 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 794 bool result = true; 795 struct pwl_params *shaper_lut = NULL; 796 797 if (plane_state->in_shaper_func) { 798 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 799 shaper_lut = &plane_state->in_shaper_func->pwl; 800 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 801 cm_helper_translate_curve_to_hw_format( 802 plane_state->in_shaper_func, 803 &dpp_base->shaper_params, true); 804 shaper_lut = &dpp_base->shaper_params; 805 } 806 } 807 808 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); 809 if (plane_state->lut3d_func && 810 plane_state->lut3d_func->state.bits.initialized == 1) 811 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, 812 &plane_state->lut3d_func->lut_3d); 813 else 814 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); 815 816 return result; 817 } 818 819 bool dcn20_set_input_transfer_func(struct dc *dc, 820 struct pipe_ctx *pipe_ctx, 821 const struct dc_plane_state *plane_state) 822 { 823 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 824 const struct dc_transfer_func *tf = NULL; 825 bool result = true; 826 bool use_degamma_ram = false; 827 828 if (dpp_base == NULL || plane_state == NULL) 829 return false; 830 831 dc->hwss.set_shaper_3dlut(pipe_ctx, plane_state); 832 dc->hwss.set_blend_lut(pipe_ctx, plane_state); 833 834 if (plane_state->in_transfer_func) 835 tf = plane_state->in_transfer_func; 836 837 838 if (tf == NULL) { 839 dpp_base->funcs->dpp_set_degamma(dpp_base, 840 IPP_DEGAMMA_MODE_BYPASS); 841 return true; 842 } 843 844 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS) 845 use_degamma_ram = true; 846 847 if (use_degamma_ram == true) { 848 if (tf->type == TF_TYPE_HWPWL) 849 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 850 &tf->pwl); 851 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 852 cm_helper_translate_curve_to_degamma_hw_format(tf, 853 &dpp_base->degamma_params); 854 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 855 &dpp_base->degamma_params); 856 } 857 return true; 858 } 859 /* handle here the optimized cases when de-gamma ROM could be used. 860 * 861 */ 862 if (tf->type == TF_TYPE_PREDEFINED) { 863 switch (tf->tf) { 864 case TRANSFER_FUNCTION_SRGB: 865 dpp_base->funcs->dpp_set_degamma(dpp_base, 866 IPP_DEGAMMA_MODE_HW_sRGB); 867 break; 868 case TRANSFER_FUNCTION_BT709: 869 dpp_base->funcs->dpp_set_degamma(dpp_base, 870 IPP_DEGAMMA_MODE_HW_xvYCC); 871 break; 872 case TRANSFER_FUNCTION_LINEAR: 873 dpp_base->funcs->dpp_set_degamma(dpp_base, 874 IPP_DEGAMMA_MODE_BYPASS); 875 break; 876 case TRANSFER_FUNCTION_PQ: 877 default: 878 result = false; 879 break; 880 } 881 } else if (tf->type == TF_TYPE_BYPASS) 882 dpp_base->funcs->dpp_set_degamma(dpp_base, 883 IPP_DEGAMMA_MODE_BYPASS); 884 else { 885 /* 886 * if we are here, we did not handle correctly. 887 * fix is required for this use case 888 */ 889 BREAK_TO_DEBUGGER(); 890 dpp_base->funcs->dpp_set_degamma(dpp_base, 891 IPP_DEGAMMA_MODE_BYPASS); 892 } 893 894 return result; 895 } 896 897 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 898 { 899 struct pipe_ctx *odm_pipe; 900 int opp_cnt = 1; 901 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 902 903 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 904 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 905 opp_cnt++; 906 } 907 908 if (opp_cnt > 1) 909 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 910 pipe_ctx->stream_res.tg, 911 opp_inst, opp_cnt, 912 &pipe_ctx->stream->timing); 913 else 914 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 915 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 916 } 917 918 void dcn20_blank_pixel_data( 919 struct dc *dc, 920 struct pipe_ctx *pipe_ctx, 921 bool blank) 922 { 923 struct tg_color black_color = {0}; 924 struct stream_resource *stream_res = &pipe_ctx->stream_res; 925 struct dc_stream_state *stream = pipe_ctx->stream; 926 enum dc_color_space color_space = stream->output_color_space; 927 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; 928 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; 929 struct pipe_ctx *odm_pipe; 930 int odm_cnt = 1; 931 932 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 933 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; 934 935 /* get opp dpg blank color */ 936 color_space_to_black_color(dc, color_space, &black_color); 937 938 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 939 odm_cnt++; 940 941 width = width / odm_cnt; 942 943 if (blank) { 944 if (stream_res->abm) 945 stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm); 946 947 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { 948 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; 949 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; 950 } 951 } else { 952 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; 953 } 954 955 stream_res->opp->funcs->opp_set_disp_pattern_generator( 956 stream_res->opp, 957 test_pattern, 958 test_pattern_color_space, 959 stream->timing.display_color_depth, 960 &black_color, 961 width, 962 height); 963 964 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 965 odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator( 966 odm_pipe->stream_res.opp, 967 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ? 968 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern, 969 test_pattern_color_space, 970 stream->timing.display_color_depth, 971 &black_color, 972 width, 973 height); 974 } 975 976 if (!blank) 977 if (stream_res->abm) { 978 stream_res->abm->funcs->set_pipe(stream_res->abm, stream_res->tg->inst + 1); 979 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level); 980 } 981 } 982 983 984 static void dcn20_power_on_plane( 985 struct dce_hwseq *hws, 986 struct pipe_ctx *pipe_ctx) 987 { 988 DC_LOGGER_INIT(hws->ctx->logger); 989 if (REG(DC_IP_REQUEST_CNTL)) { 990 REG_SET(DC_IP_REQUEST_CNTL, 0, 991 IP_REQUEST_EN, 1); 992 dcn20_dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); 993 dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true); 994 REG_SET(DC_IP_REQUEST_CNTL, 0, 995 IP_REQUEST_EN, 0); 996 DC_LOG_DEBUG( 997 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst); 998 } 999 } 1000 1001 void dcn20_enable_plane( 1002 struct dc *dc, 1003 struct pipe_ctx *pipe_ctx, 1004 struct dc_state *context) 1005 { 1006 //if (dc->debug.sanity_checks) { 1007 // dcn10_verify_allow_pstate_change_high(dc); 1008 //} 1009 dcn20_power_on_plane(dc->hwseq, pipe_ctx); 1010 1011 /* enable DCFCLK current DCHUB */ 1012 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); 1013 1014 /* initialize HUBP on power up */ 1015 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); 1016 1017 /* make sure OPP_PIPE_CLOCK_EN = 1 */ 1018 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 1019 pipe_ctx->stream_res.opp, 1020 true); 1021 1022 /* TODO: enable/disable in dm as per update type. 1023 if (plane_state) { 1024 DC_LOG_DC(dc->ctx->logger, 1025 "Pipe:%d 0x%x: addr hi:0x%x, " 1026 "addr low:0x%x, " 1027 "src: %d, %d, %d," 1028 " %d; dst: %d, %d, %d, %d;\n", 1029 pipe_ctx->pipe_idx, 1030 plane_state, 1031 plane_state->address.grph.addr.high_part, 1032 plane_state->address.grph.addr.low_part, 1033 plane_state->src_rect.x, 1034 plane_state->src_rect.y, 1035 plane_state->src_rect.width, 1036 plane_state->src_rect.height, 1037 plane_state->dst_rect.x, 1038 plane_state->dst_rect.y, 1039 plane_state->dst_rect.width, 1040 plane_state->dst_rect.height); 1041 1042 DC_LOG_DC(dc->ctx->logger, 1043 "Pipe %d: width, height, x, y format:%d\n" 1044 "viewport:%d, %d, %d, %d\n" 1045 "recout: %d, %d, %d, %d\n", 1046 pipe_ctx->pipe_idx, 1047 plane_state->format, 1048 pipe_ctx->plane_res.scl_data.viewport.width, 1049 pipe_ctx->plane_res.scl_data.viewport.height, 1050 pipe_ctx->plane_res.scl_data.viewport.x, 1051 pipe_ctx->plane_res.scl_data.viewport.y, 1052 pipe_ctx->plane_res.scl_data.recout.width, 1053 pipe_ctx->plane_res.scl_data.recout.height, 1054 pipe_ctx->plane_res.scl_data.recout.x, 1055 pipe_ctx->plane_res.scl_data.recout.y); 1056 print_rq_dlg_ttu(dc, pipe_ctx); 1057 } 1058 */ 1059 if (dc->vm_pa_config.valid) { 1060 struct vm_system_aperture_param apt; 1061 1062 apt.sys_default.quad_part = 0; 1063 1064 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr; 1065 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr; 1066 1067 // Program system aperture settings 1068 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); 1069 } 1070 1071 // if (dc->debug.sanity_checks) { 1072 // dcn10_verify_allow_pstate_change_high(dc); 1073 // } 1074 } 1075 1076 1077 void dcn20_pipe_control_lock_global( 1078 struct dc *dc, 1079 struct pipe_ctx *pipe, 1080 bool lock) 1081 { 1082 if (lock) { 1083 pipe->stream_res.tg->funcs->lock_doublebuffer_enable( 1084 pipe->stream_res.tg); 1085 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1086 } else { 1087 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1088 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, 1089 CRTC_STATE_VACTIVE); 1090 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, 1091 CRTC_STATE_VBLANK); 1092 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, 1093 CRTC_STATE_VACTIVE); 1094 pipe->stream_res.tg->funcs->lock_doublebuffer_disable( 1095 pipe->stream_res.tg); 1096 } 1097 } 1098 1099 void dcn20_pipe_control_lock( 1100 struct dc *dc, 1101 struct pipe_ctx *pipe, 1102 bool lock) 1103 { 1104 bool flip_immediate = false; 1105 1106 /* use TG master update lock to lock everything on the TG 1107 * therefore only top pipe need to lock 1108 */ 1109 if (pipe->top_pipe) 1110 return; 1111 1112 if (pipe->plane_state != NULL) 1113 flip_immediate = pipe->plane_state->flip_immediate; 1114 1115 /* In flip immediate and pipe splitting case, we need to use GSL 1116 * for synchronization. Only do setup on locking and on flip type change. 1117 */ 1118 if (lock && pipe->bottom_pipe != NULL) 1119 if ((flip_immediate && pipe->stream_res.gsl_group == 0) || 1120 (!flip_immediate && pipe->stream_res.gsl_group > 0)) 1121 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate); 1122 1123 if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) { 1124 if (lock) 1125 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); 1126 else 1127 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); 1128 } else { 1129 if (lock) 1130 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1131 else 1132 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1133 } 1134 } 1135 1136 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe) 1137 { 1138 new_pipe->update_flags.raw = 0; 1139 1140 /* Exit on unchanged, unused pipe */ 1141 if (!old_pipe->plane_state && !new_pipe->plane_state) 1142 return; 1143 /* Detect pipe enable/disable */ 1144 if (!old_pipe->plane_state && new_pipe->plane_state) { 1145 new_pipe->update_flags.bits.enable = 1; 1146 new_pipe->update_flags.bits.mpcc = 1; 1147 new_pipe->update_flags.bits.dppclk = 1; 1148 new_pipe->update_flags.bits.hubp_interdependent = 1; 1149 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1150 new_pipe->update_flags.bits.gamut_remap = 1; 1151 new_pipe->update_flags.bits.scaler = 1; 1152 new_pipe->update_flags.bits.viewport = 1; 1153 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1154 new_pipe->update_flags.bits.odm = 1; 1155 new_pipe->update_flags.bits.global_sync = 1; 1156 } 1157 return; 1158 } 1159 if (old_pipe->plane_state && !new_pipe->plane_state) { 1160 new_pipe->update_flags.bits.disable = 1; 1161 return; 1162 } 1163 1164 /* Detect top pipe only changes */ 1165 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1166 /* Detect odm changes */ 1167 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe 1168 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx) 1169 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe) 1170 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe) 1171 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1172 new_pipe->update_flags.bits.odm = 1; 1173 1174 /* Detect global sync changes */ 1175 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset 1176 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start 1177 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset 1178 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) 1179 new_pipe->update_flags.bits.global_sync = 1; 1180 } 1181 1182 /* 1183 * Detect opp / tg change, only set on change, not on enable 1184 * Assume mpcc inst = pipe index, if not this code needs to be updated 1185 * since mpcc is what is affected by these. In fact all of our sequence 1186 * makes this assumption at the moment with how hubp reset is matched to 1187 * same index mpcc reset. 1188 */ 1189 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1190 new_pipe->update_flags.bits.opp_changed = 1; 1191 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg) 1192 new_pipe->update_flags.bits.tg_changed = 1; 1193 1194 /* Detect mpcc blending changes, only dpp inst and bot matter here */ 1195 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp 1196 || old_pipe->stream_res.opp != new_pipe->stream_res.opp 1197 || (!old_pipe->bottom_pipe && new_pipe->bottom_pipe) 1198 || (old_pipe->bottom_pipe && !new_pipe->bottom_pipe) 1199 || (old_pipe->bottom_pipe && new_pipe->bottom_pipe 1200 && old_pipe->bottom_pipe->plane_res.mpcc_inst 1201 != new_pipe->bottom_pipe->plane_res.mpcc_inst)) 1202 new_pipe->update_flags.bits.mpcc = 1; 1203 1204 /* Detect dppclk change */ 1205 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) 1206 new_pipe->update_flags.bits.dppclk = 1; 1207 1208 /* Check for scl update */ 1209 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data))) 1210 new_pipe->update_flags.bits.scaler = 1; 1211 /* Check for vp update */ 1212 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect)) 1213 || memcmp(&old_pipe->plane_res.scl_data.viewport_c, 1214 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect))) 1215 new_pipe->update_flags.bits.viewport = 1; 1216 1217 /* Detect dlg/ttu/rq updates */ 1218 { 1219 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs; 1220 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs; 1221 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs; 1222 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs; 1223 1224 /* Detect pipe interdependent updates */ 1225 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch || 1226 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch || 1227 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c || 1228 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank || 1229 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank || 1230 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip || 1231 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip || 1232 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l || 1233 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c || 1234 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l || 1235 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l || 1236 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c || 1237 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l || 1238 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c || 1239 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 || 1240 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 || 1241 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank || 1242 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) { 1243 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch; 1244 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch; 1245 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c; 1246 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank; 1247 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank; 1248 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip; 1249 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip; 1250 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l; 1251 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c; 1252 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l; 1253 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l; 1254 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c; 1255 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l; 1256 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c; 1257 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0; 1258 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1; 1259 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank; 1260 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip; 1261 new_pipe->update_flags.bits.hubp_interdependent = 1; 1262 } 1263 /* Detect any other updates to ttu/rq/dlg */ 1264 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) || 1265 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) || 1266 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs))) 1267 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1268 } 1269 } 1270 1271 static void dcn20_update_dchubp_dpp( 1272 struct dc *dc, 1273 struct pipe_ctx *pipe_ctx, 1274 struct dc_state *context) 1275 { 1276 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1277 struct dpp *dpp = pipe_ctx->plane_res.dpp; 1278 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1279 1280 if (pipe_ctx->update_flags.bits.dppclk) 1281 dpp->funcs->dpp_dppclk_control(dpp, false, true); 1282 1283 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG 1284 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. 1285 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG 1286 */ 1287 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) { 1288 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst); 1289 1290 hubp->funcs->hubp_setup( 1291 hubp, 1292 &pipe_ctx->dlg_regs, 1293 &pipe_ctx->ttu_regs, 1294 &pipe_ctx->rq_regs, 1295 &pipe_ctx->pipe_dlg_param); 1296 } 1297 if (pipe_ctx->update_flags.bits.hubp_interdependent) 1298 hubp->funcs->hubp_setup_interdependent( 1299 hubp, 1300 &pipe_ctx->dlg_regs, 1301 &pipe_ctx->ttu_regs); 1302 1303 if (pipe_ctx->update_flags.bits.enable || 1304 plane_state->update_flags.bits.bpp_change || 1305 plane_state->update_flags.bits.input_csc_change || 1306 plane_state->update_flags.bits.color_space_change || 1307 plane_state->update_flags.bits.coeff_reduction_change) { 1308 struct dc_bias_and_scale bns_params = {0}; 1309 1310 // program the input csc 1311 dpp->funcs->dpp_setup(dpp, 1312 plane_state->format, 1313 EXPANSION_MODE_ZERO, 1314 plane_state->input_csc_color_matrix, 1315 plane_state->color_space, 1316 NULL); 1317 1318 if (dpp->funcs->dpp_program_bias_and_scale) { 1319 //TODO :for CNVC set scale and bias registers if necessary 1320 build_prescale_params(&bns_params, plane_state); 1321 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); 1322 } 1323 } 1324 1325 if (pipe_ctx->update_flags.bits.mpcc 1326 || plane_state->update_flags.bits.global_alpha_change 1327 || plane_state->update_flags.bits.per_pixel_alpha_change) { 1328 /* Need mpcc to be idle if changing opp */ 1329 if (pipe_ctx->update_flags.bits.opp_changed) { 1330 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 1331 int mpcc_inst; 1332 1333 for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) { 1334 if (!old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) 1335 continue; 1336 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); 1337 old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false; 1338 } 1339 } 1340 dc->hwss.update_mpcc(dc, pipe_ctx); 1341 } 1342 1343 if (pipe_ctx->update_flags.bits.scaler || 1344 plane_state->update_flags.bits.scaling_change || 1345 plane_state->update_flags.bits.position_change || 1346 plane_state->update_flags.bits.per_pixel_alpha_change || 1347 pipe_ctx->stream->update_flags.bits.scaling) { 1348 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; 1349 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_30BPP); 1350 /* scaler configuration */ 1351 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( 1352 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); 1353 } 1354 1355 if (pipe_ctx->update_flags.bits.viewport || 1356 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) || 1357 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) 1358 hubp->funcs->mem_program_viewport( 1359 hubp, 1360 &pipe_ctx->plane_res.scl_data.viewport, 1361 &pipe_ctx->plane_res.scl_data.viewport_c); 1362 1363 /* Any updates are handled in dc interface, just need to apply existing for plane enable */ 1364 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed) 1365 && pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { 1366 dc->hwss.set_cursor_position(pipe_ctx); 1367 dc->hwss.set_cursor_attribute(pipe_ctx); 1368 1369 if (dc->hwss.set_cursor_sdr_white_level) 1370 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 1371 } 1372 1373 /* Any updates are handled in dc interface, just need 1374 * to apply existing for plane enable / opp change */ 1375 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed 1376 || pipe_ctx->stream->update_flags.bits.gamut_remap 1377 || pipe_ctx->stream->update_flags.bits.out_csc) { 1378 /* dpp/cm gamut remap*/ 1379 dc->hwss.program_gamut_remap(pipe_ctx); 1380 1381 /*call the dcn2 method which uses mpc csc*/ 1382 dc->hwss.program_output_csc(dc, 1383 pipe_ctx, 1384 pipe_ctx->stream->output_color_space, 1385 pipe_ctx->stream->csc_color_matrix.matrix, 1386 hubp->opp_id); 1387 } 1388 1389 if (pipe_ctx->update_flags.bits.enable || 1390 pipe_ctx->update_flags.bits.opp_changed || 1391 plane_state->update_flags.bits.pixel_format_change || 1392 plane_state->update_flags.bits.horizontal_mirror_change || 1393 plane_state->update_flags.bits.rotation_change || 1394 plane_state->update_flags.bits.swizzle_change || 1395 plane_state->update_flags.bits.dcc_change || 1396 plane_state->update_flags.bits.bpp_change || 1397 plane_state->update_flags.bits.scaling_change || 1398 plane_state->update_flags.bits.plane_size_change) { 1399 struct plane_size size = plane_state->plane_size; 1400 1401 size.surface_size = pipe_ctx->plane_res.scl_data.viewport; 1402 hubp->funcs->hubp_program_surface_config( 1403 hubp, 1404 plane_state->format, 1405 &plane_state->tiling_info, 1406 &size, 1407 plane_state->rotation, 1408 &plane_state->dcc, 1409 plane_state->horizontal_mirror, 1410 0); 1411 hubp->power_gated = false; 1412 } 1413 1414 if (pipe_ctx->update_flags.bits.enable || plane_state->update_flags.bits.addr_update) 1415 dc->hwss.update_plane_addr(dc, pipe_ctx); 1416 1417 if (pipe_ctx->update_flags.bits.enable) 1418 hubp->funcs->set_blank(hubp, false); 1419 } 1420 1421 1422 static void dcn20_program_pipe( 1423 struct dc *dc, 1424 struct pipe_ctx *pipe_ctx, 1425 struct dc_state *context) 1426 { 1427 /* Only need to unblank on top pipe */ 1428 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level) 1429 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) 1430 dc->hwss.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible); 1431 1432 if (pipe_ctx->update_flags.bits.global_sync) { 1433 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1434 pipe_ctx->stream_res.tg, 1435 pipe_ctx->pipe_dlg_param.vready_offset, 1436 pipe_ctx->pipe_dlg_param.vstartup_start, 1437 pipe_ctx->pipe_dlg_param.vupdate_offset, 1438 pipe_ctx->pipe_dlg_param.vupdate_width); 1439 1440 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1441 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1442 1443 if (dc->hwss.setup_vupdate_interrupt) 1444 dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx); 1445 } 1446 1447 if (pipe_ctx->update_flags.bits.odm) 1448 dc->hwss.update_odm(dc, context, pipe_ctx); 1449 1450 if (pipe_ctx->update_flags.bits.enable) 1451 dcn20_enable_plane(dc, pipe_ctx, context); 1452 1453 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) 1454 dcn20_update_dchubp_dpp(dc, pipe_ctx, context); 1455 1456 if (pipe_ctx->update_flags.bits.enable 1457 || pipe_ctx->plane_state->update_flags.bits.hdr_mult) 1458 dc->hwss.set_hdr_multiplier(pipe_ctx); 1459 1460 if (pipe_ctx->update_flags.bits.enable || 1461 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 1462 pipe_ctx->plane_state->update_flags.bits.gamma_change) 1463 dc->hwss.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 1464 1465 /* dcn10_translate_regamma_to_hw_format takes 750us to finish 1466 * only do gamma programming for powering on, internal memcmp to avoid 1467 * updating on slave planes 1468 */ 1469 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf) 1470 dc->hwss.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 1471 1472 /* If the pipe has been enabled or has a different opp, we 1473 * should reprogram the fmt. This deals with cases where 1474 * interation between mpc and odm combine on different streams 1475 * causes a different pipe to be chosen to odm combine with. 1476 */ 1477 if (pipe_ctx->update_flags.bits.enable 1478 || pipe_ctx->update_flags.bits.opp_changed) { 1479 1480 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1481 pipe_ctx->stream_res.opp, 1482 COLOR_SPACE_YCBCR601, 1483 pipe_ctx->stream->timing.display_color_depth, 1484 pipe_ctx->stream->signal); 1485 1486 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1487 pipe_ctx->stream_res.opp, 1488 &pipe_ctx->stream->bit_depth_params, 1489 &pipe_ctx->stream->clamping); 1490 } 1491 } 1492 1493 static bool does_pipe_need_lock(struct pipe_ctx *pipe) 1494 { 1495 if ((pipe->plane_state && pipe->plane_state->update_flags.raw) 1496 || pipe->update_flags.raw) 1497 return true; 1498 if (pipe->bottom_pipe) 1499 return does_pipe_need_lock(pipe->bottom_pipe); 1500 1501 return false; 1502 } 1503 1504 void dcn20_program_front_end_for_ctx( 1505 struct dc *dc, 1506 struct dc_state *context) 1507 { 1508 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100; 1509 int i; 1510 bool pipe_locked[MAX_PIPES] = {false}; 1511 DC_LOGGER_INIT(dc->ctx->logger); 1512 1513 /* Carry over GSL groups in case the context is changing. */ 1514 for (i = 0; i < dc->res_pool->pipe_count; i++) 1515 if (context->res_ctx.pipe_ctx[i].stream == dc->current_state->res_ctx.pipe_ctx[i].stream) 1516 context->res_ctx.pipe_ctx[i].stream_res.gsl_group = 1517 dc->current_state->res_ctx.pipe_ctx[i].stream_res.gsl_group; 1518 1519 /* Set pipe update flags and lock pipes */ 1520 for (i = 0; i < dc->res_pool->pipe_count; i++) 1521 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i], 1522 &context->res_ctx.pipe_ctx[i]); 1523 for (i = 0; i < dc->res_pool->pipe_count; i++) 1524 if (!context->res_ctx.pipe_ctx[i].top_pipe && 1525 does_pipe_need_lock(&context->res_ctx.pipe_ctx[i])) { 1526 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1527 1528 if (pipe_ctx->update_flags.bits.tg_changed || pipe_ctx->update_flags.bits.enable) 1529 dc->hwss.pipe_control_lock(dc, pipe_ctx, true); 1530 if (!pipe_ctx->update_flags.bits.enable) 1531 dc->hwss.pipe_control_lock(dc, &dc->current_state->res_ctx.pipe_ctx[i], true); 1532 pipe_locked[i] = true; 1533 } 1534 1535 /* OTG blank before disabling all front ends */ 1536 for (i = 0; i < dc->res_pool->pipe_count; i++) 1537 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1538 && !context->res_ctx.pipe_ctx[i].top_pipe 1539 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe 1540 && context->res_ctx.pipe_ctx[i].stream) 1541 dc->hwss.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); 1542 1543 /* Disconnect mpcc */ 1544 for (i = 0; i < dc->res_pool->pipe_count; i++) 1545 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1546 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) { 1547 dc->hwss.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1548 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); 1549 } 1550 1551 /* 1552 * Program all updated pipes, order matters for mpcc setup. Start with 1553 * top pipe and program all pipes that follow in order 1554 */ 1555 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1556 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1557 1558 if (pipe->plane_state && !pipe->top_pipe) { 1559 while (pipe) { 1560 dcn20_program_pipe(dc, pipe, context); 1561 pipe = pipe->bottom_pipe; 1562 } 1563 /* Program secondary blending tree and writeback pipes */ 1564 pipe = &context->res_ctx.pipe_ctx[i]; 1565 if (!pipe->prev_odm_pipe && pipe->stream->num_wb_info > 0 1566 && (pipe->update_flags.raw || pipe->plane_state->update_flags.raw || pipe->stream->update_flags.raw) 1567 && dc->hwss.program_all_writeback_pipes_in_tree) 1568 dc->hwss.program_all_writeback_pipes_in_tree(dc, pipe->stream, context); 1569 } 1570 } 1571 1572 /* Unlock all locked pipes */ 1573 for (i = 0; i < dc->res_pool->pipe_count; i++) 1574 if (pipe_locked[i]) { 1575 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1576 1577 if (pipe_ctx->update_flags.bits.tg_changed || pipe_ctx->update_flags.bits.enable) 1578 dc->hwss.pipe_control_lock(dc, pipe_ctx, false); 1579 if (!pipe_ctx->update_flags.bits.enable) 1580 dc->hwss.pipe_control_lock(dc, &dc->current_state->res_ctx.pipe_ctx[i], false); 1581 } 1582 1583 for (i = 0; i < dc->res_pool->pipe_count; i++) 1584 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1585 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1586 1587 /* 1588 * If we are enabling a pipe, we need to wait for pending clear as this is a critical 1589 * part of the enable operation otherwise, DM may request an immediate flip which 1590 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which 1591 * is unsupported on DCN. 1592 */ 1593 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1594 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1595 1596 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable) { 1597 struct hubp *hubp = pipe->plane_res.hubp; 1598 int j = 0; 1599 1600 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS 1601 && hubp->funcs->hubp_is_flip_pending(hubp); j++) 1602 msleep(1); 1603 } 1604 } 1605 1606 /* WA to apply WM setting*/ 1607 if (dc->hwseq->wa.DEGVIDCN21) 1608 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub); 1609 } 1610 1611 1612 void dcn20_prepare_bandwidth( 1613 struct dc *dc, 1614 struct dc_state *context) 1615 { 1616 struct hubbub *hubbub = dc->res_pool->hubbub; 1617 1618 dc->clk_mgr->funcs->update_clocks( 1619 dc->clk_mgr, 1620 context, 1621 false); 1622 1623 /* program dchubbub watermarks */ 1624 hubbub->funcs->program_watermarks(hubbub, 1625 &context->bw_ctx.bw.dcn.watermarks, 1626 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1627 false); 1628 } 1629 1630 void dcn20_optimize_bandwidth( 1631 struct dc *dc, 1632 struct dc_state *context) 1633 { 1634 struct hubbub *hubbub = dc->res_pool->hubbub; 1635 1636 /* program dchubbub watermarks */ 1637 hubbub->funcs->program_watermarks(hubbub, 1638 &context->bw_ctx.bw.dcn.watermarks, 1639 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1640 true); 1641 1642 dc->clk_mgr->funcs->update_clocks( 1643 dc->clk_mgr, 1644 context, 1645 true); 1646 } 1647 1648 bool dcn20_update_bandwidth( 1649 struct dc *dc, 1650 struct dc_state *context) 1651 { 1652 int i; 1653 1654 /* recalculate DML parameters */ 1655 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) 1656 return false; 1657 1658 /* apply updated bandwidth parameters */ 1659 dc->hwss.prepare_bandwidth(dc, context); 1660 1661 /* update hubp configs for all pipes */ 1662 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1663 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1664 1665 if (pipe_ctx->plane_state == NULL) 1666 continue; 1667 1668 if (pipe_ctx->top_pipe == NULL) { 1669 bool blank = !is_pipe_tree_visible(pipe_ctx); 1670 1671 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1672 pipe_ctx->stream_res.tg, 1673 pipe_ctx->pipe_dlg_param.vready_offset, 1674 pipe_ctx->pipe_dlg_param.vstartup_start, 1675 pipe_ctx->pipe_dlg_param.vupdate_offset, 1676 pipe_ctx->pipe_dlg_param.vupdate_width); 1677 1678 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1679 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1680 1681 if (pipe_ctx->prev_odm_pipe == NULL) 1682 dc->hwss.blank_pixel_data(dc, pipe_ctx, blank); 1683 1684 if (dc->hwss.setup_vupdate_interrupt) 1685 dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx); 1686 } 1687 1688 pipe_ctx->plane_res.hubp->funcs->hubp_setup( 1689 pipe_ctx->plane_res.hubp, 1690 &pipe_ctx->dlg_regs, 1691 &pipe_ctx->ttu_regs, 1692 &pipe_ctx->rq_regs, 1693 &pipe_ctx->pipe_dlg_param); 1694 } 1695 1696 return true; 1697 } 1698 1699 void dcn20_enable_writeback( 1700 struct dc *dc, 1701 const struct dc_stream_status *stream_status, 1702 struct dc_writeback_info *wb_info, 1703 struct dc_state *context) 1704 { 1705 struct dwbc *dwb; 1706 struct mcif_wb *mcif_wb; 1707 struct timing_generator *optc; 1708 1709 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 1710 ASSERT(wb_info->wb_enabled); 1711 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 1712 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 1713 1714 /* set the OPTC source mux */ 1715 ASSERT(stream_status->primary_otg_inst < MAX_PIPES); 1716 optc = dc->res_pool->timing_generators[stream_status->primary_otg_inst]; 1717 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); 1718 /* set MCIF_WB buffer and arbitration configuration */ 1719 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 1720 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 1721 /* Enable MCIF_WB */ 1722 mcif_wb->funcs->enable_mcif(mcif_wb); 1723 /* Enable DWB */ 1724 dwb->funcs->enable(dwb, &wb_info->dwb_params); 1725 /* TODO: add sequence to enable/disable warmup */ 1726 } 1727 1728 void dcn20_disable_writeback( 1729 struct dc *dc, 1730 unsigned int dwb_pipe_inst) 1731 { 1732 struct dwbc *dwb; 1733 struct mcif_wb *mcif_wb; 1734 1735 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); 1736 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; 1737 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; 1738 1739 dwb->funcs->disable(dwb); 1740 mcif_wb->funcs->disable_mcif(mcif_wb); 1741 } 1742 1743 bool dcn20_wait_for_blank_complete( 1744 struct output_pixel_processor *opp) 1745 { 1746 int counter; 1747 1748 for (counter = 0; counter < 1000; counter++) { 1749 if (opp->funcs->dpg_is_blanked(opp)) 1750 break; 1751 1752 udelay(100); 1753 } 1754 1755 if (counter == 1000) { 1756 dm_error("DC: failed to blank crtc!\n"); 1757 return false; 1758 } 1759 1760 return true; 1761 } 1762 1763 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) 1764 { 1765 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1766 1767 if (!hubp) 1768 return false; 1769 return hubp->funcs->dmdata_status_done(hubp); 1770 } 1771 1772 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 1773 { 1774 struct dce_hwseq *hws = dc->hwseq; 1775 1776 if (pipe_ctx->stream_res.dsc) { 1777 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1778 1779 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); 1780 while (odm_pipe) { 1781 dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true); 1782 odm_pipe = odm_pipe->next_odm_pipe; 1783 } 1784 } 1785 } 1786 1787 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 1788 { 1789 struct dce_hwseq *hws = dc->hwseq; 1790 1791 if (pipe_ctx->stream_res.dsc) { 1792 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1793 1794 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false); 1795 while (odm_pipe) { 1796 dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false); 1797 odm_pipe = odm_pipe->next_odm_pipe; 1798 } 1799 } 1800 } 1801 1802 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) 1803 { 1804 struct dc_dmdata_attributes attr = { 0 }; 1805 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1806 1807 attr.dmdata_mode = DMDATA_HW_MODE; 1808 attr.dmdata_size = 1809 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; 1810 attr.address.quad_part = 1811 pipe_ctx->stream->dmdata_address.quad_part; 1812 attr.dmdata_dl_delta = 0; 1813 attr.dmdata_qos_mode = 0; 1814 attr.dmdata_qos_level = 0; 1815 attr.dmdata_repeat = 1; /* always repeat */ 1816 attr.dmdata_updated = 1; 1817 attr.dmdata_sw_data = NULL; 1818 1819 hubp->funcs->dmdata_set_attributes(hubp, &attr); 1820 } 1821 1822 void dcn20_init_vm_ctx( 1823 struct dce_hwseq *hws, 1824 struct dc *dc, 1825 struct dc_virtual_addr_space_config *va_config, 1826 int vmid) 1827 { 1828 struct dcn_hubbub_virt_addr_config config; 1829 1830 if (vmid == 0) { 1831 ASSERT(0); /* VMID cannot be 0 for vm context */ 1832 return; 1833 } 1834 1835 config.page_table_start_addr = va_config->page_table_start_addr; 1836 config.page_table_end_addr = va_config->page_table_end_addr; 1837 config.page_table_block_size = va_config->page_table_block_size_in_bytes; 1838 config.page_table_depth = va_config->page_table_depth; 1839 config.page_table_base_addr = va_config->page_table_base_addr; 1840 1841 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); 1842 } 1843 1844 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 1845 { 1846 struct dcn_hubbub_phys_addr_config config; 1847 1848 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 1849 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 1850 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 1851 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 1852 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 1853 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 1854 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 1855 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 1856 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 1857 config.page_table_default_page_addr = pa_config->page_table_default_page_addr; 1858 1859 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 1860 } 1861 1862 static bool patch_address_for_sbs_tb_stereo( 1863 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) 1864 { 1865 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1866 bool sec_split = pipe_ctx->top_pipe && 1867 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; 1868 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && 1869 (pipe_ctx->stream->timing.timing_3d_format == 1870 TIMING_3D_FORMAT_SIDE_BY_SIDE || 1871 pipe_ctx->stream->timing.timing_3d_format == 1872 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { 1873 *addr = plane_state->address.grph_stereo.left_addr; 1874 plane_state->address.grph_stereo.left_addr = 1875 plane_state->address.grph_stereo.right_addr; 1876 return true; 1877 } 1878 1879 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && 1880 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { 1881 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; 1882 plane_state->address.grph_stereo.right_addr = 1883 plane_state->address.grph_stereo.left_addr; 1884 } 1885 return false; 1886 } 1887 1888 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) 1889 { 1890 bool addr_patched = false; 1891 PHYSICAL_ADDRESS_LOC addr; 1892 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1893 1894 if (plane_state == NULL) 1895 return; 1896 1897 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); 1898 1899 // Call Helper to track VMID use 1900 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); 1901 1902 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( 1903 pipe_ctx->plane_res.hubp, 1904 &plane_state->address, 1905 plane_state->flip_immediate); 1906 1907 plane_state->status.requested_address = plane_state->address; 1908 1909 if (plane_state->flip_immediate) 1910 plane_state->status.current_address = plane_state->address; 1911 1912 if (addr_patched) 1913 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; 1914 } 1915 1916 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, 1917 struct dc_link_settings *link_settings) 1918 { 1919 struct encoder_unblank_param params = { { 0 } }; 1920 struct dc_stream_state *stream = pipe_ctx->stream; 1921 struct dc_link *link = stream->link; 1922 struct pipe_ctx *odm_pipe; 1923 1924 params.opp_cnt = 1; 1925 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1926 params.opp_cnt++; 1927 } 1928 /* only 3 items below are used by unblank */ 1929 params.timing = pipe_ctx->stream->timing; 1930 1931 params.link_settings.link_rate = link_settings->link_rate; 1932 1933 if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1934 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1) 1935 params.timing.pix_clk_100hz /= 2; 1936 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 1937 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1); 1938 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); 1939 } 1940 1941 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1942 link->dc->hwss.edp_backlight_control(link, true); 1943 } 1944 } 1945 1946 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx) 1947 { 1948 struct timing_generator *tg = pipe_ctx->stream_res.tg; 1949 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx); 1950 1951 if (start_line < 0) 1952 start_line = 0; 1953 1954 if (tg->funcs->setup_vertical_interrupt2) 1955 tg->funcs->setup_vertical_interrupt2(tg, start_line); 1956 } 1957 1958 static void dcn20_reset_back_end_for_pipe( 1959 struct dc *dc, 1960 struct pipe_ctx *pipe_ctx, 1961 struct dc_state *context) 1962 { 1963 int i; 1964 DC_LOGGER_INIT(dc->ctx->logger); 1965 if (pipe_ctx->stream_res.stream_enc == NULL) { 1966 pipe_ctx->stream = NULL; 1967 return; 1968 } 1969 1970 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 1971 /* DPMS may already disable */ 1972 if (!pipe_ctx->stream->dpms_off) 1973 core_link_disable_stream(pipe_ctx); 1974 else if (pipe_ctx->stream_res.audio) 1975 dc->hwss.disable_audio_stream(pipe_ctx); 1976 1977 /* free acquired resources */ 1978 if (pipe_ctx->stream_res.audio) { 1979 /*disable az_endpoint*/ 1980 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 1981 1982 /*free audio*/ 1983 if (dc->caps.dynamic_audio == true) { 1984 /*we have to dynamic arbitrate the audio endpoints*/ 1985 /*we free the resource, need reset is_audio_acquired*/ 1986 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 1987 pipe_ctx->stream_res.audio, false); 1988 pipe_ctx->stream_res.audio = NULL; 1989 } 1990 } 1991 } 1992 else if (pipe_ctx->stream_res.dsc) { 1993 dp_set_dsc_enable(pipe_ctx, false); 1994 } 1995 1996 /* by upper caller loop, parent pipe: pipe0, will be reset last. 1997 * back end share by all pipes and will be disable only when disable 1998 * parent pipe. 1999 */ 2000 if (pipe_ctx->top_pipe == NULL) { 2001 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 2002 2003 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 2004 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 2005 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 2006 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 2007 2008 if (pipe_ctx->stream_res.tg->funcs->set_drr) 2009 pipe_ctx->stream_res.tg->funcs->set_drr( 2010 pipe_ctx->stream_res.tg, NULL); 2011 } 2012 2013 for (i = 0; i < dc->res_pool->pipe_count; i++) 2014 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) 2015 break; 2016 2017 if (i == dc->res_pool->pipe_count) 2018 return; 2019 2020 pipe_ctx->stream = NULL; 2021 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 2022 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 2023 } 2024 2025 void dcn20_reset_hw_ctx_wrap( 2026 struct dc *dc, 2027 struct dc_state *context) 2028 { 2029 int i; 2030 2031 /* Reset Back End*/ 2032 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 2033 struct pipe_ctx *pipe_ctx_old = 2034 &dc->current_state->res_ctx.pipe_ctx[i]; 2035 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2036 2037 if (!pipe_ctx_old->stream) 2038 continue; 2039 2040 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 2041 continue; 2042 2043 if (!pipe_ctx->stream || 2044 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 2045 struct clock_source *old_clk = pipe_ctx_old->clock_source; 2046 2047 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 2048 if (dc->hwss.enable_stream_gating) 2049 dc->hwss.enable_stream_gating(dc, pipe_ctx); 2050 if (old_clk) 2051 old_clk->funcs->cs_power_down(old_clk); 2052 } 2053 } 2054 } 2055 2056 void dcn20_get_mpctree_visual_confirm_color( 2057 struct pipe_ctx *pipe_ctx, 2058 struct tg_color *color) 2059 { 2060 const struct tg_color pipe_colors[6] = { 2061 {MAX_TG_COLOR_VALUE, 0, 0}, // red 2062 {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, // yellow 2063 {0, MAX_TG_COLOR_VALUE, 0}, // blue 2064 {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, // purple 2065 {0, 0, MAX_TG_COLOR_VALUE}, // green 2066 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE * 2 / 3, 0}, // orange 2067 }; 2068 2069 struct pipe_ctx *top_pipe = pipe_ctx; 2070 2071 while (top_pipe->top_pipe) { 2072 top_pipe = top_pipe->top_pipe; 2073 } 2074 2075 *color = pipe_colors[top_pipe->pipe_idx]; 2076 } 2077 2078 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 2079 { 2080 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2081 struct mpcc_blnd_cfg blnd_cfg = { {0} }; 2082 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; 2083 int mpcc_id; 2084 struct mpcc *new_mpcc; 2085 struct mpc *mpc = dc->res_pool->mpc; 2086 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); 2087 2088 // input to MPCC is always RGB, by default leave black_color at 0 2089 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) { 2090 dc->hwss.get_hdr_visual_confirm_color( 2091 pipe_ctx, &blnd_cfg.black_color); 2092 } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) { 2093 dc->hwss.get_surface_visual_confirm_color( 2094 pipe_ctx, &blnd_cfg.black_color); 2095 } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) { 2096 dcn20_get_mpctree_visual_confirm_color( 2097 pipe_ctx, &blnd_cfg.black_color); 2098 } 2099 2100 if (per_pixel_alpha) 2101 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2102 else 2103 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 2104 2105 blnd_cfg.overlap_only = false; 2106 blnd_cfg.global_gain = 0xff; 2107 2108 if (pipe_ctx->plane_state->global_alpha) 2109 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; 2110 else 2111 blnd_cfg.global_alpha = 0xff; 2112 2113 blnd_cfg.background_color_bpc = 4; 2114 blnd_cfg.bottom_gain_mode = 0; 2115 blnd_cfg.top_gain = 0x1f000; 2116 blnd_cfg.bottom_inside_gain = 0x1f000; 2117 blnd_cfg.bottom_outside_gain = 0x1f000; 2118 blnd_cfg.pre_multiplied_alpha = per_pixel_alpha; 2119 2120 /* 2121 * TODO: remove hack 2122 * Note: currently there is a bug in init_hw such that 2123 * on resume from hibernate, BIOS sets up MPCC0, and 2124 * we do mpcc_remove but the mpcc cannot go to idle 2125 * after remove. This cause us to pick mpcc1 here, 2126 * which causes a pstate hang for yet unknown reason. 2127 */ 2128 mpcc_id = hubp->inst; 2129 2130 /* If there is no full update, don't need to touch MPC tree*/ 2131 if (!pipe_ctx->plane_state->update_flags.bits.full_update) { 2132 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); 2133 return; 2134 } 2135 2136 /* check if this MPCC is already being used */ 2137 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 2138 /* remove MPCC if being used */ 2139 if (new_mpcc != NULL) 2140 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); 2141 else 2142 if (dc->debug.sanity_checks) 2143 mpc->funcs->assert_mpcc_idle_before_connect( 2144 dc->res_pool->mpc, mpcc_id); 2145 2146 /* Call MPC to insert new plane */ 2147 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, 2148 mpc_tree_params, 2149 &blnd_cfg, 2150 NULL, 2151 NULL, 2152 hubp->inst, 2153 mpcc_id); 2154 2155 ASSERT(new_mpcc != NULL); 2156 hubp->opp_id = pipe_ctx->stream_res.opp->inst; 2157 hubp->mpcc_id = mpcc_id; 2158 } 2159 2160 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 2161 { 2162 enum dc_lane_count lane_count = 2163 pipe_ctx->stream->link->cur_link_settings.lane_count; 2164 2165 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 2166 struct dc_link *link = pipe_ctx->stream->link; 2167 2168 uint32_t active_total_with_borders; 2169 uint32_t early_control = 0; 2170 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2171 2172 /* For MST, there are multiply stream go to only one link. 2173 * connect DIG back_end to front_end while enable_stream and 2174 * disconnect them during disable_stream 2175 * BY this, it is logic clean to separate stream and link 2176 */ 2177 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, 2178 pipe_ctx->stream_res.stream_enc->id, true); 2179 2180 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) { 2181 if (link->dc->hwss.program_dmdata_engine) 2182 link->dc->hwss.program_dmdata_engine(pipe_ctx); 2183 } 2184 2185 link->dc->hwss.update_info_frame(pipe_ctx); 2186 2187 /* enable early control to avoid corruption on DP monitor*/ 2188 active_total_with_borders = 2189 timing->h_addressable 2190 + timing->h_border_left 2191 + timing->h_border_right; 2192 2193 if (lane_count != 0) 2194 early_control = active_total_with_borders % lane_count; 2195 2196 if (early_control == 0) 2197 early_control = lane_count; 2198 2199 tg->funcs->set_early_control(tg, early_control); 2200 2201 /* enable audio only within mode set */ 2202 if (pipe_ctx->stream_res.audio != NULL) { 2203 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2204 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 2205 } 2206 } 2207 2208 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx) 2209 { 2210 struct dc_stream_state *stream = pipe_ctx->stream; 2211 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2212 bool enable = false; 2213 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2214 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) 2215 ? dmdata_dp 2216 : dmdata_hdmi; 2217 2218 /* if using dynamic meta, don't set up generic infopackets */ 2219 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { 2220 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; 2221 enable = true; 2222 } 2223 2224 if (!hubp) 2225 return; 2226 2227 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) 2228 return; 2229 2230 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, 2231 hubp->inst, mode); 2232 } 2233 2234 void dcn20_fpga_init_hw(struct dc *dc) 2235 { 2236 int i, j; 2237 struct dce_hwseq *hws = dc->hwseq; 2238 struct resource_pool *res_pool = dc->res_pool; 2239 struct dc_state *context = dc->current_state; 2240 2241 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 2242 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 2243 2244 // Initialize the dccg 2245 if (res_pool->dccg->funcs->dccg_init) 2246 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 2247 2248 //Enable ability to power gate / don't force power on permanently 2249 dc->hwss.enable_power_gating_plane(hws, true); 2250 2251 // Specific to FPGA dccg and registers 2252 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); 2253 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 2254 2255 dc->hwss.dccg_init(hws); 2256 2257 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); 2258 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 2259 REG_WRITE(REFCLK_CNTL, 0); 2260 // 2261 2262 2263 /* Blank pixel data with OPP DPG */ 2264 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2265 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2266 2267 if (tg->funcs->is_tg_enabled(tg)) 2268 dcn20_init_blank(dc, tg); 2269 } 2270 2271 for (i = 0; i < res_pool->timing_generator_count; i++) { 2272 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2273 2274 if (tg->funcs->is_tg_enabled(tg)) 2275 tg->funcs->lock(tg); 2276 } 2277 2278 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2279 struct dpp *dpp = res_pool->dpps[i]; 2280 2281 dpp->funcs->dpp_reset(dpp); 2282 } 2283 2284 /* Reset all MPCC muxes */ 2285 res_pool->mpc->funcs->mpc_init(res_pool->mpc); 2286 2287 /* initialize OPP mpc_tree parameter */ 2288 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 2289 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; 2290 res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2291 for (j = 0; j < MAX_PIPES; j++) 2292 res_pool->opps[i]->mpcc_disconnect_pending[j] = false; 2293 } 2294 2295 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2296 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2297 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2298 struct hubp *hubp = dc->res_pool->hubps[i]; 2299 struct dpp *dpp = dc->res_pool->dpps[i]; 2300 2301 pipe_ctx->stream_res.tg = tg; 2302 pipe_ctx->pipe_idx = i; 2303 2304 pipe_ctx->plane_res.hubp = hubp; 2305 pipe_ctx->plane_res.dpp = dpp; 2306 pipe_ctx->plane_res.mpcc_inst = dpp->inst; 2307 hubp->mpcc_id = dpp->inst; 2308 hubp->opp_id = OPP_ID_INVALID; 2309 hubp->power_gated = false; 2310 pipe_ctx->stream_res.opp = NULL; 2311 2312 hubp->funcs->hubp_init(hubp); 2313 2314 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; 2315 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2316 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; 2317 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; 2318 /*to do*/ 2319 dc->hwss.plane_atomic_disconnect(dc, pipe_ctx); 2320 } 2321 2322 /* initialize DWB pointer to MCIF_WB */ 2323 for (i = 0; i < res_pool->res_cap->num_dwb; i++) 2324 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; 2325 2326 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2327 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2328 2329 if (tg->funcs->is_tg_enabled(tg)) 2330 tg->funcs->unlock(tg); 2331 } 2332 2333 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2334 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2335 2336 dc->hwss.disable_plane(dc, pipe_ctx); 2337 2338 pipe_ctx->stream_res.tg = NULL; 2339 pipe_ctx->plane_res.hubp = NULL; 2340 } 2341 2342 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2343 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2344 2345 tg->funcs->tg_init(tg); 2346 } 2347 } 2348