1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include <linux/delay.h> 26 27 #include "dm_services.h" 28 #include "basics/dc_common.h" 29 #include "dm_helpers.h" 30 #include "core_types.h" 31 #include "resource.h" 32 #include "dcn20_resource.h" 33 #include "dcn20_hwseq.h" 34 #include "dce/dce_hwseq.h" 35 #include "dcn20_dsc.h" 36 #include "dcn20_optc.h" 37 #include "abm.h" 38 #include "clk_mgr.h" 39 #include "dmcu.h" 40 #include "hubp.h" 41 #include "timing_generator.h" 42 #include "opp.h" 43 #include "ipp.h" 44 #include "mpc.h" 45 #include "mcif_wb.h" 46 #include "dchubbub.h" 47 #include "reg_helper.h" 48 #include "dcn10/dcn10_cm_common.h" 49 #include "dc_link_dp.h" 50 #include "vm_helper.h" 51 #include "dccg.h" 52 #include "dc_dmub_srv.h" 53 #include "dce/dmub_hw_lock_mgr.h" 54 #include "hw_sequencer.h" 55 #include "inc/link_dpcd.h" 56 #include "dpcd_defs.h" 57 #include "inc/link_enc_cfg.h" 58 59 #define DC_LOGGER_INIT(logger) 60 61 #define CTX \ 62 hws->ctx 63 #define REG(reg)\ 64 hws->regs->reg 65 66 #undef FN 67 #define FN(reg_name, field_name) \ 68 hws->shifts->field_name, hws->masks->field_name 69 70 static int find_free_gsl_group(const struct dc *dc) 71 { 72 if (dc->res_pool->gsl_groups.gsl_0 == 0) 73 return 1; 74 if (dc->res_pool->gsl_groups.gsl_1 == 0) 75 return 2; 76 if (dc->res_pool->gsl_groups.gsl_2 == 0) 77 return 3; 78 79 return 0; 80 } 81 82 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock) 83 * This is only used to lock pipes in pipe splitting case with immediate flip 84 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate, 85 * so we get tearing with freesync since we cannot flip multiple pipes 86 * atomically. 87 * We use GSL for this: 88 * - immediate flip: find first available GSL group if not already assigned 89 * program gsl with that group, set current OTG as master 90 * and always us 0x4 = AND of flip_ready from all pipes 91 * - vsync flip: disable GSL if used 92 * 93 * Groups in stream_res are stored as +1 from HW registers, i.e. 94 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1 95 * Using a magic value like -1 would require tracking all inits/resets 96 */ 97 static void dcn20_setup_gsl_group_as_lock( 98 const struct dc *dc, 99 struct pipe_ctx *pipe_ctx, 100 bool enable) 101 { 102 struct gsl_params gsl; 103 int group_idx; 104 105 memset(&gsl, 0, sizeof(struct gsl_params)); 106 107 if (enable) { 108 /* return if group already assigned since GSL was set up 109 * for vsync flip, we would unassign so it can't be "left over" 110 */ 111 if (pipe_ctx->stream_res.gsl_group > 0) 112 return; 113 114 group_idx = find_free_gsl_group(dc); 115 ASSERT(group_idx != 0); 116 pipe_ctx->stream_res.gsl_group = group_idx; 117 118 /* set gsl group reg field and mark resource used */ 119 switch (group_idx) { 120 case 1: 121 gsl.gsl0_en = 1; 122 dc->res_pool->gsl_groups.gsl_0 = 1; 123 break; 124 case 2: 125 gsl.gsl1_en = 1; 126 dc->res_pool->gsl_groups.gsl_1 = 1; 127 break; 128 case 3: 129 gsl.gsl2_en = 1; 130 dc->res_pool->gsl_groups.gsl_2 = 1; 131 break; 132 default: 133 BREAK_TO_DEBUGGER(); 134 return; // invalid case 135 } 136 gsl.gsl_master_en = 1; 137 } else { 138 group_idx = pipe_ctx->stream_res.gsl_group; 139 if (group_idx == 0) 140 return; // if not in use, just return 141 142 pipe_ctx->stream_res.gsl_group = 0; 143 144 /* unset gsl group reg field and mark resource free */ 145 switch (group_idx) { 146 case 1: 147 gsl.gsl0_en = 0; 148 dc->res_pool->gsl_groups.gsl_0 = 0; 149 break; 150 case 2: 151 gsl.gsl1_en = 0; 152 dc->res_pool->gsl_groups.gsl_1 = 0; 153 break; 154 case 3: 155 gsl.gsl2_en = 0; 156 dc->res_pool->gsl_groups.gsl_2 = 0; 157 break; 158 default: 159 BREAK_TO_DEBUGGER(); 160 return; 161 } 162 gsl.gsl_master_en = 0; 163 } 164 165 /* at this point we want to program whether it's to enable or disable */ 166 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && 167 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { 168 pipe_ctx->stream_res.tg->funcs->set_gsl( 169 pipe_ctx->stream_res.tg, 170 &gsl); 171 172 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( 173 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); 174 } else 175 BREAK_TO_DEBUGGER(); 176 } 177 178 void dcn20_set_flip_control_gsl( 179 struct pipe_ctx *pipe_ctx, 180 bool flip_immediate) 181 { 182 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) 183 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( 184 pipe_ctx->plane_res.hubp, flip_immediate); 185 186 } 187 188 void dcn20_enable_power_gating_plane( 189 struct dce_hwseq *hws, 190 bool enable) 191 { 192 bool force_on = true; /* disable power gating */ 193 194 if (enable) 195 force_on = false; 196 197 /* DCHUBP0/1/2/3/4/5 */ 198 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); 199 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); 200 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); 201 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); 202 if (REG(DOMAIN8_PG_CONFIG)) 203 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 204 if (REG(DOMAIN10_PG_CONFIG)) 205 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 206 207 /* DPP0/1/2/3/4/5 */ 208 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); 209 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); 210 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); 211 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); 212 if (REG(DOMAIN9_PG_CONFIG)) 213 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 214 if (REG(DOMAIN11_PG_CONFIG)) 215 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 216 217 /* DCS0/1/2/3/4/5 */ 218 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on); 219 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on); 220 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on); 221 if (REG(DOMAIN19_PG_CONFIG)) 222 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on); 223 if (REG(DOMAIN20_PG_CONFIG)) 224 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on); 225 if (REG(DOMAIN21_PG_CONFIG)) 226 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); 227 } 228 229 void dcn20_dccg_init(struct dce_hwseq *hws) 230 { 231 /* 232 * set MICROSECOND_TIME_BASE_DIV 233 * 100Mhz refclk -> 0x120264 234 * 27Mhz refclk -> 0x12021b 235 * 48Mhz refclk -> 0x120230 236 * 237 */ 238 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); 239 240 /* 241 * set MILLISECOND_TIME_BASE_DIV 242 * 100Mhz refclk -> 0x1186a0 243 * 27Mhz refclk -> 0x106978 244 * 48Mhz refclk -> 0x10bb80 245 * 246 */ 247 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); 248 249 /* This value is dependent on the hardware pipeline delay so set once per SOC */ 250 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c); 251 } 252 253 void dcn20_disable_vga( 254 struct dce_hwseq *hws) 255 { 256 REG_WRITE(D1VGA_CONTROL, 0); 257 REG_WRITE(D2VGA_CONTROL, 0); 258 REG_WRITE(D3VGA_CONTROL, 0); 259 REG_WRITE(D4VGA_CONTROL, 0); 260 REG_WRITE(D5VGA_CONTROL, 0); 261 REG_WRITE(D6VGA_CONTROL, 0); 262 } 263 264 void dcn20_program_triple_buffer( 265 const struct dc *dc, 266 struct pipe_ctx *pipe_ctx, 267 bool enable_triple_buffer) 268 { 269 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { 270 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( 271 pipe_ctx->plane_res.hubp, 272 enable_triple_buffer); 273 } 274 } 275 276 /* Blank pixel data during initialization */ 277 void dcn20_init_blank( 278 struct dc *dc, 279 struct timing_generator *tg) 280 { 281 struct dce_hwseq *hws = dc->hwseq; 282 enum dc_color_space color_space; 283 struct tg_color black_color = {0}; 284 struct output_pixel_processor *opp = NULL; 285 struct output_pixel_processor *bottom_opp = NULL; 286 uint32_t num_opps, opp_id_src0, opp_id_src1; 287 uint32_t otg_active_width, otg_active_height; 288 289 /* program opp dpg blank color */ 290 color_space = COLOR_SPACE_SRGB; 291 color_space_to_black_color(dc, color_space, &black_color); 292 293 /* get the OTG active size */ 294 tg->funcs->get_otg_active_size(tg, 295 &otg_active_width, 296 &otg_active_height); 297 298 /* get the OPTC source */ 299 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 300 301 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { 302 ASSERT(false); 303 return; 304 } 305 opp = dc->res_pool->opps[opp_id_src0]; 306 307 if (num_opps == 2) { 308 otg_active_width = otg_active_width / 2; 309 310 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { 311 ASSERT(false); 312 return; 313 } 314 bottom_opp = dc->res_pool->opps[opp_id_src1]; 315 } 316 317 opp->funcs->opp_set_disp_pattern_generator( 318 opp, 319 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 320 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 321 COLOR_DEPTH_UNDEFINED, 322 &black_color, 323 otg_active_width, 324 otg_active_height, 325 0); 326 327 if (num_opps == 2) { 328 bottom_opp->funcs->opp_set_disp_pattern_generator( 329 bottom_opp, 330 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 331 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 332 COLOR_DEPTH_UNDEFINED, 333 &black_color, 334 otg_active_width, 335 otg_active_height, 336 0); 337 } 338 339 hws->funcs.wait_for_blank_complete(opp); 340 } 341 342 void dcn20_dsc_pg_control( 343 struct dce_hwseq *hws, 344 unsigned int dsc_inst, 345 bool power_on) 346 { 347 uint32_t power_gate = power_on ? 0 : 1; 348 uint32_t pwr_status = power_on ? 0 : 2; 349 uint32_t org_ip_request_cntl = 0; 350 351 if (hws->ctx->dc->debug.disable_dsc_power_gate) 352 return; 353 354 if (REG(DOMAIN16_PG_CONFIG) == 0) 355 return; 356 357 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 358 if (org_ip_request_cntl == 0) 359 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 360 361 switch (dsc_inst) { 362 case 0: /* DSC0 */ 363 REG_UPDATE(DOMAIN16_PG_CONFIG, 364 DOMAIN16_POWER_GATE, power_gate); 365 366 REG_WAIT(DOMAIN16_PG_STATUS, 367 DOMAIN16_PGFSM_PWR_STATUS, pwr_status, 368 1, 1000); 369 break; 370 case 1: /* DSC1 */ 371 REG_UPDATE(DOMAIN17_PG_CONFIG, 372 DOMAIN17_POWER_GATE, power_gate); 373 374 REG_WAIT(DOMAIN17_PG_STATUS, 375 DOMAIN17_PGFSM_PWR_STATUS, pwr_status, 376 1, 1000); 377 break; 378 case 2: /* DSC2 */ 379 REG_UPDATE(DOMAIN18_PG_CONFIG, 380 DOMAIN18_POWER_GATE, power_gate); 381 382 REG_WAIT(DOMAIN18_PG_STATUS, 383 DOMAIN18_PGFSM_PWR_STATUS, pwr_status, 384 1, 1000); 385 break; 386 case 3: /* DSC3 */ 387 REG_UPDATE(DOMAIN19_PG_CONFIG, 388 DOMAIN19_POWER_GATE, power_gate); 389 390 REG_WAIT(DOMAIN19_PG_STATUS, 391 DOMAIN19_PGFSM_PWR_STATUS, pwr_status, 392 1, 1000); 393 break; 394 case 4: /* DSC4 */ 395 REG_UPDATE(DOMAIN20_PG_CONFIG, 396 DOMAIN20_POWER_GATE, power_gate); 397 398 REG_WAIT(DOMAIN20_PG_STATUS, 399 DOMAIN20_PGFSM_PWR_STATUS, pwr_status, 400 1, 1000); 401 break; 402 case 5: /* DSC5 */ 403 REG_UPDATE(DOMAIN21_PG_CONFIG, 404 DOMAIN21_POWER_GATE, power_gate); 405 406 REG_WAIT(DOMAIN21_PG_STATUS, 407 DOMAIN21_PGFSM_PWR_STATUS, pwr_status, 408 1, 1000); 409 break; 410 default: 411 BREAK_TO_DEBUGGER(); 412 break; 413 } 414 415 if (org_ip_request_cntl == 0) 416 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 417 } 418 419 void dcn20_dpp_pg_control( 420 struct dce_hwseq *hws, 421 unsigned int dpp_inst, 422 bool power_on) 423 { 424 uint32_t power_gate = power_on ? 0 : 1; 425 uint32_t pwr_status = power_on ? 0 : 2; 426 427 if (hws->ctx->dc->debug.disable_dpp_power_gate) 428 return; 429 if (REG(DOMAIN1_PG_CONFIG) == 0) 430 return; 431 432 switch (dpp_inst) { 433 case 0: /* DPP0 */ 434 REG_UPDATE(DOMAIN1_PG_CONFIG, 435 DOMAIN1_POWER_GATE, power_gate); 436 437 REG_WAIT(DOMAIN1_PG_STATUS, 438 DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 439 1, 1000); 440 break; 441 case 1: /* DPP1 */ 442 REG_UPDATE(DOMAIN3_PG_CONFIG, 443 DOMAIN3_POWER_GATE, power_gate); 444 445 REG_WAIT(DOMAIN3_PG_STATUS, 446 DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 447 1, 1000); 448 break; 449 case 2: /* DPP2 */ 450 REG_UPDATE(DOMAIN5_PG_CONFIG, 451 DOMAIN5_POWER_GATE, power_gate); 452 453 REG_WAIT(DOMAIN5_PG_STATUS, 454 DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 455 1, 1000); 456 break; 457 case 3: /* DPP3 */ 458 REG_UPDATE(DOMAIN7_PG_CONFIG, 459 DOMAIN7_POWER_GATE, power_gate); 460 461 REG_WAIT(DOMAIN7_PG_STATUS, 462 DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 463 1, 1000); 464 break; 465 case 4: /* DPP4 */ 466 REG_UPDATE(DOMAIN9_PG_CONFIG, 467 DOMAIN9_POWER_GATE, power_gate); 468 469 REG_WAIT(DOMAIN9_PG_STATUS, 470 DOMAIN9_PGFSM_PWR_STATUS, pwr_status, 471 1, 1000); 472 break; 473 case 5: /* DPP5 */ 474 /* 475 * Do not power gate DPP5, should be left at HW default, power on permanently. 476 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 477 * reset. 478 * REG_UPDATE(DOMAIN11_PG_CONFIG, 479 * DOMAIN11_POWER_GATE, power_gate); 480 * 481 * REG_WAIT(DOMAIN11_PG_STATUS, 482 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, 483 * 1, 1000); 484 */ 485 break; 486 default: 487 BREAK_TO_DEBUGGER(); 488 break; 489 } 490 } 491 492 493 void dcn20_hubp_pg_control( 494 struct dce_hwseq *hws, 495 unsigned int hubp_inst, 496 bool power_on) 497 { 498 uint32_t power_gate = power_on ? 0 : 1; 499 uint32_t pwr_status = power_on ? 0 : 2; 500 501 if (hws->ctx->dc->debug.disable_hubp_power_gate) 502 return; 503 if (REG(DOMAIN0_PG_CONFIG) == 0) 504 return; 505 506 switch (hubp_inst) { 507 case 0: /* DCHUBP0 */ 508 REG_UPDATE(DOMAIN0_PG_CONFIG, 509 DOMAIN0_POWER_GATE, power_gate); 510 511 REG_WAIT(DOMAIN0_PG_STATUS, 512 DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 513 1, 1000); 514 break; 515 case 1: /* DCHUBP1 */ 516 REG_UPDATE(DOMAIN2_PG_CONFIG, 517 DOMAIN2_POWER_GATE, power_gate); 518 519 REG_WAIT(DOMAIN2_PG_STATUS, 520 DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 521 1, 1000); 522 break; 523 case 2: /* DCHUBP2 */ 524 REG_UPDATE(DOMAIN4_PG_CONFIG, 525 DOMAIN4_POWER_GATE, power_gate); 526 527 REG_WAIT(DOMAIN4_PG_STATUS, 528 DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 529 1, 1000); 530 break; 531 case 3: /* DCHUBP3 */ 532 REG_UPDATE(DOMAIN6_PG_CONFIG, 533 DOMAIN6_POWER_GATE, power_gate); 534 535 REG_WAIT(DOMAIN6_PG_STATUS, 536 DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 537 1, 1000); 538 break; 539 case 4: /* DCHUBP4 */ 540 REG_UPDATE(DOMAIN8_PG_CONFIG, 541 DOMAIN8_POWER_GATE, power_gate); 542 543 REG_WAIT(DOMAIN8_PG_STATUS, 544 DOMAIN8_PGFSM_PWR_STATUS, pwr_status, 545 1, 1000); 546 break; 547 case 5: /* DCHUBP5 */ 548 /* 549 * Do not power gate DCHUB5, should be left at HW default, power on permanently. 550 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 551 * reset. 552 * REG_UPDATE(DOMAIN10_PG_CONFIG, 553 * DOMAIN10_POWER_GATE, power_gate); 554 * 555 * REG_WAIT(DOMAIN10_PG_STATUS, 556 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status, 557 * 1, 1000); 558 */ 559 break; 560 default: 561 BREAK_TO_DEBUGGER(); 562 break; 563 } 564 } 565 566 567 /* disable HW used by plane. 568 * note: cannot disable until disconnect is complete 569 */ 570 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 571 { 572 struct dce_hwseq *hws = dc->hwseq; 573 struct hubp *hubp = pipe_ctx->plane_res.hubp; 574 struct dpp *dpp = pipe_ctx->plane_res.dpp; 575 576 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); 577 578 /* In flip immediate with pipe splitting case GSL is used for 579 * synchronization so we must disable it when the plane is disabled. 580 */ 581 if (pipe_ctx->stream_res.gsl_group != 0) 582 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false); 583 584 dc->hwss.set_flip_control_gsl(pipe_ctx, false); 585 586 hubp->funcs->hubp_clk_cntl(hubp, false); 587 588 dpp->funcs->dpp_dppclk_control(dpp, false, false); 589 590 hubp->power_gated = true; 591 592 hws->funcs.plane_atomic_power_down(dc, 593 pipe_ctx->plane_res.dpp, 594 pipe_ctx->plane_res.hubp); 595 596 pipe_ctx->stream = NULL; 597 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); 598 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); 599 pipe_ctx->top_pipe = NULL; 600 pipe_ctx->bottom_pipe = NULL; 601 pipe_ctx->plane_state = NULL; 602 } 603 604 605 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) 606 { 607 DC_LOGGER_INIT(dc->ctx->logger); 608 609 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) 610 return; 611 612 dcn20_plane_atomic_disable(dc, pipe_ctx); 613 614 DC_LOG_DC("Power down front end %d\n", 615 pipe_ctx->pipe_idx); 616 } 617 618 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 619 int opp_cnt) 620 { 621 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 622 int flow_ctrl_cnt; 623 624 if (opp_cnt >= 2) 625 hblank_halved = true; 626 627 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 628 stream->timing.h_border_left - 629 stream->timing.h_border_right; 630 631 if (hblank_halved) 632 flow_ctrl_cnt /= 2; 633 634 /* ODM combine 4:1 case */ 635 if (opp_cnt == 4) 636 flow_ctrl_cnt /= 2; 637 638 return flow_ctrl_cnt; 639 } 640 641 enum dc_status dcn20_enable_stream_timing( 642 struct pipe_ctx *pipe_ctx, 643 struct dc_state *context, 644 struct dc *dc) 645 { 646 struct dce_hwseq *hws = dc->hwseq; 647 struct dc_stream_state *stream = pipe_ctx->stream; 648 struct drr_params params = {0}; 649 unsigned int event_triggers = 0; 650 struct pipe_ctx *odm_pipe; 651 int opp_cnt = 1; 652 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 653 bool interlace = stream->timing.flags.INTERLACE; 654 int i; 655 struct mpc_dwb_flow_control flow_control; 656 struct mpc *mpc = dc->res_pool->mpc; 657 bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing)); 658 659 /* by upper caller loop, pipe0 is parent pipe and be called first. 660 * back end is set up by for pipe0. Other children pipe share back end 661 * with pipe 0. No program is needed. 662 */ 663 if (pipe_ctx->top_pipe != NULL) 664 return DC_OK; 665 666 /* TODO check if timing_changed, disable stream if timing changed */ 667 668 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 669 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 670 opp_cnt++; 671 } 672 673 if (opp_cnt > 1) 674 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 675 pipe_ctx->stream_res.tg, 676 opp_inst, opp_cnt, 677 &pipe_ctx->stream->timing); 678 679 /* HW program guide assume display already disable 680 * by unplug sequence. OTG assume stop. 681 */ 682 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); 683 684 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 685 pipe_ctx->clock_source, 686 &pipe_ctx->stream_res.pix_clk_params, 687 &pipe_ctx->pll_settings)) { 688 BREAK_TO_DEBUGGER(); 689 return DC_ERROR_UNEXPECTED; 690 } 691 692 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal))) 693 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx); 694 695 pipe_ctx->stream_res.tg->funcs->program_timing( 696 pipe_ctx->stream_res.tg, 697 &stream->timing, 698 pipe_ctx->pipe_dlg_param.vready_offset, 699 pipe_ctx->pipe_dlg_param.vstartup_start, 700 pipe_ctx->pipe_dlg_param.vupdate_offset, 701 pipe_ctx->pipe_dlg_param.vupdate_width, 702 pipe_ctx->stream->signal, 703 true); 704 705 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 706 flow_control.flow_ctrl_mode = 0; 707 flow_control.flow_ctrl_cnt0 = 0x80; 708 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt); 709 if (mpc->funcs->set_out_rate_control) { 710 for (i = 0; i < opp_cnt; ++i) { 711 mpc->funcs->set_out_rate_control( 712 mpc, opp_inst[i], 713 true, 714 rate_control_2x_pclk, 715 &flow_control); 716 } 717 } 718 719 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 720 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 721 odm_pipe->stream_res.opp, 722 true); 723 724 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 725 pipe_ctx->stream_res.opp, 726 true); 727 728 hws->funcs.blank_pixel_data(dc, pipe_ctx, true); 729 730 /* VTG is within DCHUB command block. DCFCLK is always on */ 731 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { 732 BREAK_TO_DEBUGGER(); 733 return DC_ERROR_UNEXPECTED; 734 } 735 736 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp); 737 738 params.vertical_total_min = stream->adjust.v_total_min; 739 params.vertical_total_max = stream->adjust.v_total_max; 740 params.vertical_total_mid = stream->adjust.v_total_mid; 741 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num; 742 if (pipe_ctx->stream_res.tg->funcs->set_drr) 743 pipe_ctx->stream_res.tg->funcs->set_drr( 744 pipe_ctx->stream_res.tg, ¶ms); 745 746 // DRR should set trigger event to monitor surface update event 747 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 748 event_triggers = 0x80; 749 /* Event triggers and num frames initialized for DRR, but can be 750 * later updated for PSR use. Note DRR trigger events are generated 751 * regardless of whether num frames met. 752 */ 753 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 754 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 755 pipe_ctx->stream_res.tg, event_triggers, 2); 756 757 /* TODO program crtc source select for non-virtual signal*/ 758 /* TODO program FMT */ 759 /* TODO setup link_enc */ 760 /* TODO set stream attributes */ 761 /* TODO program audio */ 762 /* TODO enable stream if timing changed */ 763 /* TODO unblank stream if DP */ 764 765 return DC_OK; 766 } 767 768 void dcn20_program_output_csc(struct dc *dc, 769 struct pipe_ctx *pipe_ctx, 770 enum dc_color_space colorspace, 771 uint16_t *matrix, 772 int opp_id) 773 { 774 struct mpc *mpc = dc->res_pool->mpc; 775 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; 776 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 777 778 if (mpc->funcs->power_on_mpc_mem_pwr) 779 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 780 781 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 782 if (mpc->funcs->set_output_csc != NULL) 783 mpc->funcs->set_output_csc(mpc, 784 opp_id, 785 matrix, 786 ocsc_mode); 787 } else { 788 if (mpc->funcs->set_ocsc_default != NULL) 789 mpc->funcs->set_ocsc_default(mpc, 790 opp_id, 791 colorspace, 792 ocsc_mode); 793 } 794 } 795 796 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 797 const struct dc_stream_state *stream) 798 { 799 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 800 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 801 struct pwl_params *params = NULL; 802 /* 803 * program OGAM only for the top pipe 804 * if there is a pipe split then fix diagnostic is required: 805 * how to pass OGAM parameter for stream. 806 * if programming for all pipes is required then remove condition 807 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic. 808 */ 809 if (mpc->funcs->power_on_mpc_mem_pwr) 810 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 811 if (pipe_ctx->top_pipe == NULL 812 && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 813 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 814 params = &stream->out_transfer_func->pwl; 815 else if (pipe_ctx->stream->out_transfer_func->type == 816 TF_TYPE_DISTRIBUTED_POINTS && 817 cm_helper_translate_curve_to_hw_format( 818 stream->out_transfer_func, 819 &mpc->blender_params, false)) 820 params = &mpc->blender_params; 821 /* 822 * there is no ROM 823 */ 824 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 825 BREAK_TO_DEBUGGER(); 826 } 827 /* 828 * if above if is not executed then 'params' equal to 0 and set in bypass 829 */ 830 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 831 832 return true; 833 } 834 835 bool dcn20_set_blend_lut( 836 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 837 { 838 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 839 bool result = true; 840 struct pwl_params *blend_lut = NULL; 841 842 if (plane_state->blend_tf) { 843 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 844 blend_lut = &plane_state->blend_tf->pwl; 845 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 846 cm_helper_translate_curve_to_hw_format( 847 plane_state->blend_tf, 848 &dpp_base->regamma_params, false); 849 blend_lut = &dpp_base->regamma_params; 850 } 851 } 852 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); 853 854 return result; 855 } 856 857 bool dcn20_set_shaper_3dlut( 858 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 859 { 860 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 861 bool result = true; 862 struct pwl_params *shaper_lut = NULL; 863 864 if (plane_state->in_shaper_func) { 865 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 866 shaper_lut = &plane_state->in_shaper_func->pwl; 867 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 868 cm_helper_translate_curve_to_hw_format( 869 plane_state->in_shaper_func, 870 &dpp_base->shaper_params, true); 871 shaper_lut = &dpp_base->shaper_params; 872 } 873 } 874 875 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); 876 if (plane_state->lut3d_func && 877 plane_state->lut3d_func->state.bits.initialized == 1) 878 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, 879 &plane_state->lut3d_func->lut_3d); 880 else 881 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); 882 883 return result; 884 } 885 886 bool dcn20_set_input_transfer_func(struct dc *dc, 887 struct pipe_ctx *pipe_ctx, 888 const struct dc_plane_state *plane_state) 889 { 890 struct dce_hwseq *hws = dc->hwseq; 891 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 892 const struct dc_transfer_func *tf = NULL; 893 bool result = true; 894 bool use_degamma_ram = false; 895 896 if (dpp_base == NULL || plane_state == NULL) 897 return false; 898 899 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); 900 hws->funcs.set_blend_lut(pipe_ctx, plane_state); 901 902 if (plane_state->in_transfer_func) 903 tf = plane_state->in_transfer_func; 904 905 906 if (tf == NULL) { 907 dpp_base->funcs->dpp_set_degamma(dpp_base, 908 IPP_DEGAMMA_MODE_BYPASS); 909 return true; 910 } 911 912 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS) 913 use_degamma_ram = true; 914 915 if (use_degamma_ram == true) { 916 if (tf->type == TF_TYPE_HWPWL) 917 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 918 &tf->pwl); 919 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 920 cm_helper_translate_curve_to_degamma_hw_format(tf, 921 &dpp_base->degamma_params); 922 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 923 &dpp_base->degamma_params); 924 } 925 return true; 926 } 927 /* handle here the optimized cases when de-gamma ROM could be used. 928 * 929 */ 930 if (tf->type == TF_TYPE_PREDEFINED) { 931 switch (tf->tf) { 932 case TRANSFER_FUNCTION_SRGB: 933 dpp_base->funcs->dpp_set_degamma(dpp_base, 934 IPP_DEGAMMA_MODE_HW_sRGB); 935 break; 936 case TRANSFER_FUNCTION_BT709: 937 dpp_base->funcs->dpp_set_degamma(dpp_base, 938 IPP_DEGAMMA_MODE_HW_xvYCC); 939 break; 940 case TRANSFER_FUNCTION_LINEAR: 941 dpp_base->funcs->dpp_set_degamma(dpp_base, 942 IPP_DEGAMMA_MODE_BYPASS); 943 break; 944 case TRANSFER_FUNCTION_PQ: 945 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL); 946 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params); 947 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params); 948 result = true; 949 break; 950 default: 951 result = false; 952 break; 953 } 954 } else if (tf->type == TF_TYPE_BYPASS) 955 dpp_base->funcs->dpp_set_degamma(dpp_base, 956 IPP_DEGAMMA_MODE_BYPASS); 957 else { 958 /* 959 * if we are here, we did not handle correctly. 960 * fix is required for this use case 961 */ 962 BREAK_TO_DEBUGGER(); 963 dpp_base->funcs->dpp_set_degamma(dpp_base, 964 IPP_DEGAMMA_MODE_BYPASS); 965 } 966 967 return result; 968 } 969 970 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 971 { 972 struct pipe_ctx *odm_pipe; 973 int opp_cnt = 1; 974 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 975 976 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 977 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 978 opp_cnt++; 979 } 980 981 if (opp_cnt > 1) 982 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 983 pipe_ctx->stream_res.tg, 984 opp_inst, opp_cnt, 985 &pipe_ctx->stream->timing); 986 else 987 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 988 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 989 } 990 991 void dcn20_blank_pixel_data( 992 struct dc *dc, 993 struct pipe_ctx *pipe_ctx, 994 bool blank) 995 { 996 struct tg_color black_color = {0}; 997 struct stream_resource *stream_res = &pipe_ctx->stream_res; 998 struct dc_stream_state *stream = pipe_ctx->stream; 999 enum dc_color_space color_space = stream->output_color_space; 1000 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; 1001 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; 1002 struct pipe_ctx *odm_pipe; 1003 int odm_cnt = 1; 1004 1005 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 1006 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; 1007 1008 if (stream->link->test_pattern_enabled) 1009 return; 1010 1011 /* get opp dpg blank color */ 1012 color_space_to_black_color(dc, color_space, &black_color); 1013 1014 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1015 odm_cnt++; 1016 1017 width = width / odm_cnt; 1018 1019 if (blank) { 1020 dc->hwss.set_abm_immediate_disable(pipe_ctx); 1021 1022 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { 1023 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; 1024 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; 1025 } 1026 } else { 1027 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; 1028 } 1029 1030 dc->hwss.set_disp_pattern_generator(dc, 1031 pipe_ctx, 1032 test_pattern, 1033 test_pattern_color_space, 1034 stream->timing.display_color_depth, 1035 &black_color, 1036 width, 1037 height, 1038 0); 1039 1040 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1041 dc->hwss.set_disp_pattern_generator(dc, 1042 odm_pipe, 1043 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ? 1044 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern, 1045 test_pattern_color_space, 1046 stream->timing.display_color_depth, 1047 &black_color, 1048 width, 1049 height, 1050 0); 1051 } 1052 1053 if (!blank) 1054 if (stream_res->abm) { 1055 dc->hwss.set_pipe(pipe_ctx); 1056 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level); 1057 } 1058 } 1059 1060 1061 static void dcn20_power_on_plane( 1062 struct dce_hwseq *hws, 1063 struct pipe_ctx *pipe_ctx) 1064 { 1065 DC_LOGGER_INIT(hws->ctx->logger); 1066 if (REG(DC_IP_REQUEST_CNTL)) { 1067 REG_SET(DC_IP_REQUEST_CNTL, 0, 1068 IP_REQUEST_EN, 1); 1069 1070 if (hws->funcs.dpp_pg_control) 1071 hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); 1072 1073 if (hws->funcs.hubp_pg_control) 1074 hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true); 1075 1076 REG_SET(DC_IP_REQUEST_CNTL, 0, 1077 IP_REQUEST_EN, 0); 1078 DC_LOG_DEBUG( 1079 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst); 1080 } 1081 } 1082 1083 void dcn20_enable_plane( 1084 struct dc *dc, 1085 struct pipe_ctx *pipe_ctx, 1086 struct dc_state *context) 1087 { 1088 //if (dc->debug.sanity_checks) { 1089 // dcn10_verify_allow_pstate_change_high(dc); 1090 //} 1091 dcn20_power_on_plane(dc->hwseq, pipe_ctx); 1092 1093 /* enable DCFCLK current DCHUB */ 1094 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); 1095 1096 /* initialize HUBP on power up */ 1097 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); 1098 1099 /* make sure OPP_PIPE_CLOCK_EN = 1 */ 1100 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 1101 pipe_ctx->stream_res.opp, 1102 true); 1103 1104 /* TODO: enable/disable in dm as per update type. 1105 if (plane_state) { 1106 DC_LOG_DC(dc->ctx->logger, 1107 "Pipe:%d 0x%x: addr hi:0x%x, " 1108 "addr low:0x%x, " 1109 "src: %d, %d, %d," 1110 " %d; dst: %d, %d, %d, %d;\n", 1111 pipe_ctx->pipe_idx, 1112 plane_state, 1113 plane_state->address.grph.addr.high_part, 1114 plane_state->address.grph.addr.low_part, 1115 plane_state->src_rect.x, 1116 plane_state->src_rect.y, 1117 plane_state->src_rect.width, 1118 plane_state->src_rect.height, 1119 plane_state->dst_rect.x, 1120 plane_state->dst_rect.y, 1121 plane_state->dst_rect.width, 1122 plane_state->dst_rect.height); 1123 1124 DC_LOG_DC(dc->ctx->logger, 1125 "Pipe %d: width, height, x, y format:%d\n" 1126 "viewport:%d, %d, %d, %d\n" 1127 "recout: %d, %d, %d, %d\n", 1128 pipe_ctx->pipe_idx, 1129 plane_state->format, 1130 pipe_ctx->plane_res.scl_data.viewport.width, 1131 pipe_ctx->plane_res.scl_data.viewport.height, 1132 pipe_ctx->plane_res.scl_data.viewport.x, 1133 pipe_ctx->plane_res.scl_data.viewport.y, 1134 pipe_ctx->plane_res.scl_data.recout.width, 1135 pipe_ctx->plane_res.scl_data.recout.height, 1136 pipe_ctx->plane_res.scl_data.recout.x, 1137 pipe_ctx->plane_res.scl_data.recout.y); 1138 print_rq_dlg_ttu(dc, pipe_ctx); 1139 } 1140 */ 1141 if (dc->vm_pa_config.valid) { 1142 struct vm_system_aperture_param apt; 1143 1144 apt.sys_default.quad_part = 0; 1145 1146 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr; 1147 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr; 1148 1149 // Program system aperture settings 1150 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); 1151 } 1152 1153 if (!pipe_ctx->top_pipe 1154 && pipe_ctx->plane_state 1155 && pipe_ctx->plane_state->flip_int_enabled 1156 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) 1157 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); 1158 1159 // if (dc->debug.sanity_checks) { 1160 // dcn10_verify_allow_pstate_change_high(dc); 1161 // } 1162 } 1163 1164 void dcn20_pipe_control_lock( 1165 struct dc *dc, 1166 struct pipe_ctx *pipe, 1167 bool lock) 1168 { 1169 struct pipe_ctx *temp_pipe; 1170 bool flip_immediate = false; 1171 1172 /* use TG master update lock to lock everything on the TG 1173 * therefore only top pipe need to lock 1174 */ 1175 if (!pipe || pipe->top_pipe) 1176 return; 1177 1178 if (pipe->plane_state != NULL) 1179 flip_immediate = pipe->plane_state->flip_immediate; 1180 1181 if (pipe->stream_res.gsl_group > 0) { 1182 temp_pipe = pipe->bottom_pipe; 1183 while (!flip_immediate && temp_pipe) { 1184 if (temp_pipe->plane_state != NULL) 1185 flip_immediate = temp_pipe->plane_state->flip_immediate; 1186 temp_pipe = temp_pipe->bottom_pipe; 1187 } 1188 } 1189 1190 if (flip_immediate && lock) { 1191 const int TIMEOUT_FOR_FLIP_PENDING = 100000; 1192 int i; 1193 1194 temp_pipe = pipe; 1195 while (temp_pipe) { 1196 if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) { 1197 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) { 1198 if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp)) 1199 break; 1200 udelay(1); 1201 } 1202 1203 /* no reason it should take this long for immediate flips */ 1204 ASSERT(i != TIMEOUT_FOR_FLIP_PENDING); 1205 } 1206 temp_pipe = temp_pipe->bottom_pipe; 1207 } 1208 } 1209 1210 /* In flip immediate and pipe splitting case, we need to use GSL 1211 * for synchronization. Only do setup on locking and on flip type change. 1212 */ 1213 if (lock && (pipe->bottom_pipe != NULL || !flip_immediate)) 1214 if ((flip_immediate && pipe->stream_res.gsl_group == 0) || 1215 (!flip_immediate && pipe->stream_res.gsl_group > 0)) 1216 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate); 1217 1218 if (pipe->plane_state != NULL) 1219 flip_immediate = pipe->plane_state->flip_immediate; 1220 1221 temp_pipe = pipe->bottom_pipe; 1222 while (flip_immediate && temp_pipe) { 1223 if (temp_pipe->plane_state != NULL) 1224 flip_immediate = temp_pipe->plane_state->flip_immediate; 1225 temp_pipe = temp_pipe->bottom_pipe; 1226 } 1227 1228 if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state && 1229 !flip_immediate) 1230 dcn20_setup_gsl_group_as_lock(dc, pipe, false); 1231 1232 if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) { 1233 union dmub_hw_lock_flags hw_locks = { 0 }; 1234 struct dmub_hw_lock_inst_flags inst_flags = { 0 }; 1235 1236 hw_locks.bits.lock_pipe = 1; 1237 inst_flags.otg_inst = pipe->stream_res.tg->inst; 1238 1239 if (pipe->plane_state != NULL) 1240 hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips; 1241 1242 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, 1243 lock, 1244 &hw_locks, 1245 &inst_flags); 1246 } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) { 1247 if (lock) 1248 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); 1249 else 1250 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); 1251 } else { 1252 if (lock) 1253 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1254 else 1255 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1256 } 1257 } 1258 1259 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe) 1260 { 1261 new_pipe->update_flags.raw = 0; 1262 1263 /* Exit on unchanged, unused pipe */ 1264 if (!old_pipe->plane_state && !new_pipe->plane_state) 1265 return; 1266 /* Detect pipe enable/disable */ 1267 if (!old_pipe->plane_state && new_pipe->plane_state) { 1268 new_pipe->update_flags.bits.enable = 1; 1269 new_pipe->update_flags.bits.mpcc = 1; 1270 new_pipe->update_flags.bits.dppclk = 1; 1271 new_pipe->update_flags.bits.hubp_interdependent = 1; 1272 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1273 new_pipe->update_flags.bits.gamut_remap = 1; 1274 new_pipe->update_flags.bits.scaler = 1; 1275 new_pipe->update_flags.bits.viewport = 1; 1276 new_pipe->update_flags.bits.det_size = 1; 1277 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1278 new_pipe->update_flags.bits.odm = 1; 1279 new_pipe->update_flags.bits.global_sync = 1; 1280 } 1281 return; 1282 } 1283 if (old_pipe->plane_state && !new_pipe->plane_state) { 1284 new_pipe->update_flags.bits.disable = 1; 1285 return; 1286 } 1287 1288 /* Detect plane change */ 1289 if (old_pipe->plane_state != new_pipe->plane_state) { 1290 new_pipe->update_flags.bits.plane_changed = true; 1291 } 1292 1293 /* Detect top pipe only changes */ 1294 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1295 /* Detect odm changes */ 1296 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe 1297 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx) 1298 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe) 1299 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe) 1300 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1301 new_pipe->update_flags.bits.odm = 1; 1302 1303 /* Detect global sync changes */ 1304 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset 1305 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start 1306 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset 1307 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) 1308 new_pipe->update_flags.bits.global_sync = 1; 1309 } 1310 1311 if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb) 1312 new_pipe->update_flags.bits.det_size = 1; 1313 1314 /* 1315 * Detect opp / tg change, only set on change, not on enable 1316 * Assume mpcc inst = pipe index, if not this code needs to be updated 1317 * since mpcc is what is affected by these. In fact all of our sequence 1318 * makes this assumption at the moment with how hubp reset is matched to 1319 * same index mpcc reset. 1320 */ 1321 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1322 new_pipe->update_flags.bits.opp_changed = 1; 1323 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg) 1324 new_pipe->update_flags.bits.tg_changed = 1; 1325 1326 /* 1327 * Detect mpcc blending changes, only dpp inst and opp matter here, 1328 * mpccs getting removed/inserted update connected ones during their own 1329 * programming 1330 */ 1331 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp 1332 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1333 new_pipe->update_flags.bits.mpcc = 1; 1334 1335 /* Detect dppclk change */ 1336 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) 1337 new_pipe->update_flags.bits.dppclk = 1; 1338 1339 /* Check for scl update */ 1340 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data))) 1341 new_pipe->update_flags.bits.scaler = 1; 1342 /* Check for vp update */ 1343 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect)) 1344 || memcmp(&old_pipe->plane_res.scl_data.viewport_c, 1345 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect))) 1346 new_pipe->update_flags.bits.viewport = 1; 1347 1348 /* Detect dlg/ttu/rq updates */ 1349 { 1350 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs; 1351 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs; 1352 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs; 1353 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs; 1354 1355 /* Detect pipe interdependent updates */ 1356 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch || 1357 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch || 1358 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c || 1359 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank || 1360 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank || 1361 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip || 1362 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip || 1363 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l || 1364 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c || 1365 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l || 1366 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l || 1367 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c || 1368 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l || 1369 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c || 1370 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 || 1371 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 || 1372 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank || 1373 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) { 1374 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch; 1375 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch; 1376 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c; 1377 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank; 1378 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank; 1379 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip; 1380 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip; 1381 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l; 1382 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c; 1383 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l; 1384 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l; 1385 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c; 1386 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l; 1387 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c; 1388 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0; 1389 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1; 1390 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank; 1391 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip; 1392 new_pipe->update_flags.bits.hubp_interdependent = 1; 1393 } 1394 /* Detect any other updates to ttu/rq/dlg */ 1395 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) || 1396 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) || 1397 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs))) 1398 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1399 } 1400 } 1401 1402 static void dcn20_update_dchubp_dpp( 1403 struct dc *dc, 1404 struct pipe_ctx *pipe_ctx, 1405 struct dc_state *context) 1406 { 1407 struct dce_hwseq *hws = dc->hwseq; 1408 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1409 struct dpp *dpp = pipe_ctx->plane_res.dpp; 1410 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1411 bool viewport_changed = false; 1412 1413 if (pipe_ctx->update_flags.bits.dppclk) 1414 dpp->funcs->dpp_dppclk_control(dpp, false, true); 1415 1416 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG 1417 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. 1418 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG 1419 */ 1420 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) { 1421 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst); 1422 1423 hubp->funcs->hubp_setup( 1424 hubp, 1425 &pipe_ctx->dlg_regs, 1426 &pipe_ctx->ttu_regs, 1427 &pipe_ctx->rq_regs, 1428 &pipe_ctx->pipe_dlg_param); 1429 1430 if (hubp->funcs->set_unbounded_requesting) 1431 hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req); 1432 } 1433 if (pipe_ctx->update_flags.bits.hubp_interdependent) 1434 hubp->funcs->hubp_setup_interdependent( 1435 hubp, 1436 &pipe_ctx->dlg_regs, 1437 &pipe_ctx->ttu_regs); 1438 1439 if (pipe_ctx->update_flags.bits.enable || 1440 pipe_ctx->update_flags.bits.plane_changed || 1441 plane_state->update_flags.bits.bpp_change || 1442 plane_state->update_flags.bits.input_csc_change || 1443 plane_state->update_flags.bits.color_space_change || 1444 plane_state->update_flags.bits.coeff_reduction_change) { 1445 struct dc_bias_and_scale bns_params = {0}; 1446 1447 // program the input csc 1448 dpp->funcs->dpp_setup(dpp, 1449 plane_state->format, 1450 EXPANSION_MODE_ZERO, 1451 plane_state->input_csc_color_matrix, 1452 plane_state->color_space, 1453 NULL); 1454 1455 if (dpp->funcs->dpp_program_bias_and_scale) { 1456 //TODO :for CNVC set scale and bias registers if necessary 1457 build_prescale_params(&bns_params, plane_state); 1458 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); 1459 } 1460 } 1461 1462 if (pipe_ctx->update_flags.bits.mpcc 1463 || pipe_ctx->update_flags.bits.plane_changed 1464 || plane_state->update_flags.bits.global_alpha_change 1465 || plane_state->update_flags.bits.per_pixel_alpha_change) { 1466 // MPCC inst is equal to pipe index in practice 1467 int mpcc_inst = hubp->inst; 1468 int opp_inst; 1469 int opp_count = dc->res_pool->pipe_count; 1470 1471 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) { 1472 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) { 1473 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); 1474 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; 1475 break; 1476 } 1477 } 1478 hws->funcs.update_mpcc(dc, pipe_ctx); 1479 } 1480 1481 if (pipe_ctx->update_flags.bits.scaler || 1482 plane_state->update_flags.bits.scaling_change || 1483 plane_state->update_flags.bits.position_change || 1484 plane_state->update_flags.bits.per_pixel_alpha_change || 1485 pipe_ctx->stream->update_flags.bits.scaling) { 1486 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; 1487 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP); 1488 /* scaler configuration */ 1489 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( 1490 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); 1491 } 1492 1493 if (pipe_ctx->update_flags.bits.viewport || 1494 (context == dc->current_state && plane_state->update_flags.bits.position_change) || 1495 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) || 1496 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) { 1497 1498 hubp->funcs->mem_program_viewport( 1499 hubp, 1500 &pipe_ctx->plane_res.scl_data.viewport, 1501 &pipe_ctx->plane_res.scl_data.viewport_c); 1502 viewport_changed = true; 1503 } 1504 1505 /* Any updates are handled in dc interface, just need to apply existing for plane enable */ 1506 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || 1507 pipe_ctx->update_flags.bits.scaler || viewport_changed == true) && 1508 pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { 1509 dc->hwss.set_cursor_position(pipe_ctx); 1510 dc->hwss.set_cursor_attribute(pipe_ctx); 1511 1512 if (dc->hwss.set_cursor_sdr_white_level) 1513 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 1514 } 1515 1516 /* Any updates are handled in dc interface, just need 1517 * to apply existing for plane enable / opp change */ 1518 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed 1519 || pipe_ctx->stream->update_flags.bits.gamut_remap 1520 || pipe_ctx->stream->update_flags.bits.out_csc) { 1521 /* dpp/cm gamut remap*/ 1522 dc->hwss.program_gamut_remap(pipe_ctx); 1523 1524 /*call the dcn2 method which uses mpc csc*/ 1525 dc->hwss.program_output_csc(dc, 1526 pipe_ctx, 1527 pipe_ctx->stream->output_color_space, 1528 pipe_ctx->stream->csc_color_matrix.matrix, 1529 hubp->opp_id); 1530 } 1531 1532 if (pipe_ctx->update_flags.bits.enable || 1533 pipe_ctx->update_flags.bits.plane_changed || 1534 pipe_ctx->update_flags.bits.opp_changed || 1535 plane_state->update_flags.bits.pixel_format_change || 1536 plane_state->update_flags.bits.horizontal_mirror_change || 1537 plane_state->update_flags.bits.rotation_change || 1538 plane_state->update_flags.bits.swizzle_change || 1539 plane_state->update_flags.bits.dcc_change || 1540 plane_state->update_flags.bits.bpp_change || 1541 plane_state->update_flags.bits.scaling_change || 1542 plane_state->update_flags.bits.plane_size_change) { 1543 struct plane_size size = plane_state->plane_size; 1544 1545 size.surface_size = pipe_ctx->plane_res.scl_data.viewport; 1546 hubp->funcs->hubp_program_surface_config( 1547 hubp, 1548 plane_state->format, 1549 &plane_state->tiling_info, 1550 &size, 1551 plane_state->rotation, 1552 &plane_state->dcc, 1553 plane_state->horizontal_mirror, 1554 0); 1555 hubp->power_gated = false; 1556 } 1557 1558 if (pipe_ctx->update_flags.bits.enable || 1559 pipe_ctx->update_flags.bits.plane_changed || 1560 plane_state->update_flags.bits.addr_update) 1561 hws->funcs.update_plane_addr(dc, pipe_ctx); 1562 1563 1564 1565 if (pipe_ctx->update_flags.bits.enable) 1566 hubp->funcs->set_blank(hubp, false); 1567 } 1568 1569 1570 static void dcn20_program_pipe( 1571 struct dc *dc, 1572 struct pipe_ctx *pipe_ctx, 1573 struct dc_state *context) 1574 { 1575 struct dce_hwseq *hws = dc->hwseq; 1576 /* Only need to unblank on top pipe */ 1577 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level) 1578 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) 1579 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible); 1580 1581 /* Only update TG on top pipe */ 1582 if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe 1583 && !pipe_ctx->prev_odm_pipe) { 1584 1585 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1586 pipe_ctx->stream_res.tg, 1587 pipe_ctx->pipe_dlg_param.vready_offset, 1588 pipe_ctx->pipe_dlg_param.vstartup_start, 1589 pipe_ctx->pipe_dlg_param.vupdate_offset, 1590 pipe_ctx->pipe_dlg_param.vupdate_width); 1591 1592 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); 1593 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); 1594 1595 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1596 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true); 1597 1598 if (hws->funcs.setup_vupdate_interrupt) 1599 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1600 } 1601 1602 if (pipe_ctx->update_flags.bits.odm) 1603 hws->funcs.update_odm(dc, context, pipe_ctx); 1604 1605 if (pipe_ctx->update_flags.bits.enable) { 1606 dcn20_enable_plane(dc, pipe_ctx, context); 1607 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes) 1608 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub); 1609 } 1610 1611 if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size) 1612 dc->res_pool->hubbub->funcs->program_det_size( 1613 dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb); 1614 1615 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) 1616 dcn20_update_dchubp_dpp(dc, pipe_ctx, context); 1617 1618 if (pipe_ctx->update_flags.bits.enable 1619 || pipe_ctx->plane_state->update_flags.bits.hdr_mult) 1620 hws->funcs.set_hdr_multiplier(pipe_ctx); 1621 1622 if (pipe_ctx->update_flags.bits.enable || 1623 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 1624 pipe_ctx->plane_state->update_flags.bits.gamma_change) 1625 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 1626 1627 /* dcn10_translate_regamma_to_hw_format takes 750us to finish 1628 * only do gamma programming for powering on, internal memcmp to avoid 1629 * updating on slave planes 1630 */ 1631 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf) 1632 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 1633 1634 /* If the pipe has been enabled or has a different opp, we 1635 * should reprogram the fmt. This deals with cases where 1636 * interation between mpc and odm combine on different streams 1637 * causes a different pipe to be chosen to odm combine with. 1638 */ 1639 if (pipe_ctx->update_flags.bits.enable 1640 || pipe_ctx->update_flags.bits.opp_changed) { 1641 1642 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1643 pipe_ctx->stream_res.opp, 1644 COLOR_SPACE_YCBCR601, 1645 pipe_ctx->stream->timing.display_color_depth, 1646 pipe_ctx->stream->signal); 1647 1648 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1649 pipe_ctx->stream_res.opp, 1650 &pipe_ctx->stream->bit_depth_params, 1651 &pipe_ctx->stream->clamping); 1652 } 1653 } 1654 1655 void dcn20_program_front_end_for_ctx( 1656 struct dc *dc, 1657 struct dc_state *context) 1658 { 1659 int i; 1660 struct dce_hwseq *hws = dc->hwseq; 1661 DC_LOGGER_INIT(dc->ctx->logger); 1662 1663 /* Carry over GSL groups in case the context is changing. */ 1664 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1665 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1666 struct pipe_ctx *old_pipe_ctx = 1667 &dc->current_state->res_ctx.pipe_ctx[i]; 1668 1669 if (pipe_ctx->stream == old_pipe_ctx->stream) 1670 pipe_ctx->stream_res.gsl_group = 1671 old_pipe_ctx->stream_res.gsl_group; 1672 } 1673 1674 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) { 1675 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1676 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1677 1678 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) { 1679 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips); 1680 /*turn off triple buffer for full update*/ 1681 dc->hwss.program_triplebuffer( 1682 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); 1683 } 1684 } 1685 } 1686 1687 /* Set pipe update flags and lock pipes */ 1688 for (i = 0; i < dc->res_pool->pipe_count; i++) 1689 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i], 1690 &context->res_ctx.pipe_ctx[i]); 1691 1692 /* OTG blank before disabling all front ends */ 1693 for (i = 0; i < dc->res_pool->pipe_count; i++) 1694 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1695 && !context->res_ctx.pipe_ctx[i].top_pipe 1696 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe 1697 && context->res_ctx.pipe_ctx[i].stream) 1698 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); 1699 1700 1701 /* Disconnect mpcc */ 1702 for (i = 0; i < dc->res_pool->pipe_count; i++) 1703 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1704 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) { 1705 struct hubbub *hubbub = dc->res_pool->hubbub; 1706 1707 if (hubbub->funcs->program_det_size && context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1708 hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0); 1709 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1710 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); 1711 } 1712 1713 /* 1714 * Program all updated pipes, order matters for mpcc setup. Start with 1715 * top pipe and program all pipes that follow in order 1716 */ 1717 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1718 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1719 1720 if (pipe->plane_state && !pipe->top_pipe) { 1721 while (pipe) { 1722 if (hws->funcs.program_pipe) 1723 hws->funcs.program_pipe(dc, pipe, context); 1724 else 1725 dcn20_program_pipe(dc, pipe, context); 1726 1727 pipe = pipe->bottom_pipe; 1728 } 1729 } 1730 /* Program secondary blending tree and writeback pipes */ 1731 pipe = &context->res_ctx.pipe_ctx[i]; 1732 if (!pipe->top_pipe && !pipe->prev_odm_pipe 1733 && pipe->stream && pipe->stream->num_wb_info > 0 1734 && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw) 1735 || pipe->stream->update_flags.raw) 1736 && hws->funcs.program_all_writeback_pipes_in_tree) 1737 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context); 1738 } 1739 } 1740 1741 void dcn20_post_unlock_program_front_end( 1742 struct dc *dc, 1743 struct dc_state *context) 1744 { 1745 int i; 1746 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100; 1747 struct dce_hwseq *hwseq = dc->hwseq; 1748 1749 DC_LOGGER_INIT(dc->ctx->logger); 1750 1751 for (i = 0; i < dc->res_pool->pipe_count; i++) 1752 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1753 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1754 1755 /* 1756 * If we are enabling a pipe, we need to wait for pending clear as this is a critical 1757 * part of the enable operation otherwise, DM may request an immediate flip which 1758 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which 1759 * is unsupported on DCN. 1760 */ 1761 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1762 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1763 1764 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable) { 1765 struct hubp *hubp = pipe->plane_res.hubp; 1766 int j = 0; 1767 1768 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000 1769 && hubp->funcs->hubp_is_flip_pending(hubp); j++) 1770 mdelay(1); 1771 } 1772 } 1773 1774 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1775 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1776 struct pipe_ctx *mpcc_pipe; 1777 1778 if (pipe->vtp_locked) { 1779 dc->hwseq->funcs.wait_for_blank_complete(pipe->stream_res.opp); 1780 pipe->plane_res.hubp->funcs->set_blank(pipe->plane_res.hubp, true); 1781 pipe->vtp_locked = false; 1782 1783 for (mpcc_pipe = pipe->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe) 1784 mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true); 1785 1786 for (i = 0; i < dc->res_pool->pipe_count; i++) 1787 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1788 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1789 } 1790 } 1791 /* WA to apply WM setting*/ 1792 if (hwseq->wa.DEGVIDCN21) 1793 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub); 1794 1795 1796 /* WA for stutter underflow during MPO transitions when adding 2nd plane */ 1797 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) { 1798 1799 if (dc->current_state->stream_status[0].plane_count == 1 && 1800 context->stream_status[0].plane_count > 1) { 1801 1802 struct timing_generator *tg = dc->res_pool->timing_generators[0]; 1803 1804 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false); 1805 1806 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true; 1807 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg); 1808 } 1809 } 1810 } 1811 1812 void dcn20_prepare_bandwidth( 1813 struct dc *dc, 1814 struct dc_state *context) 1815 { 1816 struct hubbub *hubbub = dc->res_pool->hubbub; 1817 1818 dc->clk_mgr->funcs->update_clocks( 1819 dc->clk_mgr, 1820 context, 1821 false); 1822 1823 /* program dchubbub watermarks */ 1824 dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub, 1825 &context->bw_ctx.bw.dcn.watermarks, 1826 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1827 false); 1828 /* decrease compbuf size */ 1829 if (hubbub->funcs->program_compbuf_size) 1830 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, false); 1831 } 1832 1833 void dcn20_optimize_bandwidth( 1834 struct dc *dc, 1835 struct dc_state *context) 1836 { 1837 struct hubbub *hubbub = dc->res_pool->hubbub; 1838 1839 /* program dchubbub watermarks */ 1840 hubbub->funcs->program_watermarks(hubbub, 1841 &context->bw_ctx.bw.dcn.watermarks, 1842 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1843 true); 1844 1845 dc->clk_mgr->funcs->update_clocks( 1846 dc->clk_mgr, 1847 context, 1848 true); 1849 /* increase compbuf size */ 1850 if (hubbub->funcs->program_compbuf_size) 1851 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true); 1852 } 1853 1854 bool dcn20_update_bandwidth( 1855 struct dc *dc, 1856 struct dc_state *context) 1857 { 1858 int i; 1859 struct dce_hwseq *hws = dc->hwseq; 1860 1861 /* recalculate DML parameters */ 1862 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) 1863 return false; 1864 1865 /* apply updated bandwidth parameters */ 1866 dc->hwss.prepare_bandwidth(dc, context); 1867 1868 /* update hubp configs for all pipes */ 1869 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1870 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1871 1872 if (pipe_ctx->plane_state == NULL) 1873 continue; 1874 1875 if (pipe_ctx->top_pipe == NULL) { 1876 bool blank = !is_pipe_tree_visible(pipe_ctx); 1877 1878 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1879 pipe_ctx->stream_res.tg, 1880 pipe_ctx->pipe_dlg_param.vready_offset, 1881 pipe_ctx->pipe_dlg_param.vstartup_start, 1882 pipe_ctx->pipe_dlg_param.vupdate_offset, 1883 pipe_ctx->pipe_dlg_param.vupdate_width); 1884 1885 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1886 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false); 1887 1888 if (pipe_ctx->prev_odm_pipe == NULL) 1889 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank); 1890 1891 if (hws->funcs.setup_vupdate_interrupt) 1892 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1893 } 1894 1895 pipe_ctx->plane_res.hubp->funcs->hubp_setup( 1896 pipe_ctx->plane_res.hubp, 1897 &pipe_ctx->dlg_regs, 1898 &pipe_ctx->ttu_regs, 1899 &pipe_ctx->rq_regs, 1900 &pipe_ctx->pipe_dlg_param); 1901 } 1902 1903 return true; 1904 } 1905 1906 void dcn20_enable_writeback( 1907 struct dc *dc, 1908 struct dc_writeback_info *wb_info, 1909 struct dc_state *context) 1910 { 1911 struct dwbc *dwb; 1912 struct mcif_wb *mcif_wb; 1913 struct timing_generator *optc; 1914 1915 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 1916 ASSERT(wb_info->wb_enabled); 1917 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 1918 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 1919 1920 /* set the OPTC source mux */ 1921 optc = dc->res_pool->timing_generators[dwb->otg_inst]; 1922 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); 1923 /* set MCIF_WB buffer and arbitration configuration */ 1924 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 1925 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 1926 /* Enable MCIF_WB */ 1927 mcif_wb->funcs->enable_mcif(mcif_wb); 1928 /* Enable DWB */ 1929 dwb->funcs->enable(dwb, &wb_info->dwb_params); 1930 /* TODO: add sequence to enable/disable warmup */ 1931 } 1932 1933 void dcn20_disable_writeback( 1934 struct dc *dc, 1935 unsigned int dwb_pipe_inst) 1936 { 1937 struct dwbc *dwb; 1938 struct mcif_wb *mcif_wb; 1939 1940 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); 1941 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; 1942 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; 1943 1944 dwb->funcs->disable(dwb); 1945 mcif_wb->funcs->disable_mcif(mcif_wb); 1946 } 1947 1948 bool dcn20_wait_for_blank_complete( 1949 struct output_pixel_processor *opp) 1950 { 1951 int counter; 1952 1953 for (counter = 0; counter < 1000; counter++) { 1954 if (opp->funcs->dpg_is_blanked(opp)) 1955 break; 1956 1957 udelay(100); 1958 } 1959 1960 if (counter == 1000) { 1961 dm_error("DC: failed to blank crtc!\n"); 1962 return false; 1963 } 1964 1965 return true; 1966 } 1967 1968 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) 1969 { 1970 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1971 1972 if (!hubp) 1973 return false; 1974 return hubp->funcs->dmdata_status_done(hubp); 1975 } 1976 1977 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 1978 { 1979 struct dce_hwseq *hws = dc->hwseq; 1980 1981 if (pipe_ctx->stream_res.dsc) { 1982 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1983 1984 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); 1985 while (odm_pipe) { 1986 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true); 1987 odm_pipe = odm_pipe->next_odm_pipe; 1988 } 1989 } 1990 } 1991 1992 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 1993 { 1994 struct dce_hwseq *hws = dc->hwseq; 1995 1996 if (pipe_ctx->stream_res.dsc) { 1997 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1998 1999 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false); 2000 while (odm_pipe) { 2001 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false); 2002 odm_pipe = odm_pipe->next_odm_pipe; 2003 } 2004 } 2005 } 2006 2007 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) 2008 { 2009 struct dc_dmdata_attributes attr = { 0 }; 2010 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2011 2012 attr.dmdata_mode = DMDATA_HW_MODE; 2013 attr.dmdata_size = 2014 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; 2015 attr.address.quad_part = 2016 pipe_ctx->stream->dmdata_address.quad_part; 2017 attr.dmdata_dl_delta = 0; 2018 attr.dmdata_qos_mode = 0; 2019 attr.dmdata_qos_level = 0; 2020 attr.dmdata_repeat = 1; /* always repeat */ 2021 attr.dmdata_updated = 1; 2022 attr.dmdata_sw_data = NULL; 2023 2024 hubp->funcs->dmdata_set_attributes(hubp, &attr); 2025 } 2026 2027 void dcn20_init_vm_ctx( 2028 struct dce_hwseq *hws, 2029 struct dc *dc, 2030 struct dc_virtual_addr_space_config *va_config, 2031 int vmid) 2032 { 2033 struct dcn_hubbub_virt_addr_config config; 2034 2035 if (vmid == 0) { 2036 ASSERT(0); /* VMID cannot be 0 for vm context */ 2037 return; 2038 } 2039 2040 config.page_table_start_addr = va_config->page_table_start_addr; 2041 config.page_table_end_addr = va_config->page_table_end_addr; 2042 config.page_table_block_size = va_config->page_table_block_size_in_bytes; 2043 config.page_table_depth = va_config->page_table_depth; 2044 config.page_table_base_addr = va_config->page_table_base_addr; 2045 2046 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); 2047 } 2048 2049 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 2050 { 2051 struct dcn_hubbub_phys_addr_config config; 2052 2053 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 2054 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 2055 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 2056 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 2057 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 2058 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 2059 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 2060 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 2061 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 2062 config.page_table_default_page_addr = pa_config->page_table_default_page_addr; 2063 2064 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 2065 } 2066 2067 static bool patch_address_for_sbs_tb_stereo( 2068 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) 2069 { 2070 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2071 bool sec_split = pipe_ctx->top_pipe && 2072 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; 2073 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && 2074 (pipe_ctx->stream->timing.timing_3d_format == 2075 TIMING_3D_FORMAT_SIDE_BY_SIDE || 2076 pipe_ctx->stream->timing.timing_3d_format == 2077 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { 2078 *addr = plane_state->address.grph_stereo.left_addr; 2079 plane_state->address.grph_stereo.left_addr = 2080 plane_state->address.grph_stereo.right_addr; 2081 return true; 2082 } 2083 2084 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && 2085 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { 2086 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; 2087 plane_state->address.grph_stereo.right_addr = 2088 plane_state->address.grph_stereo.left_addr; 2089 plane_state->address.grph_stereo.right_meta_addr = 2090 plane_state->address.grph_stereo.left_meta_addr; 2091 } 2092 return false; 2093 } 2094 2095 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) 2096 { 2097 bool addr_patched = false; 2098 PHYSICAL_ADDRESS_LOC addr; 2099 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2100 2101 if (plane_state == NULL) 2102 return; 2103 2104 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); 2105 2106 // Call Helper to track VMID use 2107 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); 2108 2109 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( 2110 pipe_ctx->plane_res.hubp, 2111 &plane_state->address, 2112 plane_state->flip_immediate); 2113 2114 plane_state->status.requested_address = plane_state->address; 2115 2116 if (plane_state->flip_immediate) 2117 plane_state->status.current_address = plane_state->address; 2118 2119 if (addr_patched) 2120 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; 2121 } 2122 2123 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, 2124 struct dc_link_settings *link_settings) 2125 { 2126 struct encoder_unblank_param params = {0}; 2127 struct dc_stream_state *stream = pipe_ctx->stream; 2128 struct dc_link *link = stream->link; 2129 struct dce_hwseq *hws = link->dc->hwseq; 2130 struct pipe_ctx *odm_pipe; 2131 2132 params.opp_cnt = 1; 2133 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 2134 params.opp_cnt++; 2135 } 2136 /* only 3 items below are used by unblank */ 2137 params.timing = pipe_ctx->stream->timing; 2138 2139 params.link_settings.link_rate = link_settings->link_rate; 2140 2141 if (is_dp_128b_132b_signal(pipe_ctx)) { 2142 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 2143 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 2144 pipe_ctx->stream_res.hpo_dp_stream_enc, 2145 pipe_ctx->stream_res.tg->inst); 2146 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 2147 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1) 2148 params.timing.pix_clk_100hz /= 2; 2149 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 2150 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1); 2151 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 2152 } 2153 2154 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 2155 hws->funcs.edp_backlight_control(link, true); 2156 } 2157 } 2158 2159 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx) 2160 { 2161 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2162 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx); 2163 2164 if (start_line < 0) 2165 start_line = 0; 2166 2167 if (tg->funcs->setup_vertical_interrupt2) 2168 tg->funcs->setup_vertical_interrupt2(tg, start_line); 2169 } 2170 2171 static void dcn20_reset_back_end_for_pipe( 2172 struct dc *dc, 2173 struct pipe_ctx *pipe_ctx, 2174 struct dc_state *context) 2175 { 2176 int i; 2177 struct dc_link *link; 2178 DC_LOGGER_INIT(dc->ctx->logger); 2179 if (pipe_ctx->stream_res.stream_enc == NULL) { 2180 pipe_ctx->stream = NULL; 2181 return; 2182 } 2183 2184 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 2185 link = pipe_ctx->stream->link; 2186 /* DPMS may already disable or */ 2187 /* dpms_off status is incorrect due to fastboot 2188 * feature. When system resume from S4 with second 2189 * screen only, the dpms_off would be true but 2190 * VBIOS lit up eDP, so check link status too. 2191 */ 2192 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 2193 core_link_disable_stream(pipe_ctx); 2194 else if (pipe_ctx->stream_res.audio) 2195 dc->hwss.disable_audio_stream(pipe_ctx); 2196 2197 /* free acquired resources */ 2198 if (pipe_ctx->stream_res.audio) { 2199 /*disable az_endpoint*/ 2200 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 2201 2202 /*free audio*/ 2203 if (dc->caps.dynamic_audio == true) { 2204 /*we have to dynamic arbitrate the audio endpoints*/ 2205 /*we free the resource, need reset is_audio_acquired*/ 2206 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 2207 pipe_ctx->stream_res.audio, false); 2208 pipe_ctx->stream_res.audio = NULL; 2209 } 2210 } 2211 } 2212 else if (pipe_ctx->stream_res.dsc) { 2213 dp_set_dsc_enable(pipe_ctx, false); 2214 } 2215 2216 /* by upper caller loop, parent pipe: pipe0, will be reset last. 2217 * back end share by all pipes and will be disable only when disable 2218 * parent pipe. 2219 */ 2220 if (pipe_ctx->top_pipe == NULL) { 2221 2222 dc->hwss.set_abm_immediate_disable(pipe_ctx); 2223 2224 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 2225 2226 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 2227 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 2228 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 2229 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 2230 2231 if (pipe_ctx->stream_res.tg->funcs->set_drr) 2232 pipe_ctx->stream_res.tg->funcs->set_drr( 2233 pipe_ctx->stream_res.tg, NULL); 2234 } 2235 2236 for (i = 0; i < dc->res_pool->pipe_count; i++) 2237 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) 2238 break; 2239 2240 if (i == dc->res_pool->pipe_count) 2241 return; 2242 2243 pipe_ctx->stream = NULL; 2244 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 2245 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 2246 } 2247 2248 void dcn20_reset_hw_ctx_wrap( 2249 struct dc *dc, 2250 struct dc_state *context) 2251 { 2252 int i; 2253 struct dce_hwseq *hws = dc->hwseq; 2254 2255 /* Reset Back End*/ 2256 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 2257 struct pipe_ctx *pipe_ctx_old = 2258 &dc->current_state->res_ctx.pipe_ctx[i]; 2259 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2260 2261 if (!pipe_ctx_old->stream) 2262 continue; 2263 2264 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 2265 continue; 2266 2267 if (!pipe_ctx->stream || 2268 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 2269 struct clock_source *old_clk = pipe_ctx_old->clock_source; 2270 2271 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 2272 if (hws->funcs.enable_stream_gating) 2273 hws->funcs.enable_stream_gating(dc, pipe_ctx); 2274 if (old_clk) 2275 old_clk->funcs->cs_power_down(old_clk); 2276 } 2277 } 2278 } 2279 2280 void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id) 2281 { 2282 struct mpc *mpc = dc->res_pool->mpc; 2283 2284 // input to MPCC is always RGB, by default leave black_color at 0 2285 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) 2286 get_hdr_visual_confirm_color(pipe_ctx, color); 2287 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) 2288 get_surface_visual_confirm_color(pipe_ctx, color); 2289 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) 2290 get_mpctree_visual_confirm_color(pipe_ctx, color); 2291 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE) 2292 get_surface_tile_visual_confirm_color(pipe_ctx, color); 2293 2294 if (mpc->funcs->set_bg_color) 2295 mpc->funcs->set_bg_color(mpc, color, mpcc_id); 2296 } 2297 2298 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 2299 { 2300 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2301 struct mpcc_blnd_cfg blnd_cfg = {0}; 2302 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; 2303 int mpcc_id; 2304 struct mpcc *new_mpcc; 2305 struct mpc *mpc = dc->res_pool->mpc; 2306 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); 2307 2308 if (per_pixel_alpha) 2309 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2310 else 2311 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 2312 2313 blnd_cfg.overlap_only = false; 2314 blnd_cfg.global_gain = 0xff; 2315 2316 if (pipe_ctx->plane_state->global_alpha) 2317 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; 2318 else 2319 blnd_cfg.global_alpha = 0xff; 2320 2321 blnd_cfg.background_color_bpc = 4; 2322 blnd_cfg.bottom_gain_mode = 0; 2323 blnd_cfg.top_gain = 0x1f000; 2324 blnd_cfg.bottom_inside_gain = 0x1f000; 2325 blnd_cfg.bottom_outside_gain = 0x1f000; 2326 blnd_cfg.pre_multiplied_alpha = per_pixel_alpha; 2327 if (pipe_ctx->plane_state->format 2328 == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA) 2329 blnd_cfg.pre_multiplied_alpha = false; 2330 2331 /* 2332 * TODO: remove hack 2333 * Note: currently there is a bug in init_hw such that 2334 * on resume from hibernate, BIOS sets up MPCC0, and 2335 * we do mpcc_remove but the mpcc cannot go to idle 2336 * after remove. This cause us to pick mpcc1 here, 2337 * which causes a pstate hang for yet unknown reason. 2338 */ 2339 mpcc_id = hubp->inst; 2340 2341 /* If there is no full update, don't need to touch MPC tree*/ 2342 if (!pipe_ctx->plane_state->update_flags.bits.full_update && 2343 !pipe_ctx->update_flags.bits.mpcc) { 2344 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); 2345 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); 2346 return; 2347 } 2348 2349 /* check if this MPCC is already being used */ 2350 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 2351 /* remove MPCC if being used */ 2352 if (new_mpcc != NULL) 2353 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); 2354 else 2355 if (dc->debug.sanity_checks) 2356 mpc->funcs->assert_mpcc_idle_before_connect( 2357 dc->res_pool->mpc, mpcc_id); 2358 2359 /* Call MPC to insert new plane */ 2360 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, 2361 mpc_tree_params, 2362 &blnd_cfg, 2363 NULL, 2364 NULL, 2365 hubp->inst, 2366 mpcc_id); 2367 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); 2368 2369 ASSERT(new_mpcc != NULL); 2370 hubp->opp_id = pipe_ctx->stream_res.opp->inst; 2371 hubp->mpcc_id = mpcc_id; 2372 } 2373 2374 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 2375 { 2376 enum dc_lane_count lane_count = 2377 pipe_ctx->stream->link->cur_link_settings.lane_count; 2378 2379 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 2380 struct dc_link *link = pipe_ctx->stream->link; 2381 2382 uint32_t active_total_with_borders; 2383 uint32_t early_control = 0; 2384 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2385 struct link_encoder *link_enc; 2386 2387 if (link->is_dig_mapping_flexible && 2388 link->dc->res_pool->funcs->link_encs_assign) 2389 link_enc = link_enc_cfg_get_link_enc_used_by_stream(link->ctx->dc, pipe_ctx->stream); 2390 else 2391 link_enc = link->link_enc; 2392 ASSERT(link_enc); 2393 2394 /* For MST, there are multiply stream go to only one link. 2395 * connect DIG back_end to front_end while enable_stream and 2396 * disconnect them during disable_stream 2397 * BY this, it is logic clean to separate stream and link 2398 */ 2399 if (is_dp_128b_132b_signal(pipe_ctx)) { 2400 if (pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control) 2401 pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control( 2402 pipe_ctx->stream->ctx->dc->hwseq, true); 2403 setup_dp_hpo_stream(pipe_ctx, true); 2404 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->enable_stream( 2405 pipe_ctx->stream_res.hpo_dp_stream_enc); 2406 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->map_stream_to_link( 2407 pipe_ctx->stream_res.hpo_dp_stream_enc, 2408 pipe_ctx->stream_res.hpo_dp_stream_enc->inst, 2409 link->hpo_dp_link_enc->inst); 2410 } 2411 2412 if (!is_dp_128b_132b_signal(pipe_ctx) && link_enc) 2413 link_enc->funcs->connect_dig_be_to_fe( 2414 link_enc, pipe_ctx->stream_res.stream_enc->id, true); 2415 2416 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2417 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_BE); 2418 2419 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) { 2420 if (link->dc->hwss.program_dmdata_engine) 2421 link->dc->hwss.program_dmdata_engine(pipe_ctx); 2422 } 2423 2424 link->dc->hwss.update_info_frame(pipe_ctx); 2425 2426 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2427 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2428 2429 /* enable early control to avoid corruption on DP monitor*/ 2430 active_total_with_borders = 2431 timing->h_addressable 2432 + timing->h_border_left 2433 + timing->h_border_right; 2434 2435 if (lane_count != 0) 2436 early_control = active_total_with_borders % lane_count; 2437 2438 if (early_control == 0) 2439 early_control = lane_count; 2440 2441 tg->funcs->set_early_control(tg, early_control); 2442 2443 /* enable audio only within mode set */ 2444 if (pipe_ctx->stream_res.audio != NULL) { 2445 if (is_dp_128b_132b_signal(pipe_ctx)) 2446 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.hpo_dp_stream_enc); 2447 else if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2448 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 2449 } 2450 } 2451 2452 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx) 2453 { 2454 struct dc_stream_state *stream = pipe_ctx->stream; 2455 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2456 bool enable = false; 2457 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2458 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) 2459 ? dmdata_dp 2460 : dmdata_hdmi; 2461 2462 /* if using dynamic meta, don't set up generic infopackets */ 2463 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { 2464 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; 2465 enable = true; 2466 } 2467 2468 if (!hubp) 2469 return; 2470 2471 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) 2472 return; 2473 2474 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, 2475 hubp->inst, mode); 2476 } 2477 2478 void dcn20_fpga_init_hw(struct dc *dc) 2479 { 2480 int i, j; 2481 struct dce_hwseq *hws = dc->hwseq; 2482 struct resource_pool *res_pool = dc->res_pool; 2483 struct dc_state *context = dc->current_state; 2484 2485 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 2486 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 2487 2488 // Initialize the dccg 2489 if (res_pool->dccg->funcs->dccg_init) 2490 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 2491 2492 //Enable ability to power gate / don't force power on permanently 2493 hws->funcs.enable_power_gating_plane(hws, true); 2494 2495 // Specific to FPGA dccg and registers 2496 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); 2497 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 2498 2499 hws->funcs.dccg_init(hws); 2500 2501 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); 2502 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 2503 if (REG(REFCLK_CNTL)) 2504 REG_WRITE(REFCLK_CNTL, 0); 2505 // 2506 2507 2508 /* Blank pixel data with OPP DPG */ 2509 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2510 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2511 2512 if (tg->funcs->is_tg_enabled(tg)) 2513 dcn20_init_blank(dc, tg); 2514 } 2515 2516 for (i = 0; i < res_pool->timing_generator_count; i++) { 2517 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2518 2519 if (tg->funcs->is_tg_enabled(tg)) 2520 tg->funcs->lock(tg); 2521 } 2522 2523 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2524 struct dpp *dpp = res_pool->dpps[i]; 2525 2526 dpp->funcs->dpp_reset(dpp); 2527 } 2528 2529 /* Reset all MPCC muxes */ 2530 res_pool->mpc->funcs->mpc_init(res_pool->mpc); 2531 2532 /* initialize OPP mpc_tree parameter */ 2533 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 2534 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; 2535 res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2536 for (j = 0; j < MAX_PIPES; j++) 2537 res_pool->opps[i]->mpcc_disconnect_pending[j] = false; 2538 } 2539 2540 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2541 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2542 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2543 struct hubp *hubp = dc->res_pool->hubps[i]; 2544 struct dpp *dpp = dc->res_pool->dpps[i]; 2545 2546 pipe_ctx->stream_res.tg = tg; 2547 pipe_ctx->pipe_idx = i; 2548 2549 pipe_ctx->plane_res.hubp = hubp; 2550 pipe_ctx->plane_res.dpp = dpp; 2551 pipe_ctx->plane_res.mpcc_inst = dpp->inst; 2552 hubp->mpcc_id = dpp->inst; 2553 hubp->opp_id = OPP_ID_INVALID; 2554 hubp->power_gated = false; 2555 pipe_ctx->stream_res.opp = NULL; 2556 2557 hubp->funcs->hubp_init(hubp); 2558 2559 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; 2560 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2561 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; 2562 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; 2563 /*to do*/ 2564 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx); 2565 } 2566 2567 /* initialize DWB pointer to MCIF_WB */ 2568 for (i = 0; i < res_pool->res_cap->num_dwb; i++) 2569 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; 2570 2571 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2572 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2573 2574 if (tg->funcs->is_tg_enabled(tg)) 2575 tg->funcs->unlock(tg); 2576 } 2577 2578 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2579 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2580 2581 dc->hwss.disable_plane(dc, pipe_ctx); 2582 2583 pipe_ctx->stream_res.tg = NULL; 2584 pipe_ctx->plane_res.hubp = NULL; 2585 } 2586 2587 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2588 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2589 2590 tg->funcs->tg_init(tg); 2591 } 2592 2593 if (dc->res_pool->hubbub->funcs->init_crb) 2594 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 2595 } 2596 #ifndef TRIM_FSFT 2597 bool dcn20_optimize_timing_for_fsft(struct dc *dc, 2598 struct dc_crtc_timing *timing, 2599 unsigned int max_input_rate_in_khz) 2600 { 2601 unsigned int old_v_front_porch; 2602 unsigned int old_v_total; 2603 unsigned int max_input_rate_in_100hz; 2604 unsigned long long new_v_total; 2605 2606 max_input_rate_in_100hz = max_input_rate_in_khz * 10; 2607 if (max_input_rate_in_100hz < timing->pix_clk_100hz) 2608 return false; 2609 2610 old_v_total = timing->v_total; 2611 old_v_front_porch = timing->v_front_porch; 2612 2613 timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz; 2614 timing->pix_clk_100hz = max_input_rate_in_100hz; 2615 2616 new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz); 2617 2618 timing->v_total = new_v_total; 2619 timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total); 2620 return true; 2621 } 2622 #endif 2623 2624 void dcn20_set_disp_pattern_generator(const struct dc *dc, 2625 struct pipe_ctx *pipe_ctx, 2626 enum controller_dp_test_pattern test_pattern, 2627 enum controller_dp_color_space color_space, 2628 enum dc_color_depth color_depth, 2629 const struct tg_color *solid_color, 2630 int width, int height, int offset) 2631 { 2632 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern, 2633 color_space, color_depth, solid_color, width, height, offset); 2634 } 2635