1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include <linux/delay.h> 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dcn20/dcn20_resource.h" 32 #include "dce110/dce110_hw_sequencer.h" 33 #include "dcn10/dcn10_hw_sequencer.h" 34 #include "dcn20_hwseq.h" 35 #include "dce/dce_hwseq.h" 36 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 37 #include "dcn20/dcn20_dsc.h" 38 #endif 39 #include "abm.h" 40 #include "clk_mgr.h" 41 #include "dmcu.h" 42 #include "hubp.h" 43 #include "timing_generator.h" 44 #include "opp.h" 45 #include "ipp.h" 46 #include "mpc.h" 47 #include "mcif_wb.h" 48 #include "reg_helper.h" 49 #include "dcn10/dcn10_cm_common.h" 50 #include "dcn10/dcn10_hubbub.h" 51 #include "dcn10/dcn10_optc.h" 52 #include "dc_link_dp.h" 53 #include "vm_helper.h" 54 #include "dccg.h" 55 56 #define DC_LOGGER_INIT(logger) 57 58 #define CTX \ 59 hws->ctx 60 #define REG(reg)\ 61 hws->regs->reg 62 63 #undef FN 64 #define FN(reg_name, field_name) \ 65 hws->shifts->field_name, hws->masks->field_name 66 67 static void bios_golden_init(struct dc *dc) 68 { 69 struct dc_bios *bp = dc->ctx->dc_bios; 70 int i; 71 72 /* initialize dcn global */ 73 bp->funcs->enable_disp_power_gating(bp, 74 CONTROLLER_ID_D0, ASIC_PIPE_INIT); 75 76 for (i = 0; i < dc->res_pool->pipe_count; i++) { 77 /* initialize dcn per pipe */ 78 bp->funcs->enable_disp_power_gating(bp, 79 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE); 80 } 81 } 82 83 static void enable_power_gating_plane( 84 struct dce_hwseq *hws, 85 bool enable) 86 { 87 bool force_on = 1; /* disable power gating */ 88 89 if (enable) 90 force_on = 0; 91 92 /* DCHUBP0/1/2/3/4/5 */ 93 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); 94 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); 95 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); 96 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); 97 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 98 /*Do not power gate DCHUB5, should be left at HW default, power on permanently*/ 99 /*REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, force_on);*/ 100 101 /* DPP0/1/2/3/4/5 */ 102 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); 103 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); 104 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); 105 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); 106 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 107 /*Do not power gate DPP5, should be left at HW default, power on permanently*/ 108 /*REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, force_on);*/ 109 110 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on); 111 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on); 112 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on); 113 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on); 114 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on); 115 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); 116 } 117 118 static void dcn20_dccg_init(struct dce_hwseq *hws) 119 { 120 /* 121 * set MICROSECOND_TIME_BASE_DIV 122 * 100Mhz refclk -> 0x120264 123 * 27Mhz refclk -> 0x12021b 124 * 48Mhz refclk -> 0x120230 125 * 126 */ 127 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); 128 129 /* 130 * set MILLISECOND_TIME_BASE_DIV 131 * 100Mhz refclk -> 0x1186a0 132 * 27Mhz refclk -> 0x106978 133 * 48Mhz refclk -> 0x10bb80 134 * 135 */ 136 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); 137 138 /* This value is dependent on the hardware pipeline delay so set once per SOC */ 139 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c); 140 } 141 142 static void disable_vga( 143 struct dce_hwseq *hws) 144 { 145 REG_WRITE(D1VGA_CONTROL, 0); 146 REG_WRITE(D2VGA_CONTROL, 0); 147 REG_WRITE(D3VGA_CONTROL, 0); 148 REG_WRITE(D4VGA_CONTROL, 0); 149 REG_WRITE(D5VGA_CONTROL, 0); 150 REG_WRITE(D6VGA_CONTROL, 0); 151 } 152 153 void dcn20_program_tripleBuffer( 154 const struct dc *dc, 155 struct pipe_ctx *pipe_ctx, 156 bool enableTripleBuffer) 157 { 158 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { 159 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( 160 pipe_ctx->plane_res.hubp, 161 enableTripleBuffer); 162 } 163 } 164 165 /* Blank pixel data during initialization */ 166 static void dcn20_init_blank( 167 struct dc *dc, 168 struct timing_generator *tg) 169 { 170 enum dc_color_space color_space; 171 struct tg_color black_color = {0}; 172 struct output_pixel_processor *opp = NULL; 173 struct output_pixel_processor *bottom_opp = NULL; 174 uint32_t num_opps, opp_id_src0, opp_id_src1; 175 uint32_t otg_active_width, otg_active_height; 176 177 /* program opp dpg blank color */ 178 color_space = COLOR_SPACE_SRGB; 179 color_space_to_black_color(dc, color_space, &black_color); 180 181 /* get the OTG active size */ 182 tg->funcs->get_otg_active_size(tg, 183 &otg_active_width, 184 &otg_active_height); 185 186 /* get the OPTC source */ 187 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 188 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); 189 opp = dc->res_pool->opps[opp_id_src0]; 190 191 if (num_opps == 2) { 192 otg_active_width = otg_active_width / 2; 193 ASSERT(opp_id_src1 < dc->res_pool->res_cap->num_opp); 194 bottom_opp = dc->res_pool->opps[opp_id_src1]; 195 } 196 197 opp->funcs->opp_set_disp_pattern_generator( 198 opp, 199 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 200 COLOR_DEPTH_UNDEFINED, 201 &black_color, 202 otg_active_width, 203 otg_active_height); 204 205 if (num_opps == 2) { 206 bottom_opp->funcs->opp_set_disp_pattern_generator( 207 bottom_opp, 208 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 209 COLOR_DEPTH_UNDEFINED, 210 &black_color, 211 otg_active_width, 212 otg_active_height); 213 } 214 215 dcn20_hwss_wait_for_blank_complete(opp); 216 } 217 218 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 219 static void dcn20_dsc_pg_control( 220 struct dce_hwseq *hws, 221 unsigned int dsc_inst, 222 bool power_on) 223 { 224 uint32_t power_gate = power_on ? 0 : 1; 225 uint32_t pwr_status = power_on ? 0 : 2; 226 uint32_t org_ip_request_cntl = 0; 227 228 if (hws->ctx->dc->debug.disable_dsc_power_gate) 229 return; 230 231 if (REG(DOMAIN16_PG_CONFIG) == 0) 232 return; 233 234 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 235 if (org_ip_request_cntl == 0) 236 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 237 238 switch (dsc_inst) { 239 case 0: /* DSC0 */ 240 REG_UPDATE(DOMAIN16_PG_CONFIG, 241 DOMAIN16_POWER_GATE, power_gate); 242 243 REG_WAIT(DOMAIN16_PG_STATUS, 244 DOMAIN16_PGFSM_PWR_STATUS, pwr_status, 245 1, 1000); 246 break; 247 case 1: /* DSC1 */ 248 REG_UPDATE(DOMAIN17_PG_CONFIG, 249 DOMAIN17_POWER_GATE, power_gate); 250 251 REG_WAIT(DOMAIN17_PG_STATUS, 252 DOMAIN17_PGFSM_PWR_STATUS, pwr_status, 253 1, 1000); 254 break; 255 case 2: /* DSC2 */ 256 REG_UPDATE(DOMAIN18_PG_CONFIG, 257 DOMAIN18_POWER_GATE, power_gate); 258 259 REG_WAIT(DOMAIN18_PG_STATUS, 260 DOMAIN18_PGFSM_PWR_STATUS, pwr_status, 261 1, 1000); 262 break; 263 case 3: /* DSC3 */ 264 REG_UPDATE(DOMAIN19_PG_CONFIG, 265 DOMAIN19_POWER_GATE, power_gate); 266 267 REG_WAIT(DOMAIN19_PG_STATUS, 268 DOMAIN19_PGFSM_PWR_STATUS, pwr_status, 269 1, 1000); 270 break; 271 case 4: /* DSC4 */ 272 REG_UPDATE(DOMAIN20_PG_CONFIG, 273 DOMAIN20_POWER_GATE, power_gate); 274 275 REG_WAIT(DOMAIN20_PG_STATUS, 276 DOMAIN20_PGFSM_PWR_STATUS, pwr_status, 277 1, 1000); 278 break; 279 case 5: /* DSC5 */ 280 REG_UPDATE(DOMAIN21_PG_CONFIG, 281 DOMAIN21_POWER_GATE, power_gate); 282 283 REG_WAIT(DOMAIN21_PG_STATUS, 284 DOMAIN21_PGFSM_PWR_STATUS, pwr_status, 285 1, 1000); 286 break; 287 default: 288 BREAK_TO_DEBUGGER(); 289 break; 290 } 291 292 if (org_ip_request_cntl == 0) 293 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 294 } 295 #endif 296 297 static void dcn20_dpp_pg_control( 298 struct dce_hwseq *hws, 299 unsigned int dpp_inst, 300 bool power_on) 301 { 302 uint32_t power_gate = power_on ? 0 : 1; 303 uint32_t pwr_status = power_on ? 0 : 2; 304 305 if (hws->ctx->dc->debug.disable_dpp_power_gate) 306 return; 307 if (REG(DOMAIN1_PG_CONFIG) == 0) 308 return; 309 310 switch (dpp_inst) { 311 case 0: /* DPP0 */ 312 REG_UPDATE(DOMAIN1_PG_CONFIG, 313 DOMAIN1_POWER_GATE, power_gate); 314 315 REG_WAIT(DOMAIN1_PG_STATUS, 316 DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 317 1, 1000); 318 break; 319 case 1: /* DPP1 */ 320 REG_UPDATE(DOMAIN3_PG_CONFIG, 321 DOMAIN3_POWER_GATE, power_gate); 322 323 REG_WAIT(DOMAIN3_PG_STATUS, 324 DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 325 1, 1000); 326 break; 327 case 2: /* DPP2 */ 328 REG_UPDATE(DOMAIN5_PG_CONFIG, 329 DOMAIN5_POWER_GATE, power_gate); 330 331 REG_WAIT(DOMAIN5_PG_STATUS, 332 DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 333 1, 1000); 334 break; 335 case 3: /* DPP3 */ 336 REG_UPDATE(DOMAIN7_PG_CONFIG, 337 DOMAIN7_POWER_GATE, power_gate); 338 339 REG_WAIT(DOMAIN7_PG_STATUS, 340 DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 341 1, 1000); 342 break; 343 case 4: /* DPP4 */ 344 REG_UPDATE(DOMAIN9_PG_CONFIG, 345 DOMAIN9_POWER_GATE, power_gate); 346 347 REG_WAIT(DOMAIN9_PG_STATUS, 348 DOMAIN9_PGFSM_PWR_STATUS, pwr_status, 349 1, 1000); 350 break; 351 case 5: /* DPP5 */ 352 /* 353 * Do not power gate DPP5, should be left at HW default, power on permanently. 354 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 355 * reset. 356 * REG_UPDATE(DOMAIN11_PG_CONFIG, 357 * DOMAIN11_POWER_GATE, power_gate); 358 * 359 * REG_WAIT(DOMAIN11_PG_STATUS, 360 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, 361 * 1, 1000); 362 */ 363 break; 364 default: 365 BREAK_TO_DEBUGGER(); 366 break; 367 } 368 } 369 370 371 static void dcn20_hubp_pg_control( 372 struct dce_hwseq *hws, 373 unsigned int hubp_inst, 374 bool power_on) 375 { 376 uint32_t power_gate = power_on ? 0 : 1; 377 uint32_t pwr_status = power_on ? 0 : 2; 378 379 if (hws->ctx->dc->debug.disable_hubp_power_gate) 380 return; 381 if (REG(DOMAIN0_PG_CONFIG) == 0) 382 return; 383 384 switch (hubp_inst) { 385 case 0: /* DCHUBP0 */ 386 REG_UPDATE(DOMAIN0_PG_CONFIG, 387 DOMAIN0_POWER_GATE, power_gate); 388 389 REG_WAIT(DOMAIN0_PG_STATUS, 390 DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 391 1, 1000); 392 break; 393 case 1: /* DCHUBP1 */ 394 REG_UPDATE(DOMAIN2_PG_CONFIG, 395 DOMAIN2_POWER_GATE, power_gate); 396 397 REG_WAIT(DOMAIN2_PG_STATUS, 398 DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 399 1, 1000); 400 break; 401 case 2: /* DCHUBP2 */ 402 REG_UPDATE(DOMAIN4_PG_CONFIG, 403 DOMAIN4_POWER_GATE, power_gate); 404 405 REG_WAIT(DOMAIN4_PG_STATUS, 406 DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 407 1, 1000); 408 break; 409 case 3: /* DCHUBP3 */ 410 REG_UPDATE(DOMAIN6_PG_CONFIG, 411 DOMAIN6_POWER_GATE, power_gate); 412 413 REG_WAIT(DOMAIN6_PG_STATUS, 414 DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 415 1, 1000); 416 break; 417 case 4: /* DCHUBP4 */ 418 REG_UPDATE(DOMAIN8_PG_CONFIG, 419 DOMAIN8_POWER_GATE, power_gate); 420 421 REG_WAIT(DOMAIN8_PG_STATUS, 422 DOMAIN8_PGFSM_PWR_STATUS, pwr_status, 423 1, 1000); 424 break; 425 case 5: /* DCHUBP5 */ 426 /* 427 * Do not power gate DCHUB5, should be left at HW default, power on permanently. 428 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 429 * reset. 430 * REG_UPDATE(DOMAIN10_PG_CONFIG, 431 * DOMAIN10_POWER_GATE, power_gate); 432 * 433 * REG_WAIT(DOMAIN10_PG_STATUS, 434 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status, 435 * 1, 1000); 436 */ 437 break; 438 default: 439 BREAK_TO_DEBUGGER(); 440 break; 441 } 442 } 443 444 445 446 static void dcn20_plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx) 447 { 448 struct dce_hwseq *hws = dc->hwseq; 449 struct dpp *dpp = pipe_ctx->plane_res.dpp; 450 451 DC_LOGGER_INIT(dc->ctx->logger); 452 453 if (REG(DC_IP_REQUEST_CNTL)) { 454 REG_SET(DC_IP_REQUEST_CNTL, 0, 455 IP_REQUEST_EN, 1); 456 dcn20_dpp_pg_control(hws, dpp->inst, false); 457 dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, false); 458 dpp->funcs->dpp_reset(dpp); 459 REG_SET(DC_IP_REQUEST_CNTL, 0, 460 IP_REQUEST_EN, 0); 461 DC_LOG_DEBUG( 462 "Power gated front end %d\n", pipe_ctx->pipe_idx); 463 } 464 } 465 466 467 468 /* disable HW used by plane. 469 * note: cannot disable until disconnect is complete 470 */ 471 static void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 472 { 473 struct hubp *hubp = pipe_ctx->plane_res.hubp; 474 struct dpp *dpp = pipe_ctx->plane_res.dpp; 475 476 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); 477 478 /* In flip immediate with pipe splitting case GSL is used for 479 * synchronization so we must disable it when the plane is disabled. 480 */ 481 if (pipe_ctx->stream_res.gsl_group != 0) 482 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false); 483 484 dc->hwss.set_flip_control_gsl(pipe_ctx, false); 485 486 hubp->funcs->hubp_clk_cntl(hubp, false); 487 488 dpp->funcs->dpp_dppclk_control(dpp, false, false); 489 490 hubp->power_gated = true; 491 dc->optimized_required = false; /* We're powering off, no need to optimize */ 492 493 dcn20_plane_atomic_power_down(dc, pipe_ctx); 494 495 pipe_ctx->stream = NULL; 496 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); 497 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); 498 pipe_ctx->top_pipe = NULL; 499 pipe_ctx->bottom_pipe = NULL; 500 pipe_ctx->plane_state = NULL; 501 } 502 503 504 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) 505 { 506 DC_LOGGER_INIT(dc->ctx->logger); 507 508 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) 509 return; 510 511 dcn20_plane_atomic_disable(dc, pipe_ctx); 512 513 DC_LOG_DC("Power down front end %d\n", 514 pipe_ctx->pipe_idx); 515 } 516 517 static void dcn20_init_hw(struct dc *dc) 518 { 519 int i, j; 520 struct abm *abm = dc->res_pool->abm; 521 struct dmcu *dmcu = dc->res_pool->dmcu; 522 struct dce_hwseq *hws = dc->hwseq; 523 struct dc_bios *dcb = dc->ctx->dc_bios; 524 struct resource_pool *res_pool = dc->res_pool; 525 struct dc_state *context = dc->current_state; 526 527 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 528 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 529 530 // Initialize the dccg 531 if (res_pool->dccg->funcs->dccg_init) 532 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 533 534 //Enable ability to power gate / don't force power on permanently 535 enable_power_gating_plane(dc->hwseq, true); 536 537 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 538 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); 539 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 540 541 dcn20_dccg_init(hws); 542 543 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); 544 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 545 REG_WRITE(REFCLK_CNTL, 0); 546 } else { 547 if (!dcb->funcs->is_accelerated_mode(dcb)) { 548 bios_golden_init(dc); 549 disable_vga(dc->hwseq); 550 } 551 552 for (i = 0; i < dc->link_count; i++) { 553 /* Power up AND update implementation according to the 554 * required signal (which may be different from the 555 * default signal on connector). 556 */ 557 struct dc_link *link = dc->links[i]; 558 559 link->link_enc->funcs->hw_init(link->link_enc); 560 } 561 } 562 563 /* Blank pixel data with OPP DPG */ 564 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 565 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 566 567 if (tg->funcs->is_tg_enabled(tg)) { 568 dcn20_init_blank(dc, tg); 569 } 570 } 571 572 for (i = 0; i < res_pool->timing_generator_count; i++) { 573 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 574 575 if (tg->funcs->is_tg_enabled(tg)) 576 tg->funcs->lock(tg); 577 } 578 579 for (i = 0; i < dc->res_pool->pipe_count; i++) { 580 struct dpp *dpp = res_pool->dpps[i]; 581 582 dpp->funcs->dpp_reset(dpp); 583 } 584 585 /* Reset all MPCC muxes */ 586 res_pool->mpc->funcs->mpc_init(res_pool->mpc); 587 588 /* initialize OPP mpc_tree parameter */ 589 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 590 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; 591 res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 592 for (j = 0; j < MAX_PIPES; j++) 593 res_pool->opps[i]->mpcc_disconnect_pending[j] = false; 594 } 595 596 for (i = 0; i < dc->res_pool->pipe_count; i++) { 597 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 598 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 599 struct hubp *hubp = dc->res_pool->hubps[i]; 600 struct dpp *dpp = dc->res_pool->dpps[i]; 601 602 pipe_ctx->stream_res.tg = tg; 603 pipe_ctx->pipe_idx = i; 604 605 pipe_ctx->plane_res.hubp = hubp; 606 pipe_ctx->plane_res.dpp = dpp; 607 pipe_ctx->plane_res.mpcc_inst = dpp->inst; 608 hubp->mpcc_id = dpp->inst; 609 hubp->opp_id = OPP_ID_INVALID; 610 hubp->power_gated = false; 611 pipe_ctx->stream_res.opp = NULL; 612 613 hubp->funcs->hubp_init(hubp); 614 615 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; 616 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 617 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; 618 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; 619 /*to do*/ 620 hwss1_plane_atomic_disconnect(dc, pipe_ctx); 621 } 622 623 /* initialize DWB pointer to MCIF_WB */ 624 for (i = 0; i < res_pool->res_cap->num_dwb; i++) 625 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; 626 627 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 628 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 629 630 if (tg->funcs->is_tg_enabled(tg)) 631 tg->funcs->unlock(tg); 632 } 633 634 for (i = 0; i < dc->res_pool->pipe_count; i++) { 635 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 636 637 dc->hwss.disable_plane(dc, pipe_ctx); 638 639 pipe_ctx->stream_res.tg = NULL; 640 pipe_ctx->plane_res.hubp = NULL; 641 } 642 643 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 644 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 645 646 tg->funcs->tg_init(tg); 647 } 648 649 /* end of FPGA. Below if real ASIC */ 650 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 651 return; 652 653 654 for (i = 0; i < res_pool->audio_count; i++) { 655 struct audio *audio = res_pool->audios[i]; 656 657 audio->funcs->hw_init(audio); 658 } 659 660 if (abm != NULL) { 661 abm->funcs->init_backlight(abm); 662 abm->funcs->abm_init(abm); 663 } 664 665 if (dmcu != NULL) 666 dmcu->funcs->dmcu_init(dmcu); 667 668 if (abm != NULL && dmcu != NULL) 669 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 670 671 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 672 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 673 674 if (!dc->debug.disable_clock_gate) { 675 /* enable all DCN clock gating */ 676 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 677 678 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 679 680 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 681 } 682 683 } 684 685 enum dc_status dcn20_enable_stream_timing( 686 struct pipe_ctx *pipe_ctx, 687 struct dc_state *context, 688 struct dc *dc) 689 { 690 struct dc_stream_state *stream = pipe_ctx->stream; 691 struct drr_params params = {0}; 692 unsigned int event_triggers = 0; 693 694 695 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 696 struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); 697 #endif 698 699 /* by upper caller loop, pipe0 is parent pipe and be called first. 700 * back end is set up by for pipe0. Other children pipe share back end 701 * with pipe 0. No program is needed. 702 */ 703 if (pipe_ctx->top_pipe != NULL) 704 return DC_OK; 705 706 /* TODO check if timing_changed, disable stream if timing changed */ 707 708 if (odm_pipe) 709 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 710 pipe_ctx->stream_res.tg, 711 odm_pipe->stream_res.opp->inst, 712 pipe_ctx->stream->timing.h_addressable/2, 713 pipe_ctx->stream->timing.pixel_encoding); 714 /* HW program guide assume display already disable 715 * by unplug sequence. OTG assume stop. 716 */ 717 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); 718 719 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 720 pipe_ctx->clock_source, 721 &pipe_ctx->stream_res.pix_clk_params, 722 &pipe_ctx->pll_settings)) { 723 BREAK_TO_DEBUGGER(); 724 return DC_ERROR_UNEXPECTED; 725 } 726 727 pipe_ctx->stream_res.tg->funcs->program_timing( 728 pipe_ctx->stream_res.tg, 729 &stream->timing, 730 pipe_ctx->pipe_dlg_param.vready_offset, 731 pipe_ctx->pipe_dlg_param.vstartup_start, 732 pipe_ctx->pipe_dlg_param.vupdate_offset, 733 pipe_ctx->pipe_dlg_param.vupdate_width, 734 pipe_ctx->stream->signal, 735 true); 736 737 if (pipe_ctx->stream_res.tg->funcs->setup_global_lock) 738 pipe_ctx->stream_res.tg->funcs->setup_global_lock( 739 pipe_ctx->stream_res.tg); 740 741 if (odm_pipe) 742 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 743 odm_pipe->stream_res.opp, 744 true); 745 746 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 747 pipe_ctx->stream_res.opp, 748 true); 749 750 dc->hwss.blank_pixel_data(dc, pipe_ctx, true); 751 752 /* VTG is within DCHUB command block. DCFCLK is always on */ 753 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { 754 BREAK_TO_DEBUGGER(); 755 return DC_ERROR_UNEXPECTED; 756 } 757 758 dcn20_hwss_wait_for_blank_complete(pipe_ctx->stream_res.opp); 759 760 params.vertical_total_min = stream->adjust.v_total_min; 761 params.vertical_total_max = stream->adjust.v_total_max; 762 if (pipe_ctx->stream_res.tg->funcs->set_drr) 763 pipe_ctx->stream_res.tg->funcs->set_drr( 764 pipe_ctx->stream_res.tg, ¶ms); 765 766 // DRR should set trigger event to monitor surface update event 767 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 768 event_triggers = 0x80; 769 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 770 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 771 pipe_ctx->stream_res.tg, event_triggers); 772 773 /* TODO program crtc source select for non-virtual signal*/ 774 /* TODO program FMT */ 775 /* TODO setup link_enc */ 776 /* TODO set stream attributes */ 777 /* TODO program audio */ 778 /* TODO enable stream if timing changed */ 779 /* TODO unblank stream if DP */ 780 781 return DC_OK; 782 } 783 784 void dcn20_program_output_csc(struct dc *dc, 785 struct pipe_ctx *pipe_ctx, 786 enum dc_color_space colorspace, 787 uint16_t *matrix, 788 int opp_id) 789 { 790 struct mpc *mpc = dc->res_pool->mpc; 791 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; 792 793 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 794 if (mpc->funcs->set_output_csc != NULL) 795 mpc->funcs->set_output_csc(mpc, 796 opp_id, 797 matrix, 798 ocsc_mode); 799 } else { 800 if (mpc->funcs->set_ocsc_default != NULL) 801 mpc->funcs->set_ocsc_default(mpc, 802 opp_id, 803 colorspace, 804 ocsc_mode); 805 } 806 } 807 808 bool dcn20_set_output_transfer_func(struct pipe_ctx *pipe_ctx, 809 const struct dc_stream_state *stream) 810 { 811 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 812 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 813 struct pwl_params *params = NULL; 814 /* 815 * program OGAM only for the top pipe 816 * if there is a pipe split then fix diagnostic is required: 817 * how to pass OGAM parameter for stream. 818 * if programming for all pipes is required then remove condition 819 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic. 820 */ 821 if ((pipe_ctx->top_pipe == NULL || dc_res_is_odm_head_pipe(pipe_ctx)) 822 && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 823 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 824 params = &stream->out_transfer_func->pwl; 825 else if (pipe_ctx->stream->out_transfer_func->type == 826 TF_TYPE_DISTRIBUTED_POINTS && 827 cm_helper_translate_curve_to_hw_format( 828 stream->out_transfer_func, 829 &mpc->blender_params, false)) 830 params = &mpc->blender_params; 831 /* 832 * there is no ROM 833 */ 834 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 835 BREAK_TO_DEBUGGER(); 836 } 837 /* 838 * if above if is not executed then 'params' equal to 0 and set in bypass 839 */ 840 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 841 842 return true; 843 } 844 845 static bool dcn20_set_blend_lut( 846 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 847 { 848 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 849 bool result = true; 850 struct pwl_params *blend_lut = NULL; 851 852 if (plane_state->blend_tf) { 853 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 854 blend_lut = &plane_state->blend_tf->pwl; 855 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 856 cm_helper_translate_curve_to_hw_format( 857 plane_state->blend_tf, 858 &dpp_base->regamma_params, false); 859 blend_lut = &dpp_base->regamma_params; 860 } 861 } 862 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); 863 864 return result; 865 } 866 867 static bool dcn20_set_shaper_3dlut( 868 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 869 { 870 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 871 bool result = true; 872 struct pwl_params *shaper_lut = NULL; 873 874 if (plane_state->in_shaper_func) { 875 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 876 shaper_lut = &plane_state->in_shaper_func->pwl; 877 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 878 cm_helper_translate_curve_to_hw_format( 879 plane_state->in_shaper_func, 880 &dpp_base->shaper_params, true); 881 shaper_lut = &dpp_base->shaper_params; 882 } 883 } 884 885 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); 886 if (plane_state->lut3d_func && 887 plane_state->lut3d_func->initialized == true) 888 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, 889 &plane_state->lut3d_func->lut_3d); 890 else 891 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); 892 893 if (plane_state->lut3d_func && 894 plane_state->lut3d_func->initialized == true && 895 plane_state->lut3d_func->hdr_multiplier != 0) 896 dpp_base->funcs->dpp_set_hdr_multiplier(dpp_base, 897 plane_state->lut3d_func->hdr_multiplier); 898 else 899 dpp_base->funcs->dpp_set_hdr_multiplier(dpp_base, 0x1f000); 900 901 return result; 902 } 903 904 bool dcn20_set_input_transfer_func(struct pipe_ctx *pipe_ctx, 905 const struct dc_plane_state *plane_state) 906 { 907 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 908 const struct dc_transfer_func *tf = NULL; 909 bool result = true; 910 bool use_degamma_ram = false; 911 912 if (dpp_base == NULL || plane_state == NULL) 913 return false; 914 915 dcn20_set_shaper_3dlut(pipe_ctx, plane_state); 916 dcn20_set_blend_lut(pipe_ctx, plane_state); 917 918 if (plane_state->in_transfer_func) 919 tf = plane_state->in_transfer_func; 920 921 922 if (tf == NULL) { 923 dpp_base->funcs->dpp_set_degamma(dpp_base, 924 IPP_DEGAMMA_MODE_BYPASS); 925 return true; 926 } 927 928 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS) 929 use_degamma_ram = true; 930 931 if (use_degamma_ram == true) { 932 if (tf->type == TF_TYPE_HWPWL) 933 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 934 &tf->pwl); 935 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 936 cm_helper_translate_curve_to_degamma_hw_format(tf, 937 &dpp_base->degamma_params); 938 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 939 &dpp_base->degamma_params); 940 } 941 return true; 942 } 943 /* handle here the optimized cases when de-gamma ROM could be used. 944 * 945 */ 946 if (tf->type == TF_TYPE_PREDEFINED) { 947 switch (tf->tf) { 948 case TRANSFER_FUNCTION_SRGB: 949 dpp_base->funcs->dpp_set_degamma(dpp_base, 950 IPP_DEGAMMA_MODE_HW_sRGB); 951 break; 952 case TRANSFER_FUNCTION_BT709: 953 dpp_base->funcs->dpp_set_degamma(dpp_base, 954 IPP_DEGAMMA_MODE_HW_xvYCC); 955 break; 956 case TRANSFER_FUNCTION_LINEAR: 957 dpp_base->funcs->dpp_set_degamma(dpp_base, 958 IPP_DEGAMMA_MODE_BYPASS); 959 break; 960 case TRANSFER_FUNCTION_PQ: 961 default: 962 result = false; 963 break; 964 } 965 } else if (tf->type == TF_TYPE_BYPASS) 966 dpp_base->funcs->dpp_set_degamma(dpp_base, 967 IPP_DEGAMMA_MODE_BYPASS); 968 else { 969 /* 970 * if we are here, we did not handle correctly. 971 * fix is required for this use case 972 */ 973 BREAK_TO_DEBUGGER(); 974 dpp_base->funcs->dpp_set_degamma(dpp_base, 975 IPP_DEGAMMA_MODE_BYPASS); 976 } 977 978 return result; 979 } 980 981 static void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 982 { 983 struct pipe_ctx *combine_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); 984 985 if (combine_pipe) 986 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 987 pipe_ctx->stream_res.tg, 988 combine_pipe->stream_res.opp->inst, 989 pipe_ctx->plane_res.scl_data.h_active, 990 pipe_ctx->stream->timing.pixel_encoding); 991 else 992 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 993 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 994 } 995 996 void dcn20_blank_pixel_data( 997 struct dc *dc, 998 struct pipe_ctx *pipe_ctx, 999 bool blank) 1000 { 1001 struct tg_color black_color = {0}; 1002 struct stream_resource *stream_res = &pipe_ctx->stream_res; 1003 struct dc_stream_state *stream = pipe_ctx->stream; 1004 enum dc_color_space color_space = stream->output_color_space; 1005 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; 1006 struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); 1007 1008 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 1009 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; 1010 1011 /* get opp dpg blank color */ 1012 color_space_to_black_color(dc, color_space, &black_color); 1013 1014 if (bot_odm_pipe) 1015 width = width / 2; 1016 1017 if (blank) { 1018 if (stream_res->abm) 1019 stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm); 1020 1021 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) 1022 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; 1023 } else { 1024 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; 1025 } 1026 1027 stream_res->opp->funcs->opp_set_disp_pattern_generator( 1028 stream_res->opp, 1029 test_pattern, 1030 stream->timing.display_color_depth, 1031 &black_color, 1032 width, 1033 height); 1034 1035 if (bot_odm_pipe) { 1036 bot_odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator( 1037 bot_odm_pipe->stream_res.opp, 1038 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE ? 1039 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern, 1040 stream->timing.display_color_depth, 1041 &black_color, 1042 width, 1043 height); 1044 } 1045 1046 if (!blank) 1047 if (stream_res->abm) { 1048 stream_res->abm->funcs->set_pipe(stream_res->abm, stream_res->tg->inst + 1); 1049 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level); 1050 } 1051 } 1052 1053 1054 static void dcn20_power_on_plane( 1055 struct dce_hwseq *hws, 1056 struct pipe_ctx *pipe_ctx) 1057 { 1058 DC_LOGGER_INIT(hws->ctx->logger); 1059 if (REG(DC_IP_REQUEST_CNTL)) { 1060 REG_SET(DC_IP_REQUEST_CNTL, 0, 1061 IP_REQUEST_EN, 1); 1062 dcn20_dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); 1063 dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true); 1064 REG_SET(DC_IP_REQUEST_CNTL, 0, 1065 IP_REQUEST_EN, 0); 1066 DC_LOG_DEBUG( 1067 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst); 1068 } 1069 } 1070 1071 void dcn20_enable_plane( 1072 struct dc *dc, 1073 struct pipe_ctx *pipe_ctx, 1074 struct dc_state *context) 1075 { 1076 //if (dc->debug.sanity_checks) { 1077 // dcn10_verify_allow_pstate_change_high(dc); 1078 //} 1079 dcn20_power_on_plane(dc->hwseq, pipe_ctx); 1080 1081 /* enable DCFCLK current DCHUB */ 1082 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); 1083 1084 /* make sure OPP_PIPE_CLOCK_EN = 1 */ 1085 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 1086 pipe_ctx->stream_res.opp, 1087 true); 1088 1089 /* TODO: enable/disable in dm as per update type. 1090 if (plane_state) { 1091 DC_LOG_DC(dc->ctx->logger, 1092 "Pipe:%d 0x%x: addr hi:0x%x, " 1093 "addr low:0x%x, " 1094 "src: %d, %d, %d," 1095 " %d; dst: %d, %d, %d, %d;\n", 1096 pipe_ctx->pipe_idx, 1097 plane_state, 1098 plane_state->address.grph.addr.high_part, 1099 plane_state->address.grph.addr.low_part, 1100 plane_state->src_rect.x, 1101 plane_state->src_rect.y, 1102 plane_state->src_rect.width, 1103 plane_state->src_rect.height, 1104 plane_state->dst_rect.x, 1105 plane_state->dst_rect.y, 1106 plane_state->dst_rect.width, 1107 plane_state->dst_rect.height); 1108 1109 DC_LOG_DC(dc->ctx->logger, 1110 "Pipe %d: width, height, x, y format:%d\n" 1111 "viewport:%d, %d, %d, %d\n" 1112 "recout: %d, %d, %d, %d\n", 1113 pipe_ctx->pipe_idx, 1114 plane_state->format, 1115 pipe_ctx->plane_res.scl_data.viewport.width, 1116 pipe_ctx->plane_res.scl_data.viewport.height, 1117 pipe_ctx->plane_res.scl_data.viewport.x, 1118 pipe_ctx->plane_res.scl_data.viewport.y, 1119 pipe_ctx->plane_res.scl_data.recout.width, 1120 pipe_ctx->plane_res.scl_data.recout.height, 1121 pipe_ctx->plane_res.scl_data.recout.x, 1122 pipe_ctx->plane_res.scl_data.recout.y); 1123 print_rq_dlg_ttu(dc, pipe_ctx); 1124 } 1125 */ 1126 if (dc->vm_pa_config.valid) { 1127 struct vm_system_aperture_param apt; 1128 1129 apt.sys_default.quad_part = 0; 1130 1131 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.start_addr; 1132 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.end_addr; 1133 1134 // Program system aperture settings 1135 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); 1136 } 1137 1138 // if (dc->debug.sanity_checks) { 1139 // dcn10_verify_allow_pstate_change_high(dc); 1140 // } 1141 } 1142 1143 1144 static void dcn20_program_pipe( 1145 struct dc *dc, 1146 struct pipe_ctx *pipe_ctx, 1147 struct dc_state *context) 1148 { 1149 pipe_ctx->plane_state->update_flags.bits.full_update = 1150 context->commit_hints.full_update_needed ? 1 : pipe_ctx->plane_state->update_flags.bits.full_update; 1151 1152 if (pipe_ctx->plane_state->update_flags.bits.full_update) 1153 dcn20_enable_plane(dc, pipe_ctx, context); 1154 1155 update_dchubp_dpp(dc, pipe_ctx, context); 1156 1157 set_hdr_multiplier(pipe_ctx); 1158 1159 if (pipe_ctx->plane_state->update_flags.bits.full_update || 1160 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 1161 pipe_ctx->plane_state->update_flags.bits.gamma_change) 1162 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); 1163 1164 /* dcn10_translate_regamma_to_hw_format takes 750us to finish 1165 * only do gamma programming for full update. 1166 * TODO: This can be further optimized/cleaned up 1167 * Always call this for now since it does memcmp inside before 1168 * doing heavy calculation and programming 1169 */ 1170 if (pipe_ctx->plane_state->update_flags.bits.full_update) 1171 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); 1172 } 1173 1174 static void dcn20_program_all_pipe_in_tree( 1175 struct dc *dc, 1176 struct pipe_ctx *pipe_ctx, 1177 struct dc_state *context) 1178 { 1179 if (pipe_ctx->top_pipe == NULL) { 1180 bool blank = !is_pipe_tree_visible(pipe_ctx); 1181 1182 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1183 pipe_ctx->stream_res.tg, 1184 pipe_ctx->pipe_dlg_param.vready_offset, 1185 pipe_ctx->pipe_dlg_param.vstartup_start, 1186 pipe_ctx->pipe_dlg_param.vupdate_offset, 1187 pipe_ctx->pipe_dlg_param.vupdate_width); 1188 1189 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1190 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1191 1192 dc->hwss.blank_pixel_data(dc, pipe_ctx, blank); 1193 1194 if (dc->hwss.update_odm) 1195 dc->hwss.update_odm(dc, context, pipe_ctx); 1196 } 1197 1198 if (pipe_ctx->plane_state != NULL) 1199 dcn20_program_pipe(dc, pipe_ctx, context); 1200 1201 if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx) 1202 dcn20_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context); 1203 } 1204 1205 void dcn20_pipe_control_lock_global( 1206 struct dc *dc, 1207 struct pipe_ctx *pipe, 1208 bool lock) 1209 { 1210 if (lock) { 1211 pipe->stream_res.tg->funcs->lock_doublebuffer_enable( 1212 pipe->stream_res.tg); 1213 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1214 } else { 1215 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1216 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, 1217 CRTC_STATE_VACTIVE); 1218 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, 1219 CRTC_STATE_VBLANK); 1220 pipe->stream_res.tg->funcs->lock_doublebuffer_disable( 1221 pipe->stream_res.tg); 1222 } 1223 } 1224 1225 void dcn20_pipe_control_lock( 1226 struct dc *dc, 1227 struct pipe_ctx *pipe, 1228 bool lock) 1229 { 1230 bool flip_immediate = false; 1231 1232 /* use TG master update lock to lock everything on the TG 1233 * therefore only top pipe need to lock 1234 */ 1235 if (pipe->top_pipe) 1236 return; 1237 1238 if (pipe->plane_state != NULL) 1239 flip_immediate = pipe->plane_state->flip_immediate; 1240 1241 /* In flip immediate and pipe splitting case, we need to use GSL 1242 * for synchronization. Only do setup on locking and on flip type change. 1243 */ 1244 if (lock && pipe->bottom_pipe != NULL) 1245 if ((flip_immediate && pipe->stream_res.gsl_group == 0) || 1246 (!flip_immediate && pipe->stream_res.gsl_group > 0)) 1247 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate); 1248 1249 if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) { 1250 if (lock) 1251 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); 1252 else 1253 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); 1254 } else { 1255 if (lock) 1256 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1257 else 1258 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1259 } 1260 } 1261 1262 static void dcn20_apply_ctx_for_surface( 1263 struct dc *dc, 1264 const struct dc_stream_state *stream, 1265 int num_planes, 1266 struct dc_state *context) 1267 { 1268 1269 int i; 1270 struct timing_generator *tg; 1271 bool removed_pipe[6] = { false }; 1272 bool interdependent_update = false; 1273 struct pipe_ctx *top_pipe_to_program = 1274 find_top_pipe_for_stream(dc, context, stream); 1275 DC_LOGGER_INIT(dc->ctx->logger); 1276 1277 if (!top_pipe_to_program) 1278 return; 1279 1280 tg = top_pipe_to_program->stream_res.tg; 1281 1282 interdependent_update = top_pipe_to_program->plane_state && 1283 top_pipe_to_program->plane_state->update_flags.bits.full_update; 1284 1285 if (interdependent_update) 1286 lock_all_pipes(dc, context, true); 1287 else 1288 dcn20_pipe_control_lock(dc, top_pipe_to_program, true); 1289 1290 if (num_planes == 0) { 1291 /* OTG blank before remove all front end */ 1292 dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true); 1293 } 1294 1295 /* Disconnect unused mpcc */ 1296 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1297 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1298 struct pipe_ctx *old_pipe_ctx = 1299 &dc->current_state->res_ctx.pipe_ctx[i]; 1300 /* 1301 * Powergate reused pipes that are not powergated 1302 * fairly hacky right now, using opp_id as indicator 1303 * TODO: After move dc_post to dc_update, this will 1304 * be removed. 1305 */ 1306 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) { 1307 if (old_pipe_ctx->stream_res.tg == tg && 1308 old_pipe_ctx->plane_res.hubp && 1309 old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID) 1310 dcn20_disable_plane(dc, old_pipe_ctx); 1311 } 1312 1313 if ((!pipe_ctx->plane_state || 1314 pipe_ctx->stream_res.tg != old_pipe_ctx->stream_res.tg) && 1315 old_pipe_ctx->plane_state && 1316 old_pipe_ctx->stream_res.tg == tg) { 1317 1318 dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx); 1319 removed_pipe[i] = true; 1320 1321 DC_LOG_DC("Reset mpcc for pipe %d\n", 1322 old_pipe_ctx->pipe_idx); 1323 } 1324 } 1325 1326 if (num_planes > 0) 1327 dcn20_program_all_pipe_in_tree(dc, top_pipe_to_program, context); 1328 1329 /* Program secondary blending tree and writeback pipes */ 1330 if ((stream->num_wb_info > 0) && (dc->hwss.program_all_writeback_pipes_in_tree)) 1331 dc->hwss.program_all_writeback_pipes_in_tree(dc, stream, context); 1332 1333 if (interdependent_update) 1334 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1335 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1336 1337 /* Skip inactive pipes and ones already updated */ 1338 if (!pipe_ctx->stream || pipe_ctx->stream == stream || 1339 !pipe_ctx->plane_state || !tg->funcs->is_tg_enabled(tg)) 1340 continue; 1341 1342 pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent( 1343 pipe_ctx->plane_res.hubp, 1344 &pipe_ctx->dlg_regs, 1345 &pipe_ctx->ttu_regs); 1346 } 1347 1348 if (interdependent_update) 1349 lock_all_pipes(dc, context, false); 1350 else 1351 dcn20_pipe_control_lock(dc, top_pipe_to_program, false); 1352 1353 for (i = 0; i < dc->res_pool->pipe_count; i++) 1354 if (removed_pipe[i]) 1355 dcn20_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1356 } 1357 1358 1359 void dcn20_prepare_bandwidth( 1360 struct dc *dc, 1361 struct dc_state *context) 1362 { 1363 struct hubbub *hubbub = dc->res_pool->hubbub; 1364 1365 /* program dchubbub watermarks */ 1366 hubbub->funcs->program_watermarks(hubbub, 1367 &context->bw_ctx.bw.dcn.watermarks, 1368 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1369 false); 1370 1371 dc->clk_mgr->funcs->update_clocks( 1372 dc->clk_mgr, 1373 context, 1374 false); 1375 } 1376 1377 void dcn20_optimize_bandwidth( 1378 struct dc *dc, 1379 struct dc_state *context) 1380 { 1381 struct hubbub *hubbub = dc->res_pool->hubbub; 1382 1383 /* program dchubbub watermarks */ 1384 hubbub->funcs->program_watermarks(hubbub, 1385 &context->bw_ctx.bw.dcn.watermarks, 1386 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1387 true); 1388 1389 dc->clk_mgr->funcs->update_clocks( 1390 dc->clk_mgr, 1391 context, 1392 true); 1393 } 1394 1395 bool dcn20_update_bandwidth( 1396 struct dc *dc, 1397 struct dc_state *context) 1398 { 1399 int i; 1400 1401 /* recalculate DML parameters */ 1402 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) 1403 return false; 1404 1405 /* apply updated bandwidth parameters */ 1406 dc->hwss.prepare_bandwidth(dc, context); 1407 1408 /* update hubp configs for all pipes */ 1409 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1410 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1411 1412 if (pipe_ctx->plane_state == NULL) 1413 continue; 1414 1415 if (pipe_ctx->top_pipe == NULL) { 1416 bool blank = !is_pipe_tree_visible(pipe_ctx); 1417 1418 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1419 pipe_ctx->stream_res.tg, 1420 pipe_ctx->pipe_dlg_param.vready_offset, 1421 pipe_ctx->pipe_dlg_param.vstartup_start, 1422 pipe_ctx->pipe_dlg_param.vupdate_offset, 1423 pipe_ctx->pipe_dlg_param.vupdate_width); 1424 1425 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1426 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1427 1428 dc->hwss.blank_pixel_data(dc, pipe_ctx, blank); 1429 } 1430 1431 pipe_ctx->plane_res.hubp->funcs->hubp_setup( 1432 pipe_ctx->plane_res.hubp, 1433 &pipe_ctx->dlg_regs, 1434 &pipe_ctx->ttu_regs, 1435 &pipe_ctx->rq_regs, 1436 &pipe_ctx->pipe_dlg_param); 1437 } 1438 1439 return true; 1440 } 1441 1442 static void dcn20_enable_writeback( 1443 struct dc *dc, 1444 const struct dc_stream_status *stream_status, 1445 struct dc_writeback_info *wb_info) 1446 { 1447 struct dwbc *dwb; 1448 struct mcif_wb *mcif_wb; 1449 struct timing_generator *optc; 1450 1451 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 1452 ASSERT(wb_info->wb_enabled); 1453 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 1454 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 1455 1456 /* set the OPTC source mux */ 1457 ASSERT(stream_status->primary_otg_inst < MAX_PIPES); 1458 optc = dc->res_pool->timing_generators[stream_status->primary_otg_inst]; 1459 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); 1460 /* set MCIF_WB buffer and arbitration configuration */ 1461 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 1462 mcif_wb->funcs->config_mcif_arb(mcif_wb, &dc->current_state->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 1463 /* Enable MCIF_WB */ 1464 mcif_wb->funcs->enable_mcif(mcif_wb); 1465 /* Enable DWB */ 1466 dwb->funcs->enable(dwb, &wb_info->dwb_params); 1467 /* TODO: add sequence to enable/disable warmup */ 1468 } 1469 1470 void dcn20_disable_writeback( 1471 struct dc *dc, 1472 unsigned int dwb_pipe_inst) 1473 { 1474 struct dwbc *dwb; 1475 struct mcif_wb *mcif_wb; 1476 1477 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); 1478 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; 1479 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; 1480 1481 dwb->funcs->disable(dwb); 1482 mcif_wb->funcs->disable_mcif(mcif_wb); 1483 } 1484 1485 bool dcn20_hwss_wait_for_blank_complete( 1486 struct output_pixel_processor *opp) 1487 { 1488 int counter; 1489 1490 for (counter = 0; counter < 1000; counter++) { 1491 if (opp->funcs->dpg_is_blanked(opp)) 1492 break; 1493 1494 udelay(100); 1495 } 1496 1497 if (counter == 1000) { 1498 dm_error("DC: failed to blank crtc!\n"); 1499 return false; 1500 } 1501 1502 return true; 1503 } 1504 1505 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) 1506 { 1507 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1508 1509 if (!hubp) 1510 return false; 1511 return hubp->funcs->dmdata_status_done(hubp); 1512 } 1513 1514 static void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 1515 { 1516 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1517 struct dce_hwseq *hws = dc->hwseq; 1518 struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); 1519 1520 if (pipe_ctx->stream_res.dsc) { 1521 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); 1522 if (bot_odm_pipe) 1523 dcn20_dsc_pg_control(hws, bot_odm_pipe->stream_res.dsc->inst, true); 1524 } 1525 #endif 1526 } 1527 1528 static void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 1529 { 1530 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1531 struct dce_hwseq *hws = dc->hwseq; 1532 struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx); 1533 1534 if (pipe_ctx->stream_res.dsc) { 1535 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false); 1536 if (bot_odm_pipe) 1537 dcn20_dsc_pg_control(hws, bot_odm_pipe->stream_res.dsc->inst, false); 1538 } 1539 #endif 1540 } 1541 1542 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) 1543 { 1544 struct dc_dmdata_attributes attr = { 0 }; 1545 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1546 1547 attr.dmdata_mode = DMDATA_HW_MODE; 1548 attr.dmdata_size = 1549 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; 1550 attr.address.quad_part = 1551 pipe_ctx->stream->dmdata_address.quad_part; 1552 attr.dmdata_dl_delta = 0; 1553 attr.dmdata_qos_mode = 0; 1554 attr.dmdata_qos_level = 0; 1555 attr.dmdata_repeat = 1; /* always repeat */ 1556 attr.dmdata_updated = 1; 1557 attr.dmdata_sw_data = NULL; 1558 1559 hubp->funcs->dmdata_set_attributes(hubp, &attr); 1560 } 1561 1562 void dcn20_disable_stream(struct pipe_ctx *pipe_ctx, int option) 1563 { 1564 dce110_disable_stream(pipe_ctx, option); 1565 } 1566 1567 static void dcn20_init_vm_ctx( 1568 struct dce_hwseq *hws, 1569 struct dc *dc, 1570 struct dc_virtual_addr_space_config *va_config, 1571 int vmid) 1572 { 1573 struct dcn_hubbub_virt_addr_config config; 1574 1575 if (vmid == 0) { 1576 ASSERT(0); /* VMID cannot be 0 for vm context */ 1577 return; 1578 } 1579 1580 config.page_table_start_addr = va_config->page_table_start_addr; 1581 config.page_table_end_addr = va_config->page_table_end_addr; 1582 config.page_table_block_size = va_config->page_table_block_size_in_bytes; 1583 config.page_table_depth = va_config->page_table_depth; 1584 config.page_table_base_addr = va_config->page_table_base_addr; 1585 1586 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); 1587 } 1588 1589 static int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 1590 { 1591 struct dcn_hubbub_phys_addr_config config; 1592 1593 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 1594 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 1595 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 1596 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 1597 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 1598 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 1599 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 1600 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 1601 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 1602 1603 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 1604 } 1605 1606 static bool patch_address_for_sbs_tb_stereo( 1607 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) 1608 { 1609 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1610 bool sec_split = pipe_ctx->top_pipe && 1611 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; 1612 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && 1613 (pipe_ctx->stream->timing.timing_3d_format == 1614 TIMING_3D_FORMAT_SIDE_BY_SIDE || 1615 pipe_ctx->stream->timing.timing_3d_format == 1616 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { 1617 *addr = plane_state->address.grph_stereo.left_addr; 1618 plane_state->address.grph_stereo.left_addr = 1619 plane_state->address.grph_stereo.right_addr; 1620 return true; 1621 } 1622 1623 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && 1624 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { 1625 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; 1626 plane_state->address.grph_stereo.right_addr = 1627 plane_state->address.grph_stereo.left_addr; 1628 } 1629 return false; 1630 } 1631 1632 1633 static void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) 1634 { 1635 bool addr_patched = false; 1636 PHYSICAL_ADDRESS_LOC addr; 1637 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1638 1639 if (plane_state == NULL) 1640 return; 1641 1642 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); 1643 1644 // Call Helper to track VMID use 1645 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); 1646 1647 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( 1648 pipe_ctx->plane_res.hubp, 1649 &plane_state->address, 1650 plane_state->flip_immediate); 1651 1652 plane_state->status.requested_address = plane_state->address; 1653 1654 if (plane_state->flip_immediate) 1655 plane_state->status.current_address = plane_state->address; 1656 1657 if (addr_patched) 1658 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; 1659 } 1660 1661 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, 1662 struct dc_link_settings *link_settings) 1663 { 1664 struct encoder_unblank_param params = { { 0 } }; 1665 struct dc_stream_state *stream = pipe_ctx->stream; 1666 struct dc_link *link = stream->link; 1667 params.odm = dc_res_get_odm_bottom_pipe(pipe_ctx); 1668 1669 /* only 3 items below are used by unblank */ 1670 params.timing = pipe_ctx->stream->timing; 1671 1672 params.link_settings.link_rate = link_settings->link_rate; 1673 1674 if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1675 if (optc1_is_two_pixels_per_containter(&stream->timing) || params.odm) 1676 params.timing.pix_clk_100hz /= 2; 1677 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 1678 pipe_ctx->stream_res.stream_enc, params.odm); 1679 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); 1680 } 1681 1682 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1683 link->dc->hwss.edp_backlight_control(link, true); 1684 } 1685 } 1686 1687 void dcn20_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx) 1688 { 1689 struct timing_generator *tg = pipe_ctx->stream_res.tg; 1690 int start_line = get_vupdate_offset_from_vsync(pipe_ctx); 1691 1692 if (start_line < 0) 1693 start_line = 0; 1694 1695 if (tg->funcs->setup_vertical_interrupt2) 1696 tg->funcs->setup_vertical_interrupt2(tg, start_line); 1697 } 1698 1699 static void dcn20_reset_back_end_for_pipe( 1700 struct dc *dc, 1701 struct pipe_ctx *pipe_ctx, 1702 struct dc_state *context) 1703 { 1704 int i; 1705 DC_LOGGER_INIT(dc->ctx->logger); 1706 if (pipe_ctx->stream_res.stream_enc == NULL) { 1707 pipe_ctx->stream = NULL; 1708 return; 1709 } 1710 1711 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 1712 /* DPMS may already disable */ 1713 if (!pipe_ctx->stream->dpms_off) 1714 core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE); 1715 else if (pipe_ctx->stream_res.audio) { 1716 dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE); 1717 } 1718 1719 } 1720 1721 /* by upper caller loop, parent pipe: pipe0, will be reset last. 1722 * back end share by all pipes and will be disable only when disable 1723 * parent pipe. 1724 */ 1725 if (pipe_ctx->top_pipe == NULL) { 1726 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 1727 1728 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 1729 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 1730 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1731 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1732 } 1733 1734 for (i = 0; i < dc->res_pool->pipe_count; i++) 1735 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) 1736 break; 1737 1738 if (i == dc->res_pool->pipe_count) 1739 return; 1740 1741 pipe_ctx->stream = NULL; 1742 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 1743 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 1744 } 1745 1746 static void dcn20_reset_hw_ctx_wrap( 1747 struct dc *dc, 1748 struct dc_state *context) 1749 { 1750 int i; 1751 1752 /* Reset Back End*/ 1753 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 1754 struct pipe_ctx *pipe_ctx_old = 1755 &dc->current_state->res_ctx.pipe_ctx[i]; 1756 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1757 1758 if (!pipe_ctx_old->stream) 1759 continue; 1760 1761 if (pipe_ctx_old->top_pipe) 1762 continue; 1763 1764 if (!pipe_ctx->stream || 1765 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 1766 struct clock_source *old_clk = pipe_ctx_old->clock_source; 1767 1768 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 1769 if (dc->hwss.enable_stream_gating) 1770 dc->hwss.enable_stream_gating(dc, pipe_ctx); 1771 if (old_clk) 1772 old_clk->funcs->cs_power_down(old_clk); 1773 } 1774 } 1775 } 1776 1777 static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 1778 { 1779 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1780 struct mpcc_blnd_cfg blnd_cfg = { {0} }; 1781 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; 1782 int mpcc_id; 1783 struct mpcc *new_mpcc; 1784 struct mpc *mpc = dc->res_pool->mpc; 1785 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); 1786 1787 // input to MPCC is always RGB, by default leave black_color at 0 1788 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) { 1789 dcn10_get_hdr_visual_confirm_color( 1790 pipe_ctx, &blnd_cfg.black_color); 1791 } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) { 1792 dcn10_get_surface_visual_confirm_color( 1793 pipe_ctx, &blnd_cfg.black_color); 1794 } 1795 1796 if (per_pixel_alpha) 1797 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 1798 else 1799 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 1800 1801 blnd_cfg.overlap_only = false; 1802 blnd_cfg.global_gain = 0xff; 1803 1804 if (pipe_ctx->plane_state->global_alpha) 1805 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; 1806 else 1807 blnd_cfg.global_alpha = 0xff; 1808 1809 blnd_cfg.background_color_bpc = 4; 1810 blnd_cfg.bottom_gain_mode = 0; 1811 blnd_cfg.top_gain = 0x1f000; 1812 blnd_cfg.bottom_inside_gain = 0x1f000; 1813 blnd_cfg.bottom_outside_gain = 0x1f000; 1814 blnd_cfg.pre_multiplied_alpha = per_pixel_alpha; 1815 1816 /* 1817 * TODO: remove hack 1818 * Note: currently there is a bug in init_hw such that 1819 * on resume from hibernate, BIOS sets up MPCC0, and 1820 * we do mpcc_remove but the mpcc cannot go to idle 1821 * after remove. This cause us to pick mpcc1 here, 1822 * which causes a pstate hang for yet unknown reason. 1823 */ 1824 mpcc_id = hubp->inst; 1825 1826 /* If there is no full update, don't need to touch MPC tree*/ 1827 if (!pipe_ctx->plane_state->update_flags.bits.full_update) { 1828 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); 1829 return; 1830 } 1831 1832 /* check if this MPCC is already being used */ 1833 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 1834 /* remove MPCC if being used */ 1835 if (new_mpcc != NULL) 1836 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); 1837 else 1838 if (dc->debug.sanity_checks) 1839 mpc->funcs->assert_mpcc_idle_before_connect( 1840 dc->res_pool->mpc, mpcc_id); 1841 1842 /* Call MPC to insert new plane */ 1843 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, 1844 mpc_tree_params, 1845 &blnd_cfg, 1846 NULL, 1847 NULL, 1848 hubp->inst, 1849 mpcc_id); 1850 1851 ASSERT(new_mpcc != NULL); 1852 hubp->opp_id = pipe_ctx->stream_res.opp->inst; 1853 hubp->mpcc_id = mpcc_id; 1854 } 1855 1856 static int find_free_gsl_group(const struct dc *dc) 1857 { 1858 if (dc->res_pool->gsl_groups.gsl_0 == 0) 1859 return 1; 1860 if (dc->res_pool->gsl_groups.gsl_1 == 0) 1861 return 2; 1862 if (dc->res_pool->gsl_groups.gsl_2 == 0) 1863 return 3; 1864 1865 return 0; 1866 } 1867 1868 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock) 1869 * This is only used to lock pipes in pipe splitting case with immediate flip 1870 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate, 1871 * so we get tearing with freesync since we cannot flip multiple pipes 1872 * atomically. 1873 * We use GSL for this: 1874 * - immediate flip: find first available GSL group if not already assigned 1875 * program gsl with that group, set current OTG as master 1876 * and always us 0x4 = AND of flip_ready from all pipes 1877 * - vsync flip: disable GSL if used 1878 * 1879 * Groups in stream_res are stored as +1 from HW registers, i.e. 1880 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1 1881 * Using a magic value like -1 would require tracking all inits/resets 1882 */ 1883 void dcn20_setup_gsl_group_as_lock( 1884 const struct dc *dc, 1885 struct pipe_ctx *pipe_ctx, 1886 bool enable) 1887 { 1888 struct gsl_params gsl; 1889 int group_idx; 1890 1891 memset(&gsl, 0, sizeof(struct gsl_params)); 1892 1893 if (enable) { 1894 /* return if group already assigned since GSL was set up 1895 * for vsync flip, we would unassign so it can't be "left over" 1896 */ 1897 if (pipe_ctx->stream_res.gsl_group > 0) 1898 return; 1899 1900 group_idx = find_free_gsl_group(dc); 1901 ASSERT(group_idx != 0); 1902 pipe_ctx->stream_res.gsl_group = group_idx; 1903 1904 /* set gsl group reg field and mark resource used */ 1905 switch (group_idx) { 1906 case 1: 1907 gsl.gsl0_en = 1; 1908 dc->res_pool->gsl_groups.gsl_0 = 1; 1909 break; 1910 case 2: 1911 gsl.gsl1_en = 1; 1912 dc->res_pool->gsl_groups.gsl_1 = 1; 1913 break; 1914 case 3: 1915 gsl.gsl2_en = 1; 1916 dc->res_pool->gsl_groups.gsl_2 = 1; 1917 break; 1918 default: 1919 BREAK_TO_DEBUGGER(); 1920 return; // invalid case 1921 } 1922 gsl.gsl_master_en = 1; 1923 } else { 1924 group_idx = pipe_ctx->stream_res.gsl_group; 1925 if (group_idx == 0) 1926 return; // if not in use, just return 1927 1928 pipe_ctx->stream_res.gsl_group = 0; 1929 1930 /* unset gsl group reg field and mark resource free */ 1931 switch (group_idx) { 1932 case 1: 1933 gsl.gsl0_en = 0; 1934 dc->res_pool->gsl_groups.gsl_0 = 0; 1935 break; 1936 case 2: 1937 gsl.gsl1_en = 0; 1938 dc->res_pool->gsl_groups.gsl_1 = 0; 1939 break; 1940 case 3: 1941 gsl.gsl2_en = 0; 1942 dc->res_pool->gsl_groups.gsl_2 = 0; 1943 break; 1944 default: 1945 BREAK_TO_DEBUGGER(); 1946 return; 1947 } 1948 gsl.gsl_master_en = 0; 1949 } 1950 1951 /* at this point we want to program whether it's to enable or disable */ 1952 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && 1953 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { 1954 pipe_ctx->stream_res.tg->funcs->set_gsl( 1955 pipe_ctx->stream_res.tg, 1956 &gsl); 1957 1958 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( 1959 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); 1960 } else 1961 BREAK_TO_DEBUGGER(); 1962 } 1963 1964 static void dcn20_set_flip_control_gsl( 1965 struct pipe_ctx *pipe_ctx, 1966 bool flip_immediate) 1967 { 1968 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) 1969 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( 1970 pipe_ctx->plane_res.hubp, flip_immediate); 1971 1972 } 1973 1974 void dcn20_hw_sequencer_construct(struct dc *dc) 1975 { 1976 dcn10_hw_sequencer_construct(dc); 1977 dc->hwss.init_hw = dcn20_init_hw; 1978 dc->hwss.init_pipes = NULL; 1979 dc->hwss.unblank_stream = dcn20_unblank_stream; 1980 dc->hwss.update_plane_addr = dcn20_update_plane_addr; 1981 dc->hwss.disable_plane = dcn20_disable_plane, 1982 dc->hwss.enable_stream_timing = dcn20_enable_stream_timing; 1983 dc->hwss.program_triplebuffer = dcn20_program_tripleBuffer; 1984 dc->hwss.set_input_transfer_func = dcn20_set_input_transfer_func; 1985 dc->hwss.set_output_transfer_func = dcn20_set_output_transfer_func; 1986 dc->hwss.apply_ctx_for_surface = dcn20_apply_ctx_for_surface; 1987 dc->hwss.pipe_control_lock = dcn20_pipe_control_lock; 1988 dc->hwss.pipe_control_lock_global = dcn20_pipe_control_lock_global; 1989 dc->hwss.optimize_bandwidth = dcn20_optimize_bandwidth; 1990 dc->hwss.prepare_bandwidth = dcn20_prepare_bandwidth; 1991 dc->hwss.update_bandwidth = dcn20_update_bandwidth; 1992 dc->hwss.enable_writeback = dcn20_enable_writeback; 1993 dc->hwss.disable_writeback = dcn20_disable_writeback; 1994 dc->hwss.program_output_csc = dcn20_program_output_csc; 1995 dc->hwss.update_odm = dcn20_update_odm; 1996 dc->hwss.blank_pixel_data = dcn20_blank_pixel_data; 1997 dc->hwss.dmdata_status_done = dcn20_dmdata_status_done; 1998 dc->hwss.disable_stream = dcn20_disable_stream; 1999 dc->hwss.init_sys_ctx = dcn20_init_sys_ctx; 2000 dc->hwss.init_vm_ctx = dcn20_init_vm_ctx; 2001 dc->hwss.disable_stream_gating = dcn20_disable_stream_gating; 2002 dc->hwss.enable_stream_gating = dcn20_enable_stream_gating; 2003 dc->hwss.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt; 2004 dc->hwss.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap; 2005 dc->hwss.update_mpcc = dcn20_update_mpcc; 2006 dc->hwss.set_flip_control_gsl = dcn20_set_flip_control_gsl; 2007 dc->hwss.did_underflow_occur = dcn10_did_underflow_occur; 2008 } 2009