1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include <linux/delay.h> 26 27 #include "dm_services.h" 28 #include "basics/dc_common.h" 29 #include "dm_helpers.h" 30 #include "core_types.h" 31 #include "resource.h" 32 #include "dcn20_resource.h" 33 #include "dcn20_hwseq.h" 34 #include "dce/dce_hwseq.h" 35 #include "dcn20_dsc.h" 36 #include "dcn20_optc.h" 37 #include "abm.h" 38 #include "clk_mgr.h" 39 #include "dmcu.h" 40 #include "hubp.h" 41 #include "timing_generator.h" 42 #include "opp.h" 43 #include "ipp.h" 44 #include "mpc.h" 45 #include "mcif_wb.h" 46 #include "dchubbub.h" 47 #include "reg_helper.h" 48 #include "dcn10/dcn10_cm_common.h" 49 #include "dc_link_dp.h" 50 #include "vm_helper.h" 51 #include "dccg.h" 52 #include "dc_dmub_srv.h" 53 #include "dce/dmub_hw_lock_mgr.h" 54 #include "hw_sequencer.h" 55 #include "inc/link_dpcd.h" 56 #include "dpcd_defs.h" 57 #include "inc/link_enc_cfg.h" 58 #include "link_hwss.h" 59 60 #define DC_LOGGER_INIT(logger) 61 62 #define CTX \ 63 hws->ctx 64 #define REG(reg)\ 65 hws->regs->reg 66 67 #undef FN 68 #define FN(reg_name, field_name) \ 69 hws->shifts->field_name, hws->masks->field_name 70 71 static int find_free_gsl_group(const struct dc *dc) 72 { 73 if (dc->res_pool->gsl_groups.gsl_0 == 0) 74 return 1; 75 if (dc->res_pool->gsl_groups.gsl_1 == 0) 76 return 2; 77 if (dc->res_pool->gsl_groups.gsl_2 == 0) 78 return 3; 79 80 return 0; 81 } 82 83 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock) 84 * This is only used to lock pipes in pipe splitting case with immediate flip 85 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate, 86 * so we get tearing with freesync since we cannot flip multiple pipes 87 * atomically. 88 * We use GSL for this: 89 * - immediate flip: find first available GSL group if not already assigned 90 * program gsl with that group, set current OTG as master 91 * and always us 0x4 = AND of flip_ready from all pipes 92 * - vsync flip: disable GSL if used 93 * 94 * Groups in stream_res are stored as +1 from HW registers, i.e. 95 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1 96 * Using a magic value like -1 would require tracking all inits/resets 97 */ 98 static void dcn20_setup_gsl_group_as_lock( 99 const struct dc *dc, 100 struct pipe_ctx *pipe_ctx, 101 bool enable) 102 { 103 struct gsl_params gsl; 104 int group_idx; 105 106 memset(&gsl, 0, sizeof(struct gsl_params)); 107 108 if (enable) { 109 /* return if group already assigned since GSL was set up 110 * for vsync flip, we would unassign so it can't be "left over" 111 */ 112 if (pipe_ctx->stream_res.gsl_group > 0) 113 return; 114 115 group_idx = find_free_gsl_group(dc); 116 ASSERT(group_idx != 0); 117 pipe_ctx->stream_res.gsl_group = group_idx; 118 119 /* set gsl group reg field and mark resource used */ 120 switch (group_idx) { 121 case 1: 122 gsl.gsl0_en = 1; 123 dc->res_pool->gsl_groups.gsl_0 = 1; 124 break; 125 case 2: 126 gsl.gsl1_en = 1; 127 dc->res_pool->gsl_groups.gsl_1 = 1; 128 break; 129 case 3: 130 gsl.gsl2_en = 1; 131 dc->res_pool->gsl_groups.gsl_2 = 1; 132 break; 133 default: 134 BREAK_TO_DEBUGGER(); 135 return; // invalid case 136 } 137 gsl.gsl_master_en = 1; 138 } else { 139 group_idx = pipe_ctx->stream_res.gsl_group; 140 if (group_idx == 0) 141 return; // if not in use, just return 142 143 pipe_ctx->stream_res.gsl_group = 0; 144 145 /* unset gsl group reg field and mark resource free */ 146 switch (group_idx) { 147 case 1: 148 gsl.gsl0_en = 0; 149 dc->res_pool->gsl_groups.gsl_0 = 0; 150 break; 151 case 2: 152 gsl.gsl1_en = 0; 153 dc->res_pool->gsl_groups.gsl_1 = 0; 154 break; 155 case 3: 156 gsl.gsl2_en = 0; 157 dc->res_pool->gsl_groups.gsl_2 = 0; 158 break; 159 default: 160 BREAK_TO_DEBUGGER(); 161 return; 162 } 163 gsl.gsl_master_en = 0; 164 } 165 166 /* at this point we want to program whether it's to enable or disable */ 167 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && 168 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { 169 pipe_ctx->stream_res.tg->funcs->set_gsl( 170 pipe_ctx->stream_res.tg, 171 &gsl); 172 173 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( 174 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); 175 } else 176 BREAK_TO_DEBUGGER(); 177 } 178 179 void dcn20_set_flip_control_gsl( 180 struct pipe_ctx *pipe_ctx, 181 bool flip_immediate) 182 { 183 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) 184 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( 185 pipe_ctx->plane_res.hubp, flip_immediate); 186 187 } 188 189 void dcn20_enable_power_gating_plane( 190 struct dce_hwseq *hws, 191 bool enable) 192 { 193 bool force_on = true; /* disable power gating */ 194 195 if (enable) 196 force_on = false; 197 198 /* DCHUBP0/1/2/3/4/5 */ 199 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); 200 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); 201 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); 202 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); 203 if (REG(DOMAIN8_PG_CONFIG)) 204 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 205 if (REG(DOMAIN10_PG_CONFIG)) 206 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 207 208 /* DPP0/1/2/3/4/5 */ 209 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); 210 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); 211 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); 212 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); 213 if (REG(DOMAIN9_PG_CONFIG)) 214 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 215 if (REG(DOMAIN11_PG_CONFIG)) 216 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 217 218 /* DCS0/1/2/3/4/5 */ 219 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on); 220 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on); 221 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on); 222 if (REG(DOMAIN19_PG_CONFIG)) 223 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on); 224 if (REG(DOMAIN20_PG_CONFIG)) 225 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on); 226 if (REG(DOMAIN21_PG_CONFIG)) 227 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); 228 } 229 230 void dcn20_dccg_init(struct dce_hwseq *hws) 231 { 232 /* 233 * set MICROSECOND_TIME_BASE_DIV 234 * 100Mhz refclk -> 0x120264 235 * 27Mhz refclk -> 0x12021b 236 * 48Mhz refclk -> 0x120230 237 * 238 */ 239 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); 240 241 /* 242 * set MILLISECOND_TIME_BASE_DIV 243 * 100Mhz refclk -> 0x1186a0 244 * 27Mhz refclk -> 0x106978 245 * 48Mhz refclk -> 0x10bb80 246 * 247 */ 248 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); 249 250 /* This value is dependent on the hardware pipeline delay so set once per SOC */ 251 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c); 252 } 253 254 void dcn20_disable_vga( 255 struct dce_hwseq *hws) 256 { 257 REG_WRITE(D1VGA_CONTROL, 0); 258 REG_WRITE(D2VGA_CONTROL, 0); 259 REG_WRITE(D3VGA_CONTROL, 0); 260 REG_WRITE(D4VGA_CONTROL, 0); 261 REG_WRITE(D5VGA_CONTROL, 0); 262 REG_WRITE(D6VGA_CONTROL, 0); 263 } 264 265 void dcn20_program_triple_buffer( 266 const struct dc *dc, 267 struct pipe_ctx *pipe_ctx, 268 bool enable_triple_buffer) 269 { 270 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { 271 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( 272 pipe_ctx->plane_res.hubp, 273 enable_triple_buffer); 274 } 275 } 276 277 /* Blank pixel data during initialization */ 278 void dcn20_init_blank( 279 struct dc *dc, 280 struct timing_generator *tg) 281 { 282 struct dce_hwseq *hws = dc->hwseq; 283 enum dc_color_space color_space; 284 struct tg_color black_color = {0}; 285 struct output_pixel_processor *opp = NULL; 286 struct output_pixel_processor *bottom_opp = NULL; 287 uint32_t num_opps, opp_id_src0, opp_id_src1; 288 uint32_t otg_active_width, otg_active_height; 289 290 /* program opp dpg blank color */ 291 color_space = COLOR_SPACE_SRGB; 292 color_space_to_black_color(dc, color_space, &black_color); 293 294 /* get the OTG active size */ 295 tg->funcs->get_otg_active_size(tg, 296 &otg_active_width, 297 &otg_active_height); 298 299 /* get the OPTC source */ 300 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 301 302 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { 303 ASSERT(false); 304 return; 305 } 306 opp = dc->res_pool->opps[opp_id_src0]; 307 308 if (num_opps == 2) { 309 otg_active_width = otg_active_width / 2; 310 311 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { 312 ASSERT(false); 313 return; 314 } 315 bottom_opp = dc->res_pool->opps[opp_id_src1]; 316 } 317 318 opp->funcs->opp_set_disp_pattern_generator( 319 opp, 320 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 321 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 322 COLOR_DEPTH_UNDEFINED, 323 &black_color, 324 otg_active_width, 325 otg_active_height, 326 0); 327 328 if (num_opps == 2) { 329 bottom_opp->funcs->opp_set_disp_pattern_generator( 330 bottom_opp, 331 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 332 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 333 COLOR_DEPTH_UNDEFINED, 334 &black_color, 335 otg_active_width, 336 otg_active_height, 337 0); 338 } 339 340 hws->funcs.wait_for_blank_complete(opp); 341 } 342 343 void dcn20_dsc_pg_control( 344 struct dce_hwseq *hws, 345 unsigned int dsc_inst, 346 bool power_on) 347 { 348 uint32_t power_gate = power_on ? 0 : 1; 349 uint32_t pwr_status = power_on ? 0 : 2; 350 uint32_t org_ip_request_cntl = 0; 351 352 if (hws->ctx->dc->debug.disable_dsc_power_gate) 353 return; 354 355 if (REG(DOMAIN16_PG_CONFIG) == 0) 356 return; 357 358 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 359 if (org_ip_request_cntl == 0) 360 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 361 362 switch (dsc_inst) { 363 case 0: /* DSC0 */ 364 REG_UPDATE(DOMAIN16_PG_CONFIG, 365 DOMAIN16_POWER_GATE, power_gate); 366 367 REG_WAIT(DOMAIN16_PG_STATUS, 368 DOMAIN16_PGFSM_PWR_STATUS, pwr_status, 369 1, 1000); 370 break; 371 case 1: /* DSC1 */ 372 REG_UPDATE(DOMAIN17_PG_CONFIG, 373 DOMAIN17_POWER_GATE, power_gate); 374 375 REG_WAIT(DOMAIN17_PG_STATUS, 376 DOMAIN17_PGFSM_PWR_STATUS, pwr_status, 377 1, 1000); 378 break; 379 case 2: /* DSC2 */ 380 REG_UPDATE(DOMAIN18_PG_CONFIG, 381 DOMAIN18_POWER_GATE, power_gate); 382 383 REG_WAIT(DOMAIN18_PG_STATUS, 384 DOMAIN18_PGFSM_PWR_STATUS, pwr_status, 385 1, 1000); 386 break; 387 case 3: /* DSC3 */ 388 REG_UPDATE(DOMAIN19_PG_CONFIG, 389 DOMAIN19_POWER_GATE, power_gate); 390 391 REG_WAIT(DOMAIN19_PG_STATUS, 392 DOMAIN19_PGFSM_PWR_STATUS, pwr_status, 393 1, 1000); 394 break; 395 case 4: /* DSC4 */ 396 REG_UPDATE(DOMAIN20_PG_CONFIG, 397 DOMAIN20_POWER_GATE, power_gate); 398 399 REG_WAIT(DOMAIN20_PG_STATUS, 400 DOMAIN20_PGFSM_PWR_STATUS, pwr_status, 401 1, 1000); 402 break; 403 case 5: /* DSC5 */ 404 REG_UPDATE(DOMAIN21_PG_CONFIG, 405 DOMAIN21_POWER_GATE, power_gate); 406 407 REG_WAIT(DOMAIN21_PG_STATUS, 408 DOMAIN21_PGFSM_PWR_STATUS, pwr_status, 409 1, 1000); 410 break; 411 default: 412 BREAK_TO_DEBUGGER(); 413 break; 414 } 415 416 if (org_ip_request_cntl == 0) 417 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 418 } 419 420 void dcn20_dpp_pg_control( 421 struct dce_hwseq *hws, 422 unsigned int dpp_inst, 423 bool power_on) 424 { 425 uint32_t power_gate = power_on ? 0 : 1; 426 uint32_t pwr_status = power_on ? 0 : 2; 427 428 if (hws->ctx->dc->debug.disable_dpp_power_gate) 429 return; 430 if (REG(DOMAIN1_PG_CONFIG) == 0) 431 return; 432 433 switch (dpp_inst) { 434 case 0: /* DPP0 */ 435 REG_UPDATE(DOMAIN1_PG_CONFIG, 436 DOMAIN1_POWER_GATE, power_gate); 437 438 REG_WAIT(DOMAIN1_PG_STATUS, 439 DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 440 1, 1000); 441 break; 442 case 1: /* DPP1 */ 443 REG_UPDATE(DOMAIN3_PG_CONFIG, 444 DOMAIN3_POWER_GATE, power_gate); 445 446 REG_WAIT(DOMAIN3_PG_STATUS, 447 DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 448 1, 1000); 449 break; 450 case 2: /* DPP2 */ 451 REG_UPDATE(DOMAIN5_PG_CONFIG, 452 DOMAIN5_POWER_GATE, power_gate); 453 454 REG_WAIT(DOMAIN5_PG_STATUS, 455 DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 456 1, 1000); 457 break; 458 case 3: /* DPP3 */ 459 REG_UPDATE(DOMAIN7_PG_CONFIG, 460 DOMAIN7_POWER_GATE, power_gate); 461 462 REG_WAIT(DOMAIN7_PG_STATUS, 463 DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 464 1, 1000); 465 break; 466 case 4: /* DPP4 */ 467 REG_UPDATE(DOMAIN9_PG_CONFIG, 468 DOMAIN9_POWER_GATE, power_gate); 469 470 REG_WAIT(DOMAIN9_PG_STATUS, 471 DOMAIN9_PGFSM_PWR_STATUS, pwr_status, 472 1, 1000); 473 break; 474 case 5: /* DPP5 */ 475 /* 476 * Do not power gate DPP5, should be left at HW default, power on permanently. 477 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 478 * reset. 479 * REG_UPDATE(DOMAIN11_PG_CONFIG, 480 * DOMAIN11_POWER_GATE, power_gate); 481 * 482 * REG_WAIT(DOMAIN11_PG_STATUS, 483 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, 484 * 1, 1000); 485 */ 486 break; 487 default: 488 BREAK_TO_DEBUGGER(); 489 break; 490 } 491 } 492 493 494 void dcn20_hubp_pg_control( 495 struct dce_hwseq *hws, 496 unsigned int hubp_inst, 497 bool power_on) 498 { 499 uint32_t power_gate = power_on ? 0 : 1; 500 uint32_t pwr_status = power_on ? 0 : 2; 501 502 if (hws->ctx->dc->debug.disable_hubp_power_gate) 503 return; 504 if (REG(DOMAIN0_PG_CONFIG) == 0) 505 return; 506 507 switch (hubp_inst) { 508 case 0: /* DCHUBP0 */ 509 REG_UPDATE(DOMAIN0_PG_CONFIG, 510 DOMAIN0_POWER_GATE, power_gate); 511 512 REG_WAIT(DOMAIN0_PG_STATUS, 513 DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 514 1, 1000); 515 break; 516 case 1: /* DCHUBP1 */ 517 REG_UPDATE(DOMAIN2_PG_CONFIG, 518 DOMAIN2_POWER_GATE, power_gate); 519 520 REG_WAIT(DOMAIN2_PG_STATUS, 521 DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 522 1, 1000); 523 break; 524 case 2: /* DCHUBP2 */ 525 REG_UPDATE(DOMAIN4_PG_CONFIG, 526 DOMAIN4_POWER_GATE, power_gate); 527 528 REG_WAIT(DOMAIN4_PG_STATUS, 529 DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 530 1, 1000); 531 break; 532 case 3: /* DCHUBP3 */ 533 REG_UPDATE(DOMAIN6_PG_CONFIG, 534 DOMAIN6_POWER_GATE, power_gate); 535 536 REG_WAIT(DOMAIN6_PG_STATUS, 537 DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 538 1, 1000); 539 break; 540 case 4: /* DCHUBP4 */ 541 REG_UPDATE(DOMAIN8_PG_CONFIG, 542 DOMAIN8_POWER_GATE, power_gate); 543 544 REG_WAIT(DOMAIN8_PG_STATUS, 545 DOMAIN8_PGFSM_PWR_STATUS, pwr_status, 546 1, 1000); 547 break; 548 case 5: /* DCHUBP5 */ 549 /* 550 * Do not power gate DCHUB5, should be left at HW default, power on permanently. 551 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 552 * reset. 553 * REG_UPDATE(DOMAIN10_PG_CONFIG, 554 * DOMAIN10_POWER_GATE, power_gate); 555 * 556 * REG_WAIT(DOMAIN10_PG_STATUS, 557 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status, 558 * 1, 1000); 559 */ 560 break; 561 default: 562 BREAK_TO_DEBUGGER(); 563 break; 564 } 565 } 566 567 568 /* disable HW used by plane. 569 * note: cannot disable until disconnect is complete 570 */ 571 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 572 { 573 struct dce_hwseq *hws = dc->hwseq; 574 struct hubp *hubp = pipe_ctx->plane_res.hubp; 575 struct dpp *dpp = pipe_ctx->plane_res.dpp; 576 577 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); 578 579 /* In flip immediate with pipe splitting case GSL is used for 580 * synchronization so we must disable it when the plane is disabled. 581 */ 582 if (pipe_ctx->stream_res.gsl_group != 0) 583 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false); 584 585 dc->hwss.set_flip_control_gsl(pipe_ctx, false); 586 587 hubp->funcs->hubp_clk_cntl(hubp, false); 588 589 dpp->funcs->dpp_dppclk_control(dpp, false, false); 590 591 hubp->power_gated = true; 592 593 hws->funcs.plane_atomic_power_down(dc, 594 pipe_ctx->plane_res.dpp, 595 pipe_ctx->plane_res.hubp); 596 597 pipe_ctx->stream = NULL; 598 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); 599 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); 600 pipe_ctx->top_pipe = NULL; 601 pipe_ctx->bottom_pipe = NULL; 602 pipe_ctx->plane_state = NULL; 603 } 604 605 606 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) 607 { 608 DC_LOGGER_INIT(dc->ctx->logger); 609 610 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) 611 return; 612 613 dcn20_plane_atomic_disable(dc, pipe_ctx); 614 615 DC_LOG_DC("Power down front end %d\n", 616 pipe_ctx->pipe_idx); 617 } 618 619 void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank) 620 { 621 dcn20_blank_pixel_data(dc, pipe_ctx, blank); 622 } 623 624 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 625 int opp_cnt) 626 { 627 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 628 int flow_ctrl_cnt; 629 630 if (opp_cnt >= 2) 631 hblank_halved = true; 632 633 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 634 stream->timing.h_border_left - 635 stream->timing.h_border_right; 636 637 if (hblank_halved) 638 flow_ctrl_cnt /= 2; 639 640 /* ODM combine 4:1 case */ 641 if (opp_cnt == 4) 642 flow_ctrl_cnt /= 2; 643 644 return flow_ctrl_cnt; 645 } 646 647 enum dc_status dcn20_enable_stream_timing( 648 struct pipe_ctx *pipe_ctx, 649 struct dc_state *context, 650 struct dc *dc) 651 { 652 struct dce_hwseq *hws = dc->hwseq; 653 struct dc_stream_state *stream = pipe_ctx->stream; 654 struct drr_params params = {0}; 655 unsigned int event_triggers = 0; 656 struct pipe_ctx *odm_pipe; 657 int opp_cnt = 1; 658 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 659 bool interlace = stream->timing.flags.INTERLACE; 660 int i; 661 struct mpc_dwb_flow_control flow_control; 662 struct mpc *mpc = dc->res_pool->mpc; 663 bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing)); 664 unsigned int k1_div = PIXEL_RATE_DIV_NA; 665 unsigned int k2_div = PIXEL_RATE_DIV_NA; 666 667 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { 668 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); 669 670 dc->res_pool->dccg->funcs->set_pixel_rate_div( 671 dc->res_pool->dccg, 672 pipe_ctx->stream_res.tg->inst, 673 k1_div, k2_div); 674 } 675 /* by upper caller loop, pipe0 is parent pipe and be called first. 676 * back end is set up by for pipe0. Other children pipe share back end 677 * with pipe 0. No program is needed. 678 */ 679 if (pipe_ctx->top_pipe != NULL) 680 return DC_OK; 681 682 /* TODO check if timing_changed, disable stream if timing changed */ 683 684 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 685 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 686 opp_cnt++; 687 } 688 689 if (opp_cnt > 1) 690 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 691 pipe_ctx->stream_res.tg, 692 opp_inst, opp_cnt, 693 &pipe_ctx->stream->timing); 694 695 /* HW program guide assume display already disable 696 * by unplug sequence. OTG assume stop. 697 */ 698 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); 699 700 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 701 pipe_ctx->clock_source, 702 &pipe_ctx->stream_res.pix_clk_params, 703 &pipe_ctx->pll_settings)) { 704 BREAK_TO_DEBUGGER(); 705 return DC_ERROR_UNEXPECTED; 706 } 707 708 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal))) 709 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx); 710 711 pipe_ctx->stream_res.tg->funcs->program_timing( 712 pipe_ctx->stream_res.tg, 713 &stream->timing, 714 pipe_ctx->pipe_dlg_param.vready_offset, 715 pipe_ctx->pipe_dlg_param.vstartup_start, 716 pipe_ctx->pipe_dlg_param.vupdate_offset, 717 pipe_ctx->pipe_dlg_param.vupdate_width, 718 pipe_ctx->stream->signal, 719 true); 720 721 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 722 flow_control.flow_ctrl_mode = 0; 723 flow_control.flow_ctrl_cnt0 = 0x80; 724 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt); 725 if (mpc->funcs->set_out_rate_control) { 726 for (i = 0; i < opp_cnt; ++i) { 727 mpc->funcs->set_out_rate_control( 728 mpc, opp_inst[i], 729 true, 730 rate_control_2x_pclk, 731 &flow_control); 732 } 733 } 734 735 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 736 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 737 odm_pipe->stream_res.opp, 738 true); 739 740 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 741 pipe_ctx->stream_res.opp, 742 true); 743 744 hws->funcs.blank_pixel_data(dc, pipe_ctx, true); 745 746 /* VTG is within DCHUB command block. DCFCLK is always on */ 747 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { 748 BREAK_TO_DEBUGGER(); 749 return DC_ERROR_UNEXPECTED; 750 } 751 752 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp); 753 754 params.vertical_total_min = stream->adjust.v_total_min; 755 params.vertical_total_max = stream->adjust.v_total_max; 756 params.vertical_total_mid = stream->adjust.v_total_mid; 757 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num; 758 if (pipe_ctx->stream_res.tg->funcs->set_drr) 759 pipe_ctx->stream_res.tg->funcs->set_drr( 760 pipe_ctx->stream_res.tg, ¶ms); 761 762 // DRR should set trigger event to monitor surface update event 763 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 764 event_triggers = 0x80; 765 /* Event triggers and num frames initialized for DRR, but can be 766 * later updated for PSR use. Note DRR trigger events are generated 767 * regardless of whether num frames met. 768 */ 769 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 770 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 771 pipe_ctx->stream_res.tg, event_triggers, 2); 772 773 /* TODO program crtc source select for non-virtual signal*/ 774 /* TODO program FMT */ 775 /* TODO setup link_enc */ 776 /* TODO set stream attributes */ 777 /* TODO program audio */ 778 /* TODO enable stream if timing changed */ 779 /* TODO unblank stream if DP */ 780 781 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) { 782 if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable) 783 pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg); 784 } 785 return DC_OK; 786 } 787 788 void dcn20_program_output_csc(struct dc *dc, 789 struct pipe_ctx *pipe_ctx, 790 enum dc_color_space colorspace, 791 uint16_t *matrix, 792 int opp_id) 793 { 794 struct mpc *mpc = dc->res_pool->mpc; 795 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; 796 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 797 798 if (mpc->funcs->power_on_mpc_mem_pwr) 799 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 800 801 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 802 if (mpc->funcs->set_output_csc != NULL) 803 mpc->funcs->set_output_csc(mpc, 804 opp_id, 805 matrix, 806 ocsc_mode); 807 } else { 808 if (mpc->funcs->set_ocsc_default != NULL) 809 mpc->funcs->set_ocsc_default(mpc, 810 opp_id, 811 colorspace, 812 ocsc_mode); 813 } 814 } 815 816 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 817 const struct dc_stream_state *stream) 818 { 819 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 820 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 821 struct pwl_params *params = NULL; 822 /* 823 * program OGAM only for the top pipe 824 * if there is a pipe split then fix diagnostic is required: 825 * how to pass OGAM parameter for stream. 826 * if programming for all pipes is required then remove condition 827 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic. 828 */ 829 if (mpc->funcs->power_on_mpc_mem_pwr) 830 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 831 if (pipe_ctx->top_pipe == NULL 832 && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 833 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 834 params = &stream->out_transfer_func->pwl; 835 else if (pipe_ctx->stream->out_transfer_func->type == 836 TF_TYPE_DISTRIBUTED_POINTS && 837 cm_helper_translate_curve_to_hw_format( 838 stream->out_transfer_func, 839 &mpc->blender_params, false)) 840 params = &mpc->blender_params; 841 /* 842 * there is no ROM 843 */ 844 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 845 BREAK_TO_DEBUGGER(); 846 } 847 /* 848 * if above if is not executed then 'params' equal to 0 and set in bypass 849 */ 850 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 851 852 return true; 853 } 854 855 bool dcn20_set_blend_lut( 856 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 857 { 858 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 859 bool result = true; 860 struct pwl_params *blend_lut = NULL; 861 862 if (plane_state->blend_tf) { 863 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 864 blend_lut = &plane_state->blend_tf->pwl; 865 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 866 cm_helper_translate_curve_to_hw_format( 867 plane_state->blend_tf, 868 &dpp_base->regamma_params, false); 869 blend_lut = &dpp_base->regamma_params; 870 } 871 } 872 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); 873 874 return result; 875 } 876 877 bool dcn20_set_shaper_3dlut( 878 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 879 { 880 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 881 bool result = true; 882 struct pwl_params *shaper_lut = NULL; 883 884 if (plane_state->in_shaper_func) { 885 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 886 shaper_lut = &plane_state->in_shaper_func->pwl; 887 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 888 cm_helper_translate_curve_to_hw_format( 889 plane_state->in_shaper_func, 890 &dpp_base->shaper_params, true); 891 shaper_lut = &dpp_base->shaper_params; 892 } 893 } 894 895 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); 896 if (plane_state->lut3d_func && 897 plane_state->lut3d_func->state.bits.initialized == 1) 898 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, 899 &plane_state->lut3d_func->lut_3d); 900 else 901 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); 902 903 return result; 904 } 905 906 bool dcn20_set_input_transfer_func(struct dc *dc, 907 struct pipe_ctx *pipe_ctx, 908 const struct dc_plane_state *plane_state) 909 { 910 struct dce_hwseq *hws = dc->hwseq; 911 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 912 const struct dc_transfer_func *tf = NULL; 913 bool result = true; 914 bool use_degamma_ram = false; 915 916 if (dpp_base == NULL || plane_state == NULL) 917 return false; 918 919 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); 920 hws->funcs.set_blend_lut(pipe_ctx, plane_state); 921 922 if (plane_state->in_transfer_func) 923 tf = plane_state->in_transfer_func; 924 925 926 if (tf == NULL) { 927 dpp_base->funcs->dpp_set_degamma(dpp_base, 928 IPP_DEGAMMA_MODE_BYPASS); 929 return true; 930 } 931 932 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS) 933 use_degamma_ram = true; 934 935 if (use_degamma_ram == true) { 936 if (tf->type == TF_TYPE_HWPWL) 937 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 938 &tf->pwl); 939 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 940 cm_helper_translate_curve_to_degamma_hw_format(tf, 941 &dpp_base->degamma_params); 942 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 943 &dpp_base->degamma_params); 944 } 945 return true; 946 } 947 /* handle here the optimized cases when de-gamma ROM could be used. 948 * 949 */ 950 if (tf->type == TF_TYPE_PREDEFINED) { 951 switch (tf->tf) { 952 case TRANSFER_FUNCTION_SRGB: 953 dpp_base->funcs->dpp_set_degamma(dpp_base, 954 IPP_DEGAMMA_MODE_HW_sRGB); 955 break; 956 case TRANSFER_FUNCTION_BT709: 957 dpp_base->funcs->dpp_set_degamma(dpp_base, 958 IPP_DEGAMMA_MODE_HW_xvYCC); 959 break; 960 case TRANSFER_FUNCTION_LINEAR: 961 dpp_base->funcs->dpp_set_degamma(dpp_base, 962 IPP_DEGAMMA_MODE_BYPASS); 963 break; 964 case TRANSFER_FUNCTION_PQ: 965 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL); 966 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params); 967 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params); 968 result = true; 969 break; 970 default: 971 result = false; 972 break; 973 } 974 } else if (tf->type == TF_TYPE_BYPASS) 975 dpp_base->funcs->dpp_set_degamma(dpp_base, 976 IPP_DEGAMMA_MODE_BYPASS); 977 else { 978 /* 979 * if we are here, we did not handle correctly. 980 * fix is required for this use case 981 */ 982 BREAK_TO_DEBUGGER(); 983 dpp_base->funcs->dpp_set_degamma(dpp_base, 984 IPP_DEGAMMA_MODE_BYPASS); 985 } 986 987 return result; 988 } 989 990 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 991 { 992 struct pipe_ctx *odm_pipe; 993 int opp_cnt = 1; 994 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 995 996 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 997 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 998 opp_cnt++; 999 } 1000 1001 if (opp_cnt > 1) 1002 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 1003 pipe_ctx->stream_res.tg, 1004 opp_inst, opp_cnt, 1005 &pipe_ctx->stream->timing); 1006 else 1007 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1008 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1009 } 1010 1011 void dcn20_blank_pixel_data( 1012 struct dc *dc, 1013 struct pipe_ctx *pipe_ctx, 1014 bool blank) 1015 { 1016 struct tg_color black_color = {0}; 1017 struct stream_resource *stream_res = &pipe_ctx->stream_res; 1018 struct dc_stream_state *stream = pipe_ctx->stream; 1019 enum dc_color_space color_space = stream->output_color_space; 1020 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; 1021 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; 1022 struct pipe_ctx *odm_pipe; 1023 int odm_cnt = 1; 1024 1025 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 1026 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; 1027 1028 if (stream->link->test_pattern_enabled) 1029 return; 1030 1031 /* get opp dpg blank color */ 1032 color_space_to_black_color(dc, color_space, &black_color); 1033 1034 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1035 odm_cnt++; 1036 1037 width = width / odm_cnt; 1038 1039 if (blank) { 1040 dc->hwss.set_abm_immediate_disable(pipe_ctx); 1041 1042 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { 1043 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; 1044 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; 1045 } 1046 } else { 1047 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; 1048 } 1049 1050 dc->hwss.set_disp_pattern_generator(dc, 1051 pipe_ctx, 1052 test_pattern, 1053 test_pattern_color_space, 1054 stream->timing.display_color_depth, 1055 &black_color, 1056 width, 1057 height, 1058 0); 1059 1060 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1061 dc->hwss.set_disp_pattern_generator(dc, 1062 odm_pipe, 1063 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ? 1064 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern, 1065 test_pattern_color_space, 1066 stream->timing.display_color_depth, 1067 &black_color, 1068 width, 1069 height, 1070 0); 1071 } 1072 1073 if (!blank) 1074 if (stream_res->abm) { 1075 dc->hwss.set_pipe(pipe_ctx); 1076 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level); 1077 } 1078 } 1079 1080 1081 static void dcn20_power_on_plane( 1082 struct dce_hwseq *hws, 1083 struct pipe_ctx *pipe_ctx) 1084 { 1085 DC_LOGGER_INIT(hws->ctx->logger); 1086 if (REG(DC_IP_REQUEST_CNTL)) { 1087 REG_SET(DC_IP_REQUEST_CNTL, 0, 1088 IP_REQUEST_EN, 1); 1089 1090 if (hws->funcs.dpp_pg_control) 1091 hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); 1092 1093 if (hws->funcs.hubp_pg_control) 1094 hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true); 1095 1096 REG_SET(DC_IP_REQUEST_CNTL, 0, 1097 IP_REQUEST_EN, 0); 1098 DC_LOG_DEBUG( 1099 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst); 1100 } 1101 } 1102 1103 static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx, 1104 struct dc_state *context) 1105 { 1106 //if (dc->debug.sanity_checks) { 1107 // dcn10_verify_allow_pstate_change_high(dc); 1108 //} 1109 dcn20_power_on_plane(dc->hwseq, pipe_ctx); 1110 1111 /* enable DCFCLK current DCHUB */ 1112 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); 1113 1114 /* initialize HUBP on power up */ 1115 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); 1116 1117 /* make sure OPP_PIPE_CLOCK_EN = 1 */ 1118 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 1119 pipe_ctx->stream_res.opp, 1120 true); 1121 1122 /* TODO: enable/disable in dm as per update type. 1123 if (plane_state) { 1124 DC_LOG_DC(dc->ctx->logger, 1125 "Pipe:%d 0x%x: addr hi:0x%x, " 1126 "addr low:0x%x, " 1127 "src: %d, %d, %d," 1128 " %d; dst: %d, %d, %d, %d;\n", 1129 pipe_ctx->pipe_idx, 1130 plane_state, 1131 plane_state->address.grph.addr.high_part, 1132 plane_state->address.grph.addr.low_part, 1133 plane_state->src_rect.x, 1134 plane_state->src_rect.y, 1135 plane_state->src_rect.width, 1136 plane_state->src_rect.height, 1137 plane_state->dst_rect.x, 1138 plane_state->dst_rect.y, 1139 plane_state->dst_rect.width, 1140 plane_state->dst_rect.height); 1141 1142 DC_LOG_DC(dc->ctx->logger, 1143 "Pipe %d: width, height, x, y format:%d\n" 1144 "viewport:%d, %d, %d, %d\n" 1145 "recout: %d, %d, %d, %d\n", 1146 pipe_ctx->pipe_idx, 1147 plane_state->format, 1148 pipe_ctx->plane_res.scl_data.viewport.width, 1149 pipe_ctx->plane_res.scl_data.viewport.height, 1150 pipe_ctx->plane_res.scl_data.viewport.x, 1151 pipe_ctx->plane_res.scl_data.viewport.y, 1152 pipe_ctx->plane_res.scl_data.recout.width, 1153 pipe_ctx->plane_res.scl_data.recout.height, 1154 pipe_ctx->plane_res.scl_data.recout.x, 1155 pipe_ctx->plane_res.scl_data.recout.y); 1156 print_rq_dlg_ttu(dc, pipe_ctx); 1157 } 1158 */ 1159 if (dc->vm_pa_config.valid) { 1160 struct vm_system_aperture_param apt; 1161 1162 apt.sys_default.quad_part = 0; 1163 1164 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr; 1165 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr; 1166 1167 // Program system aperture settings 1168 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); 1169 } 1170 1171 if (!pipe_ctx->top_pipe 1172 && pipe_ctx->plane_state 1173 && pipe_ctx->plane_state->flip_int_enabled 1174 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) 1175 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); 1176 1177 // if (dc->debug.sanity_checks) { 1178 // dcn10_verify_allow_pstate_change_high(dc); 1179 // } 1180 } 1181 1182 void dcn20_pipe_control_lock( 1183 struct dc *dc, 1184 struct pipe_ctx *pipe, 1185 bool lock) 1186 { 1187 struct pipe_ctx *temp_pipe; 1188 bool flip_immediate = false; 1189 1190 /* use TG master update lock to lock everything on the TG 1191 * therefore only top pipe need to lock 1192 */ 1193 if (!pipe || pipe->top_pipe) 1194 return; 1195 1196 if (pipe->plane_state != NULL) 1197 flip_immediate = pipe->plane_state->flip_immediate; 1198 1199 if (pipe->stream_res.gsl_group > 0) { 1200 temp_pipe = pipe->bottom_pipe; 1201 while (!flip_immediate && temp_pipe) { 1202 if (temp_pipe->plane_state != NULL) 1203 flip_immediate = temp_pipe->plane_state->flip_immediate; 1204 temp_pipe = temp_pipe->bottom_pipe; 1205 } 1206 } 1207 1208 if (flip_immediate && lock) { 1209 const int TIMEOUT_FOR_FLIP_PENDING = 100000; 1210 int i; 1211 1212 temp_pipe = pipe; 1213 while (temp_pipe) { 1214 if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) { 1215 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) { 1216 if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp)) 1217 break; 1218 udelay(1); 1219 } 1220 1221 /* no reason it should take this long for immediate flips */ 1222 ASSERT(i != TIMEOUT_FOR_FLIP_PENDING); 1223 } 1224 temp_pipe = temp_pipe->bottom_pipe; 1225 } 1226 } 1227 1228 /* In flip immediate and pipe splitting case, we need to use GSL 1229 * for synchronization. Only do setup on locking and on flip type change. 1230 */ 1231 if (lock && (pipe->bottom_pipe != NULL || !flip_immediate)) 1232 if ((flip_immediate && pipe->stream_res.gsl_group == 0) || 1233 (!flip_immediate && pipe->stream_res.gsl_group > 0)) 1234 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate); 1235 1236 if (pipe->plane_state != NULL) 1237 flip_immediate = pipe->plane_state->flip_immediate; 1238 1239 temp_pipe = pipe->bottom_pipe; 1240 while (flip_immediate && temp_pipe) { 1241 if (temp_pipe->plane_state != NULL) 1242 flip_immediate = temp_pipe->plane_state->flip_immediate; 1243 temp_pipe = temp_pipe->bottom_pipe; 1244 } 1245 1246 if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state && 1247 !flip_immediate) 1248 dcn20_setup_gsl_group_as_lock(dc, pipe, false); 1249 1250 if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) { 1251 union dmub_hw_lock_flags hw_locks = { 0 }; 1252 struct dmub_hw_lock_inst_flags inst_flags = { 0 }; 1253 1254 hw_locks.bits.lock_pipe = 1; 1255 inst_flags.otg_inst = pipe->stream_res.tg->inst; 1256 1257 if (pipe->plane_state != NULL) 1258 hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips; 1259 1260 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, 1261 lock, 1262 &hw_locks, 1263 &inst_flags); 1264 } else if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 1265 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; 1266 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; 1267 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; 1268 hw_lock_cmd.bits.lock_pipe = 1; 1269 hw_lock_cmd.bits.otg_inst = pipe->stream_res.tg->inst; 1270 hw_lock_cmd.bits.lock = lock; 1271 if (!lock) 1272 hw_lock_cmd.bits.should_release = 1; 1273 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); 1274 } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) { 1275 if (lock) 1276 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); 1277 else 1278 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); 1279 } else { 1280 if (lock) 1281 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1282 else 1283 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1284 } 1285 } 1286 1287 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe) 1288 { 1289 new_pipe->update_flags.raw = 0; 1290 1291 /* Exit on unchanged, unused pipe */ 1292 if (!old_pipe->plane_state && !new_pipe->plane_state) 1293 return; 1294 /* Detect pipe enable/disable */ 1295 if (!old_pipe->plane_state && new_pipe->plane_state) { 1296 new_pipe->update_flags.bits.enable = 1; 1297 new_pipe->update_flags.bits.mpcc = 1; 1298 new_pipe->update_flags.bits.dppclk = 1; 1299 new_pipe->update_flags.bits.hubp_interdependent = 1; 1300 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1301 new_pipe->update_flags.bits.gamut_remap = 1; 1302 new_pipe->update_flags.bits.scaler = 1; 1303 new_pipe->update_flags.bits.viewport = 1; 1304 new_pipe->update_flags.bits.det_size = 1; 1305 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1306 new_pipe->update_flags.bits.odm = 1; 1307 new_pipe->update_flags.bits.global_sync = 1; 1308 } 1309 return; 1310 } 1311 if (old_pipe->plane_state && !new_pipe->plane_state) { 1312 new_pipe->update_flags.bits.disable = 1; 1313 return; 1314 } 1315 1316 /* Detect plane change */ 1317 if (old_pipe->plane_state != new_pipe->plane_state) { 1318 new_pipe->update_flags.bits.plane_changed = true; 1319 } 1320 1321 /* Detect top pipe only changes */ 1322 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1323 /* Detect odm changes */ 1324 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe 1325 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx) 1326 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe) 1327 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe) 1328 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1329 new_pipe->update_flags.bits.odm = 1; 1330 1331 /* Detect global sync changes */ 1332 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset 1333 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start 1334 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset 1335 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) 1336 new_pipe->update_flags.bits.global_sync = 1; 1337 } 1338 1339 if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb) 1340 new_pipe->update_flags.bits.det_size = 1; 1341 1342 /* 1343 * Detect opp / tg change, only set on change, not on enable 1344 * Assume mpcc inst = pipe index, if not this code needs to be updated 1345 * since mpcc is what is affected by these. In fact all of our sequence 1346 * makes this assumption at the moment with how hubp reset is matched to 1347 * same index mpcc reset. 1348 */ 1349 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1350 new_pipe->update_flags.bits.opp_changed = 1; 1351 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg) 1352 new_pipe->update_flags.bits.tg_changed = 1; 1353 1354 /* 1355 * Detect mpcc blending changes, only dpp inst and opp matter here, 1356 * mpccs getting removed/inserted update connected ones during their own 1357 * programming 1358 */ 1359 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp 1360 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1361 new_pipe->update_flags.bits.mpcc = 1; 1362 1363 /* Detect dppclk change */ 1364 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) 1365 new_pipe->update_flags.bits.dppclk = 1; 1366 1367 /* Check for scl update */ 1368 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data))) 1369 new_pipe->update_flags.bits.scaler = 1; 1370 /* Check for vp update */ 1371 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect)) 1372 || memcmp(&old_pipe->plane_res.scl_data.viewport_c, 1373 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect))) 1374 new_pipe->update_flags.bits.viewport = 1; 1375 1376 /* Detect dlg/ttu/rq updates */ 1377 { 1378 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs; 1379 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs; 1380 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs; 1381 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs; 1382 1383 /* Detect pipe interdependent updates */ 1384 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch || 1385 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch || 1386 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c || 1387 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank || 1388 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank || 1389 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip || 1390 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip || 1391 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l || 1392 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c || 1393 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l || 1394 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l || 1395 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c || 1396 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l || 1397 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c || 1398 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 || 1399 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 || 1400 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank || 1401 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) { 1402 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch; 1403 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch; 1404 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c; 1405 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank; 1406 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank; 1407 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip; 1408 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip; 1409 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l; 1410 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c; 1411 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l; 1412 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l; 1413 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c; 1414 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l; 1415 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c; 1416 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0; 1417 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1; 1418 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank; 1419 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip; 1420 new_pipe->update_flags.bits.hubp_interdependent = 1; 1421 } 1422 /* Detect any other updates to ttu/rq/dlg */ 1423 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) || 1424 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) || 1425 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs))) 1426 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1427 } 1428 } 1429 1430 static void dcn20_update_dchubp_dpp( 1431 struct dc *dc, 1432 struct pipe_ctx *pipe_ctx, 1433 struct dc_state *context) 1434 { 1435 struct dce_hwseq *hws = dc->hwseq; 1436 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1437 struct dpp *dpp = pipe_ctx->plane_res.dpp; 1438 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1439 struct dccg *dccg = dc->res_pool->dccg; 1440 bool viewport_changed = false; 1441 1442 if (pipe_ctx->update_flags.bits.dppclk) 1443 dpp->funcs->dpp_dppclk_control(dpp, false, true); 1444 1445 if (pipe_ctx->update_flags.bits.enable) 1446 dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz); 1447 1448 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG 1449 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. 1450 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG 1451 */ 1452 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) { 1453 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst); 1454 1455 hubp->funcs->hubp_setup( 1456 hubp, 1457 &pipe_ctx->dlg_regs, 1458 &pipe_ctx->ttu_regs, 1459 &pipe_ctx->rq_regs, 1460 &pipe_ctx->pipe_dlg_param); 1461 1462 if (hubp->funcs->set_unbounded_requesting) 1463 hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req); 1464 } 1465 if (pipe_ctx->update_flags.bits.hubp_interdependent) 1466 hubp->funcs->hubp_setup_interdependent( 1467 hubp, 1468 &pipe_ctx->dlg_regs, 1469 &pipe_ctx->ttu_regs); 1470 1471 if (pipe_ctx->update_flags.bits.enable || 1472 pipe_ctx->update_flags.bits.plane_changed || 1473 plane_state->update_flags.bits.bpp_change || 1474 plane_state->update_flags.bits.input_csc_change || 1475 plane_state->update_flags.bits.color_space_change || 1476 plane_state->update_flags.bits.coeff_reduction_change) { 1477 struct dc_bias_and_scale bns_params = {0}; 1478 1479 // program the input csc 1480 dpp->funcs->dpp_setup(dpp, 1481 plane_state->format, 1482 EXPANSION_MODE_ZERO, 1483 plane_state->input_csc_color_matrix, 1484 plane_state->color_space, 1485 NULL); 1486 1487 if (dpp->funcs->dpp_program_bias_and_scale) { 1488 //TODO :for CNVC set scale and bias registers if necessary 1489 build_prescale_params(&bns_params, plane_state); 1490 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); 1491 } 1492 } 1493 1494 if (pipe_ctx->update_flags.bits.mpcc 1495 || pipe_ctx->update_flags.bits.plane_changed 1496 || plane_state->update_flags.bits.global_alpha_change 1497 || plane_state->update_flags.bits.per_pixel_alpha_change) { 1498 // MPCC inst is equal to pipe index in practice 1499 int mpcc_inst = hubp->inst; 1500 int opp_inst; 1501 int opp_count = dc->res_pool->pipe_count; 1502 1503 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) { 1504 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) { 1505 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); 1506 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; 1507 break; 1508 } 1509 } 1510 hws->funcs.update_mpcc(dc, pipe_ctx); 1511 } 1512 1513 if (pipe_ctx->update_flags.bits.scaler || 1514 plane_state->update_flags.bits.scaling_change || 1515 plane_state->update_flags.bits.position_change || 1516 plane_state->update_flags.bits.per_pixel_alpha_change || 1517 pipe_ctx->stream->update_flags.bits.scaling) { 1518 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; 1519 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP); 1520 /* scaler configuration */ 1521 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( 1522 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); 1523 } 1524 1525 if (pipe_ctx->update_flags.bits.viewport || 1526 (context == dc->current_state && plane_state->update_flags.bits.position_change) || 1527 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) || 1528 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) { 1529 1530 hubp->funcs->mem_program_viewport( 1531 hubp, 1532 &pipe_ctx->plane_res.scl_data.viewport, 1533 &pipe_ctx->plane_res.scl_data.viewport_c); 1534 viewport_changed = true; 1535 } 1536 1537 /* Any updates are handled in dc interface, just need to apply existing for plane enable */ 1538 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || 1539 pipe_ctx->update_flags.bits.scaler || viewport_changed == true) && 1540 pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { 1541 dc->hwss.set_cursor_position(pipe_ctx); 1542 dc->hwss.set_cursor_attribute(pipe_ctx); 1543 1544 if (dc->hwss.set_cursor_sdr_white_level) 1545 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 1546 } 1547 1548 /* Any updates are handled in dc interface, just need 1549 * to apply existing for plane enable / opp change */ 1550 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed 1551 || pipe_ctx->stream->update_flags.bits.gamut_remap 1552 || pipe_ctx->stream->update_flags.bits.out_csc) { 1553 /* dpp/cm gamut remap*/ 1554 dc->hwss.program_gamut_remap(pipe_ctx); 1555 1556 /*call the dcn2 method which uses mpc csc*/ 1557 dc->hwss.program_output_csc(dc, 1558 pipe_ctx, 1559 pipe_ctx->stream->output_color_space, 1560 pipe_ctx->stream->csc_color_matrix.matrix, 1561 hubp->opp_id); 1562 } 1563 1564 if (pipe_ctx->update_flags.bits.enable || 1565 pipe_ctx->update_flags.bits.plane_changed || 1566 pipe_ctx->update_flags.bits.opp_changed || 1567 plane_state->update_flags.bits.pixel_format_change || 1568 plane_state->update_flags.bits.horizontal_mirror_change || 1569 plane_state->update_flags.bits.rotation_change || 1570 plane_state->update_flags.bits.swizzle_change || 1571 plane_state->update_flags.bits.dcc_change || 1572 plane_state->update_flags.bits.bpp_change || 1573 plane_state->update_flags.bits.scaling_change || 1574 plane_state->update_flags.bits.plane_size_change) { 1575 struct plane_size size = plane_state->plane_size; 1576 1577 size.surface_size = pipe_ctx->plane_res.scl_data.viewport; 1578 hubp->funcs->hubp_program_surface_config( 1579 hubp, 1580 plane_state->format, 1581 &plane_state->tiling_info, 1582 &size, 1583 plane_state->rotation, 1584 &plane_state->dcc, 1585 plane_state->horizontal_mirror, 1586 0); 1587 hubp->power_gated = false; 1588 } 1589 1590 if (pipe_ctx->update_flags.bits.enable || 1591 pipe_ctx->update_flags.bits.plane_changed || 1592 plane_state->update_flags.bits.addr_update) 1593 hws->funcs.update_plane_addr(dc, pipe_ctx); 1594 1595 if (pipe_ctx->update_flags.bits.enable) 1596 hubp->funcs->set_blank(hubp, false); 1597 /* If the stream paired with this plane is phantom, the plane is also phantom */ 1598 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM 1599 && hubp->funcs->phantom_hubp_post_enable) 1600 hubp->funcs->phantom_hubp_post_enable(hubp); 1601 } 1602 1603 1604 static void dcn20_program_pipe( 1605 struct dc *dc, 1606 struct pipe_ctx *pipe_ctx, 1607 struct dc_state *context) 1608 { 1609 struct dce_hwseq *hws = dc->hwseq; 1610 /* Only need to unblank on top pipe */ 1611 1612 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level) 1613 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) 1614 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible); 1615 1616 /* Only update TG on top pipe */ 1617 if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe 1618 && !pipe_ctx->prev_odm_pipe) { 1619 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1620 pipe_ctx->stream_res.tg, 1621 pipe_ctx->pipe_dlg_param.vready_offset, 1622 pipe_ctx->pipe_dlg_param.vstartup_start, 1623 pipe_ctx->pipe_dlg_param.vupdate_offset, 1624 pipe_ctx->pipe_dlg_param.vupdate_width); 1625 1626 if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1627 pipe_ctx->stream_res.tg->funcs->wait_for_state( 1628 pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); 1629 pipe_ctx->stream_res.tg->funcs->wait_for_state( 1630 pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); 1631 } 1632 1633 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1634 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true); 1635 1636 if (hws->funcs.setup_vupdate_interrupt) 1637 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1638 } 1639 1640 if (pipe_ctx->update_flags.bits.odm) 1641 hws->funcs.update_odm(dc, context, pipe_ctx); 1642 1643 if (pipe_ctx->update_flags.bits.enable) { 1644 dcn20_enable_plane(dc, pipe_ctx, context); 1645 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes) 1646 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub); 1647 } 1648 1649 if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size) 1650 dc->res_pool->hubbub->funcs->program_det_size( 1651 dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb); 1652 1653 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) 1654 dcn20_update_dchubp_dpp(dc, pipe_ctx, context); 1655 1656 if (pipe_ctx->update_flags.bits.enable 1657 || pipe_ctx->plane_state->update_flags.bits.hdr_mult) 1658 hws->funcs.set_hdr_multiplier(pipe_ctx); 1659 1660 if (pipe_ctx->update_flags.bits.enable || 1661 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 1662 pipe_ctx->plane_state->update_flags.bits.gamma_change) 1663 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 1664 1665 /* dcn10_translate_regamma_to_hw_format takes 750us to finish 1666 * only do gamma programming for powering on, internal memcmp to avoid 1667 * updating on slave planes 1668 */ 1669 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf) 1670 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 1671 1672 /* If the pipe has been enabled or has a different opp, we 1673 * should reprogram the fmt. This deals with cases where 1674 * interation between mpc and odm combine on different streams 1675 * causes a different pipe to be chosen to odm combine with. 1676 */ 1677 if (pipe_ctx->update_flags.bits.enable 1678 || pipe_ctx->update_flags.bits.opp_changed) { 1679 1680 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1681 pipe_ctx->stream_res.opp, 1682 COLOR_SPACE_YCBCR601, 1683 pipe_ctx->stream->timing.display_color_depth, 1684 pipe_ctx->stream->signal); 1685 1686 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1687 pipe_ctx->stream_res.opp, 1688 &pipe_ctx->stream->bit_depth_params, 1689 &pipe_ctx->stream->clamping); 1690 } 1691 } 1692 1693 void dcn20_program_front_end_for_ctx( 1694 struct dc *dc, 1695 struct dc_state *context) 1696 { 1697 int i; 1698 struct dce_hwseq *hws = dc->hwseq; 1699 DC_LOGGER_INIT(dc->ctx->logger); 1700 1701 /* Carry over GSL groups in case the context is changing. */ 1702 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1703 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1704 struct pipe_ctx *old_pipe_ctx = 1705 &dc->current_state->res_ctx.pipe_ctx[i]; 1706 1707 if (pipe_ctx->stream == old_pipe_ctx->stream) 1708 pipe_ctx->stream_res.gsl_group = 1709 old_pipe_ctx->stream_res.gsl_group; 1710 } 1711 1712 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) { 1713 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1714 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1715 1716 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) { 1717 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips); 1718 /*turn off triple buffer for full update*/ 1719 dc->hwss.program_triplebuffer( 1720 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); 1721 } 1722 } 1723 } 1724 1725 /* Set pipe update flags and lock pipes */ 1726 for (i = 0; i < dc->res_pool->pipe_count; i++) 1727 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i], 1728 &context->res_ctx.pipe_ctx[i]); 1729 1730 /* OTG blank before disabling all front ends */ 1731 for (i = 0; i < dc->res_pool->pipe_count; i++) 1732 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1733 && !context->res_ctx.pipe_ctx[i].top_pipe 1734 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe 1735 && context->res_ctx.pipe_ctx[i].stream) 1736 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); 1737 1738 1739 /* Disconnect mpcc */ 1740 for (i = 0; i < dc->res_pool->pipe_count; i++) 1741 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1742 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) { 1743 struct hubbub *hubbub = dc->res_pool->hubbub; 1744 1745 if (hubbub->funcs->program_det_size && context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1746 hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0); 1747 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1748 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); 1749 } 1750 1751 /* 1752 * Program all updated pipes, order matters for mpcc setup. Start with 1753 * top pipe and program all pipes that follow in order 1754 */ 1755 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1756 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1757 1758 if (pipe->plane_state && !pipe->top_pipe) { 1759 while (pipe) { 1760 if (hws->funcs.program_pipe) 1761 hws->funcs.program_pipe(dc, pipe, context); 1762 else 1763 dcn20_program_pipe(dc, pipe, context); 1764 1765 pipe = pipe->bottom_pipe; 1766 } 1767 } 1768 /* Program secondary blending tree and writeback pipes */ 1769 pipe = &context->res_ctx.pipe_ctx[i]; 1770 if (!pipe->top_pipe && !pipe->prev_odm_pipe 1771 && pipe->stream && pipe->stream->num_wb_info > 0 1772 && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw) 1773 || pipe->stream->update_flags.raw) 1774 && hws->funcs.program_all_writeback_pipes_in_tree) 1775 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context); 1776 1777 /* Avoid underflow by check of pipe line read when adding 2nd plane. */ 1778 if (hws->wa.wait_hubpret_read_start_during_mpo_transition && 1779 !pipe->top_pipe && 1780 pipe->stream && 1781 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start && 1782 dc->current_state->stream_status[0].plane_count == 1 && 1783 context->stream_status[0].plane_count > 1) { 1784 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp); 1785 } 1786 } 1787 if (hws->funcs.program_mall_pipe_config) 1788 hws->funcs.program_mall_pipe_config(dc, context); 1789 } 1790 1791 void dcn20_post_unlock_program_front_end( 1792 struct dc *dc, 1793 struct dc_state *context) 1794 { 1795 int i; 1796 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100; 1797 struct dce_hwseq *hwseq = dc->hwseq; 1798 1799 DC_LOGGER_INIT(dc->ctx->logger); 1800 1801 for (i = 0; i < dc->res_pool->pipe_count; i++) 1802 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1803 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1804 1805 /* 1806 * If we are enabling a pipe, we need to wait for pending clear as this is a critical 1807 * part of the enable operation otherwise, DM may request an immediate flip which 1808 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which 1809 * is unsupported on DCN. 1810 */ 1811 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1812 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1813 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable) { 1814 struct hubp *hubp = pipe->plane_res.hubp; 1815 int j = 0; 1816 1817 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000 1818 && hubp->funcs->hubp_is_flip_pending(hubp); j++) 1819 mdelay(1); 1820 } 1821 } 1822 1823 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1824 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1825 struct pipe_ctx *mpcc_pipe; 1826 1827 if (pipe->vtp_locked) { 1828 dc->hwseq->funcs.wait_for_blank_complete(pipe->stream_res.opp); 1829 pipe->plane_res.hubp->funcs->set_blank(pipe->plane_res.hubp, true); 1830 pipe->vtp_locked = false; 1831 1832 for (mpcc_pipe = pipe->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe) 1833 mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true); 1834 1835 for (i = 0; i < dc->res_pool->pipe_count; i++) 1836 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1837 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1838 } 1839 } 1840 /* WA to apply WM setting*/ 1841 if (hwseq->wa.DEGVIDCN21) 1842 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub); 1843 1844 1845 /* WA for stutter underflow during MPO transitions when adding 2nd plane */ 1846 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) { 1847 1848 if (dc->current_state->stream_status[0].plane_count == 1 && 1849 context->stream_status[0].plane_count > 1) { 1850 1851 struct timing_generator *tg = dc->res_pool->timing_generators[0]; 1852 1853 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false); 1854 1855 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true; 1856 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg); 1857 } 1858 } 1859 } 1860 1861 void dcn20_prepare_bandwidth( 1862 struct dc *dc, 1863 struct dc_state *context) 1864 { 1865 struct hubbub *hubbub = dc->res_pool->hubbub; 1866 unsigned int compbuf_size_kb = 0; 1867 1868 dc->clk_mgr->funcs->update_clocks( 1869 dc->clk_mgr, 1870 context, 1871 false); 1872 1873 /* program dchubbub watermarks */ 1874 dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub, 1875 &context->bw_ctx.bw.dcn.watermarks, 1876 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1877 false); 1878 1879 /* decrease compbuf size */ 1880 if (hubbub->funcs->program_compbuf_size) { 1881 if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes) 1882 compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes; 1883 else 1884 compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb; 1885 1886 hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false); 1887 } 1888 } 1889 1890 void dcn20_optimize_bandwidth( 1891 struct dc *dc, 1892 struct dc_state *context) 1893 { 1894 struct hubbub *hubbub = dc->res_pool->hubbub; 1895 int i; 1896 1897 /* program dchubbub watermarks */ 1898 hubbub->funcs->program_watermarks(hubbub, 1899 &context->bw_ctx.bw.dcn.watermarks, 1900 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1901 true); 1902 1903 if (dc->clk_mgr->dc_mode_softmax_enabled) 1904 if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && 1905 context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) 1906 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk); 1907 1908 dc->clk_mgr->funcs->update_clocks( 1909 dc->clk_mgr, 1910 context, 1911 true); 1912 if (dc_extended_blank_supported(dc) && context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) { 1913 for (i = 0; i < dc->res_pool->pipe_count; ++i) { 1914 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1915 1916 if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank 1917 && pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max 1918 && pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total) 1919 pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp, 1920 pipe_ctx->dlg_regs.optimized_min_dst_y_next_start); 1921 } 1922 } 1923 /* increase compbuf size */ 1924 if (hubbub->funcs->program_compbuf_size) 1925 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true); 1926 } 1927 1928 bool dcn20_update_bandwidth( 1929 struct dc *dc, 1930 struct dc_state *context) 1931 { 1932 int i; 1933 struct dce_hwseq *hws = dc->hwseq; 1934 1935 /* recalculate DML parameters */ 1936 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) 1937 return false; 1938 1939 /* apply updated bandwidth parameters */ 1940 dc->hwss.prepare_bandwidth(dc, context); 1941 1942 /* update hubp configs for all pipes */ 1943 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1944 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1945 1946 if (pipe_ctx->plane_state == NULL) 1947 continue; 1948 1949 if (pipe_ctx->top_pipe == NULL) { 1950 bool blank = !is_pipe_tree_visible(pipe_ctx); 1951 1952 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1953 pipe_ctx->stream_res.tg, 1954 pipe_ctx->pipe_dlg_param.vready_offset, 1955 pipe_ctx->pipe_dlg_param.vstartup_start, 1956 pipe_ctx->pipe_dlg_param.vupdate_offset, 1957 pipe_ctx->pipe_dlg_param.vupdate_width); 1958 1959 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1960 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false); 1961 1962 if (pipe_ctx->prev_odm_pipe == NULL) 1963 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank); 1964 1965 if (hws->funcs.setup_vupdate_interrupt) 1966 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1967 } 1968 1969 pipe_ctx->plane_res.hubp->funcs->hubp_setup( 1970 pipe_ctx->plane_res.hubp, 1971 &pipe_ctx->dlg_regs, 1972 &pipe_ctx->ttu_regs, 1973 &pipe_ctx->rq_regs, 1974 &pipe_ctx->pipe_dlg_param); 1975 } 1976 1977 return true; 1978 } 1979 1980 void dcn20_enable_writeback( 1981 struct dc *dc, 1982 struct dc_writeback_info *wb_info, 1983 struct dc_state *context) 1984 { 1985 struct dwbc *dwb; 1986 struct mcif_wb *mcif_wb; 1987 struct timing_generator *optc; 1988 1989 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 1990 ASSERT(wb_info->wb_enabled); 1991 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 1992 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 1993 1994 /* set the OPTC source mux */ 1995 optc = dc->res_pool->timing_generators[dwb->otg_inst]; 1996 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); 1997 /* set MCIF_WB buffer and arbitration configuration */ 1998 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 1999 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 2000 /* Enable MCIF_WB */ 2001 mcif_wb->funcs->enable_mcif(mcif_wb); 2002 /* Enable DWB */ 2003 dwb->funcs->enable(dwb, &wb_info->dwb_params); 2004 /* TODO: add sequence to enable/disable warmup */ 2005 } 2006 2007 void dcn20_disable_writeback( 2008 struct dc *dc, 2009 unsigned int dwb_pipe_inst) 2010 { 2011 struct dwbc *dwb; 2012 struct mcif_wb *mcif_wb; 2013 2014 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); 2015 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; 2016 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; 2017 2018 dwb->funcs->disable(dwb); 2019 mcif_wb->funcs->disable_mcif(mcif_wb); 2020 } 2021 2022 bool dcn20_wait_for_blank_complete( 2023 struct output_pixel_processor *opp) 2024 { 2025 int counter; 2026 2027 for (counter = 0; counter < 1000; counter++) { 2028 if (opp->funcs->dpg_is_blanked(opp)) 2029 break; 2030 2031 udelay(100); 2032 } 2033 2034 if (counter == 1000) { 2035 dm_error("DC: failed to blank crtc!\n"); 2036 return false; 2037 } 2038 2039 return true; 2040 } 2041 2042 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) 2043 { 2044 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2045 2046 if (!hubp) 2047 return false; 2048 return hubp->funcs->dmdata_status_done(hubp); 2049 } 2050 2051 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 2052 { 2053 struct dce_hwseq *hws = dc->hwseq; 2054 2055 if (pipe_ctx->stream_res.dsc) { 2056 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2057 2058 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); 2059 while (odm_pipe) { 2060 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true); 2061 odm_pipe = odm_pipe->next_odm_pipe; 2062 } 2063 } 2064 } 2065 2066 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 2067 { 2068 struct dce_hwseq *hws = dc->hwseq; 2069 2070 if (pipe_ctx->stream_res.dsc) { 2071 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2072 2073 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false); 2074 while (odm_pipe) { 2075 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false); 2076 odm_pipe = odm_pipe->next_odm_pipe; 2077 } 2078 } 2079 } 2080 2081 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) 2082 { 2083 struct dc_dmdata_attributes attr = { 0 }; 2084 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2085 2086 attr.dmdata_mode = DMDATA_HW_MODE; 2087 attr.dmdata_size = 2088 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; 2089 attr.address.quad_part = 2090 pipe_ctx->stream->dmdata_address.quad_part; 2091 attr.dmdata_dl_delta = 0; 2092 attr.dmdata_qos_mode = 0; 2093 attr.dmdata_qos_level = 0; 2094 attr.dmdata_repeat = 1; /* always repeat */ 2095 attr.dmdata_updated = 1; 2096 attr.dmdata_sw_data = NULL; 2097 2098 hubp->funcs->dmdata_set_attributes(hubp, &attr); 2099 } 2100 2101 void dcn20_init_vm_ctx( 2102 struct dce_hwseq *hws, 2103 struct dc *dc, 2104 struct dc_virtual_addr_space_config *va_config, 2105 int vmid) 2106 { 2107 struct dcn_hubbub_virt_addr_config config; 2108 2109 if (vmid == 0) { 2110 ASSERT(0); /* VMID cannot be 0 for vm context */ 2111 return; 2112 } 2113 2114 config.page_table_start_addr = va_config->page_table_start_addr; 2115 config.page_table_end_addr = va_config->page_table_end_addr; 2116 config.page_table_block_size = va_config->page_table_block_size_in_bytes; 2117 config.page_table_depth = va_config->page_table_depth; 2118 config.page_table_base_addr = va_config->page_table_base_addr; 2119 2120 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); 2121 } 2122 2123 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 2124 { 2125 struct dcn_hubbub_phys_addr_config config; 2126 2127 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 2128 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 2129 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 2130 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 2131 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 2132 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 2133 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 2134 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 2135 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 2136 config.page_table_default_page_addr = pa_config->page_table_default_page_addr; 2137 2138 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 2139 } 2140 2141 static bool patch_address_for_sbs_tb_stereo( 2142 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) 2143 { 2144 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2145 bool sec_split = pipe_ctx->top_pipe && 2146 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; 2147 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && 2148 (pipe_ctx->stream->timing.timing_3d_format == 2149 TIMING_3D_FORMAT_SIDE_BY_SIDE || 2150 pipe_ctx->stream->timing.timing_3d_format == 2151 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { 2152 *addr = plane_state->address.grph_stereo.left_addr; 2153 plane_state->address.grph_stereo.left_addr = 2154 plane_state->address.grph_stereo.right_addr; 2155 return true; 2156 } 2157 2158 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && 2159 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { 2160 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; 2161 plane_state->address.grph_stereo.right_addr = 2162 plane_state->address.grph_stereo.left_addr; 2163 plane_state->address.grph_stereo.right_meta_addr = 2164 plane_state->address.grph_stereo.left_meta_addr; 2165 } 2166 return false; 2167 } 2168 2169 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) 2170 { 2171 bool addr_patched = false; 2172 PHYSICAL_ADDRESS_LOC addr; 2173 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2174 2175 if (plane_state == NULL) 2176 return; 2177 2178 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); 2179 2180 // Call Helper to track VMID use 2181 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); 2182 2183 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( 2184 pipe_ctx->plane_res.hubp, 2185 &plane_state->address, 2186 plane_state->flip_immediate); 2187 2188 plane_state->status.requested_address = plane_state->address; 2189 2190 if (plane_state->flip_immediate) 2191 plane_state->status.current_address = plane_state->address; 2192 2193 if (addr_patched) 2194 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; 2195 } 2196 2197 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, 2198 struct dc_link_settings *link_settings) 2199 { 2200 struct encoder_unblank_param params = {0}; 2201 struct dc_stream_state *stream = pipe_ctx->stream; 2202 struct dc_link *link = stream->link; 2203 struct dce_hwseq *hws = link->dc->hwseq; 2204 struct pipe_ctx *odm_pipe; 2205 2206 params.opp_cnt = 1; 2207 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 2208 params.opp_cnt++; 2209 } 2210 /* only 3 items below are used by unblank */ 2211 params.timing = pipe_ctx->stream->timing; 2212 2213 params.link_settings.link_rate = link_settings->link_rate; 2214 2215 if (is_dp_128b_132b_signal(pipe_ctx)) { 2216 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 2217 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 2218 pipe_ctx->stream_res.hpo_dp_stream_enc, 2219 pipe_ctx->stream_res.tg->inst); 2220 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 2221 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1) 2222 params.timing.pix_clk_100hz /= 2; 2223 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 2224 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1); 2225 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 2226 } 2227 2228 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 2229 hws->funcs.edp_backlight_control(link, true); 2230 } 2231 } 2232 2233 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx) 2234 { 2235 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2236 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx); 2237 2238 if (start_line < 0) 2239 start_line = 0; 2240 2241 if (tg->funcs->setup_vertical_interrupt2) 2242 tg->funcs->setup_vertical_interrupt2(tg, start_line); 2243 } 2244 2245 static void dcn20_reset_back_end_for_pipe( 2246 struct dc *dc, 2247 struct pipe_ctx *pipe_ctx, 2248 struct dc_state *context) 2249 { 2250 int i; 2251 struct dc_link *link; 2252 DC_LOGGER_INIT(dc->ctx->logger); 2253 if (pipe_ctx->stream_res.stream_enc == NULL) { 2254 pipe_ctx->stream = NULL; 2255 return; 2256 } 2257 2258 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 2259 link = pipe_ctx->stream->link; 2260 /* DPMS may already disable or */ 2261 /* dpms_off status is incorrect due to fastboot 2262 * feature. When system resume from S4 with second 2263 * screen only, the dpms_off would be true but 2264 * VBIOS lit up eDP, so check link status too. 2265 */ 2266 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 2267 core_link_disable_stream(pipe_ctx); 2268 else if (pipe_ctx->stream_res.audio) 2269 dc->hwss.disable_audio_stream(pipe_ctx); 2270 2271 /* free acquired resources */ 2272 if (pipe_ctx->stream_res.audio) { 2273 /*disable az_endpoint*/ 2274 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 2275 2276 /*free audio*/ 2277 if (dc->caps.dynamic_audio == true) { 2278 /*we have to dynamic arbitrate the audio endpoints*/ 2279 /*we free the resource, need reset is_audio_acquired*/ 2280 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 2281 pipe_ctx->stream_res.audio, false); 2282 pipe_ctx->stream_res.audio = NULL; 2283 } 2284 } 2285 } 2286 else if (pipe_ctx->stream_res.dsc) { 2287 dp_set_dsc_enable(pipe_ctx, false); 2288 } 2289 2290 /* by upper caller loop, parent pipe: pipe0, will be reset last. 2291 * back end share by all pipes and will be disable only when disable 2292 * parent pipe. 2293 */ 2294 if (pipe_ctx->top_pipe == NULL) { 2295 2296 dc->hwss.set_abm_immediate_disable(pipe_ctx); 2297 2298 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 2299 2300 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 2301 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 2302 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 2303 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 2304 2305 if (pipe_ctx->stream_res.tg->funcs->set_drr) 2306 pipe_ctx->stream_res.tg->funcs->set_drr( 2307 pipe_ctx->stream_res.tg, NULL); 2308 } 2309 2310 for (i = 0; i < dc->res_pool->pipe_count; i++) 2311 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) 2312 break; 2313 2314 if (i == dc->res_pool->pipe_count) 2315 return; 2316 2317 pipe_ctx->stream = NULL; 2318 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 2319 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 2320 } 2321 2322 void dcn20_reset_hw_ctx_wrap( 2323 struct dc *dc, 2324 struct dc_state *context) 2325 { 2326 int i; 2327 struct dce_hwseq *hws = dc->hwseq; 2328 2329 /* Reset Back End*/ 2330 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 2331 struct pipe_ctx *pipe_ctx_old = 2332 &dc->current_state->res_ctx.pipe_ctx[i]; 2333 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2334 2335 if (!pipe_ctx_old->stream) 2336 continue; 2337 2338 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 2339 continue; 2340 2341 if (!pipe_ctx->stream || 2342 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 2343 struct clock_source *old_clk = pipe_ctx_old->clock_source; 2344 2345 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 2346 if (hws->funcs.enable_stream_gating) 2347 hws->funcs.enable_stream_gating(dc, pipe_ctx_old); 2348 if (old_clk) 2349 old_clk->funcs->cs_power_down(old_clk); 2350 } 2351 } 2352 } 2353 2354 void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id) 2355 { 2356 struct mpc *mpc = dc->res_pool->mpc; 2357 2358 // input to MPCC is always RGB, by default leave black_color at 0 2359 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) 2360 get_hdr_visual_confirm_color(pipe_ctx, color); 2361 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) 2362 get_surface_visual_confirm_color(pipe_ctx, color); 2363 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) 2364 get_mpctree_visual_confirm_color(pipe_ctx, color); 2365 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE) 2366 get_surface_tile_visual_confirm_color(pipe_ctx, color); 2367 2368 if (mpc->funcs->set_bg_color) 2369 mpc->funcs->set_bg_color(mpc, color, mpcc_id); 2370 } 2371 2372 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 2373 { 2374 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2375 struct mpcc_blnd_cfg blnd_cfg = {0}; 2376 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; 2377 int mpcc_id; 2378 struct mpcc *new_mpcc; 2379 struct mpc *mpc = dc->res_pool->mpc; 2380 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); 2381 2382 blnd_cfg.overlap_only = false; 2383 blnd_cfg.global_gain = 0xff; 2384 2385 if (per_pixel_alpha) { 2386 blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha; 2387 if (pipe_ctx->plane_state->global_alpha) { 2388 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; 2389 blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value; 2390 } else { 2391 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2392 } 2393 } else { 2394 blnd_cfg.pre_multiplied_alpha = false; 2395 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 2396 } 2397 2398 if (pipe_ctx->plane_state->global_alpha) 2399 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; 2400 else 2401 blnd_cfg.global_alpha = 0xff; 2402 2403 blnd_cfg.background_color_bpc = 4; 2404 blnd_cfg.bottom_gain_mode = 0; 2405 blnd_cfg.top_gain = 0x1f000; 2406 blnd_cfg.bottom_inside_gain = 0x1f000; 2407 blnd_cfg.bottom_outside_gain = 0x1f000; 2408 2409 if (pipe_ctx->plane_state->format 2410 == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA) 2411 blnd_cfg.pre_multiplied_alpha = false; 2412 2413 /* 2414 * TODO: remove hack 2415 * Note: currently there is a bug in init_hw such that 2416 * on resume from hibernate, BIOS sets up MPCC0, and 2417 * we do mpcc_remove but the mpcc cannot go to idle 2418 * after remove. This cause us to pick mpcc1 here, 2419 * which causes a pstate hang for yet unknown reason. 2420 */ 2421 mpcc_id = hubp->inst; 2422 2423 /* If there is no full update, don't need to touch MPC tree*/ 2424 if (!pipe_ctx->plane_state->update_flags.bits.full_update && 2425 !pipe_ctx->update_flags.bits.mpcc) { 2426 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); 2427 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); 2428 return; 2429 } 2430 2431 /* check if this MPCC is already being used */ 2432 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 2433 /* remove MPCC if being used */ 2434 if (new_mpcc != NULL) 2435 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); 2436 else 2437 if (dc->debug.sanity_checks) 2438 mpc->funcs->assert_mpcc_idle_before_connect( 2439 dc->res_pool->mpc, mpcc_id); 2440 2441 /* Call MPC to insert new plane */ 2442 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, 2443 mpc_tree_params, 2444 &blnd_cfg, 2445 NULL, 2446 NULL, 2447 hubp->inst, 2448 mpcc_id); 2449 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); 2450 2451 ASSERT(new_mpcc != NULL); 2452 hubp->opp_id = pipe_ctx->stream_res.opp->inst; 2453 hubp->mpcc_id = mpcc_id; 2454 } 2455 2456 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 2457 { 2458 enum dc_lane_count lane_count = 2459 pipe_ctx->stream->link->cur_link_settings.lane_count; 2460 2461 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 2462 struct dc_link *link = pipe_ctx->stream->link; 2463 2464 uint32_t active_total_with_borders; 2465 uint32_t early_control = 0; 2466 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2467 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2468 struct dc *dc = pipe_ctx->stream->ctx->dc; 2469 2470 if (is_dp_128b_132b_signal(pipe_ctx)) { 2471 if (dc->hwseq->funcs.setup_hpo_hw_control) 2472 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, true); 2473 } 2474 2475 link_hwss->setup_stream_encoder(pipe_ctx); 2476 2477 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) { 2478 if (dc->hwss.program_dmdata_engine) 2479 dc->hwss.program_dmdata_engine(pipe_ctx); 2480 } 2481 2482 dc->hwss.update_info_frame(pipe_ctx); 2483 2484 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2485 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2486 2487 /* enable early control to avoid corruption on DP monitor*/ 2488 active_total_with_borders = 2489 timing->h_addressable 2490 + timing->h_border_left 2491 + timing->h_border_right; 2492 2493 if (lane_count != 0) 2494 early_control = active_total_with_borders % lane_count; 2495 2496 if (early_control == 0) 2497 early_control = lane_count; 2498 2499 tg->funcs->set_early_control(tg, early_control); 2500 2501 if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode) 2502 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc, 2503 timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 ? 2 : 1); 2504 2505 /* enable audio only within mode set */ 2506 if (pipe_ctx->stream_res.audio != NULL) { 2507 if (is_dp_128b_132b_signal(pipe_ctx)) 2508 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.hpo_dp_stream_enc); 2509 else if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2510 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 2511 } 2512 } 2513 2514 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx) 2515 { 2516 struct dc_stream_state *stream = pipe_ctx->stream; 2517 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2518 bool enable = false; 2519 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2520 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) 2521 ? dmdata_dp 2522 : dmdata_hdmi; 2523 2524 /* if using dynamic meta, don't set up generic infopackets */ 2525 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { 2526 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; 2527 enable = true; 2528 } 2529 2530 if (!hubp) 2531 return; 2532 2533 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) 2534 return; 2535 2536 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, 2537 hubp->inst, mode); 2538 } 2539 2540 void dcn20_fpga_init_hw(struct dc *dc) 2541 { 2542 int i, j; 2543 struct dce_hwseq *hws = dc->hwseq; 2544 struct resource_pool *res_pool = dc->res_pool; 2545 struct dc_state *context = dc->current_state; 2546 2547 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 2548 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 2549 2550 // Initialize the dccg 2551 if (res_pool->dccg->funcs->dccg_init) 2552 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 2553 2554 //Enable ability to power gate / don't force power on permanently 2555 hws->funcs.enable_power_gating_plane(hws, true); 2556 2557 // Specific to FPGA dccg and registers 2558 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); 2559 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 2560 2561 hws->funcs.dccg_init(hws); 2562 2563 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); 2564 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 2565 if (REG(REFCLK_CNTL)) 2566 REG_WRITE(REFCLK_CNTL, 0); 2567 // 2568 2569 2570 /* Blank pixel data with OPP DPG */ 2571 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2572 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2573 2574 if (tg->funcs->is_tg_enabled(tg)) 2575 dcn20_init_blank(dc, tg); 2576 } 2577 2578 for (i = 0; i < res_pool->timing_generator_count; i++) { 2579 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2580 2581 if (tg->funcs->is_tg_enabled(tg)) 2582 tg->funcs->lock(tg); 2583 } 2584 2585 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2586 struct dpp *dpp = res_pool->dpps[i]; 2587 2588 dpp->funcs->dpp_reset(dpp); 2589 } 2590 2591 /* Reset all MPCC muxes */ 2592 res_pool->mpc->funcs->mpc_init(res_pool->mpc); 2593 2594 /* initialize OPP mpc_tree parameter */ 2595 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 2596 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; 2597 res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2598 for (j = 0; j < MAX_PIPES; j++) 2599 res_pool->opps[i]->mpcc_disconnect_pending[j] = false; 2600 } 2601 2602 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2603 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2604 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2605 struct hubp *hubp = dc->res_pool->hubps[i]; 2606 struct dpp *dpp = dc->res_pool->dpps[i]; 2607 2608 pipe_ctx->stream_res.tg = tg; 2609 pipe_ctx->pipe_idx = i; 2610 2611 pipe_ctx->plane_res.hubp = hubp; 2612 pipe_ctx->plane_res.dpp = dpp; 2613 pipe_ctx->plane_res.mpcc_inst = dpp->inst; 2614 hubp->mpcc_id = dpp->inst; 2615 hubp->opp_id = OPP_ID_INVALID; 2616 hubp->power_gated = false; 2617 pipe_ctx->stream_res.opp = NULL; 2618 2619 hubp->funcs->hubp_init(hubp); 2620 2621 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; 2622 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2623 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; 2624 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; 2625 /*to do*/ 2626 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx); 2627 } 2628 2629 /* initialize DWB pointer to MCIF_WB */ 2630 for (i = 0; i < res_pool->res_cap->num_dwb; i++) 2631 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; 2632 2633 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2634 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2635 2636 if (tg->funcs->is_tg_enabled(tg)) 2637 tg->funcs->unlock(tg); 2638 } 2639 2640 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2641 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2642 2643 dc->hwss.disable_plane(dc, pipe_ctx); 2644 2645 pipe_ctx->stream_res.tg = NULL; 2646 pipe_ctx->plane_res.hubp = NULL; 2647 } 2648 2649 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2650 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2651 2652 tg->funcs->tg_init(tg); 2653 } 2654 2655 if (dc->res_pool->hubbub->funcs->init_crb) 2656 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 2657 } 2658 #ifndef TRIM_FSFT 2659 bool dcn20_optimize_timing_for_fsft(struct dc *dc, 2660 struct dc_crtc_timing *timing, 2661 unsigned int max_input_rate_in_khz) 2662 { 2663 unsigned int old_v_front_porch; 2664 unsigned int old_v_total; 2665 unsigned int max_input_rate_in_100hz; 2666 unsigned long long new_v_total; 2667 2668 max_input_rate_in_100hz = max_input_rate_in_khz * 10; 2669 if (max_input_rate_in_100hz < timing->pix_clk_100hz) 2670 return false; 2671 2672 old_v_total = timing->v_total; 2673 old_v_front_porch = timing->v_front_porch; 2674 2675 timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz; 2676 timing->pix_clk_100hz = max_input_rate_in_100hz; 2677 2678 new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz); 2679 2680 timing->v_total = new_v_total; 2681 timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total); 2682 return true; 2683 } 2684 #endif 2685 2686 void dcn20_set_disp_pattern_generator(const struct dc *dc, 2687 struct pipe_ctx *pipe_ctx, 2688 enum controller_dp_test_pattern test_pattern, 2689 enum controller_dp_color_space color_space, 2690 enum dc_color_depth color_depth, 2691 const struct tg_color *solid_color, 2692 int width, int height, int offset) 2693 { 2694 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern, 2695 color_space, color_depth, solid_color, width, height, offset); 2696 } 2697